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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /* ALSA SoC TLV320AIC3X codec driver
0003  *
0004  * Author:      Vladimir Barinov, <vbarinov@embeddedalley.com>
0005  * Copyright:   (C) 2007 MontaVista Software, Inc., <source@mvista.com>
0006  *
0007  * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
0008  *
0009  * Notes:
0010  *  The AIC3X is a driver for a low power stereo audio
0011  *  codecs aic31, aic32, aic33, aic3007.
0012  *
0013  *  It supports full aic33 codec functionality.
0014  *  The compatibility with aic32, aic31 and aic3007 is as follows:
0015  *    aic32/aic3007    |        aic31
0016  *  ---------------------------------------
0017  *   MONO_LOUT -> N/A  |  MONO_LOUT -> N/A
0018  *                     |  IN1L -> LINE1L
0019  *                     |  IN1R -> LINE1R
0020  *                     |  IN2L -> LINE2L
0021  *                     |  IN2R -> LINE2R
0022  *                     |  MIC3L/R -> N/A
0023  *   truncated internal functionality in
0024  *   accordance with documentation
0025  *  ---------------------------------------
0026  *
0027  *  Hence the machine layer should disable unsupported inputs/outputs by
0028  *  snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
0029  */
0030 
0031 #include <linux/module.h>
0032 #include <linux/moduleparam.h>
0033 #include <linux/init.h>
0034 #include <linux/delay.h>
0035 #include <linux/pm.h>
0036 #include <linux/i2c.h>
0037 #include <linux/gpio.h>
0038 #include <linux/regulator/consumer.h>
0039 #include <linux/of.h>
0040 #include <linux/of_gpio.h>
0041 #include <linux/slab.h>
0042 #include <sound/core.h>
0043 #include <sound/pcm.h>
0044 #include <sound/pcm_params.h>
0045 #include <sound/soc.h>
0046 #include <sound/initval.h>
0047 #include <sound/tlv.h>
0048 #include <sound/tlv320aic3x.h>
0049 
0050 #include "tlv320aic3x.h"
0051 
0052 #define AIC3X_NUM_SUPPLIES  4
0053 static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
0054     "IOVDD",    /* I/O Voltage */
0055     "DVDD",     /* Digital Core Voltage */
0056     "AVDD",     /* Analog DAC Voltage */
0057     "DRVDD",    /* ADC Analog and Output Driver Voltage */
0058 };
0059 
0060 static LIST_HEAD(reset_list);
0061 
0062 struct aic3x_priv;
0063 
0064 struct aic3x_disable_nb {
0065     struct notifier_block nb;
0066     struct aic3x_priv *aic3x;
0067 };
0068 
0069 /* codec private data */
0070 struct aic3x_priv {
0071     struct snd_soc_component *component;
0072     struct regmap *regmap;
0073     struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
0074     struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES];
0075     struct aic3x_setup_data *setup;
0076     unsigned int sysclk;
0077     unsigned int dai_fmt;
0078     unsigned int tdm_delay;
0079     unsigned int slot_width;
0080     struct list_head list;
0081     int master;
0082     int gpio_reset;
0083     int power;
0084     u16 model;
0085 
0086     /* Selects the micbias voltage */
0087     enum aic3x_micbias_voltage micbias_vg;
0088     /* Output Common-Mode Voltage */
0089     u8 ocmv;
0090 };
0091 
0092 static const struct reg_default aic3x_reg[] = {
0093     {   0, 0x00 }, {   1, 0x00 }, {   2, 0x00 }, {   3, 0x10 },
0094     {   4, 0x04 }, {   5, 0x00 }, {   6, 0x00 }, {   7, 0x00 },
0095     {   8, 0x00 }, {   9, 0x00 }, {  10, 0x00 }, {  11, 0x01 },
0096     {  12, 0x00 }, {  13, 0x00 }, {  14, 0x00 }, {  15, 0x80 },
0097     {  16, 0x80 }, {  17, 0xff }, {  18, 0xff }, {  19, 0x78 },
0098     {  20, 0x78 }, {  21, 0x78 }, {  22, 0x78 }, {  23, 0x78 },
0099     {  24, 0x78 }, {  25, 0x00 }, {  26, 0x00 }, {  27, 0xfe },
0100     {  28, 0x00 }, {  29, 0x00 }, {  30, 0xfe }, {  31, 0x00 },
0101     {  32, 0x18 }, {  33, 0x18 }, {  34, 0x00 }, {  35, 0x00 },
0102     {  36, 0x00 }, {  37, 0x00 }, {  38, 0x00 }, {  39, 0x00 },
0103     {  40, 0x00 }, {  41, 0x00 }, {  42, 0x00 }, {  43, 0x80 },
0104     {  44, 0x80 }, {  45, 0x00 }, {  46, 0x00 }, {  47, 0x00 },
0105     {  48, 0x00 }, {  49, 0x00 }, {  50, 0x00 }, {  51, 0x04 },
0106     {  52, 0x00 }, {  53, 0x00 }, {  54, 0x00 }, {  55, 0x00 },
0107     {  56, 0x00 }, {  57, 0x00 }, {  58, 0x04 }, {  59, 0x00 },
0108     {  60, 0x00 }, {  61, 0x00 }, {  62, 0x00 }, {  63, 0x00 },
0109     {  64, 0x00 }, {  65, 0x04 }, {  66, 0x00 }, {  67, 0x00 },
0110     {  68, 0x00 }, {  69, 0x00 }, {  70, 0x00 }, {  71, 0x00 },
0111     {  72, 0x04 }, {  73, 0x00 }, {  74, 0x00 }, {  75, 0x00 },
0112     {  76, 0x00 }, {  77, 0x00 }, {  78, 0x00 }, {  79, 0x00 },
0113     {  80, 0x00 }, {  81, 0x00 }, {  82, 0x00 }, {  83, 0x00 },
0114     {  84, 0x00 }, {  85, 0x00 }, {  86, 0x00 }, {  87, 0x00 },
0115     {  88, 0x00 }, {  89, 0x00 }, {  90, 0x00 }, {  91, 0x00 },
0116     {  92, 0x00 }, {  93, 0x00 }, {  94, 0x00 }, {  95, 0x00 },
0117     {  96, 0x00 }, {  97, 0x00 }, {  98, 0x00 }, {  99, 0x00 },
0118     { 100, 0x00 }, { 101, 0x00 }, { 102, 0x02 }, { 103, 0x00 },
0119     { 104, 0x00 }, { 105, 0x00 }, { 106, 0x00 }, { 107, 0x00 },
0120     { 108, 0x00 }, { 109, 0x00 },
0121 };
0122 
0123 static bool aic3x_volatile_reg(struct device *dev, unsigned int reg)
0124 {
0125     switch (reg) {
0126     case AIC3X_RESET:
0127         return true;
0128     default:
0129         return false;
0130     }
0131 }
0132 
0133 const struct regmap_config aic3x_regmap = {
0134     .max_register = DAC_ICC_ADJ,
0135     .reg_defaults = aic3x_reg,
0136     .num_reg_defaults = ARRAY_SIZE(aic3x_reg),
0137 
0138     .volatile_reg = aic3x_volatile_reg,
0139 
0140     .cache_type = REGCACHE_RBTREE,
0141 };
0142 EXPORT_SYMBOL_GPL(aic3x_regmap);
0143 
0144 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
0145     SOC_SINGLE_EXT(xname, reg, shift, mask, invert, \
0146         snd_soc_dapm_get_volsw, snd_soc_dapm_put_volsw_aic3x)
0147 
0148 /*
0149  * All input lines are connected when !0xf and disconnected with 0xf bit field,
0150  * so we have to use specific dapm_put call for input mixer
0151  */
0152 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
0153                     struct snd_ctl_elem_value *ucontrol)
0154 {
0155     struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
0156     struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
0157     struct soc_mixer_control *mc =
0158         (struct soc_mixer_control *)kcontrol->private_value;
0159     unsigned int reg = mc->reg;
0160     unsigned int shift = mc->shift;
0161     int max = mc->max;
0162     unsigned int mask = (1 << fls(max)) - 1;
0163     unsigned int invert = mc->invert;
0164     unsigned short val;
0165     struct snd_soc_dapm_update update = {};
0166     int connect, change;
0167 
0168     val = (ucontrol->value.integer.value[0] & mask);
0169 
0170     mask = 0xf;
0171     if (val)
0172         val = mask;
0173 
0174     connect = !!val;
0175 
0176     if (invert)
0177         val = mask - val;
0178 
0179     mask <<= shift;
0180     val <<= shift;
0181 
0182     change = snd_soc_component_test_bits(component, reg, mask, val);
0183     if (change) {
0184         update.kcontrol = kcontrol;
0185         update.reg = reg;
0186         update.mask = mask;
0187         update.val = val;
0188 
0189         snd_soc_dapm_mixer_update_power(dapm, kcontrol, connect,
0190             &update);
0191     }
0192 
0193     return change;
0194 }
0195 
0196 /*
0197  * mic bias power on/off share the same register bits with
0198  * output voltage of mic bias. when power on mic bias, we
0199  * need reclaim it to voltage value.
0200  * 0x0 = Powered off
0201  * 0x1 = MICBIAS output is powered to 2.0V,
0202  * 0x2 = MICBIAS output is powered to 2.5V
0203  * 0x3 = MICBIAS output is connected to AVDD
0204  */
0205 static int mic_bias_event(struct snd_soc_dapm_widget *w,
0206     struct snd_kcontrol *kcontrol, int event)
0207 {
0208     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0209     struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
0210 
0211     switch (event) {
0212     case SND_SOC_DAPM_POST_PMU:
0213         /* change mic bias voltage to user defined */
0214         snd_soc_component_update_bits(component, MICBIAS_CTRL,
0215                 MICBIAS_LEVEL_MASK,
0216                 aic3x->micbias_vg << MICBIAS_LEVEL_SHIFT);
0217         break;
0218 
0219     case SND_SOC_DAPM_PRE_PMD:
0220         snd_soc_component_update_bits(component, MICBIAS_CTRL,
0221                 MICBIAS_LEVEL_MASK, 0);
0222         break;
0223     }
0224     return 0;
0225 }
0226 
0227 static const char * const aic3x_left_dac_mux[] = {
0228     "DAC_L1", "DAC_L3", "DAC_L2" };
0229 static SOC_ENUM_SINGLE_DECL(aic3x_left_dac_enum, DAC_LINE_MUX, 6,
0230                 aic3x_left_dac_mux);
0231 
0232 static const char * const aic3x_right_dac_mux[] = {
0233     "DAC_R1", "DAC_R3", "DAC_R2" };
0234 static SOC_ENUM_SINGLE_DECL(aic3x_right_dac_enum, DAC_LINE_MUX, 4,
0235                 aic3x_right_dac_mux);
0236 
0237 static const char * const aic3x_left_hpcom_mux[] = {
0238     "differential of HPLOUT", "constant VCM", "single-ended" };
0239 static SOC_ENUM_SINGLE_DECL(aic3x_left_hpcom_enum, HPLCOM_CFG, 4,
0240                 aic3x_left_hpcom_mux);
0241 
0242 static const char * const aic3x_right_hpcom_mux[] = {
0243     "differential of HPROUT", "constant VCM", "single-ended",
0244     "differential of HPLCOM", "external feedback" };
0245 static SOC_ENUM_SINGLE_DECL(aic3x_right_hpcom_enum, HPRCOM_CFG, 3,
0246                 aic3x_right_hpcom_mux);
0247 
0248 static const char * const aic3x_linein_mode_mux[] = {
0249     "single-ended", "differential" };
0250 static SOC_ENUM_SINGLE_DECL(aic3x_line1l_2_l_enum, LINE1L_2_LADC_CTRL, 7,
0251                 aic3x_linein_mode_mux);
0252 static SOC_ENUM_SINGLE_DECL(aic3x_line1l_2_r_enum, LINE1L_2_RADC_CTRL, 7,
0253                 aic3x_linein_mode_mux);
0254 static SOC_ENUM_SINGLE_DECL(aic3x_line1r_2_l_enum, LINE1R_2_LADC_CTRL, 7,
0255                 aic3x_linein_mode_mux);
0256 static SOC_ENUM_SINGLE_DECL(aic3x_line1r_2_r_enum, LINE1R_2_RADC_CTRL, 7,
0257                 aic3x_linein_mode_mux);
0258 static SOC_ENUM_SINGLE_DECL(aic3x_line2l_2_ldac_enum, LINE2L_2_LADC_CTRL, 7,
0259                 aic3x_linein_mode_mux);
0260 static SOC_ENUM_SINGLE_DECL(aic3x_line2r_2_rdac_enum, LINE2R_2_RADC_CTRL, 7,
0261                 aic3x_linein_mode_mux);
0262 
0263 static const char * const aic3x_adc_hpf[] = {
0264     "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
0265 static SOC_ENUM_DOUBLE_DECL(aic3x_adc_hpf_enum, AIC3X_CODEC_DFILT_CTRL, 6, 4,
0266                 aic3x_adc_hpf);
0267 
0268 static const char * const aic3x_agc_level[] = {
0269     "-5.5dB", "-8dB", "-10dB", "-12dB",
0270     "-14dB", "-17dB", "-20dB", "-24dB" };
0271 static SOC_ENUM_SINGLE_DECL(aic3x_lagc_level_enum, LAGC_CTRL_A, 4,
0272                 aic3x_agc_level);
0273 static SOC_ENUM_SINGLE_DECL(aic3x_ragc_level_enum, RAGC_CTRL_A, 4,
0274                 aic3x_agc_level);
0275 
0276 static const char * const aic3x_agc_attack[] = {
0277     "8ms", "11ms", "16ms", "20ms" };
0278 static SOC_ENUM_SINGLE_DECL(aic3x_lagc_attack_enum, LAGC_CTRL_A, 2,
0279                 aic3x_agc_attack);
0280 static SOC_ENUM_SINGLE_DECL(aic3x_ragc_attack_enum, RAGC_CTRL_A, 2,
0281                 aic3x_agc_attack);
0282 
0283 static const char * const aic3x_agc_decay[] = {
0284     "100ms", "200ms", "400ms", "500ms" };
0285 static SOC_ENUM_SINGLE_DECL(aic3x_lagc_decay_enum, LAGC_CTRL_A, 0,
0286                 aic3x_agc_decay);
0287 static SOC_ENUM_SINGLE_DECL(aic3x_ragc_decay_enum, RAGC_CTRL_A, 0,
0288                 aic3x_agc_decay);
0289 
0290 static const char * const aic3x_poweron_time[] = {
0291     "0us", "10us", "100us", "1ms", "10ms", "50ms",
0292     "100ms", "200ms", "400ms", "800ms", "2s", "4s" };
0293 static SOC_ENUM_SINGLE_DECL(aic3x_poweron_time_enum, HPOUT_POP_REDUCTION, 4,
0294                 aic3x_poweron_time);
0295 
0296 static const char * const aic3x_rampup_step[] = { "0ms", "1ms", "2ms", "4ms" };
0297 static SOC_ENUM_SINGLE_DECL(aic3x_rampup_step_enum, HPOUT_POP_REDUCTION, 2,
0298                 aic3x_rampup_step);
0299 
0300 /*
0301  * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
0302  */
0303 static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
0304 /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
0305 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
0306 /*
0307  * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
0308  * Step size is approximately 0.5 dB over most of the scale but increasing
0309  * near the very low levels.
0310  * Define dB scale so that it is mostly correct for range about -55 to 0 dB
0311  * but having increasing dB difference below that (and where it doesn't count
0312  * so much). This setting shows -50 dB (actual is -50.3 dB) for register
0313  * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
0314  */
0315 static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
0316 
0317 /* Output volumes. From 0 to 9 dB in 1 dB steps */
0318 static const DECLARE_TLV_DB_SCALE(out_tlv, 0, 100, 0);
0319 
0320 static const struct snd_kcontrol_new aic3x_snd_controls[] = {
0321     /* Output */
0322     SOC_DOUBLE_R_TLV("PCM Playback Volume",
0323              LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
0324 
0325     /*
0326      * Output controls that map to output mixer switches. Note these are
0327      * only for swapped L-to-R and R-to-L routes. See below stereo controls
0328      * for direct L-to-L and R-to-R routes.
0329      */
0330     SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
0331                PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
0332     SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume",
0333                DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
0334 
0335     SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
0336                PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
0337     SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume",
0338                DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
0339 
0340     SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
0341                PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
0342     SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume",
0343                DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
0344 
0345     SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
0346                PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
0347     SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume",
0348                DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
0349 
0350     SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
0351                PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
0352     SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume",
0353                DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
0354 
0355     SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
0356                PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
0357     SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume",
0358                DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
0359 
0360     /* Stereo output controls for direct L-to-L and R-to-R routes */
0361     SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
0362              PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
0363              0, 118, 1, output_stage_tlv),
0364     SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
0365              DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
0366              0, 118, 1, output_stage_tlv),
0367 
0368     SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
0369              PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
0370              0, 118, 1, output_stage_tlv),
0371     SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
0372              DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
0373              0, 118, 1, output_stage_tlv),
0374 
0375     SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
0376              PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
0377              0, 118, 1, output_stage_tlv),
0378     SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
0379              DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
0380              0, 118, 1, output_stage_tlv),
0381 
0382     /* Output pin controls */
0383     SOC_DOUBLE_R_TLV("Line Playback Volume", LLOPM_CTRL, RLOPM_CTRL, 4,
0384              9, 0, out_tlv),
0385     SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
0386              0x01, 0),
0387     SOC_DOUBLE_R_TLV("HP Playback Volume", HPLOUT_CTRL, HPROUT_CTRL, 4,
0388              9, 0, out_tlv),
0389     SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
0390              0x01, 0),
0391     SOC_DOUBLE_R_TLV("HPCOM Playback Volume", HPLCOM_CTRL, HPRCOM_CTRL,
0392              4, 9, 0, out_tlv),
0393     SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
0394              0x01, 0),
0395 
0396     /*
0397      * Note: enable Automatic input Gain Controller with care. It can
0398      * adjust PGA to max value when ADC is on and will never go back.
0399     */
0400     SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
0401     SOC_ENUM("Left AGC Target level", aic3x_lagc_level_enum),
0402     SOC_ENUM("Right AGC Target level", aic3x_ragc_level_enum),
0403     SOC_ENUM("Left AGC Attack time", aic3x_lagc_attack_enum),
0404     SOC_ENUM("Right AGC Attack time", aic3x_ragc_attack_enum),
0405     SOC_ENUM("Left AGC Decay time", aic3x_lagc_decay_enum),
0406     SOC_ENUM("Right AGC Decay time", aic3x_ragc_decay_enum),
0407 
0408     /* De-emphasis */
0409     SOC_DOUBLE("De-emphasis Switch", AIC3X_CODEC_DFILT_CTRL, 2, 0, 0x01, 0),
0410 
0411     /* Input */
0412     SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
0413              0, 119, 0, adc_tlv),
0414     SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
0415 
0416     SOC_ENUM("ADC HPF Cut-off", aic3x_adc_hpf_enum),
0417 
0418     /* Pop reduction */
0419     SOC_ENUM("Output Driver Power-On time", aic3x_poweron_time_enum),
0420     SOC_ENUM("Output Driver Ramp-up step", aic3x_rampup_step_enum),
0421 };
0422 
0423 /* For other than tlv320aic3104 */
0424 static const struct snd_kcontrol_new aic3x_extra_snd_controls[] = {
0425     /*
0426      * Output controls that map to output mixer switches. Note these are
0427      * only for swapped L-to-R and R-to-L routes. See below stereo controls
0428      * for direct L-to-L and R-to-R routes.
0429      */
0430     SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
0431                LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
0432 
0433     SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume",
0434                LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
0435 
0436     SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume",
0437                LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
0438 
0439     SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume",
0440                LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
0441 
0442     SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume",
0443                LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
0444 
0445     SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume",
0446                LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
0447 
0448     /* Stereo output controls for direct L-to-L and R-to-R routes */
0449     SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume",
0450              LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
0451              0, 118, 1, output_stage_tlv),
0452 
0453     SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume",
0454              LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
0455              0, 118, 1, output_stage_tlv),
0456 
0457     SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume",
0458              LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
0459              0, 118, 1, output_stage_tlv),
0460 };
0461 
0462 static const struct snd_kcontrol_new aic3x_mono_controls[] = {
0463     SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume",
0464              LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
0465              0, 118, 1, output_stage_tlv),
0466     SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
0467              PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
0468              0, 118, 1, output_stage_tlv),
0469     SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
0470              DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
0471              0, 118, 1, output_stage_tlv),
0472 
0473     SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
0474     SOC_SINGLE_TLV("Mono Playback Volume", MONOLOPM_CTRL, 4, 9, 0,
0475             out_tlv),
0476 
0477 };
0478 
0479 /*
0480  * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps
0481  */
0482 static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0);
0483 
0484 static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl =
0485     SOC_DOUBLE_TLV("Class-D Playback Volume", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv);
0486 
0487 /* Left DAC Mux */
0488 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
0489 SOC_DAPM_ENUM("Route", aic3x_left_dac_enum);
0490 
0491 /* Right DAC Mux */
0492 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
0493 SOC_DAPM_ENUM("Route", aic3x_right_dac_enum);
0494 
0495 /* Left HPCOM Mux */
0496 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
0497 SOC_DAPM_ENUM("Route", aic3x_left_hpcom_enum);
0498 
0499 /* Right HPCOM Mux */
0500 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
0501 SOC_DAPM_ENUM("Route", aic3x_right_hpcom_enum);
0502 
0503 /* Left Line Mixer */
0504 static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = {
0505     SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
0506     SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
0507     SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
0508     SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
0509     /* Not on tlv320aic3104 */
0510     SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
0511     SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
0512 };
0513 
0514 /* Right Line Mixer */
0515 static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = {
0516     SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
0517     SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
0518     SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
0519     SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
0520     /* Not on tlv320aic3104 */
0521     SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
0522     SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
0523 };
0524 
0525 /* Mono Mixer */
0526 static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = {
0527     SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
0528     SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
0529     SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
0530     SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
0531     SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
0532     SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
0533 };
0534 
0535 /* Left HP Mixer */
0536 static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = {
0537     SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
0538     SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
0539     SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
0540     SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0),
0541     /* Not on tlv320aic3104 */
0542     SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
0543     SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0),
0544 };
0545 
0546 /* Right HP Mixer */
0547 static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = {
0548     SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
0549     SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0),
0550     SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
0551     SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
0552     /* Not on tlv320aic3104 */
0553     SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0),
0554     SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
0555 };
0556 
0557 /* Left HPCOM Mixer */
0558 static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = {
0559     SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
0560     SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
0561     SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
0562     SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0),
0563     /* Not on tlv320aic3104 */
0564     SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
0565     SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0),
0566 };
0567 
0568 /* Right HPCOM Mixer */
0569 static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = {
0570     SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
0571     SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0),
0572     SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
0573     SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
0574     /* Not on tlv320aic3104 */
0575     SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0),
0576     SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
0577 };
0578 
0579 /* Left PGA Mixer */
0580 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
0581     SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
0582     SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
0583     SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
0584     SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
0585     SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
0586 };
0587 
0588 /* Right PGA Mixer */
0589 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
0590     SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
0591     SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
0592     SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
0593     SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
0594     SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
0595 };
0596 
0597 /* Left PGA Mixer for tlv320aic3104 */
0598 static const struct snd_kcontrol_new aic3104_left_pga_mixer_controls[] = {
0599     SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
0600     SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
0601     SOC_DAPM_SINGLE_AIC3X("Mic2L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
0602     SOC_DAPM_SINGLE_AIC3X("Mic2R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
0603 };
0604 
0605 /* Right PGA Mixer for tlv320aic3104 */
0606 static const struct snd_kcontrol_new aic3104_right_pga_mixer_controls[] = {
0607     SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
0608     SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
0609     SOC_DAPM_SINGLE_AIC3X("Mic2L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
0610     SOC_DAPM_SINGLE_AIC3X("Mic2R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
0611 };
0612 
0613 /* Left Line1 Mux */
0614 static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls =
0615 SOC_DAPM_ENUM("Route", aic3x_line1l_2_l_enum);
0616 static const struct snd_kcontrol_new aic3x_right_line1l_mux_controls =
0617 SOC_DAPM_ENUM("Route", aic3x_line1l_2_r_enum);
0618 
0619 /* Right Line1 Mux */
0620 static const struct snd_kcontrol_new aic3x_right_line1r_mux_controls =
0621 SOC_DAPM_ENUM("Route", aic3x_line1r_2_r_enum);
0622 static const struct snd_kcontrol_new aic3x_left_line1r_mux_controls =
0623 SOC_DAPM_ENUM("Route", aic3x_line1r_2_l_enum);
0624 
0625 /* Left Line2 Mux */
0626 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
0627 SOC_DAPM_ENUM("Route", aic3x_line2l_2_ldac_enum);
0628 
0629 /* Right Line2 Mux */
0630 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
0631 SOC_DAPM_ENUM("Route", aic3x_line2r_2_rdac_enum);
0632 
0633 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
0634     /* Left DAC to Left Outputs */
0635     SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
0636     SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
0637              &aic3x_left_dac_mux_controls),
0638     SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
0639              &aic3x_left_hpcom_mux_controls),
0640     SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
0641     SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
0642     SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
0643 
0644     /* Right DAC to Right Outputs */
0645     SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
0646     SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
0647              &aic3x_right_dac_mux_controls),
0648     SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
0649              &aic3x_right_hpcom_mux_controls),
0650     SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
0651     SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
0652     SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
0653 
0654     /* Inputs to Left ADC */
0655     SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
0656     SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
0657              &aic3x_left_line1l_mux_controls),
0658     SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
0659              &aic3x_left_line1r_mux_controls),
0660 
0661     /* Inputs to Right ADC */
0662     SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
0663              LINE1R_2_RADC_CTRL, 2, 0),
0664     SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
0665              &aic3x_right_line1l_mux_controls),
0666     SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
0667              &aic3x_right_line1r_mux_controls),
0668 
0669     /* Mic Bias */
0670     SND_SOC_DAPM_SUPPLY("Mic Bias", MICBIAS_CTRL, 6, 0,
0671              mic_bias_event,
0672              SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
0673 
0674     SND_SOC_DAPM_OUTPUT("LLOUT"),
0675     SND_SOC_DAPM_OUTPUT("RLOUT"),
0676     SND_SOC_DAPM_OUTPUT("HPLOUT"),
0677     SND_SOC_DAPM_OUTPUT("HPROUT"),
0678     SND_SOC_DAPM_OUTPUT("HPLCOM"),
0679     SND_SOC_DAPM_OUTPUT("HPRCOM"),
0680 
0681     SND_SOC_DAPM_INPUT("LINE1L"),
0682     SND_SOC_DAPM_INPUT("LINE1R"),
0683 
0684     /*
0685      * Virtual output pin to detection block inside codec. This can be
0686      * used to keep codec bias on if gpio or detection features are needed.
0687      * Force pin on or construct a path with an input jack and mic bias
0688      * widgets.
0689      */
0690     SND_SOC_DAPM_OUTPUT("Detection"),
0691 };
0692 
0693 /* For other than tlv320aic3104 */
0694 static const struct snd_soc_dapm_widget aic3x_extra_dapm_widgets[] = {
0695     /* Inputs to Left ADC */
0696     SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
0697                &aic3x_left_pga_mixer_controls[0],
0698                ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
0699     SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
0700              &aic3x_left_line2_mux_controls),
0701 
0702     /* Inputs to Right ADC */
0703     SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
0704                &aic3x_right_pga_mixer_controls[0],
0705                ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
0706     SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
0707              &aic3x_right_line2_mux_controls),
0708 
0709     /*
0710      * Not a real mic bias widget but similar function. This is for dynamic
0711      * control of GPIO1 digital mic modulator clock output function when
0712      * using digital mic.
0713      */
0714     SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
0715              AIC3X_GPIO1_REG, 4, 0xf,
0716              AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
0717              AIC3X_GPIO1_FUNC_DISABLED),
0718 
0719     /*
0720      * Also similar function like mic bias. Selects digital mic with
0721      * configurable oversampling rate instead of ADC converter.
0722      */
0723     SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
0724              AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
0725     SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
0726              AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
0727     SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
0728              AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
0729 
0730     /* Output mixers */
0731     SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
0732                &aic3x_left_line_mixer_controls[0],
0733                ARRAY_SIZE(aic3x_left_line_mixer_controls)),
0734     SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
0735                &aic3x_right_line_mixer_controls[0],
0736                ARRAY_SIZE(aic3x_right_line_mixer_controls)),
0737     SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
0738                &aic3x_left_hp_mixer_controls[0],
0739                ARRAY_SIZE(aic3x_left_hp_mixer_controls)),
0740     SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
0741                &aic3x_right_hp_mixer_controls[0],
0742                ARRAY_SIZE(aic3x_right_hp_mixer_controls)),
0743     SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
0744                &aic3x_left_hpcom_mixer_controls[0],
0745                ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)),
0746     SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
0747                &aic3x_right_hpcom_mixer_controls[0],
0748                ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)),
0749 
0750     SND_SOC_DAPM_INPUT("MIC3L"),
0751     SND_SOC_DAPM_INPUT("MIC3R"),
0752     SND_SOC_DAPM_INPUT("LINE2L"),
0753     SND_SOC_DAPM_INPUT("LINE2R"),
0754 };
0755 
0756 /* For tlv320aic3104 */
0757 static const struct snd_soc_dapm_widget aic3104_extra_dapm_widgets[] = {
0758     /* Inputs to Left ADC */
0759     SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
0760                &aic3104_left_pga_mixer_controls[0],
0761                ARRAY_SIZE(aic3104_left_pga_mixer_controls)),
0762 
0763     /* Inputs to Right ADC */
0764     SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
0765                &aic3104_right_pga_mixer_controls[0],
0766                ARRAY_SIZE(aic3104_right_pga_mixer_controls)),
0767 
0768     /* Output mixers */
0769     SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
0770                &aic3x_left_line_mixer_controls[0],
0771                ARRAY_SIZE(aic3x_left_line_mixer_controls) - 2),
0772     SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
0773                &aic3x_right_line_mixer_controls[0],
0774                ARRAY_SIZE(aic3x_right_line_mixer_controls) - 2),
0775     SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
0776                &aic3x_left_hp_mixer_controls[0],
0777                ARRAY_SIZE(aic3x_left_hp_mixer_controls) - 2),
0778     SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
0779                &aic3x_right_hp_mixer_controls[0],
0780                ARRAY_SIZE(aic3x_right_hp_mixer_controls) - 2),
0781     SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
0782                &aic3x_left_hpcom_mixer_controls[0],
0783                ARRAY_SIZE(aic3x_left_hpcom_mixer_controls) - 2),
0784     SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
0785                &aic3x_right_hpcom_mixer_controls[0],
0786                ARRAY_SIZE(aic3x_right_hpcom_mixer_controls) - 2),
0787 
0788     SND_SOC_DAPM_INPUT("MIC2L"),
0789     SND_SOC_DAPM_INPUT("MIC2R"),
0790 };
0791 
0792 static const struct snd_soc_dapm_widget aic3x_dapm_mono_widgets[] = {
0793     /* Mono Output */
0794     SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
0795 
0796     SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0,
0797                &aic3x_mono_mixer_controls[0],
0798                ARRAY_SIZE(aic3x_mono_mixer_controls)),
0799 
0800     SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
0801 };
0802 
0803 static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = {
0804     /* Class-D outputs */
0805     SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0),
0806     SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0),
0807 
0808     SND_SOC_DAPM_OUTPUT("SPOP"),
0809     SND_SOC_DAPM_OUTPUT("SPOM"),
0810 };
0811 
0812 static const struct snd_soc_dapm_route intercon[] = {
0813     /* Left Input */
0814     {"Left Line1L Mux", "single-ended", "LINE1L"},
0815     {"Left Line1L Mux", "differential", "LINE1L"},
0816     {"Left Line1R Mux", "single-ended", "LINE1R"},
0817     {"Left Line1R Mux", "differential", "LINE1R"},
0818 
0819     {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
0820     {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
0821 
0822     {"Left ADC", NULL, "Left PGA Mixer"},
0823 
0824     /* Right Input */
0825     {"Right Line1R Mux", "single-ended", "LINE1R"},
0826     {"Right Line1R Mux", "differential", "LINE1R"},
0827     {"Right Line1L Mux", "single-ended", "LINE1L"},
0828     {"Right Line1L Mux", "differential", "LINE1L"},
0829 
0830     {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
0831     {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
0832 
0833     {"Right ADC", NULL, "Right PGA Mixer"},
0834 
0835     /* Left DAC Output */
0836     {"Left DAC Mux", "DAC_L1", "Left DAC"},
0837     {"Left DAC Mux", "DAC_L2", "Left DAC"},
0838     {"Left DAC Mux", "DAC_L3", "Left DAC"},
0839 
0840     /* Right DAC Output */
0841     {"Right DAC Mux", "DAC_R1", "Right DAC"},
0842     {"Right DAC Mux", "DAC_R2", "Right DAC"},
0843     {"Right DAC Mux", "DAC_R3", "Right DAC"},
0844 
0845     /* Left Line Output */
0846     {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
0847     {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
0848     {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
0849     {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
0850 
0851     {"Left Line Out", NULL, "Left Line Mixer"},
0852     {"Left Line Out", NULL, "Left DAC Mux"},
0853     {"LLOUT", NULL, "Left Line Out"},
0854 
0855     /* Right Line Output */
0856     {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
0857     {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
0858     {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
0859     {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
0860 
0861     {"Right Line Out", NULL, "Right Line Mixer"},
0862     {"Right Line Out", NULL, "Right DAC Mux"},
0863     {"RLOUT", NULL, "Right Line Out"},
0864 
0865     /* Left HP Output */
0866     {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
0867     {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
0868     {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
0869     {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
0870 
0871     {"Left HP Out", NULL, "Left HP Mixer"},
0872     {"Left HP Out", NULL, "Left DAC Mux"},
0873     {"HPLOUT", NULL, "Left HP Out"},
0874 
0875     /* Right HP Output */
0876     {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
0877     {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
0878     {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
0879     {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
0880 
0881     {"Right HP Out", NULL, "Right HP Mixer"},
0882     {"Right HP Out", NULL, "Right DAC Mux"},
0883     {"HPROUT", NULL, "Right HP Out"},
0884 
0885     /* Left HPCOM Output */
0886     {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
0887     {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
0888     {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
0889     {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
0890 
0891     {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"},
0892     {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"},
0893     {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
0894     {"Left HP Com", NULL, "Left HPCOM Mux"},
0895     {"HPLCOM", NULL, "Left HP Com"},
0896 
0897     /* Right HPCOM Output */
0898     {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
0899     {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
0900     {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
0901     {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
0902 
0903     {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"},
0904     {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"},
0905     {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
0906     {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"},
0907     {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"},
0908     {"Right HP Com", NULL, "Right HPCOM Mux"},
0909     {"HPRCOM", NULL, "Right HP Com"},
0910 };
0911 
0912 /* For other than tlv320aic3104 */
0913 static const struct snd_soc_dapm_route intercon_extra[] = {
0914     /* Left Input */
0915     {"Left Line2L Mux", "single-ended", "LINE2L"},
0916     {"Left Line2L Mux", "differential", "LINE2L"},
0917 
0918     {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
0919     {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
0920     {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
0921 
0922     {"Left ADC", NULL, "GPIO1 dmic modclk"},
0923 
0924     /* Right Input */
0925     {"Right Line2R Mux", "single-ended", "LINE2R"},
0926     {"Right Line2R Mux", "differential", "LINE2R"},
0927 
0928     {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
0929     {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
0930     {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
0931 
0932     {"Right ADC", NULL, "GPIO1 dmic modclk"},
0933 
0934     /*
0935      * Logical path between digital mic enable and GPIO1 modulator clock
0936      * output function
0937      */
0938     {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
0939     {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
0940     {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
0941 
0942     /* Left Line Output */
0943     {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
0944     {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
0945 
0946     /* Right Line Output */
0947     {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
0948     {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
0949 
0950     /* Left HP Output */
0951     {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
0952     {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
0953 
0954     /* Right HP Output */
0955     {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
0956     {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
0957 
0958     /* Left HPCOM Output */
0959     {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
0960     {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
0961 
0962     /* Right HPCOM Output */
0963     {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
0964     {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
0965 };
0966 
0967 /* For tlv320aic3104 */
0968 static const struct snd_soc_dapm_route intercon_extra_3104[] = {
0969     /* Left Input */
0970     {"Left PGA Mixer", "Mic2L Switch", "MIC2L"},
0971     {"Left PGA Mixer", "Mic2R Switch", "MIC2R"},
0972 
0973     /* Right Input */
0974     {"Right PGA Mixer", "Mic2L Switch", "MIC2L"},
0975     {"Right PGA Mixer", "Mic2R Switch", "MIC2R"},
0976 };
0977 
0978 static const struct snd_soc_dapm_route intercon_mono[] = {
0979     /* Mono Output */
0980     {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
0981     {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
0982     {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
0983     {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
0984     {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
0985     {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
0986     {"Mono Out", NULL, "Mono Mixer"},
0987     {"MONO_LOUT", NULL, "Mono Out"},
0988 };
0989 
0990 static const struct snd_soc_dapm_route intercon_3007[] = {
0991     /* Class-D outputs */
0992     {"Left Class-D Out", NULL, "Left Line Out"},
0993     {"Right Class-D Out", NULL, "Left Line Out"},
0994     {"SPOP", NULL, "Left Class-D Out"},
0995     {"SPOM", NULL, "Right Class-D Out"},
0996 };
0997 
0998 static int aic3x_add_widgets(struct snd_soc_component *component)
0999 {
1000     struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
1001     struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1002 
1003     switch (aic3x->model) {
1004     case AIC3X_MODEL_3X:
1005     case AIC3X_MODEL_33:
1006     case AIC3X_MODEL_3106:
1007         snd_soc_dapm_new_controls(dapm, aic3x_extra_dapm_widgets,
1008                       ARRAY_SIZE(aic3x_extra_dapm_widgets));
1009         snd_soc_dapm_add_routes(dapm, intercon_extra,
1010                     ARRAY_SIZE(intercon_extra));
1011         snd_soc_dapm_new_controls(dapm, aic3x_dapm_mono_widgets,
1012             ARRAY_SIZE(aic3x_dapm_mono_widgets));
1013         snd_soc_dapm_add_routes(dapm, intercon_mono,
1014                     ARRAY_SIZE(intercon_mono));
1015         break;
1016     case AIC3X_MODEL_3007:
1017         snd_soc_dapm_new_controls(dapm, aic3x_extra_dapm_widgets,
1018                       ARRAY_SIZE(aic3x_extra_dapm_widgets));
1019         snd_soc_dapm_add_routes(dapm, intercon_extra,
1020                     ARRAY_SIZE(intercon_extra));
1021         snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets,
1022             ARRAY_SIZE(aic3007_dapm_widgets));
1023         snd_soc_dapm_add_routes(dapm, intercon_3007,
1024                     ARRAY_SIZE(intercon_3007));
1025         break;
1026     case AIC3X_MODEL_3104:
1027         snd_soc_dapm_new_controls(dapm, aic3104_extra_dapm_widgets,
1028                 ARRAY_SIZE(aic3104_extra_dapm_widgets));
1029         snd_soc_dapm_add_routes(dapm, intercon_extra_3104,
1030                 ARRAY_SIZE(intercon_extra_3104));
1031         break;
1032     }
1033 
1034     return 0;
1035 }
1036 
1037 static int aic3x_hw_params(struct snd_pcm_substream *substream,
1038                struct snd_pcm_hw_params *params,
1039                struct snd_soc_dai *dai)
1040 {
1041     struct snd_soc_component *component = dai->component;
1042     struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
1043     int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
1044     u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
1045     u16 d, pll_d = 1;
1046     int clk;
1047     int width = aic3x->slot_width;
1048 
1049     if (!width)
1050         width = params_width(params);
1051 
1052     /* select data word length */
1053     data = snd_soc_component_read(component, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
1054     switch (width) {
1055     case 16:
1056         break;
1057     case 20:
1058         data |= (0x01 << 4);
1059         break;
1060     case 24:
1061         data |= (0x02 << 4);
1062         break;
1063     case 32:
1064         data |= (0x03 << 4);
1065         break;
1066     }
1067     snd_soc_component_write(component, AIC3X_ASD_INTF_CTRLB, data);
1068 
1069     /* Fsref can be 44100 or 48000 */
1070     fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
1071 
1072     /* Try to find a value for Q which allows us to bypass the PLL and
1073      * generate CODEC_CLK directly. */
1074     for (pll_q = 2; pll_q < 18; pll_q++)
1075         if (aic3x->sysclk / (128 * pll_q) == fsref) {
1076             bypass_pll = 1;
1077             break;
1078         }
1079 
1080     if (bypass_pll) {
1081         pll_q &= 0xf;
1082         snd_soc_component_write(component, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
1083         snd_soc_component_write(component, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
1084         /* disable PLL if it is bypassed */
1085         snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG, PLL_ENABLE, 0);
1086 
1087     } else {
1088         snd_soc_component_write(component, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
1089         /* enable PLL when it is used */
1090         snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG,
1091                     PLL_ENABLE, PLL_ENABLE);
1092     }
1093 
1094     /* Route Left DAC to left channel input and
1095      * right DAC to right channel input */
1096     data = (LDAC2LCH | RDAC2RCH);
1097     data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
1098     if (params_rate(params) >= 64000)
1099         data |= DUAL_RATE_MODE;
1100     snd_soc_component_write(component, AIC3X_CODEC_DATAPATH_REG, data);
1101 
1102     /* codec sample rate select */
1103     data = (fsref * 20) / params_rate(params);
1104     if (params_rate(params) < 64000)
1105         data /= 2;
1106     data /= 5;
1107     data -= 2;
1108     data |= (data << 4);
1109     snd_soc_component_write(component, AIC3X_SAMPLE_RATE_SEL_REG, data);
1110 
1111     if (bypass_pll)
1112         return 0;
1113 
1114     /* Use PLL, compute appropriate setup for j, d, r and p, the closest
1115      * one wins the game. Try with d==0 first, next with d!=0.
1116      * Constraints for j are according to the datasheet.
1117      * The sysclk is divided by 1000 to prevent integer overflows.
1118      */
1119 
1120     codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
1121 
1122     for (r = 1; r <= 16; r++)
1123         for (p = 1; p <= 8; p++) {
1124             for (j = 4; j <= 55; j++) {
1125                 /* This is actually 1000*((j+(d/10000))*r)/p
1126                  * The term had to be converted to get
1127                  * rid of the division by 10000; d = 0 here
1128                  */
1129                 int tmp_clk = (1000 * j * r) / p;
1130 
1131                 /* Check whether this values get closer than
1132                  * the best ones we had before
1133                  */
1134                 if (abs(codec_clk - tmp_clk) <
1135                     abs(codec_clk - last_clk)) {
1136                     pll_j = j; pll_d = 0;
1137                     pll_r = r; pll_p = p;
1138                     last_clk = tmp_clk;
1139                 }
1140 
1141                 /* Early exit for exact matches */
1142                 if (tmp_clk == codec_clk)
1143                     goto found;
1144             }
1145         }
1146 
1147     /* try with d != 0 */
1148     for (p = 1; p <= 8; p++) {
1149         j = codec_clk * p / 1000;
1150 
1151         if (j < 4 || j > 11)
1152             continue;
1153 
1154         /* do not use codec_clk here since we'd loose precision */
1155         d = ((2048 * p * fsref) - j * aic3x->sysclk)
1156             * 100 / (aic3x->sysclk/100);
1157 
1158         clk = (10000 * j + d) / (10 * p);
1159 
1160         /* check whether this values get closer than the best
1161          * ones we had before */
1162         if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
1163             pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
1164             last_clk = clk;
1165         }
1166 
1167         /* Early exit for exact matches */
1168         if (clk == codec_clk)
1169             goto found;
1170     }
1171 
1172     if (last_clk == 0) {
1173         printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
1174         return -EINVAL;
1175     }
1176 
1177 found:
1178     snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG, PLLP_MASK, pll_p);
1179     snd_soc_component_write(component, AIC3X_OVRF_STATUS_AND_PLLR_REG,
1180               pll_r << PLLR_SHIFT);
1181     snd_soc_component_write(component, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
1182     snd_soc_component_write(component, AIC3X_PLL_PROGC_REG,
1183               (pll_d >> 6) << PLLD_MSB_SHIFT);
1184     snd_soc_component_write(component, AIC3X_PLL_PROGD_REG,
1185               (pll_d & 0x3F) << PLLD_LSB_SHIFT);
1186 
1187     return 0;
1188 }
1189 
1190 static int aic3x_prepare(struct snd_pcm_substream *substream,
1191              struct snd_soc_dai *dai)
1192 {
1193     struct snd_soc_component *component = dai->component;
1194     struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
1195     int delay = 0;
1196     int width = aic3x->slot_width;
1197 
1198     if (!width)
1199         width = substream->runtime->sample_bits;
1200 
1201     /* TDM slot selection only valid in DSP_A/_B mode */
1202     if (aic3x->dai_fmt == SND_SOC_DAIFMT_DSP_A)
1203         delay += (aic3x->tdm_delay*width + 1);
1204     else if (aic3x->dai_fmt == SND_SOC_DAIFMT_DSP_B)
1205         delay += aic3x->tdm_delay*width;
1206 
1207     /* Configure data delay */
1208     snd_soc_component_write(component, AIC3X_ASD_INTF_CTRLC, delay);
1209 
1210     return 0;
1211 }
1212 
1213 static int aic3x_mute(struct snd_soc_dai *dai, int mute, int direction)
1214 {
1215     struct snd_soc_component *component = dai->component;
1216     u8 ldac_reg = snd_soc_component_read(component, LDAC_VOL) & ~MUTE_ON;
1217     u8 rdac_reg = snd_soc_component_read(component, RDAC_VOL) & ~MUTE_ON;
1218 
1219     if (mute) {
1220         snd_soc_component_write(component, LDAC_VOL, ldac_reg | MUTE_ON);
1221         snd_soc_component_write(component, RDAC_VOL, rdac_reg | MUTE_ON);
1222     } else {
1223         snd_soc_component_write(component, LDAC_VOL, ldac_reg);
1224         snd_soc_component_write(component, RDAC_VOL, rdac_reg);
1225     }
1226 
1227     return 0;
1228 }
1229 
1230 static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1231                 int clk_id, unsigned int freq, int dir)
1232 {
1233     struct snd_soc_component *component = codec_dai->component;
1234     struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
1235 
1236     /* set clock on MCLK or GPIO2 or BCLK */
1237     snd_soc_component_update_bits(component, AIC3X_CLKGEN_CTRL_REG, PLLCLK_IN_MASK,
1238                 clk_id << PLLCLK_IN_SHIFT);
1239     snd_soc_component_update_bits(component, AIC3X_CLKGEN_CTRL_REG, CLKDIV_IN_MASK,
1240                 clk_id << CLKDIV_IN_SHIFT);
1241 
1242     aic3x->sysclk = freq;
1243     return 0;
1244 }
1245 
1246 static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
1247                  unsigned int fmt)
1248 {
1249     struct snd_soc_component *component = codec_dai->component;
1250     struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
1251     u8 iface_areg, iface_breg;
1252 
1253     iface_areg = snd_soc_component_read(component, AIC3X_ASD_INTF_CTRLA) & 0x3f;
1254     iface_breg = snd_soc_component_read(component, AIC3X_ASD_INTF_CTRLB) & 0x3f;
1255 
1256     switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
1257     case SND_SOC_DAIFMT_CBP_CFP:
1258         aic3x->master = 1;
1259         iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
1260         break;
1261     case SND_SOC_DAIFMT_CBC_CFC:
1262         aic3x->master = 0;
1263         iface_areg &= ~(BIT_CLK_MASTER | WORD_CLK_MASTER);
1264         break;
1265     case SND_SOC_DAIFMT_CBP_CFC:
1266         aic3x->master = 1;
1267         iface_areg |= BIT_CLK_MASTER;
1268         iface_areg &= ~WORD_CLK_MASTER;
1269         break;
1270     case SND_SOC_DAIFMT_CBC_CFP:
1271         aic3x->master = 1;
1272         iface_areg |= WORD_CLK_MASTER;
1273         iface_areg &= ~BIT_CLK_MASTER;
1274         break;
1275     default:
1276         return -EINVAL;
1277     }
1278 
1279     /*
1280      * match both interface format and signal polarities since they
1281      * are fixed
1282      */
1283     switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
1284                SND_SOC_DAIFMT_INV_MASK)) {
1285     case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
1286         break;
1287     case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
1288     case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
1289         iface_breg |= (0x01 << 6);
1290         break;
1291     case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
1292         iface_breg |= (0x02 << 6);
1293         break;
1294     case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
1295         iface_breg |= (0x03 << 6);
1296         break;
1297     default:
1298         return -EINVAL;
1299     }
1300 
1301     aic3x->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
1302 
1303     /* set iface */
1304     snd_soc_component_write(component, AIC3X_ASD_INTF_CTRLA, iface_areg);
1305     snd_soc_component_write(component, AIC3X_ASD_INTF_CTRLB, iface_breg);
1306 
1307     return 0;
1308 }
1309 
1310 static int aic3x_set_dai_tdm_slot(struct snd_soc_dai *codec_dai,
1311                   unsigned int tx_mask, unsigned int rx_mask,
1312                   int slots, int slot_width)
1313 {
1314     struct snd_soc_component *component = codec_dai->component;
1315     struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
1316     unsigned int lsb;
1317 
1318     if (tx_mask != rx_mask) {
1319         dev_err(component->dev, "tx and rx masks must be symmetric\n");
1320         return -EINVAL;
1321     }
1322 
1323     if (unlikely(!tx_mask)) {
1324         dev_err(component->dev, "tx and rx masks need to be non 0\n");
1325         return -EINVAL;
1326     }
1327 
1328     /* TDM based on DSP mode requires slots to be adjacent */
1329     lsb = __ffs(tx_mask);
1330     if ((lsb + 1) != __fls(tx_mask)) {
1331         dev_err(component->dev, "Invalid mask, slots must be adjacent\n");
1332         return -EINVAL;
1333     }
1334 
1335     switch (slot_width) {
1336     case 16:
1337     case 20:
1338     case 24:
1339     case 32:
1340         break;
1341     default:
1342         dev_err(component->dev, "Unsupported slot width %d\n", slot_width);
1343         return -EINVAL;
1344     }
1345 
1346 
1347     aic3x->tdm_delay = lsb;
1348     aic3x->slot_width = slot_width;
1349 
1350     /* DOUT in high-impedance on inactive bit clocks */
1351     snd_soc_component_update_bits(component, AIC3X_ASD_INTF_CTRLA,
1352                 DOUT_TRISTATE, DOUT_TRISTATE);
1353 
1354     return 0;
1355 }
1356 
1357 static int aic3x_regulator_event(struct notifier_block *nb,
1358                  unsigned long event, void *data)
1359 {
1360     struct aic3x_disable_nb *disable_nb =
1361         container_of(nb, struct aic3x_disable_nb, nb);
1362     struct aic3x_priv *aic3x = disable_nb->aic3x;
1363 
1364     if (event & REGULATOR_EVENT_DISABLE) {
1365         /*
1366          * Put codec to reset and require cache sync as at least one
1367          * of the supplies was disabled
1368          */
1369         if (gpio_is_valid(aic3x->gpio_reset))
1370             gpio_set_value(aic3x->gpio_reset, 0);
1371         regcache_mark_dirty(aic3x->regmap);
1372     }
1373 
1374     return 0;
1375 }
1376 
1377 static int aic3x_set_power(struct snd_soc_component *component, int power)
1378 {
1379     struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
1380     unsigned int pll_c, pll_d;
1381     int ret;
1382 
1383     if (power) {
1384         ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
1385                         aic3x->supplies);
1386         if (ret)
1387             goto out;
1388         aic3x->power = 1;
1389 
1390         if (gpio_is_valid(aic3x->gpio_reset)) {
1391             udelay(1);
1392             gpio_set_value(aic3x->gpio_reset, 1);
1393         }
1394 
1395         /* Sync reg_cache with the hardware */
1396         regcache_cache_only(aic3x->regmap, false);
1397         regcache_sync(aic3x->regmap);
1398 
1399         /* Rewrite paired PLL D registers in case cached sync skipped
1400          * writing one of them and thus caused other one also not
1401          * being written
1402          */
1403         pll_c = snd_soc_component_read(component, AIC3X_PLL_PROGC_REG);
1404         pll_d = snd_soc_component_read(component, AIC3X_PLL_PROGD_REG);
1405         if (pll_c == aic3x_reg[AIC3X_PLL_PROGC_REG].def ||
1406             pll_d == aic3x_reg[AIC3X_PLL_PROGD_REG].def) {
1407             snd_soc_component_write(component, AIC3X_PLL_PROGC_REG, pll_c);
1408             snd_soc_component_write(component, AIC3X_PLL_PROGD_REG, pll_d);
1409         }
1410 
1411         /*
1412          * Delay is needed to reduce pop-noise after syncing back the
1413          * registers
1414          */
1415         mdelay(50);
1416     } else {
1417         /*
1418          * Do soft reset to this codec instance in order to clear
1419          * possible VDD leakage currents in case the supply regulators
1420          * remain on
1421          */
1422         snd_soc_component_write(component, AIC3X_RESET, SOFT_RESET);
1423         regcache_mark_dirty(aic3x->regmap);
1424         aic3x->power = 0;
1425         /* HW writes are needless when bias is off */
1426         regcache_cache_only(aic3x->regmap, true);
1427         ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies),
1428                          aic3x->supplies);
1429     }
1430 out:
1431     return ret;
1432 }
1433 
1434 static int aic3x_set_bias_level(struct snd_soc_component *component,
1435                 enum snd_soc_bias_level level)
1436 {
1437     struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
1438 
1439     switch (level) {
1440     case SND_SOC_BIAS_ON:
1441         break;
1442     case SND_SOC_BIAS_PREPARE:
1443         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY &&
1444             aic3x->master) {
1445             /* enable pll */
1446             snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG,
1447                         PLL_ENABLE, PLL_ENABLE);
1448         }
1449         break;
1450     case SND_SOC_BIAS_STANDBY:
1451         if (!aic3x->power)
1452             aic3x_set_power(component, 1);
1453         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE &&
1454             aic3x->master) {
1455             /* disable pll */
1456             snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG,
1457                         PLL_ENABLE, 0);
1458         }
1459         break;
1460     case SND_SOC_BIAS_OFF:
1461         if (aic3x->power)
1462             aic3x_set_power(component, 0);
1463         break;
1464     }
1465 
1466     return 0;
1467 }
1468 
1469 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1470 #define AIC3X_FORMATS   (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1471              SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE | \
1472              SNDRV_PCM_FMTBIT_S32_LE)
1473 
1474 static const struct snd_soc_dai_ops aic3x_dai_ops = {
1475     .hw_params  = aic3x_hw_params,
1476     .prepare    = aic3x_prepare,
1477     .mute_stream    = aic3x_mute,
1478     .set_sysclk = aic3x_set_dai_sysclk,
1479     .set_fmt    = aic3x_set_dai_fmt,
1480     .set_tdm_slot   = aic3x_set_dai_tdm_slot,
1481     .no_capture_mute = 1,
1482 };
1483 
1484 static struct snd_soc_dai_driver aic3x_dai = {
1485     .name = "tlv320aic3x-hifi",
1486     .playback = {
1487         .stream_name = "Playback",
1488         .channels_min = 2,
1489         .channels_max = 2,
1490         .rates = AIC3X_RATES,
1491         .formats = AIC3X_FORMATS,},
1492     .capture = {
1493         .stream_name = "Capture",
1494         .channels_min = 2,
1495         .channels_max = 2,
1496         .rates = AIC3X_RATES,
1497         .formats = AIC3X_FORMATS,},
1498     .ops = &aic3x_dai_ops,
1499     .symmetric_rate = 1,
1500 };
1501 
1502 static void aic3x_mono_init(struct snd_soc_component *component)
1503 {
1504     /* DAC to Mono Line Out default volume and route to Output mixer */
1505     snd_soc_component_write(component, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1506     snd_soc_component_write(component, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1507 
1508     /* unmute all outputs */
1509     snd_soc_component_update_bits(component, MONOLOPM_CTRL, UNMUTE, UNMUTE);
1510 
1511     /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1512     snd_soc_component_write(component, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1513     snd_soc_component_write(component, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
1514 
1515     /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1516     snd_soc_component_write(component, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1517     snd_soc_component_write(component, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
1518 }
1519 
1520 /*
1521  * initialise the AIC3X driver
1522  * register the mixer and dsp interfaces with the kernel
1523  */
1524 static int aic3x_init(struct snd_soc_component *component)
1525 {
1526     struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
1527 
1528     snd_soc_component_write(component, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1529     snd_soc_component_write(component, AIC3X_RESET, SOFT_RESET);
1530 
1531     /* DAC default volume and mute */
1532     snd_soc_component_write(component, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1533     snd_soc_component_write(component, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
1534 
1535     /* DAC to HP default volume and route to Output mixer */
1536     snd_soc_component_write(component, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1537     snd_soc_component_write(component, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1538     snd_soc_component_write(component, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1539     snd_soc_component_write(component, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1540     /* DAC to Line Out default volume and route to Output mixer */
1541     snd_soc_component_write(component, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1542     snd_soc_component_write(component, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1543 
1544     /* unmute all outputs */
1545     snd_soc_component_update_bits(component, LLOPM_CTRL, UNMUTE, UNMUTE);
1546     snd_soc_component_update_bits(component, RLOPM_CTRL, UNMUTE, UNMUTE);
1547     snd_soc_component_update_bits(component, HPLOUT_CTRL, UNMUTE, UNMUTE);
1548     snd_soc_component_update_bits(component, HPROUT_CTRL, UNMUTE, UNMUTE);
1549     snd_soc_component_update_bits(component, HPLCOM_CTRL, UNMUTE, UNMUTE);
1550     snd_soc_component_update_bits(component, HPRCOM_CTRL, UNMUTE, UNMUTE);
1551 
1552     /* ADC default volume and unmute */
1553     snd_soc_component_write(component, LADC_VOL, DEFAULT_GAIN);
1554     snd_soc_component_write(component, RADC_VOL, DEFAULT_GAIN);
1555     /* By default route Line1 to ADC PGA mixer */
1556     snd_soc_component_write(component, LINE1L_2_LADC_CTRL, 0x0);
1557     snd_soc_component_write(component, LINE1R_2_RADC_CTRL, 0x0);
1558 
1559     /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1560     snd_soc_component_write(component, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1561     snd_soc_component_write(component, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1562     snd_soc_component_write(component, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1563     snd_soc_component_write(component, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
1564     /* PGA to Line Out default volume, disconnect from Output Mixer */
1565     snd_soc_component_write(component, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1566     snd_soc_component_write(component, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
1567 
1568     /* On tlv320aic3104, these registers are reserved and must not be written */
1569     if (aic3x->model != AIC3X_MODEL_3104) {
1570         /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1571         snd_soc_component_write(component, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1572         snd_soc_component_write(component, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1573         snd_soc_component_write(component, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1574         snd_soc_component_write(component, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
1575         /* Line2 Line Out default volume, disconnect from Output Mixer */
1576         snd_soc_component_write(component, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1577         snd_soc_component_write(component, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
1578     }
1579 
1580     switch (aic3x->model) {
1581     case AIC3X_MODEL_3X:
1582     case AIC3X_MODEL_33:
1583     case AIC3X_MODEL_3106:
1584         aic3x_mono_init(component);
1585         break;
1586     case AIC3X_MODEL_3007:
1587         snd_soc_component_write(component, CLASSD_CTRL, 0);
1588         break;
1589     }
1590 
1591     /*  Output common-mode voltage = 1.5 V */
1592     snd_soc_component_update_bits(component, HPOUT_SC, HPOUT_SC_OCMV_MASK,
1593                 aic3x->ocmv << HPOUT_SC_OCMV_SHIFT);
1594 
1595     return 0;
1596 }
1597 
1598 static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x)
1599 {
1600     struct aic3x_priv *a;
1601 
1602     list_for_each_entry(a, &reset_list, list) {
1603         if (gpio_is_valid(aic3x->gpio_reset) &&
1604             aic3x->gpio_reset == a->gpio_reset)
1605             return true;
1606     }
1607 
1608     return false;
1609 }
1610 
1611 static int aic3x_component_probe(struct snd_soc_component *component)
1612 {
1613     struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
1614     int ret, i;
1615 
1616     aic3x->component = component;
1617 
1618     for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) {
1619         aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event;
1620         aic3x->disable_nb[i].aic3x = aic3x;
1621         ret = devm_regulator_register_notifier(
1622                         aic3x->supplies[i].consumer,
1623                         &aic3x->disable_nb[i].nb);
1624         if (ret) {
1625             dev_err(component->dev,
1626                 "Failed to request regulator notifier: %d\n",
1627                  ret);
1628             return ret;
1629         }
1630     }
1631 
1632     regcache_mark_dirty(aic3x->regmap);
1633     aic3x_init(component);
1634 
1635     if (aic3x->setup) {
1636         if (aic3x->model != AIC3X_MODEL_3104) {
1637             /* setup GPIO functions */
1638             snd_soc_component_write(component, AIC3X_GPIO1_REG,
1639                       (aic3x->setup->gpio_func[0] & 0xf) << 4);
1640             snd_soc_component_write(component, AIC3X_GPIO2_REG,
1641                       (aic3x->setup->gpio_func[1] & 0xf) << 4);
1642         } else {
1643             dev_warn(component->dev, "GPIO functionality is not supported on tlv320aic3104\n");
1644         }
1645     }
1646 
1647     switch (aic3x->model) {
1648     case AIC3X_MODEL_3X:
1649     case AIC3X_MODEL_33:
1650     case AIC3X_MODEL_3106:
1651         snd_soc_add_component_controls(component, aic3x_extra_snd_controls,
1652                 ARRAY_SIZE(aic3x_extra_snd_controls));
1653         snd_soc_add_component_controls(component, aic3x_mono_controls,
1654                 ARRAY_SIZE(aic3x_mono_controls));
1655         break;
1656     case AIC3X_MODEL_3007:
1657         snd_soc_add_component_controls(component, aic3x_extra_snd_controls,
1658                 ARRAY_SIZE(aic3x_extra_snd_controls));
1659         snd_soc_add_component_controls(component,
1660                 &aic3x_classd_amp_gain_ctrl, 1);
1661         break;
1662     case AIC3X_MODEL_3104:
1663         break;
1664     }
1665 
1666     /* set mic bias voltage */
1667     switch (aic3x->micbias_vg) {
1668     case AIC3X_MICBIAS_2_0V:
1669     case AIC3X_MICBIAS_2_5V:
1670     case AIC3X_MICBIAS_AVDDV:
1671         snd_soc_component_update_bits(component, MICBIAS_CTRL,
1672                     MICBIAS_LEVEL_MASK,
1673                     (aic3x->micbias_vg) << MICBIAS_LEVEL_SHIFT);
1674         break;
1675     case AIC3X_MICBIAS_OFF:
1676         /*
1677          * noting to do. target won't enter here. This is just to avoid
1678          * compile time warning "warning: enumeration value
1679          * 'AIC3X_MICBIAS_OFF' not handled in switch"
1680          */
1681         break;
1682     }
1683 
1684     aic3x_add_widgets(component);
1685 
1686     return 0;
1687 }
1688 
1689 static const struct snd_soc_component_driver soc_component_dev_aic3x = {
1690     .set_bias_level     = aic3x_set_bias_level,
1691     .probe          = aic3x_component_probe,
1692     .controls       = aic3x_snd_controls,
1693     .num_controls       = ARRAY_SIZE(aic3x_snd_controls),
1694     .dapm_widgets       = aic3x_dapm_widgets,
1695     .num_dapm_widgets   = ARRAY_SIZE(aic3x_dapm_widgets),
1696     .dapm_routes        = intercon,
1697     .num_dapm_routes    = ARRAY_SIZE(intercon),
1698     .use_pmdown_time    = 1,
1699     .endianness     = 1,
1700 };
1701 
1702 static void aic3x_configure_ocmv(struct device *dev, struct aic3x_priv *aic3x)
1703 {
1704     struct device_node *np = dev->of_node;
1705     u32 value;
1706     int dvdd, avdd;
1707 
1708     if (np && !of_property_read_u32(np, "ai3x-ocmv", &value)) {
1709         /* OCMV setting is forced by DT */
1710         if (value <= 3) {
1711             aic3x->ocmv = value;
1712             return;
1713         }
1714     }
1715 
1716     dvdd = regulator_get_voltage(aic3x->supplies[1].consumer);
1717     avdd = regulator_get_voltage(aic3x->supplies[2].consumer);
1718 
1719     if (avdd > 3600000 || dvdd > 1950000) {
1720         dev_warn(dev,
1721              "Too high supply voltage(s) AVDD: %d, DVDD: %d\n",
1722              avdd, dvdd);
1723     } else if (avdd == 3600000 && dvdd == 1950000) {
1724         aic3x->ocmv = HPOUT_SC_OCMV_1_8V;
1725     } else if (avdd > 3300000 && dvdd > 1800000) {
1726         aic3x->ocmv = HPOUT_SC_OCMV_1_65V;
1727     } else if (avdd > 3000000 && dvdd > 1650000) {
1728         aic3x->ocmv = HPOUT_SC_OCMV_1_5V;
1729     } else if (avdd >= 2700000 && dvdd >= 1525000) {
1730         aic3x->ocmv = HPOUT_SC_OCMV_1_35V;
1731     } else {
1732         dev_warn(dev,
1733              "Invalid supply voltage(s) AVDD: %d, DVDD: %d\n",
1734              avdd, dvdd);
1735     }
1736 }
1737 
1738 
1739 static const struct reg_sequence aic3007_class_d[] = {
1740     /* Class-D speaker driver init; datasheet p. 46 */
1741     { AIC3X_PAGE_SELECT, 0x0D },
1742     { 0xD, 0x0D },
1743     { 0x8, 0x5C },
1744     { 0x8, 0x5D },
1745     { 0x8, 0x5C },
1746     { AIC3X_PAGE_SELECT, 0x00 },
1747 };
1748 
1749 int aic3x_probe(struct device *dev, struct regmap *regmap, kernel_ulong_t driver_data)
1750 {
1751     struct aic3x_pdata *pdata = dev->platform_data;
1752     struct aic3x_priv *aic3x;
1753     struct aic3x_setup_data *ai3x_setup;
1754     struct device_node *np = dev->of_node;
1755     int ret, i;
1756     u32 value;
1757 
1758     aic3x = devm_kzalloc(dev, sizeof(struct aic3x_priv), GFP_KERNEL);
1759     if (!aic3x)
1760         return -ENOMEM;
1761 
1762     aic3x->regmap = regmap;
1763     if (IS_ERR(aic3x->regmap)) {
1764         ret = PTR_ERR(aic3x->regmap);
1765         return ret;
1766     }
1767 
1768     regcache_cache_only(aic3x->regmap, true);
1769 
1770     dev_set_drvdata(dev, aic3x);
1771     if (pdata) {
1772         aic3x->gpio_reset = pdata->gpio_reset;
1773         aic3x->setup = pdata->setup;
1774         aic3x->micbias_vg = pdata->micbias_vg;
1775     } else if (np) {
1776         ai3x_setup = devm_kzalloc(dev, sizeof(*ai3x_setup), GFP_KERNEL);
1777         if (!ai3x_setup)
1778             return -ENOMEM;
1779 
1780         ret = of_get_named_gpio(np, "reset-gpios", 0);
1781         if (ret >= 0) {
1782             aic3x->gpio_reset = ret;
1783         } else {
1784             ret = of_get_named_gpio(np, "gpio-reset", 0);
1785             if (ret > 0) {
1786                 dev_warn(dev, "Using deprecated property \"gpio-reset\", please update your DT");
1787                 aic3x->gpio_reset = ret;
1788             } else {
1789                 aic3x->gpio_reset = -1;
1790             }
1791         }
1792 
1793         if (of_property_read_u32_array(np, "ai3x-gpio-func",
1794                     ai3x_setup->gpio_func, 2) >= 0) {
1795             aic3x->setup = ai3x_setup;
1796         }
1797 
1798         if (!of_property_read_u32(np, "ai3x-micbias-vg", &value)) {
1799             switch (value) {
1800             case 1 :
1801                 aic3x->micbias_vg = AIC3X_MICBIAS_2_0V;
1802                 break;
1803             case 2 :
1804                 aic3x->micbias_vg = AIC3X_MICBIAS_2_5V;
1805                 break;
1806             case 3 :
1807                 aic3x->micbias_vg = AIC3X_MICBIAS_AVDDV;
1808                 break;
1809             default :
1810                 aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
1811                 dev_err(dev, "Unsuitable MicBias voltage "
1812                             "found in DT\n");
1813             }
1814         } else {
1815             aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
1816         }
1817 
1818     } else {
1819         aic3x->gpio_reset = -1;
1820     }
1821 
1822     aic3x->model = driver_data;
1823 
1824     if (gpio_is_valid(aic3x->gpio_reset) &&
1825         !aic3x_is_shared_reset(aic3x)) {
1826         ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset");
1827         if (ret != 0)
1828             goto err;
1829         gpio_direction_output(aic3x->gpio_reset, 0);
1830     }
1831 
1832     for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1833         aic3x->supplies[i].supply = aic3x_supply_names[i];
1834 
1835     ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(aic3x->supplies),
1836                       aic3x->supplies);
1837     if (ret != 0) {
1838         dev_err(dev, "Failed to request supplies: %d\n", ret);
1839         goto err_gpio;
1840     }
1841 
1842     aic3x_configure_ocmv(dev, aic3x);
1843 
1844     if (aic3x->model == AIC3X_MODEL_3007) {
1845         ret = regmap_register_patch(aic3x->regmap, aic3007_class_d,
1846                         ARRAY_SIZE(aic3007_class_d));
1847         if (ret != 0)
1848             dev_err(dev, "Failed to init class D: %d\n",
1849                 ret);
1850     }
1851 
1852     ret = devm_snd_soc_register_component(dev, &soc_component_dev_aic3x, &aic3x_dai, 1);
1853 
1854     if (ret != 0)
1855         goto err_gpio;
1856 
1857     INIT_LIST_HEAD(&aic3x->list);
1858     list_add(&aic3x->list, &reset_list);
1859 
1860     return 0;
1861 
1862 err_gpio:
1863     if (gpio_is_valid(aic3x->gpio_reset) &&
1864         !aic3x_is_shared_reset(aic3x))
1865         gpio_free(aic3x->gpio_reset);
1866 err:
1867     return ret;
1868 }
1869 EXPORT_SYMBOL(aic3x_probe);
1870 
1871 void aic3x_remove(struct device *dev)
1872 {
1873     struct aic3x_priv *aic3x = dev_get_drvdata(dev);
1874 
1875     list_del(&aic3x->list);
1876 
1877     if (gpio_is_valid(aic3x->gpio_reset) &&
1878         !aic3x_is_shared_reset(aic3x)) {
1879         gpio_set_value(aic3x->gpio_reset, 0);
1880         gpio_free(aic3x->gpio_reset);
1881     }
1882 }
1883 EXPORT_SYMBOL(aic3x_remove);
1884 
1885 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1886 MODULE_AUTHOR("Vladimir Barinov");
1887 MODULE_LICENSE("GPL");
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