soc/codecs/tlv320aic32x4.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * tlv320aic32x4.h
0004  */
0005
0006
0007 #ifndef _TLV320AIC32X4_H
0008 #define _TLV320AIC32X4_H
0009
0010 struct device;
0011 struct regmap_config;
0012
0013 enum aic32x4_type {
0014     AIC32X4_TYPE_AIC32X4 = 0,
0015     AIC32X4_TYPE_AIC32X6,
0016     AIC32X4_TYPE_TAS2505,
0017 };
0018
0019 extern const struct regmap_config aic32x4_regmap_config;
0020 int aic32x4_probe(struct device *dev, struct regmap *regmap);
0021 void aic32x4_remove(struct device *dev);
0022 int aic32x4_register_clocks(struct device *dev, const char *mclk_name);
0023
0024 /* tlv320aic32x4 register space (in decimal to match datasheet) */
0025
0026 #define AIC32X4_REG(page, reg)  ((page * 128) + reg)
0027
0028 #define AIC32X4_PSEL        AIC32X4_REG(0, 0)
0029
0030 #define AIC32X4_RESET       AIC32X4_REG(0, 1)
0031 #define AIC32X4_CLKMUX      AIC32X4_REG(0, 4)
0032 #define AIC32X4_PLLPR       AIC32X4_REG(0, 5)
0033 #define AIC32X4_PLLJ        AIC32X4_REG(0, 6)
0034 #define AIC32X4_PLLDMSB     AIC32X4_REG(0, 7)
0035 #define AIC32X4_PLLDLSB     AIC32X4_REG(0, 8)
0036 #define AIC32X4_NDAC        AIC32X4_REG(0, 11)
0037 #define AIC32X4_MDAC        AIC32X4_REG(0, 12)
0038 #define AIC32X4_DOSRMSB     AIC32X4_REG(0, 13)
0039 #define AIC32X4_DOSRLSB     AIC32X4_REG(0, 14)
0040 #define AIC32X4_NADC        AIC32X4_REG(0, 18)
0041 #define AIC32X4_MADC        AIC32X4_REG(0, 19)
0042 #define AIC32X4_AOSR        AIC32X4_REG(0, 20)
0043 #define AIC32X4_CLKMUX2     AIC32X4_REG(0, 25)
0044 #define AIC32X4_CLKOUTM     AIC32X4_REG(0, 26)
0045 #define AIC32X4_IFACE1      AIC32X4_REG(0, 27)
0046 #define AIC32X4_IFACE2      AIC32X4_REG(0, 28)
0047 #define AIC32X4_IFACE3      AIC32X4_REG(0, 29)
0048 #define AIC32X4_BCLKN       AIC32X4_REG(0, 30)
0049 #define AIC32X4_IFACE4      AIC32X4_REG(0, 31)
0050 #define AIC32X4_IFACE5      AIC32X4_REG(0, 32)
0051 #define AIC32X4_IFACE6      AIC32X4_REG(0, 33)
0052 #define AIC32X4_GPIOCTL     AIC32X4_REG(0, 52)
0053 #define AIC32X4_DOUTCTL     AIC32X4_REG(0, 53)
0054 #define AIC32X4_DINCTL      AIC32X4_REG(0, 54)
0055 #define AIC32X4_MISOCTL     AIC32X4_REG(0, 55)
0056 #define AIC32X4_SCLKCTL     AIC32X4_REG(0, 56)
0057 #define AIC32X4_DACSPB      AIC32X4_REG(0, 60)
0058 #define AIC32X4_ADCSPB      AIC32X4_REG(0, 61)
0059 #define AIC32X4_DACSETUP    AIC32X4_REG(0, 63)
0060 #define AIC32X4_DACMUTE     AIC32X4_REG(0, 64)
0061 #define AIC32X4_LDACVOL     AIC32X4_REG(0, 65)
0062 #define AIC32X4_RDACVOL     AIC32X4_REG(0, 66)
0063 #define AIC32X4_ADCSETUP    AIC32X4_REG(0, 81)
0064 #define AIC32X4_ADCFGA      AIC32X4_REG(0, 82)
0065 #define AIC32X4_LADCVOL     AIC32X4_REG(0, 83)
0066 #define AIC32X4_RADCVOL     AIC32X4_REG(0, 84)
0067 #define AIC32X4_LAGC1       AIC32X4_REG(0, 86)
0068 #define AIC32X4_LAGC2       AIC32X4_REG(0, 87)
0069 #define AIC32X4_LAGC3       AIC32X4_REG(0, 88)
0070 #define AIC32X4_LAGC4       AIC32X4_REG(0, 89)
0071 #define AIC32X4_LAGC5       AIC32X4_REG(0, 90)
0072 #define AIC32X4_LAGC6       AIC32X4_REG(0, 91)
0073 #define AIC32X4_LAGC7       AIC32X4_REG(0, 92)
0074 #define AIC32X4_RAGC1       AIC32X4_REG(0, 94)
0075 #define AIC32X4_RAGC2       AIC32X4_REG(0, 95)
0076 #define AIC32X4_RAGC3       AIC32X4_REG(0, 96)
0077 #define AIC32X4_RAGC4       AIC32X4_REG(0, 97)
0078 #define AIC32X4_RAGC5       AIC32X4_REG(0, 98)
0079 #define AIC32X4_RAGC6       AIC32X4_REG(0, 99)
0080 #define AIC32X4_RAGC7       AIC32X4_REG(0, 100)
0081
0082 #define AIC32X4_PWRCFG      AIC32X4_REG(1, 1)
0083 #define AIC32X4_LDOCTL      AIC32X4_REG(1, 2)
0084 #define AIC32X4_LPLAYBACK   AIC32X4_REG(1, 3)
0085 #define AIC32X4_RPLAYBACK   AIC32X4_REG(1, 4)
0086 #define AIC32X4_OUTPWRCTL   AIC32X4_REG(1, 9)
0087 #define AIC32X4_CMMODE      AIC32X4_REG(1, 10)
0088 #define AIC32X4_HPLROUTE    AIC32X4_REG(1, 12)
0089 #define AIC32X4_HPRROUTE    AIC32X4_REG(1, 13)
0090 #define AIC32X4_LOLROUTE    AIC32X4_REG(1, 14)
0091 #define AIC32X4_LORROUTE    AIC32X4_REG(1, 15)
0092 #define AIC32X4_HPLGAIN     AIC32X4_REG(1, 16)
0093 #define AIC32X4_HPRGAIN     AIC32X4_REG(1, 17)
0094 #define AIC32X4_LOLGAIN     AIC32X4_REG(1, 18)
0095 #define AIC32X4_LORGAIN     AIC32X4_REG(1, 19)
0096 #define AIC32X4_HEADSTART   AIC32X4_REG(1, 20)
0097 #define TAS2505_SPK     AIC32X4_REG(1, 45)
0098 #define TAS2505_SPKVOL1     AIC32X4_REG(1, 46)
0099 #define TAS2505_SPKVOL2     AIC32X4_REG(1, 48)
0100 #define AIC32X4_MICBIAS     AIC32X4_REG(1, 51)
0101 #define AIC32X4_LMICPGAPIN  AIC32X4_REG(1, 52)
0102 #define AIC32X4_LMICPGANIN  AIC32X4_REG(1, 54)
0103 #define AIC32X4_RMICPGAPIN  AIC32X4_REG(1, 55)
0104 #define AIC32X4_RMICPGANIN  AIC32X4_REG(1, 57)
0105 #define AIC32X4_FLOATINGINPUT   AIC32X4_REG(1, 58)
0106 #define AIC32X4_LMICPGAVOL  AIC32X4_REG(1, 59)
0107 #define AIC32X4_RMICPGAVOL  AIC32X4_REG(1, 60)
0108 #define TAS2505_REFPOWERUP  AIC32X4_REG(1, 122)
0109 #define AIC32X4_REFPOWERUP  AIC32X4_REG(1, 123)
0110
0111 /* Bits, masks, and shifts */
0112
0113 /* AIC32X4_CLKMUX */
0114 #define AIC32X4_PLL_CLKIN_MASK      GENMASK(3, 2)
0115 #define AIC32X4_PLL_CLKIN_SHIFT     (2)
0116 #define AIC32X4_PLL_CLKIN_MCLK      (0x00)
0117 #define AIC32X4_PLL_CLKIN_BCKL      (0x01)
0118 #define AIC32X4_PLL_CLKIN_GPIO1     (0x02)
0119 #define AIC32X4_PLL_CLKIN_DIN       (0x03)
0120 #define AIC32X4_CODEC_CLKIN_MASK    GENMASK(1, 0)
0121 #define AIC32X4_CODEC_CLKIN_SHIFT   (0)
0122 #define AIC32X4_CODEC_CLKIN_MCLK    (0x00)
0123 #define AIC32X4_CODEC_CLKIN_BCLK    (0x01)
0124 #define AIC32X4_CODEC_CLKIN_GPIO1   (0x02)
0125 #define AIC32X4_CODEC_CLKIN_PLL     (0x03)
0126
0127 /* AIC32X4_PLLPR */
0128 #define AIC32X4_PLLEN           BIT(7)
0129 #define AIC32X4_PLL_P_MASK      GENMASK(6, 4)
0130 #define AIC32X4_PLL_P_SHIFT     (4)
0131 #define AIC32X4_PLL_R_MASK      GENMASK(3, 0)
0132
0133 /* AIC32X4_NDAC */
0134 #define AIC32X4_NDACEN          BIT(7)
0135 #define AIC32X4_NDAC_MASK       GENMASK(6, 0)
0136
0137 /* AIC32X4_MDAC */
0138 #define AIC32X4_MDACEN          BIT(7)
0139 #define AIC32X4_MDAC_MASK       GENMASK(6, 0)
0140
0141 /* AIC32X4_NADC */
0142 #define AIC32X4_NADCEN          BIT(7)
0143 #define AIC32X4_NADC_MASK       GENMASK(6, 0)
0144
0145 /* AIC32X4_MADC */
0146 #define AIC32X4_MADCEN          BIT(7)
0147 #define AIC32X4_MADC_MASK       GENMASK(6, 0)
0148
0149 /* AIC32X4_BCLKN */
0150 #define AIC32X4_BCLKEN          BIT(7)
0151 #define AIC32X4_BCLK_MASK       GENMASK(6, 0)
0152
0153 /* AIC32X4_IFACE1 */
0154 #define AIC32X4_IFACE1_DATATYPE_MASK    GENMASK(7, 6)
0155 #define AIC32X4_IFACE1_DATATYPE_SHIFT   (6)
0156 #define AIC32X4_I2S_MODE        (0x00)
0157 #define AIC32X4_DSP_MODE        (0x01)
0158 #define AIC32X4_RIGHT_JUSTIFIED_MODE    (0x02)
0159 #define AIC32X4_LEFT_JUSTIFIED_MODE (0x03)
0160 #define AIC32X4_IFACE1_DATALEN_MASK GENMASK(5, 4)
0161 #define AIC32X4_IFACE1_DATALEN_SHIFT    (4)
0162 #define AIC32X4_WORD_LEN_16BITS     (0x00)
0163 #define AIC32X4_WORD_LEN_20BITS     (0x01)
0164 #define AIC32X4_WORD_LEN_24BITS     (0x02)
0165 #define AIC32X4_WORD_LEN_32BITS     (0x03)
0166 #define AIC32X4_IFACE1_MASTER_MASK  GENMASK(3, 2)
0167 #define AIC32X4_BCLKMASTER      BIT(2)
0168 #define AIC32X4_WCLKMASTER      BIT(3)
0169
0170 /* AIC32X4_IFACE2 */
0171 #define AIC32X4_DATA_OFFSET_MASK    GENMASK(7, 0)
0172
0173 /* AIC32X4_IFACE3 */
0174 #define AIC32X4_BCLKINV_MASK        BIT(3)
0175 #define AIC32X4_BDIVCLK_MASK        GENMASK(1, 0)
0176 #define AIC32X4_BDIVCLK_SHIFT       (0)
0177 #define AIC32X4_DAC2BCLK        (0x00)
0178 #define AIC32X4_DACMOD2BCLK     (0x01)
0179 #define AIC32X4_ADC2BCLK        (0x02)
0180 #define AIC32X4_ADCMOD2BCLK     (0x03)
0181
0182 /* AIC32X4_DACSETUP */
0183 #define AIC32X4_DAC_CHAN_MASK       GENMASK(5, 2)
0184 #define AIC32X4_LDAC2RCHN       BIT(5)
0185 #define AIC32X4_LDAC2LCHN       BIT(4)
0186 #define AIC32X4_RDAC2LCHN       BIT(3)
0187 #define AIC32X4_RDAC2RCHN       BIT(2)
0188
0189 /* AIC32X4_DACMUTE */
0190 #define AIC32X4_MUTEON          0x0C
0191
0192 /* AIC32X4_ADCSETUP */
0193 #define AIC32X4_LADC_EN         BIT(7)
0194 #define AIC32X4_RADC_EN         BIT(6)
0195
0196 /* AIC32X4_PWRCFG */
0197 #define AIC32X4_AVDDWEAKDISABLE     BIT(3)
0198
0199 /* AIC32X4_LDOCTL */
0200 #define AIC32X4_LDOCTLEN        BIT(0)
0201
0202 /* AIC32X4_CMMODE */
0203 #define AIC32X4_LDOIN_18_36     BIT(0)
0204 #define AIC32X4_LDOIN2HP        BIT(1)
0205
0206 /* AIC32X4_MICBIAS */
0207 #define AIC32X4_MICBIAS_LDOIN       BIT(3)
0208 #define AIC32X4_MICBIAS_2075V       0x60
0209 #define AIC32x4_MICBIAS_MASK            GENMASK(6, 3)
0210
0211 /* AIC32X4_LMICPGANIN */
0212 #define AIC32X4_LMICPGANIN_IN2R_10K 0x10
0213 #define AIC32X4_LMICPGANIN_CM1L_10K 0x40
0214
0215 /* AIC32X4_RMICPGANIN */
0216 #define AIC32X4_RMICPGANIN_IN1L_10K 0x10
0217 #define AIC32X4_RMICPGANIN_CM1R_10K 0x40
0218
0219 /* AIC32X4_REFPOWERUP */
0220 #define AIC32X4_REFPOWERUP_SLOW     0x04
0221 #define AIC32X4_REFPOWERUP_40MS     0x05
0222 #define AIC32X4_REFPOWERUP_80MS     0x06
0223 #define AIC32X4_REFPOWERUP_120MS    0x07
0224
0225 /* Common mask and enable for all of the dividers */
0226 #define AIC32X4_DIVEN           BIT(7)
0227 #define AIC32X4_DIV_MASK        GENMASK(6, 0)
0228
0229 /* Clock Limits */
0230 #define AIC32X4_MAX_DOSR_FREQ       6200000
0231 #define AIC32X4_MIN_DOSR_FREQ       2800000
0232 #define AIC32X4_MAX_CODEC_CLKIN_FREQ    110000000
0233 #define AIC32X4_MAX_PLL_CLKIN       20000000
0234
0235 #endif              /* _TLV320AIC32X4_H */