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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * linux/sound/soc/codecs/tlv320aic32x4.c
0004  *
0005  * Copyright 2011 Vista Silicon S.L.
0006  *
0007  * Author: Javier Martin <javier.martin@vista-silicon.com>
0008  *
0009  * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27.
0010  */
0011 
0012 #include <linux/module.h>
0013 #include <linux/moduleparam.h>
0014 #include <linux/init.h>
0015 #include <linux/delay.h>
0016 #include <linux/pm.h>
0017 #include <linux/gpio.h>
0018 #include <linux/of_gpio.h>
0019 #include <linux/cdev.h>
0020 #include <linux/slab.h>
0021 #include <linux/clk.h>
0022 #include <linux/of_clk.h>
0023 #include <linux/regulator/consumer.h>
0024 
0025 #include <sound/tlv320aic32x4.h>
0026 #include <sound/core.h>
0027 #include <sound/pcm.h>
0028 #include <sound/pcm_params.h>
0029 #include <sound/soc.h>
0030 #include <sound/soc-dapm.h>
0031 #include <sound/initval.h>
0032 #include <sound/tlv.h>
0033 
0034 #include "tlv320aic32x4.h"
0035 
0036 struct aic32x4_priv {
0037     struct regmap *regmap;
0038     u32 power_cfg;
0039     u32 micpga_routing;
0040     bool swapdacs;
0041     int rstn_gpio;
0042     const char *mclk_name;
0043 
0044     struct regulator *supply_ldo;
0045     struct regulator *supply_iov;
0046     struct regulator *supply_dv;
0047     struct regulator *supply_av;
0048 
0049     struct aic32x4_setup_data *setup;
0050     struct device *dev;
0051     enum aic32x4_type type;
0052 
0053     unsigned int fmt;
0054 };
0055 
0056 static int aic32x4_reset_adc(struct snd_soc_dapm_widget *w,
0057                  struct snd_kcontrol *kcontrol, int event)
0058 {
0059     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0060     u32 adc_reg;
0061 
0062     /*
0063      * Workaround: the datasheet does not mention a required programming
0064      * sequence but experiments show the ADC needs to be reset after each
0065      * capture to avoid audible artifacts.
0066      */
0067     switch (event) {
0068     case SND_SOC_DAPM_POST_PMD:
0069         adc_reg = snd_soc_component_read(component, AIC32X4_ADCSETUP);
0070         snd_soc_component_write(component, AIC32X4_ADCSETUP, adc_reg |
0071                     AIC32X4_LADC_EN | AIC32X4_RADC_EN);
0072         snd_soc_component_write(component, AIC32X4_ADCSETUP, adc_reg);
0073         break;
0074     }
0075     return 0;
0076 };
0077 
0078 static int mic_bias_event(struct snd_soc_dapm_widget *w,
0079     struct snd_kcontrol *kcontrol, int event)
0080 {
0081     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0082 
0083     switch (event) {
0084     case SND_SOC_DAPM_POST_PMU:
0085         /* Change Mic Bias Registor */
0086         snd_soc_component_update_bits(component, AIC32X4_MICBIAS,
0087                 AIC32x4_MICBIAS_MASK,
0088                 AIC32X4_MICBIAS_LDOIN |
0089                 AIC32X4_MICBIAS_2075V);
0090         printk(KERN_DEBUG "%s: Mic Bias will be turned ON\n", __func__);
0091         break;
0092     case SND_SOC_DAPM_PRE_PMD:
0093         snd_soc_component_update_bits(component, AIC32X4_MICBIAS,
0094                 AIC32x4_MICBIAS_MASK, 0);
0095         printk(KERN_DEBUG "%s: Mic Bias will be turned OFF\n",
0096                 __func__);
0097         break;
0098     }
0099 
0100     return 0;
0101 }
0102 
0103 
0104 static int aic32x4_get_mfp1_gpio(struct snd_kcontrol *kcontrol,
0105     struct snd_ctl_elem_value *ucontrol)
0106 {
0107     struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
0108     u8 val;
0109 
0110     val = snd_soc_component_read(component, AIC32X4_DINCTL);
0111 
0112     ucontrol->value.integer.value[0] = (val & 0x01);
0113 
0114     return 0;
0115 };
0116 
0117 static int aic32x4_set_mfp2_gpio(struct snd_kcontrol *kcontrol,
0118     struct snd_ctl_elem_value *ucontrol)
0119 {
0120     struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
0121     u8 val;
0122     u8 gpio_check;
0123 
0124     val = snd_soc_component_read(component, AIC32X4_DOUTCTL);
0125     gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED);
0126     if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) {
0127         printk(KERN_ERR "%s: MFP2 is not configure as a GPIO output\n",
0128             __func__);
0129         return -EINVAL;
0130     }
0131 
0132     if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP2_GPIO_OUT_HIGH))
0133         return 0;
0134 
0135     if (ucontrol->value.integer.value[0])
0136         val |= ucontrol->value.integer.value[0];
0137     else
0138         val &= ~AIC32X4_MFP2_GPIO_OUT_HIGH;
0139 
0140     snd_soc_component_write(component, AIC32X4_DOUTCTL, val);
0141 
0142     return 0;
0143 };
0144 
0145 static int aic32x4_get_mfp3_gpio(struct snd_kcontrol *kcontrol,
0146     struct snd_ctl_elem_value *ucontrol)
0147 {
0148     struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
0149     u8 val;
0150 
0151     val = snd_soc_component_read(component, AIC32X4_SCLKCTL);
0152 
0153     ucontrol->value.integer.value[0] = (val & 0x01);
0154 
0155     return 0;
0156 };
0157 
0158 static int aic32x4_set_mfp4_gpio(struct snd_kcontrol *kcontrol,
0159     struct snd_ctl_elem_value *ucontrol)
0160 {
0161     struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
0162     u8 val;
0163     u8 gpio_check;
0164 
0165     val = snd_soc_component_read(component, AIC32X4_MISOCTL);
0166     gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED);
0167     if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) {
0168         printk(KERN_ERR "%s: MFP4 is not configure as a GPIO output\n",
0169             __func__);
0170         return -EINVAL;
0171     }
0172 
0173     if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP5_GPIO_OUT_HIGH))
0174         return 0;
0175 
0176     if (ucontrol->value.integer.value[0])
0177         val |= ucontrol->value.integer.value[0];
0178     else
0179         val &= ~AIC32X4_MFP5_GPIO_OUT_HIGH;
0180 
0181     snd_soc_component_write(component, AIC32X4_MISOCTL, val);
0182 
0183     return 0;
0184 };
0185 
0186 static int aic32x4_get_mfp5_gpio(struct snd_kcontrol *kcontrol,
0187     struct snd_ctl_elem_value *ucontrol)
0188 {
0189     struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
0190     u8 val;
0191 
0192     val = snd_soc_component_read(component, AIC32X4_GPIOCTL);
0193     ucontrol->value.integer.value[0] = ((val & 0x2) >> 1);
0194 
0195     return 0;
0196 };
0197 
0198 static int aic32x4_set_mfp5_gpio(struct snd_kcontrol *kcontrol,
0199     struct snd_ctl_elem_value *ucontrol)
0200 {
0201     struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
0202     u8 val;
0203     u8 gpio_check;
0204 
0205     val = snd_soc_component_read(component, AIC32X4_GPIOCTL);
0206     gpio_check = (val & AIC32X4_MFP5_GPIO_OUTPUT);
0207     if (gpio_check != AIC32X4_MFP5_GPIO_OUTPUT) {
0208         printk(KERN_ERR "%s: MFP5 is not configure as a GPIO output\n",
0209             __func__);
0210         return -EINVAL;
0211     }
0212 
0213     if (ucontrol->value.integer.value[0] == (val & 0x1))
0214         return 0;
0215 
0216     if (ucontrol->value.integer.value[0])
0217         val |= ucontrol->value.integer.value[0];
0218     else
0219         val &= 0xfe;
0220 
0221     snd_soc_component_write(component, AIC32X4_GPIOCTL, val);
0222 
0223     return 0;
0224 };
0225 
0226 static const struct snd_kcontrol_new aic32x4_mfp1[] = {
0227     SOC_SINGLE_BOOL_EXT("MFP1 GPIO", 0, aic32x4_get_mfp1_gpio, NULL),
0228 };
0229 
0230 static const struct snd_kcontrol_new aic32x4_mfp2[] = {
0231     SOC_SINGLE_BOOL_EXT("MFP2 GPIO", 0, NULL, aic32x4_set_mfp2_gpio),
0232 };
0233 
0234 static const struct snd_kcontrol_new aic32x4_mfp3[] = {
0235     SOC_SINGLE_BOOL_EXT("MFP3 GPIO", 0, aic32x4_get_mfp3_gpio, NULL),
0236 };
0237 
0238 static const struct snd_kcontrol_new aic32x4_mfp4[] = {
0239     SOC_SINGLE_BOOL_EXT("MFP4 GPIO", 0, NULL, aic32x4_set_mfp4_gpio),
0240 };
0241 
0242 static const struct snd_kcontrol_new aic32x4_mfp5[] = {
0243     SOC_SINGLE_BOOL_EXT("MFP5 GPIO", 0, aic32x4_get_mfp5_gpio,
0244         aic32x4_set_mfp5_gpio),
0245 };
0246 
0247 /* 0dB min, 0.5dB steps */
0248 static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0);
0249 /* -63.5dB min, 0.5dB steps */
0250 static DECLARE_TLV_DB_SCALE(tlv_pcm, -6350, 50, 0);
0251 /* -6dB min, 1dB steps */
0252 static DECLARE_TLV_DB_SCALE(tlv_driver_gain, -600, 100, 0);
0253 /* -12dB min, 0.5dB steps */
0254 static DECLARE_TLV_DB_SCALE(tlv_adc_vol, -1200, 50, 0);
0255 /* -6dB min, 1dB steps */
0256 static DECLARE_TLV_DB_SCALE(tlv_tas_driver_gain, -5850, 50, 0);
0257 static DECLARE_TLV_DB_SCALE(tlv_amp_vol, 0, 600, 1);
0258 
0259 static const char * const lo_cm_text[] = {
0260     "Full Chip", "1.65V",
0261 };
0262 
0263 static SOC_ENUM_SINGLE_DECL(lo_cm_enum, AIC32X4_CMMODE, 3, lo_cm_text);
0264 
0265 static const char * const ptm_text[] = {
0266     "P3", "P2", "P1",
0267 };
0268 
0269 static SOC_ENUM_SINGLE_DECL(l_ptm_enum, AIC32X4_LPLAYBACK, 2, ptm_text);
0270 static SOC_ENUM_SINGLE_DECL(r_ptm_enum, AIC32X4_RPLAYBACK, 2, ptm_text);
0271 
0272 static const struct snd_kcontrol_new aic32x4_snd_controls[] = {
0273     SOC_DOUBLE_R_S_TLV("PCM Playback Volume", AIC32X4_LDACVOL,
0274             AIC32X4_RDACVOL, 0, -0x7f, 0x30, 7, 0, tlv_pcm),
0275     SOC_ENUM("DAC Left Playback PowerTune Switch", l_ptm_enum),
0276     SOC_ENUM("DAC Right Playback PowerTune Switch", r_ptm_enum),
0277     SOC_DOUBLE_R_S_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN,
0278             AIC32X4_HPRGAIN, 0, -0x6, 0x1d, 5, 0,
0279             tlv_driver_gain),
0280     SOC_DOUBLE_R_S_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN,
0281             AIC32X4_LORGAIN, 0, -0x6, 0x1d, 5, 0,
0282             tlv_driver_gain),
0283     SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN,
0284             AIC32X4_HPRGAIN, 6, 0x01, 1),
0285     SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN,
0286             AIC32X4_LORGAIN, 6, 0x01, 1),
0287     SOC_ENUM("LO Playback Common Mode Switch", lo_cm_enum),
0288     SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL,
0289             AIC32X4_RMICPGAVOL, 7, 0x01, 1),
0290 
0291     SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0),
0292     SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0),
0293 
0294     SOC_DOUBLE_R_S_TLV("ADC Level Volume", AIC32X4_LADCVOL,
0295             AIC32X4_RADCVOL, 0, -0x18, 0x28, 6, 0, tlv_adc_vol),
0296     SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL,
0297             AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5),
0298 
0299     SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0),
0300 
0301     SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0),
0302     SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0),
0303     SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1,
0304             4, 0x07, 0),
0305     SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1,
0306             0, 0x03, 0),
0307     SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2,
0308             6, 0x03, 0),
0309     SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2,
0310             1, 0x1F, 0),
0311     SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3,
0312             0, 0x7F, 0),
0313     SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4,
0314             3, 0x1F, 0),
0315     SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5,
0316             3, 0x1F, 0),
0317     SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6,
0318             0, 0x1F, 0),
0319     SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7,
0320             0, 0x0F, 0),
0321 };
0322 
0323 static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
0324     SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0),
0325     SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0),
0326 };
0327 
0328 static const struct snd_kcontrol_new hpr_output_mixer_controls[] = {
0329     SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0),
0330     SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0),
0331 };
0332 
0333 static const struct snd_kcontrol_new lol_output_mixer_controls[] = {
0334     SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0),
0335 };
0336 
0337 static const struct snd_kcontrol_new lor_output_mixer_controls[] = {
0338     SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0),
0339 };
0340 
0341 static const char * const resistor_text[] = {
0342     "Off", "10 kOhm", "20 kOhm", "40 kOhm",
0343 };
0344 
0345 /* Left mixer pins */
0346 static SOC_ENUM_SINGLE_DECL(in1l_lpga_p_enum, AIC32X4_LMICPGAPIN, 6, resistor_text);
0347 static SOC_ENUM_SINGLE_DECL(in2l_lpga_p_enum, AIC32X4_LMICPGAPIN, 4, resistor_text);
0348 static SOC_ENUM_SINGLE_DECL(in3l_lpga_p_enum, AIC32X4_LMICPGAPIN, 2, resistor_text);
0349 static SOC_ENUM_SINGLE_DECL(in1r_lpga_p_enum, AIC32X4_LMICPGAPIN, 0, resistor_text);
0350 
0351 static SOC_ENUM_SINGLE_DECL(cml_lpga_n_enum, AIC32X4_LMICPGANIN, 6, resistor_text);
0352 static SOC_ENUM_SINGLE_DECL(in2r_lpga_n_enum, AIC32X4_LMICPGANIN, 4, resistor_text);
0353 static SOC_ENUM_SINGLE_DECL(in3r_lpga_n_enum, AIC32X4_LMICPGANIN, 2, resistor_text);
0354 
0355 static const struct snd_kcontrol_new in1l_to_lmixer_controls[] = {
0356     SOC_DAPM_ENUM("IN1_L L+ Switch", in1l_lpga_p_enum),
0357 };
0358 static const struct snd_kcontrol_new in2l_to_lmixer_controls[] = {
0359     SOC_DAPM_ENUM("IN2_L L+ Switch", in2l_lpga_p_enum),
0360 };
0361 static const struct snd_kcontrol_new in3l_to_lmixer_controls[] = {
0362     SOC_DAPM_ENUM("IN3_L L+ Switch", in3l_lpga_p_enum),
0363 };
0364 static const struct snd_kcontrol_new in1r_to_lmixer_controls[] = {
0365     SOC_DAPM_ENUM("IN1_R L+ Switch", in1r_lpga_p_enum),
0366 };
0367 static const struct snd_kcontrol_new cml_to_lmixer_controls[] = {
0368     SOC_DAPM_ENUM("CM_L L- Switch", cml_lpga_n_enum),
0369 };
0370 static const struct snd_kcontrol_new in2r_to_lmixer_controls[] = {
0371     SOC_DAPM_ENUM("IN2_R L- Switch", in2r_lpga_n_enum),
0372 };
0373 static const struct snd_kcontrol_new in3r_to_lmixer_controls[] = {
0374     SOC_DAPM_ENUM("IN3_R L- Switch", in3r_lpga_n_enum),
0375 };
0376 
0377 /*  Right mixer pins */
0378 static SOC_ENUM_SINGLE_DECL(in1r_rpga_p_enum, AIC32X4_RMICPGAPIN, 6, resistor_text);
0379 static SOC_ENUM_SINGLE_DECL(in2r_rpga_p_enum, AIC32X4_RMICPGAPIN, 4, resistor_text);
0380 static SOC_ENUM_SINGLE_DECL(in3r_rpga_p_enum, AIC32X4_RMICPGAPIN, 2, resistor_text);
0381 static SOC_ENUM_SINGLE_DECL(in2l_rpga_p_enum, AIC32X4_RMICPGAPIN, 0, resistor_text);
0382 static SOC_ENUM_SINGLE_DECL(cmr_rpga_n_enum, AIC32X4_RMICPGANIN, 6, resistor_text);
0383 static SOC_ENUM_SINGLE_DECL(in1l_rpga_n_enum, AIC32X4_RMICPGANIN, 4, resistor_text);
0384 static SOC_ENUM_SINGLE_DECL(in3l_rpga_n_enum, AIC32X4_RMICPGANIN, 2, resistor_text);
0385 
0386 static const struct snd_kcontrol_new in1r_to_rmixer_controls[] = {
0387     SOC_DAPM_ENUM("IN1_R R+ Switch", in1r_rpga_p_enum),
0388 };
0389 static const struct snd_kcontrol_new in2r_to_rmixer_controls[] = {
0390     SOC_DAPM_ENUM("IN2_R R+ Switch", in2r_rpga_p_enum),
0391 };
0392 static const struct snd_kcontrol_new in3r_to_rmixer_controls[] = {
0393     SOC_DAPM_ENUM("IN3_R R+ Switch", in3r_rpga_p_enum),
0394 };
0395 static const struct snd_kcontrol_new in2l_to_rmixer_controls[] = {
0396     SOC_DAPM_ENUM("IN2_L R+ Switch", in2l_rpga_p_enum),
0397 };
0398 static const struct snd_kcontrol_new cmr_to_rmixer_controls[] = {
0399     SOC_DAPM_ENUM("CM_R R- Switch", cmr_rpga_n_enum),
0400 };
0401 static const struct snd_kcontrol_new in1l_to_rmixer_controls[] = {
0402     SOC_DAPM_ENUM("IN1_L R- Switch", in1l_rpga_n_enum),
0403 };
0404 static const struct snd_kcontrol_new in3l_to_rmixer_controls[] = {
0405     SOC_DAPM_ENUM("IN3_L R- Switch", in3l_rpga_n_enum),
0406 };
0407 
0408 static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = {
0409     SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0),
0410     SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0,
0411                &hpl_output_mixer_controls[0],
0412                ARRAY_SIZE(hpl_output_mixer_controls)),
0413     SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0),
0414 
0415     SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0,
0416                &lol_output_mixer_controls[0],
0417                ARRAY_SIZE(lol_output_mixer_controls)),
0418     SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0),
0419 
0420     SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0),
0421     SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0,
0422                &hpr_output_mixer_controls[0],
0423                ARRAY_SIZE(hpr_output_mixer_controls)),
0424     SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0),
0425     SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0,
0426                &lor_output_mixer_controls[0],
0427                ARRAY_SIZE(lor_output_mixer_controls)),
0428     SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0),
0429 
0430     SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0),
0431     SND_SOC_DAPM_MUX("IN1_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
0432             in1r_to_rmixer_controls),
0433     SND_SOC_DAPM_MUX("IN2_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
0434             in2r_to_rmixer_controls),
0435     SND_SOC_DAPM_MUX("IN3_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
0436             in3r_to_rmixer_controls),
0437     SND_SOC_DAPM_MUX("IN2_L to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
0438             in2l_to_rmixer_controls),
0439     SND_SOC_DAPM_MUX("CM_R to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
0440             cmr_to_rmixer_controls),
0441     SND_SOC_DAPM_MUX("IN1_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
0442             in1l_to_rmixer_controls),
0443     SND_SOC_DAPM_MUX("IN3_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
0444             in3l_to_rmixer_controls),
0445 
0446     SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0),
0447     SND_SOC_DAPM_MUX("IN1_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
0448             in1l_to_lmixer_controls),
0449     SND_SOC_DAPM_MUX("IN2_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
0450             in2l_to_lmixer_controls),
0451     SND_SOC_DAPM_MUX("IN3_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
0452             in3l_to_lmixer_controls),
0453     SND_SOC_DAPM_MUX("IN1_R to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
0454             in1r_to_lmixer_controls),
0455     SND_SOC_DAPM_MUX("CM_L to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
0456             cml_to_lmixer_controls),
0457     SND_SOC_DAPM_MUX("IN2_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
0458             in2r_to_lmixer_controls),
0459     SND_SOC_DAPM_MUX("IN3_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
0460             in3r_to_lmixer_controls),
0461 
0462     SND_SOC_DAPM_SUPPLY("Mic Bias", AIC32X4_MICBIAS, 6, 0, mic_bias_event,
0463             SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
0464 
0465     SND_SOC_DAPM_POST("ADC Reset", aic32x4_reset_adc),
0466 
0467     SND_SOC_DAPM_OUTPUT("HPL"),
0468     SND_SOC_DAPM_OUTPUT("HPR"),
0469     SND_SOC_DAPM_OUTPUT("LOL"),
0470     SND_SOC_DAPM_OUTPUT("LOR"),
0471     SND_SOC_DAPM_INPUT("IN1_L"),
0472     SND_SOC_DAPM_INPUT("IN1_R"),
0473     SND_SOC_DAPM_INPUT("IN2_L"),
0474     SND_SOC_DAPM_INPUT("IN2_R"),
0475     SND_SOC_DAPM_INPUT("IN3_L"),
0476     SND_SOC_DAPM_INPUT("IN3_R"),
0477     SND_SOC_DAPM_INPUT("CM_L"),
0478     SND_SOC_DAPM_INPUT("CM_R"),
0479 };
0480 
0481 static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = {
0482     /* Left Output */
0483     {"HPL Output Mixer", "L_DAC Switch", "Left DAC"},
0484     {"HPL Output Mixer", "IN1_L Switch", "IN1_L"},
0485 
0486     {"HPL Power", NULL, "HPL Output Mixer"},
0487     {"HPL", NULL, "HPL Power"},
0488 
0489     {"LOL Output Mixer", "L_DAC Switch", "Left DAC"},
0490 
0491     {"LOL Power", NULL, "LOL Output Mixer"},
0492     {"LOL", NULL, "LOL Power"},
0493 
0494     /* Right Output */
0495     {"HPR Output Mixer", "R_DAC Switch", "Right DAC"},
0496     {"HPR Output Mixer", "IN1_R Switch", "IN1_R"},
0497 
0498     {"HPR Power", NULL, "HPR Output Mixer"},
0499     {"HPR", NULL, "HPR Power"},
0500 
0501     {"LOR Output Mixer", "R_DAC Switch", "Right DAC"},
0502 
0503     {"LOR Power", NULL, "LOR Output Mixer"},
0504     {"LOR", NULL, "LOR Power"},
0505 
0506     /* Right Input */
0507     {"Right ADC", NULL, "IN1_R to Right Mixer Positive Resistor"},
0508     {"IN1_R to Right Mixer Positive Resistor", "10 kOhm", "IN1_R"},
0509     {"IN1_R to Right Mixer Positive Resistor", "20 kOhm", "IN1_R"},
0510     {"IN1_R to Right Mixer Positive Resistor", "40 kOhm", "IN1_R"},
0511 
0512     {"Right ADC", NULL, "IN2_R to Right Mixer Positive Resistor"},
0513     {"IN2_R to Right Mixer Positive Resistor", "10 kOhm", "IN2_R"},
0514     {"IN2_R to Right Mixer Positive Resistor", "20 kOhm", "IN2_R"},
0515     {"IN2_R to Right Mixer Positive Resistor", "40 kOhm", "IN2_R"},
0516 
0517     {"Right ADC", NULL, "IN3_R to Right Mixer Positive Resistor"},
0518     {"IN3_R to Right Mixer Positive Resistor", "10 kOhm", "IN3_R"},
0519     {"IN3_R to Right Mixer Positive Resistor", "20 kOhm", "IN3_R"},
0520     {"IN3_R to Right Mixer Positive Resistor", "40 kOhm", "IN3_R"},
0521 
0522     {"Right ADC", NULL, "IN2_L to Right Mixer Positive Resistor"},
0523     {"IN2_L to Right Mixer Positive Resistor", "10 kOhm", "IN2_L"},
0524     {"IN2_L to Right Mixer Positive Resistor", "20 kOhm", "IN2_L"},
0525     {"IN2_L to Right Mixer Positive Resistor", "40 kOhm", "IN2_L"},
0526 
0527     {"Right ADC", NULL, "CM_R to Right Mixer Negative Resistor"},
0528     {"CM_R to Right Mixer Negative Resistor", "10 kOhm", "CM_R"},
0529     {"CM_R to Right Mixer Negative Resistor", "20 kOhm", "CM_R"},
0530     {"CM_R to Right Mixer Negative Resistor", "40 kOhm", "CM_R"},
0531 
0532     {"Right ADC", NULL, "IN1_L to Right Mixer Negative Resistor"},
0533     {"IN1_L to Right Mixer Negative Resistor", "10 kOhm", "IN1_L"},
0534     {"IN1_L to Right Mixer Negative Resistor", "20 kOhm", "IN1_L"},
0535     {"IN1_L to Right Mixer Negative Resistor", "40 kOhm", "IN1_L"},
0536 
0537     {"Right ADC", NULL, "IN3_L to Right Mixer Negative Resistor"},
0538     {"IN3_L to Right Mixer Negative Resistor", "10 kOhm", "IN3_L"},
0539     {"IN3_L to Right Mixer Negative Resistor", "20 kOhm", "IN3_L"},
0540     {"IN3_L to Right Mixer Negative Resistor", "40 kOhm", "IN3_L"},
0541 
0542     /* Left Input */
0543     {"Left ADC", NULL, "IN1_L to Left Mixer Positive Resistor"},
0544     {"IN1_L to Left Mixer Positive Resistor", "10 kOhm", "IN1_L"},
0545     {"IN1_L to Left Mixer Positive Resistor", "20 kOhm", "IN1_L"},
0546     {"IN1_L to Left Mixer Positive Resistor", "40 kOhm", "IN1_L"},
0547 
0548     {"Left ADC", NULL, "IN2_L to Left Mixer Positive Resistor"},
0549     {"IN2_L to Left Mixer Positive Resistor", "10 kOhm", "IN2_L"},
0550     {"IN2_L to Left Mixer Positive Resistor", "20 kOhm", "IN2_L"},
0551     {"IN2_L to Left Mixer Positive Resistor", "40 kOhm", "IN2_L"},
0552 
0553     {"Left ADC", NULL, "IN3_L to Left Mixer Positive Resistor"},
0554     {"IN3_L to Left Mixer Positive Resistor", "10 kOhm", "IN3_L"},
0555     {"IN3_L to Left Mixer Positive Resistor", "20 kOhm", "IN3_L"},
0556     {"IN3_L to Left Mixer Positive Resistor", "40 kOhm", "IN3_L"},
0557 
0558     {"Left ADC", NULL, "IN1_R to Left Mixer Positive Resistor"},
0559     {"IN1_R to Left Mixer Positive Resistor", "10 kOhm", "IN1_R"},
0560     {"IN1_R to Left Mixer Positive Resistor", "20 kOhm", "IN1_R"},
0561     {"IN1_R to Left Mixer Positive Resistor", "40 kOhm", "IN1_R"},
0562 
0563     {"Left ADC", NULL, "CM_L to Left Mixer Negative Resistor"},
0564     {"CM_L to Left Mixer Negative Resistor", "10 kOhm", "CM_L"},
0565     {"CM_L to Left Mixer Negative Resistor", "20 kOhm", "CM_L"},
0566     {"CM_L to Left Mixer Negative Resistor", "40 kOhm", "CM_L"},
0567 
0568     {"Left ADC", NULL, "IN2_R to Left Mixer Negative Resistor"},
0569     {"IN2_R to Left Mixer Negative Resistor", "10 kOhm", "IN2_R"},
0570     {"IN2_R to Left Mixer Negative Resistor", "20 kOhm", "IN2_R"},
0571     {"IN2_R to Left Mixer Negative Resistor", "40 kOhm", "IN2_R"},
0572 
0573     {"Left ADC", NULL, "IN3_R to Left Mixer Negative Resistor"},
0574     {"IN3_R to Left Mixer Negative Resistor", "10 kOhm", "IN3_R"},
0575     {"IN3_R to Left Mixer Negative Resistor", "20 kOhm", "IN3_R"},
0576     {"IN3_R to Left Mixer Negative Resistor", "40 kOhm", "IN3_R"},
0577 };
0578 
0579 static const struct regmap_range_cfg aic32x4_regmap_pages[] = {
0580     {
0581         .selector_reg = 0,
0582         .selector_mask  = 0xff,
0583         .window_start = 0,
0584         .window_len = 128,
0585         .range_min = 0,
0586         .range_max = AIC32X4_REFPOWERUP,
0587     },
0588 };
0589 
0590 const struct regmap_config aic32x4_regmap_config = {
0591     .max_register = AIC32X4_REFPOWERUP,
0592     .ranges = aic32x4_regmap_pages,
0593     .num_ranges = ARRAY_SIZE(aic32x4_regmap_pages),
0594 };
0595 EXPORT_SYMBOL(aic32x4_regmap_config);
0596 
0597 static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai,
0598                   int clk_id, unsigned int freq, int dir)
0599 {
0600     struct snd_soc_component *component = codec_dai->component;
0601     struct clk *mclk;
0602     struct clk *pll;
0603 
0604     pll = devm_clk_get(component->dev, "pll");
0605     if (IS_ERR(pll))
0606         return PTR_ERR(pll);
0607 
0608     mclk = clk_get_parent(pll);
0609 
0610     return clk_set_rate(mclk, freq);
0611 }
0612 
0613 static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
0614 {
0615     struct snd_soc_component *component = codec_dai->component;
0616     struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
0617     u8 iface_reg_1 = 0;
0618     u8 iface_reg_2 = 0;
0619     u8 iface_reg_3 = 0;
0620 
0621     switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0622     case SND_SOC_DAIFMT_CBP_CFP:
0623         iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER;
0624         break;
0625     case SND_SOC_DAIFMT_CBC_CFC:
0626         break;
0627     default:
0628         printk(KERN_ERR "aic32x4: invalid clock provider\n");
0629         return -EINVAL;
0630     }
0631 
0632     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0633     case SND_SOC_DAIFMT_I2S:
0634         break;
0635     case SND_SOC_DAIFMT_DSP_A:
0636         iface_reg_1 |= (AIC32X4_DSP_MODE <<
0637                 AIC32X4_IFACE1_DATATYPE_SHIFT);
0638         iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */
0639         iface_reg_2 = 0x01; /* add offset 1 */
0640         break;
0641     case SND_SOC_DAIFMT_DSP_B:
0642         iface_reg_1 |= (AIC32X4_DSP_MODE <<
0643                 AIC32X4_IFACE1_DATATYPE_SHIFT);
0644         iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */
0645         break;
0646     case SND_SOC_DAIFMT_RIGHT_J:
0647         iface_reg_1 |= (AIC32X4_RIGHT_JUSTIFIED_MODE <<
0648                 AIC32X4_IFACE1_DATATYPE_SHIFT);
0649         break;
0650     case SND_SOC_DAIFMT_LEFT_J:
0651         iface_reg_1 |= (AIC32X4_LEFT_JUSTIFIED_MODE <<
0652                 AIC32X4_IFACE1_DATATYPE_SHIFT);
0653         break;
0654     default:
0655         printk(KERN_ERR "aic32x4: invalid DAI interface format\n");
0656         return -EINVAL;
0657     }
0658 
0659     aic32x4->fmt = fmt;
0660 
0661     snd_soc_component_update_bits(component, AIC32X4_IFACE1,
0662                 AIC32X4_IFACE1_DATATYPE_MASK |
0663                 AIC32X4_IFACE1_MASTER_MASK, iface_reg_1);
0664     snd_soc_component_update_bits(component, AIC32X4_IFACE2,
0665                 AIC32X4_DATA_OFFSET_MASK, iface_reg_2);
0666     snd_soc_component_update_bits(component, AIC32X4_IFACE3,
0667                 AIC32X4_BCLKINV_MASK, iface_reg_3);
0668 
0669     return 0;
0670 }
0671 
0672 static int aic32x4_set_aosr(struct snd_soc_component *component, u8 aosr)
0673 {
0674     return snd_soc_component_write(component, AIC32X4_AOSR, aosr);
0675 }
0676 
0677 static int aic32x4_set_dosr(struct snd_soc_component *component, u16 dosr)
0678 {
0679     snd_soc_component_write(component, AIC32X4_DOSRMSB, dosr >> 8);
0680     snd_soc_component_write(component, AIC32X4_DOSRLSB,
0681               (dosr & 0xff));
0682 
0683     return 0;
0684 }
0685 
0686 static int aic32x4_set_processing_blocks(struct snd_soc_component *component,
0687                         u8 r_block, u8 p_block)
0688 {
0689     struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
0690 
0691     if (aic32x4->type == AIC32X4_TYPE_TAS2505) {
0692         if (r_block || p_block > 3)
0693             return -EINVAL;
0694 
0695         snd_soc_component_write(component, AIC32X4_DACSPB, p_block);
0696     } else { /* AIC32x4 */
0697         if (r_block > 18 || p_block > 25)
0698             return -EINVAL;
0699 
0700         snd_soc_component_write(component, AIC32X4_ADCSPB, r_block);
0701         snd_soc_component_write(component, AIC32X4_DACSPB, p_block);
0702     }
0703 
0704     return 0;
0705 }
0706 
0707 static int aic32x4_setup_clocks(struct snd_soc_component *component,
0708                 unsigned int sample_rate, unsigned int channels,
0709                 unsigned int bit_depth)
0710 {
0711     struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
0712     u8 aosr;
0713     u16 dosr;
0714     u8 adc_resource_class, dac_resource_class;
0715     u8 madc, nadc, mdac, ndac, max_nadc, min_mdac, max_ndac;
0716     u8 dosr_increment;
0717     u16 max_dosr, min_dosr;
0718     unsigned long adc_clock_rate, dac_clock_rate;
0719     int ret;
0720 
0721     static struct clk_bulk_data clocks[] = {
0722         { .id = "pll" },
0723         { .id = "nadc" },
0724         { .id = "madc" },
0725         { .id = "ndac" },
0726         { .id = "mdac" },
0727         { .id = "bdiv" },
0728     };
0729     ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
0730     if (ret)
0731         return ret;
0732 
0733     if (sample_rate <= 48000) {
0734         aosr = 128;
0735         adc_resource_class = 6;
0736         dac_resource_class = 8;
0737         dosr_increment = 8;
0738         if (aic32x4->type == AIC32X4_TYPE_TAS2505)
0739             aic32x4_set_processing_blocks(component, 0, 1);
0740         else
0741             aic32x4_set_processing_blocks(component, 1, 1);
0742     } else if (sample_rate <= 96000) {
0743         aosr = 64;
0744         adc_resource_class = 6;
0745         dac_resource_class = 8;
0746         dosr_increment = 4;
0747         if (aic32x4->type == AIC32X4_TYPE_TAS2505)
0748             aic32x4_set_processing_blocks(component, 0, 1);
0749         else
0750             aic32x4_set_processing_blocks(component, 1, 9);
0751     } else if (sample_rate == 192000) {
0752         aosr = 32;
0753         adc_resource_class = 3;
0754         dac_resource_class = 4;
0755         dosr_increment = 2;
0756         if (aic32x4->type == AIC32X4_TYPE_TAS2505)
0757             aic32x4_set_processing_blocks(component, 0, 1);
0758         else
0759             aic32x4_set_processing_blocks(component, 13, 19);
0760     } else {
0761         dev_err(component->dev, "Sampling rate not supported\n");
0762         return -EINVAL;
0763     }
0764 
0765     /* PCM over I2S is always 2-channel */
0766     if ((aic32x4->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_I2S)
0767         channels = 2;
0768 
0769     madc = DIV_ROUND_UP((32 * adc_resource_class), aosr);
0770     max_dosr = (AIC32X4_MAX_DOSR_FREQ / sample_rate / dosr_increment) *
0771             dosr_increment;
0772     min_dosr = (AIC32X4_MIN_DOSR_FREQ / sample_rate / dosr_increment) *
0773             dosr_increment;
0774     max_nadc = AIC32X4_MAX_CODEC_CLKIN_FREQ / (madc * aosr * sample_rate);
0775 
0776     for (nadc = max_nadc; nadc > 0; --nadc) {
0777         adc_clock_rate = nadc * madc * aosr * sample_rate;
0778         for (dosr = max_dosr; dosr >= min_dosr;
0779                 dosr -= dosr_increment) {
0780             min_mdac = DIV_ROUND_UP((32 * dac_resource_class), dosr);
0781             max_ndac = AIC32X4_MAX_CODEC_CLKIN_FREQ /
0782                     (min_mdac * dosr * sample_rate);
0783             for (mdac = min_mdac; mdac <= 128; ++mdac) {
0784                 for (ndac = max_ndac; ndac > 0; --ndac) {
0785                     dac_clock_rate = ndac * mdac * dosr *
0786                             sample_rate;
0787                     if (dac_clock_rate == adc_clock_rate) {
0788                         if (clk_round_rate(clocks[0].clk, dac_clock_rate) == 0)
0789                             continue;
0790 
0791                         clk_set_rate(clocks[0].clk,
0792                             dac_clock_rate);
0793 
0794                         clk_set_rate(clocks[1].clk,
0795                             sample_rate * aosr *
0796                             madc);
0797                         clk_set_rate(clocks[2].clk,
0798                             sample_rate * aosr);
0799                         aic32x4_set_aosr(component,
0800                             aosr);
0801 
0802                         clk_set_rate(clocks[3].clk,
0803                             sample_rate * dosr *
0804                             mdac);
0805                         clk_set_rate(clocks[4].clk,
0806                             sample_rate * dosr);
0807                         aic32x4_set_dosr(component,
0808                             dosr);
0809 
0810                         clk_set_rate(clocks[5].clk,
0811                             sample_rate * channels *
0812                             bit_depth);
0813 
0814                         return 0;
0815                     }
0816                 }
0817             }
0818         }
0819     }
0820 
0821     dev_err(component->dev,
0822         "Could not set clocks to support sample rate.\n");
0823     return -EINVAL;
0824 }
0825 
0826 static int aic32x4_hw_params(struct snd_pcm_substream *substream,
0827                  struct snd_pcm_hw_params *params,
0828                  struct snd_soc_dai *dai)
0829 {
0830     struct snd_soc_component *component = dai->component;
0831     struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
0832     u8 iface1_reg = 0;
0833     u8 dacsetup_reg = 0;
0834 
0835     aic32x4_setup_clocks(component, params_rate(params),
0836                  params_channels(params),
0837                  params_physical_width(params));
0838 
0839     switch (params_physical_width(params)) {
0840     case 16:
0841         iface1_reg |= (AIC32X4_WORD_LEN_16BITS <<
0842                    AIC32X4_IFACE1_DATALEN_SHIFT);
0843         break;
0844     case 20:
0845         iface1_reg |= (AIC32X4_WORD_LEN_20BITS <<
0846                    AIC32X4_IFACE1_DATALEN_SHIFT);
0847         break;
0848     case 24:
0849         iface1_reg |= (AIC32X4_WORD_LEN_24BITS <<
0850                    AIC32X4_IFACE1_DATALEN_SHIFT);
0851         break;
0852     case 32:
0853         iface1_reg |= (AIC32X4_WORD_LEN_32BITS <<
0854                    AIC32X4_IFACE1_DATALEN_SHIFT);
0855         break;
0856     }
0857     snd_soc_component_update_bits(component, AIC32X4_IFACE1,
0858                 AIC32X4_IFACE1_DATALEN_MASK, iface1_reg);
0859 
0860     if (params_channels(params) == 1) {
0861         dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN;
0862     } else {
0863         if (aic32x4->swapdacs)
0864             dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2RCHN;
0865         else
0866             dacsetup_reg = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN;
0867     }
0868     snd_soc_component_update_bits(component, AIC32X4_DACSETUP,
0869                 AIC32X4_DAC_CHAN_MASK, dacsetup_reg);
0870 
0871     return 0;
0872 }
0873 
0874 static int aic32x4_mute(struct snd_soc_dai *dai, int mute, int direction)
0875 {
0876     struct snd_soc_component *component = dai->component;
0877 
0878     snd_soc_component_update_bits(component, AIC32X4_DACMUTE,
0879                 AIC32X4_MUTEON, mute ? AIC32X4_MUTEON : 0);
0880 
0881     return 0;
0882 }
0883 
0884 static int aic32x4_set_bias_level(struct snd_soc_component *component,
0885                   enum snd_soc_bias_level level)
0886 {
0887     int ret;
0888 
0889     static struct clk_bulk_data clocks[] = {
0890         { .id = "madc" },
0891         { .id = "mdac" },
0892         { .id = "bdiv" },
0893     };
0894 
0895     ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
0896     if (ret)
0897         return ret;
0898 
0899     switch (level) {
0900     case SND_SOC_BIAS_ON:
0901         ret = clk_bulk_prepare_enable(ARRAY_SIZE(clocks), clocks);
0902         if (ret) {
0903             dev_err(component->dev, "Failed to enable clocks\n");
0904             return ret;
0905         }
0906         break;
0907     case SND_SOC_BIAS_PREPARE:
0908         break;
0909     case SND_SOC_BIAS_STANDBY:
0910         /* Initial cold start */
0911         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
0912             break;
0913 
0914         clk_bulk_disable_unprepare(ARRAY_SIZE(clocks), clocks);
0915         break;
0916     case SND_SOC_BIAS_OFF:
0917         break;
0918     }
0919     return 0;
0920 }
0921 
0922 #define AIC32X4_RATES   SNDRV_PCM_RATE_8000_192000
0923 #define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
0924              | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_3LE \
0925              | SNDRV_PCM_FMTBIT_S32_LE)
0926 
0927 static const struct snd_soc_dai_ops aic32x4_ops = {
0928     .hw_params = aic32x4_hw_params,
0929     .mute_stream = aic32x4_mute,
0930     .set_fmt = aic32x4_set_dai_fmt,
0931     .set_sysclk = aic32x4_set_dai_sysclk,
0932     .no_capture_mute = 1,
0933 };
0934 
0935 static struct snd_soc_dai_driver aic32x4_dai = {
0936     .name = "tlv320aic32x4-hifi",
0937     .playback = {
0938              .stream_name = "Playback",
0939              .channels_min = 1,
0940              .channels_max = 2,
0941              .rates = AIC32X4_RATES,
0942              .formats = AIC32X4_FORMATS,},
0943     .capture = {
0944             .stream_name = "Capture",
0945             .channels_min = 1,
0946             .channels_max = 8,
0947             .rates = AIC32X4_RATES,
0948             .formats = AIC32X4_FORMATS,},
0949     .ops = &aic32x4_ops,
0950     .symmetric_rate = 1,
0951 };
0952 
0953 static void aic32x4_setup_gpios(struct snd_soc_component *component)
0954 {
0955     struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
0956 
0957     /* setup GPIO functions */
0958     /* MFP1 */
0959     if (aic32x4->setup->gpio_func[0] != AIC32X4_MFPX_DEFAULT_VALUE) {
0960         snd_soc_component_write(component, AIC32X4_DINCTL,
0961               aic32x4->setup->gpio_func[0]);
0962         snd_soc_add_component_controls(component, aic32x4_mfp1,
0963             ARRAY_SIZE(aic32x4_mfp1));
0964     }
0965 
0966     /* MFP2 */
0967     if (aic32x4->setup->gpio_func[1] != AIC32X4_MFPX_DEFAULT_VALUE) {
0968         snd_soc_component_write(component, AIC32X4_DOUTCTL,
0969               aic32x4->setup->gpio_func[1]);
0970         snd_soc_add_component_controls(component, aic32x4_mfp2,
0971             ARRAY_SIZE(aic32x4_mfp2));
0972     }
0973 
0974     /* MFP3 */
0975     if (aic32x4->setup->gpio_func[2] != AIC32X4_MFPX_DEFAULT_VALUE) {
0976         snd_soc_component_write(component, AIC32X4_SCLKCTL,
0977               aic32x4->setup->gpio_func[2]);
0978         snd_soc_add_component_controls(component, aic32x4_mfp3,
0979             ARRAY_SIZE(aic32x4_mfp3));
0980     }
0981 
0982     /* MFP4 */
0983     if (aic32x4->setup->gpio_func[3] != AIC32X4_MFPX_DEFAULT_VALUE) {
0984         snd_soc_component_write(component, AIC32X4_MISOCTL,
0985               aic32x4->setup->gpio_func[3]);
0986         snd_soc_add_component_controls(component, aic32x4_mfp4,
0987             ARRAY_SIZE(aic32x4_mfp4));
0988     }
0989 
0990     /* MFP5 */
0991     if (aic32x4->setup->gpio_func[4] != AIC32X4_MFPX_DEFAULT_VALUE) {
0992         snd_soc_component_write(component, AIC32X4_GPIOCTL,
0993               aic32x4->setup->gpio_func[4]);
0994         snd_soc_add_component_controls(component, aic32x4_mfp5,
0995             ARRAY_SIZE(aic32x4_mfp5));
0996     }
0997 }
0998 
0999 static int aic32x4_component_probe(struct snd_soc_component *component)
1000 {
1001     struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
1002     u32 tmp_reg;
1003     int ret;
1004 
1005     static struct clk_bulk_data clocks[] = {
1006         { .id = "codec_clkin" },
1007         { .id = "pll" },
1008         { .id = "bdiv" },
1009         { .id = "mdac" },
1010     };
1011 
1012     ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
1013     if (ret)
1014         return ret;
1015 
1016     if (aic32x4->setup)
1017         aic32x4_setup_gpios(component);
1018 
1019     clk_set_parent(clocks[0].clk, clocks[1].clk);
1020     clk_set_parent(clocks[2].clk, clocks[3].clk);
1021 
1022     /* Power platform configuration */
1023     if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {
1024         snd_soc_component_write(component, AIC32X4_MICBIAS,
1025                 AIC32X4_MICBIAS_LDOIN | AIC32X4_MICBIAS_2075V);
1026     }
1027     if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE)
1028         snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
1029 
1030     tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ?
1031             AIC32X4_LDOCTLEN : 0;
1032     snd_soc_component_write(component, AIC32X4_LDOCTL, tmp_reg);
1033 
1034     tmp_reg = snd_soc_component_read(component, AIC32X4_CMMODE);
1035     if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36)
1036         tmp_reg |= AIC32X4_LDOIN_18_36;
1037     if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED)
1038         tmp_reg |= AIC32X4_LDOIN2HP;
1039     snd_soc_component_write(component, AIC32X4_CMMODE, tmp_reg);
1040 
1041     /* Mic PGA routing */
1042     if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K)
1043         snd_soc_component_write(component, AIC32X4_LMICPGANIN,
1044                 AIC32X4_LMICPGANIN_IN2R_10K);
1045     else
1046         snd_soc_component_write(component, AIC32X4_LMICPGANIN,
1047                 AIC32X4_LMICPGANIN_CM1L_10K);
1048     if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K)
1049         snd_soc_component_write(component, AIC32X4_RMICPGANIN,
1050                 AIC32X4_RMICPGANIN_IN1L_10K);
1051     else
1052         snd_soc_component_write(component, AIC32X4_RMICPGANIN,
1053                 AIC32X4_RMICPGANIN_CM1R_10K);
1054 
1055     /*
1056      * Workaround: for an unknown reason, the ADC needs to be powered up
1057      * and down for the first capture to work properly. It seems related to
1058      * a HW BUG or some kind of behavior not documented in the datasheet.
1059      */
1060     tmp_reg = snd_soc_component_read(component, AIC32X4_ADCSETUP);
1061     snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg |
1062                 AIC32X4_LADC_EN | AIC32X4_RADC_EN);
1063     snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg);
1064 
1065     /*
1066      * Enable the fast charging feature and ensure the needed 40ms ellapsed
1067      * before using the analog circuits.
1068      */
1069     snd_soc_component_write(component, AIC32X4_REFPOWERUP,
1070                 AIC32X4_REFPOWERUP_40MS);
1071     msleep(40);
1072 
1073     return 0;
1074 }
1075 
1076 static const struct snd_soc_component_driver soc_component_dev_aic32x4 = {
1077     .probe          = aic32x4_component_probe,
1078     .set_bias_level     = aic32x4_set_bias_level,
1079     .controls       = aic32x4_snd_controls,
1080     .num_controls       = ARRAY_SIZE(aic32x4_snd_controls),
1081     .dapm_widgets       = aic32x4_dapm_widgets,
1082     .num_dapm_widgets   = ARRAY_SIZE(aic32x4_dapm_widgets),
1083     .dapm_routes        = aic32x4_dapm_routes,
1084     .num_dapm_routes    = ARRAY_SIZE(aic32x4_dapm_routes),
1085     .suspend_bias_off   = 1,
1086     .idle_bias_on       = 1,
1087     .use_pmdown_time    = 1,
1088     .endianness     = 1,
1089 };
1090 
1091 static const struct snd_kcontrol_new aic32x4_tas2505_snd_controls[] = {
1092     SOC_SINGLE_S8_TLV("PCM Playback Volume",
1093               AIC32X4_LDACVOL, -0x7f, 0x30, tlv_pcm),
1094     SOC_ENUM("DAC Playback PowerTune Switch", l_ptm_enum),
1095 
1096     SOC_SINGLE_TLV("HP Driver Gain Volume",
1097             AIC32X4_HPLGAIN, 0, 0x74, 1, tlv_tas_driver_gain),
1098     SOC_SINGLE("HP DAC Playback Switch", AIC32X4_HPLGAIN, 6, 1, 1),
1099 
1100     SOC_SINGLE_TLV("Speaker Driver Playback Volume",
1101             TAS2505_SPKVOL1, 0, 0x74, 1, tlv_tas_driver_gain),
1102     SOC_SINGLE_TLV("Speaker Amplifier Playback Volume",
1103             TAS2505_SPKVOL2, 4, 5, 0, tlv_amp_vol),
1104 
1105     SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0),
1106 };
1107 
1108 static const struct snd_kcontrol_new hp_output_mixer_controls[] = {
1109     SOC_DAPM_SINGLE("DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0),
1110 };
1111 
1112 static const struct snd_soc_dapm_widget aic32x4_tas2505_dapm_widgets[] = {
1113     SND_SOC_DAPM_DAC("DAC", "Playback", AIC32X4_DACSETUP, 7, 0),
1114     SND_SOC_DAPM_MIXER("HP Output Mixer", SND_SOC_NOPM, 0, 0,
1115                &hp_output_mixer_controls[0],
1116                ARRAY_SIZE(hp_output_mixer_controls)),
1117     SND_SOC_DAPM_PGA("HP Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0),
1118 
1119     SND_SOC_DAPM_PGA("Speaker Driver", TAS2505_SPK, 1, 0, NULL, 0),
1120 
1121     SND_SOC_DAPM_OUTPUT("HP"),
1122     SND_SOC_DAPM_OUTPUT("Speaker"),
1123 };
1124 
1125 static const struct snd_soc_dapm_route aic32x4_tas2505_dapm_routes[] = {
1126     /* Left Output */
1127     {"HP Output Mixer", "DAC Switch", "DAC"},
1128 
1129     {"HP Power", NULL, "HP Output Mixer"},
1130     {"HP", NULL, "HP Power"},
1131 
1132     {"Speaker Driver", NULL, "DAC"},
1133     {"Speaker", NULL, "Speaker Driver"},
1134 };
1135 
1136 static struct snd_soc_dai_driver aic32x4_tas2505_dai = {
1137     .name = "tas2505-hifi",
1138     .playback = {
1139              .stream_name = "Playback",
1140              .channels_min = 1,
1141              .channels_max = 2,
1142              .rates = SNDRV_PCM_RATE_8000_96000,
1143              .formats = AIC32X4_FORMATS,},
1144     .ops = &aic32x4_ops,
1145     .symmetric_rate = 1,
1146 };
1147 
1148 static int aic32x4_tas2505_component_probe(struct snd_soc_component *component)
1149 {
1150     struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
1151     u32 tmp_reg;
1152     int ret;
1153 
1154     static struct clk_bulk_data clocks[] = {
1155         { .id = "codec_clkin" },
1156         { .id = "pll" },
1157         { .id = "bdiv" },
1158         { .id = "mdac" },
1159     };
1160 
1161     ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
1162     if (ret)
1163         return ret;
1164 
1165     if (aic32x4->setup)
1166         aic32x4_setup_gpios(component);
1167 
1168     clk_set_parent(clocks[0].clk, clocks[1].clk);
1169     clk_set_parent(clocks[2].clk, clocks[3].clk);
1170 
1171     /* Power platform configuration */
1172     if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE)
1173         snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
1174 
1175     tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ?
1176             AIC32X4_LDOCTLEN : 0;
1177     snd_soc_component_write(component, AIC32X4_LDOCTL, tmp_reg);
1178 
1179     tmp_reg = snd_soc_component_read(component, AIC32X4_CMMODE);
1180     if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36)
1181         tmp_reg |= AIC32X4_LDOIN_18_36;
1182     if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED)
1183         tmp_reg |= AIC32X4_LDOIN2HP;
1184     snd_soc_component_write(component, AIC32X4_CMMODE, tmp_reg);
1185 
1186     /*
1187      * Enable the fast charging feature and ensure the needed 40ms ellapsed
1188      * before using the analog circuits.
1189      */
1190     snd_soc_component_write(component, TAS2505_REFPOWERUP,
1191                 AIC32X4_REFPOWERUP_40MS);
1192     msleep(40);
1193 
1194     return 0;
1195 }
1196 
1197 static const struct snd_soc_component_driver soc_component_dev_aic32x4_tas2505 = {
1198     .probe          = aic32x4_tas2505_component_probe,
1199     .set_bias_level     = aic32x4_set_bias_level,
1200     .controls       = aic32x4_tas2505_snd_controls,
1201     .num_controls       = ARRAY_SIZE(aic32x4_tas2505_snd_controls),
1202     .dapm_widgets       = aic32x4_tas2505_dapm_widgets,
1203     .num_dapm_widgets   = ARRAY_SIZE(aic32x4_tas2505_dapm_widgets),
1204     .dapm_routes        = aic32x4_tas2505_dapm_routes,
1205     .num_dapm_routes    = ARRAY_SIZE(aic32x4_tas2505_dapm_routes),
1206     .suspend_bias_off   = 1,
1207     .idle_bias_on       = 1,
1208     .use_pmdown_time    = 1,
1209     .endianness     = 1,
1210 };
1211 
1212 static int aic32x4_parse_dt(struct aic32x4_priv *aic32x4,
1213         struct device_node *np)
1214 {
1215     struct aic32x4_setup_data *aic32x4_setup;
1216     int ret;
1217 
1218     aic32x4_setup = devm_kzalloc(aic32x4->dev, sizeof(*aic32x4_setup),
1219                             GFP_KERNEL);
1220     if (!aic32x4_setup)
1221         return -ENOMEM;
1222 
1223     ret = of_property_match_string(np, "clock-names", "mclk");
1224     if (ret < 0)
1225         return -EINVAL;
1226     aic32x4->mclk_name = of_clk_get_parent_name(np, ret);
1227 
1228     aic32x4->swapdacs = false;
1229     aic32x4->micpga_routing = 0;
1230     aic32x4->rstn_gpio = of_get_named_gpio(np, "reset-gpios", 0);
1231 
1232     if (of_property_read_u32_array(np, "aic32x4-gpio-func",
1233                 aic32x4_setup->gpio_func, 5) >= 0)
1234         aic32x4->setup = aic32x4_setup;
1235     return 0;
1236 }
1237 
1238 static void aic32x4_disable_regulators(struct aic32x4_priv *aic32x4)
1239 {
1240     regulator_disable(aic32x4->supply_iov);
1241 
1242     if (!IS_ERR(aic32x4->supply_ldo))
1243         regulator_disable(aic32x4->supply_ldo);
1244 
1245     if (!IS_ERR(aic32x4->supply_dv))
1246         regulator_disable(aic32x4->supply_dv);
1247 
1248     if (!IS_ERR(aic32x4->supply_av))
1249         regulator_disable(aic32x4->supply_av);
1250 }
1251 
1252 static int aic32x4_setup_regulators(struct device *dev,
1253         struct aic32x4_priv *aic32x4)
1254 {
1255     int ret = 0;
1256 
1257     aic32x4->supply_ldo = devm_regulator_get_optional(dev, "ldoin");
1258     aic32x4->supply_iov = devm_regulator_get(dev, "iov");
1259     aic32x4->supply_dv = devm_regulator_get_optional(dev, "dv");
1260     aic32x4->supply_av = devm_regulator_get_optional(dev, "av");
1261 
1262     /* Check if the regulator requirements are fulfilled */
1263 
1264     if (IS_ERR(aic32x4->supply_iov)) {
1265         dev_err(dev, "Missing supply 'iov'\n");
1266         return PTR_ERR(aic32x4->supply_iov);
1267     }
1268 
1269     if (IS_ERR(aic32x4->supply_ldo)) {
1270         if (PTR_ERR(aic32x4->supply_ldo) == -EPROBE_DEFER)
1271             return -EPROBE_DEFER;
1272 
1273         if (IS_ERR(aic32x4->supply_dv)) {
1274             dev_err(dev, "Missing supply 'dv' or 'ldoin'\n");
1275             return PTR_ERR(aic32x4->supply_dv);
1276         }
1277         if (IS_ERR(aic32x4->supply_av)) {
1278             dev_err(dev, "Missing supply 'av' or 'ldoin'\n");
1279             return PTR_ERR(aic32x4->supply_av);
1280         }
1281     } else {
1282         if (PTR_ERR(aic32x4->supply_dv) == -EPROBE_DEFER)
1283             return -EPROBE_DEFER;
1284         if (PTR_ERR(aic32x4->supply_av) == -EPROBE_DEFER)
1285             return -EPROBE_DEFER;
1286     }
1287 
1288     ret = regulator_enable(aic32x4->supply_iov);
1289     if (ret) {
1290         dev_err(dev, "Failed to enable regulator iov\n");
1291         return ret;
1292     }
1293 
1294     if (!IS_ERR(aic32x4->supply_ldo)) {
1295         ret = regulator_enable(aic32x4->supply_ldo);
1296         if (ret) {
1297             dev_err(dev, "Failed to enable regulator ldo\n");
1298             goto error_ldo;
1299         }
1300     }
1301 
1302     if (!IS_ERR(aic32x4->supply_dv)) {
1303         ret = regulator_enable(aic32x4->supply_dv);
1304         if (ret) {
1305             dev_err(dev, "Failed to enable regulator dv\n");
1306             goto error_dv;
1307         }
1308     }
1309 
1310     if (!IS_ERR(aic32x4->supply_av)) {
1311         ret = regulator_enable(aic32x4->supply_av);
1312         if (ret) {
1313             dev_err(dev, "Failed to enable regulator av\n");
1314             goto error_av;
1315         }
1316     }
1317 
1318     if (!IS_ERR(aic32x4->supply_ldo) && IS_ERR(aic32x4->supply_av))
1319         aic32x4->power_cfg |= AIC32X4_PWR_AIC32X4_LDO_ENABLE;
1320 
1321     return 0;
1322 
1323 error_av:
1324     if (!IS_ERR(aic32x4->supply_dv))
1325         regulator_disable(aic32x4->supply_dv);
1326 
1327 error_dv:
1328     if (!IS_ERR(aic32x4->supply_ldo))
1329         regulator_disable(aic32x4->supply_ldo);
1330 
1331 error_ldo:
1332     regulator_disable(aic32x4->supply_iov);
1333     return ret;
1334 }
1335 
1336 int aic32x4_probe(struct device *dev, struct regmap *regmap)
1337 {
1338     struct aic32x4_priv *aic32x4;
1339     struct aic32x4_pdata *pdata = dev->platform_data;
1340     struct device_node *np = dev->of_node;
1341     int ret;
1342 
1343     if (IS_ERR(regmap))
1344         return PTR_ERR(regmap);
1345 
1346     aic32x4 = devm_kzalloc(dev, sizeof(struct aic32x4_priv),
1347                    GFP_KERNEL);
1348     if (aic32x4 == NULL)
1349         return -ENOMEM;
1350 
1351     aic32x4->dev = dev;
1352     aic32x4->type = (enum aic32x4_type)dev_get_drvdata(dev);
1353 
1354     dev_set_drvdata(dev, aic32x4);
1355 
1356     if (pdata) {
1357         aic32x4->power_cfg = pdata->power_cfg;
1358         aic32x4->swapdacs = pdata->swapdacs;
1359         aic32x4->micpga_routing = pdata->micpga_routing;
1360         aic32x4->rstn_gpio = pdata->rstn_gpio;
1361         aic32x4->mclk_name = "mclk";
1362     } else if (np) {
1363         ret = aic32x4_parse_dt(aic32x4, np);
1364         if (ret) {
1365             dev_err(dev, "Failed to parse DT node\n");
1366             return ret;
1367         }
1368     } else {
1369         aic32x4->power_cfg = 0;
1370         aic32x4->swapdacs = false;
1371         aic32x4->micpga_routing = 0;
1372         aic32x4->rstn_gpio = -1;
1373         aic32x4->mclk_name = "mclk";
1374     }
1375 
1376     if (gpio_is_valid(aic32x4->rstn_gpio)) {
1377         ret = devm_gpio_request_one(dev, aic32x4->rstn_gpio,
1378                 GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn");
1379         if (ret != 0)
1380             return ret;
1381     }
1382 
1383     ret = aic32x4_setup_regulators(dev, aic32x4);
1384     if (ret) {
1385         dev_err(dev, "Failed to setup regulators\n");
1386         return ret;
1387     }
1388 
1389     if (gpio_is_valid(aic32x4->rstn_gpio)) {
1390         ndelay(10);
1391         gpio_set_value_cansleep(aic32x4->rstn_gpio, 1);
1392         mdelay(1);
1393     }
1394 
1395     ret = regmap_write(regmap, AIC32X4_RESET, 0x01);
1396     if (ret)
1397         goto err_disable_regulators;
1398 
1399     ret = aic32x4_register_clocks(dev, aic32x4->mclk_name);
1400     if (ret)
1401         goto err_disable_regulators;
1402 
1403     switch (aic32x4->type) {
1404     case AIC32X4_TYPE_TAS2505:
1405         ret = devm_snd_soc_register_component(dev,
1406             &soc_component_dev_aic32x4_tas2505, &aic32x4_tas2505_dai, 1);
1407         break;
1408     default:
1409         ret = devm_snd_soc_register_component(dev,
1410             &soc_component_dev_aic32x4, &aic32x4_dai, 1);
1411     }
1412 
1413     if (ret) {
1414         dev_err(dev, "Failed to register component\n");
1415         goto err_disable_regulators;
1416     }
1417 
1418     return 0;
1419 
1420 err_disable_regulators:
1421     aic32x4_disable_regulators(aic32x4);
1422 
1423     return ret;
1424 }
1425 EXPORT_SYMBOL(aic32x4_probe);
1426 
1427 void aic32x4_remove(struct device *dev)
1428 {
1429     struct aic32x4_priv *aic32x4 = dev_get_drvdata(dev);
1430 
1431     aic32x4_disable_regulators(aic32x4);
1432 }
1433 EXPORT_SYMBOL(aic32x4_remove);
1434 
1435 MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver");
1436 MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
1437 MODULE_LICENSE("GPL");
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