soc/codecs/tlv320aic31xx.h

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * ALSA SoC TLV320AIC31xx CODEC Driver Definitions
0004  *
0005  * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
0006  */
0007
0008 #ifndef _TLV320AIC31XX_H
0009 #define _TLV320AIC31XX_H
0010
0011 #define AIC31XX_RATES   SNDRV_PCM_RATE_8000_192000
0012
0013 #define AIC31XX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
0014              SNDRV_PCM_FMTBIT_S20_3LE | \
0015              SNDRV_PCM_FMTBIT_S24_3LE | \
0016              SNDRV_PCM_FMTBIT_S24_LE | \
0017              SNDRV_PCM_FMTBIT_S32_LE)
0018
0019 #define AIC31XX_STEREO_CLASS_D_BIT  BIT(1)
0020 #define AIC31XX_MINIDSP_BIT     BIT(2)
0021 #define DAC31XX_BIT         BIT(3)
0022
0023 #define AIC31XX_JACK_MASK (SND_JACK_HEADPHONE | \
0024                SND_JACK_HEADSET | \
0025                SND_JACK_BTN_0)
0026
0027 enum aic31xx_type {
0028     AIC3100 = 0,
0029     AIC3110 = AIC31XX_STEREO_CLASS_D_BIT,
0030     AIC3120 = AIC31XX_MINIDSP_BIT,
0031     AIC3111 = AIC31XX_STEREO_CLASS_D_BIT | AIC31XX_MINIDSP_BIT,
0032     DAC3100 = DAC31XX_BIT,
0033     DAC3101 = DAC31XX_BIT | AIC31XX_STEREO_CLASS_D_BIT,
0034 };
0035
0036 struct aic31xx_pdata {
0037     enum aic31xx_type codec_type;
0038     unsigned int gpio_reset;
0039     int micbias_vg;
0040 };
0041
0042 #define AIC31XX_REG(page, reg)  ((page * 128) + reg)
0043
0044 #define AIC31XX_PAGECTL     AIC31XX_REG(0, 0) /* Page Control Register */
0045
0046 /* Page 0 Registers */
0047 #define AIC31XX_RESET       AIC31XX_REG(0, 1) /* Software reset register */
0048 #define AIC31XX_OT_FLAG     AIC31XX_REG(0, 3) /* OT FLAG register */
0049 #define AIC31XX_CLKMUX      AIC31XX_REG(0, 4) /* Clock clock Gen muxing, Multiplexers*/
0050 #define AIC31XX_PLLPR       AIC31XX_REG(0, 5) /* PLL P and R-VAL register */
0051 #define AIC31XX_PLLJ        AIC31XX_REG(0, 6) /* PLL J-VAL register */
0052 #define AIC31XX_PLLDMSB     AIC31XX_REG(0, 7) /* PLL D-VAL MSB register */
0053 #define AIC31XX_PLLDLSB     AIC31XX_REG(0, 8) /* PLL D-VAL LSB register */
0054 #define AIC31XX_NDAC        AIC31XX_REG(0, 11) /* DAC NDAC_VAL register*/
0055 #define AIC31XX_MDAC        AIC31XX_REG(0, 12) /* DAC MDAC_VAL register */
0056 #define AIC31XX_DOSRMSB     AIC31XX_REG(0, 13) /* DAC OSR setting register 1, MSB value */
0057 #define AIC31XX_DOSRLSB     AIC31XX_REG(0, 14) /* DAC OSR setting register 2, LSB value */
0058 #define AIC31XX_MINI_DSP_INPOL  AIC31XX_REG(0, 16)
0059 #define AIC31XX_NADC        AIC31XX_REG(0, 18) /* Clock setting register 8, PLL */
0060 #define AIC31XX_MADC        AIC31XX_REG(0, 19) /* Clock setting register 9, PLL */
0061 #define AIC31XX_AOSR        AIC31XX_REG(0, 20) /* ADC Oversampling (AOSR) Register */
0062 #define AIC31XX_CLKOUTMUX   AIC31XX_REG(0, 25) /* Clock setting register 9, Multiplexers */
0063 #define AIC31XX_CLKOUTMVAL  AIC31XX_REG(0, 26) /* Clock setting register 10, CLOCKOUT M divider value */
0064 #define AIC31XX_IFACE1      AIC31XX_REG(0, 27) /* Audio Interface Setting Register 1 */
0065 #define AIC31XX_DATA_OFFSET AIC31XX_REG(0, 28) /* Audio Data Slot Offset Programming */
0066 #define AIC31XX_IFACE2      AIC31XX_REG(0, 29) /* Audio Interface Setting Register 2 */
0067 #define AIC31XX_BCLKN       AIC31XX_REG(0, 30) /* Clock setting register 11, BCLK N Divider */
0068 #define AIC31XX_IFACESEC1   AIC31XX_REG(0, 31) /* Audio Interface Setting Register 3, Secondary Audio Interface */
0069 #define AIC31XX_IFACESEC2   AIC31XX_REG(0, 32) /* Audio Interface Setting Register 4 */
0070 #define AIC31XX_IFACESEC3   AIC31XX_REG(0, 33) /* Audio Interface Setting Register 5 */
0071 #define AIC31XX_I2C     AIC31XX_REG(0, 34) /* I2C Bus Condition */
0072 #define AIC31XX_ADCFLAG     AIC31XX_REG(0, 36) /* ADC FLAG */
0073 #define AIC31XX_DACFLAG1    AIC31XX_REG(0, 37) /* DAC Flag Registers */
0074 #define AIC31XX_DACFLAG2    AIC31XX_REG(0, 38)
0075 #define AIC31XX_OFFLAG      AIC31XX_REG(0, 39) /* Sticky Interrupt flag (overflow) */
0076 #define AIC31XX_INTRDACFLAG AIC31XX_REG(0, 44) /* Sticy DAC Interrupt flags */
0077 #define AIC31XX_INTRADCFLAG AIC31XX_REG(0, 45) /* Sticy ADC Interrupt flags */
0078 #define AIC31XX_INTRDACFLAG2    AIC31XX_REG(0, 46) /* DAC Interrupt flags 2 */
0079 #define AIC31XX_INTRADCFLAG2    AIC31XX_REG(0, 47) /* ADC Interrupt flags 2 */
0080 #define AIC31XX_INT1CTRL    AIC31XX_REG(0, 48) /* INT1 interrupt control */
0081 #define AIC31XX_INT2CTRL    AIC31XX_REG(0, 49) /* INT2 interrupt control */
0082 #define AIC31XX_GPIO1       AIC31XX_REG(0, 51) /* GPIO1 control */
0083 #define AIC31XX_DACPRB      AIC31XX_REG(0, 60)
0084 #define AIC31XX_ADCPRB      AIC31XX_REG(0, 61) /* ADC Instruction Set Register */
0085 #define AIC31XX_DACSETUP    AIC31XX_REG(0, 63) /* DAC channel setup register */
0086 #define AIC31XX_DACMUTE     AIC31XX_REG(0, 64) /* DAC Mute and volume control register */
0087 #define AIC31XX_LDACVOL     AIC31XX_REG(0, 65) /* Left DAC channel digital volume control */
0088 #define AIC31XX_RDACVOL     AIC31XX_REG(0, 66) /* Right DAC channel digital volume control */
0089 #define AIC31XX_HSDETECT    AIC31XX_REG(0, 67) /* Headset detection */
0090 #define AIC31XX_ADCSETUP    AIC31XX_REG(0, 81) /* ADC Digital Mic */
0091 #define AIC31XX_ADCFGA      AIC31XX_REG(0, 82) /* ADC Digital Volume Control Fine Adjust */
0092 #define AIC31XX_ADCVOL      AIC31XX_REG(0, 83) /* ADC Digital Volume Control Coarse Adjust */
0093
0094 /* Page 1 Registers */
0095 #define AIC31XX_HPDRIVER    AIC31XX_REG(1, 31) /* Headphone drivers */
0096 #define AIC31XX_SPKAMP      AIC31XX_REG(1, 32) /* Class-D Speakear Amplifier */
0097 #define AIC31XX_HPPOP       AIC31XX_REG(1, 33) /* HP Output Drivers POP Removal Settings */
0098 #define AIC31XX_SPPGARAMP   AIC31XX_REG(1, 34) /* Output Driver PGA Ramp-Down Period Control */
0099 #define AIC31XX_DACMIXERROUTE   AIC31XX_REG(1, 35) /* DAC_L and DAC_R Output Mixer Routing */
0100 #define AIC31XX_LANALOGHPL  AIC31XX_REG(1, 36) /* Left Analog Vol to HPL */
0101 #define AIC31XX_RANALOGHPR  AIC31XX_REG(1, 37) /* Right Analog Vol to HPR */
0102 #define AIC31XX_LANALOGSPL  AIC31XX_REG(1, 38) /* Left Analog Vol to SPL */
0103 #define AIC31XX_RANALOGSPR  AIC31XX_REG(1, 39) /* Right Analog Vol to SPR */
0104 #define AIC31XX_HPLGAIN     AIC31XX_REG(1, 40) /* HPL Driver */
0105 #define AIC31XX_HPRGAIN     AIC31XX_REG(1, 41) /* HPR Driver */
0106 #define AIC31XX_SPLGAIN     AIC31XX_REG(1, 42) /* SPL Driver */
0107 #define AIC31XX_SPRGAIN     AIC31XX_REG(1, 43) /* SPR Driver */
0108 #define AIC31XX_HPCONTROL   AIC31XX_REG(1, 44) /* HP Driver Control */
0109 #define AIC31XX_MICBIAS     AIC31XX_REG(1, 46) /* MIC Bias Control */
0110 #define AIC31XX_MICPGA      AIC31XX_REG(1, 47) /* MIC PGA*/
0111 #define AIC31XX_MICPGAPI    AIC31XX_REG(1, 48) /* Delta-Sigma Mono ADC Channel Fine-Gain Input Selection for P-Terminal */
0112 #define AIC31XX_MICPGAMI    AIC31XX_REG(1, 49) /* ADC Input Selection for M-Terminal */
0113 #define AIC31XX_MICPGACM    AIC31XX_REG(1, 50) /* Input CM Settings */
0114
0115 /* Bits, masks, and shifts */
0116
0117 /* AIC31XX_CLKMUX */
0118 #define AIC31XX_PLL_CLKIN_MASK      GENMASK(3, 2)
0119 #define AIC31XX_PLL_CLKIN_SHIFT     (2)
0120 #define AIC31XX_PLL_CLKIN_MCLK      0x00
0121 #define AIC31XX_PLL_CLKIN_BCLK      0x01
0122 #define AIC31XX_PLL_CLKIN_GPIO1     0x02
0123 #define AIC31XX_PLL_CLKIN_DIN       0x03
0124 #define AIC31XX_CODEC_CLKIN_MASK    GENMASK(1, 0)
0125 #define AIC31XX_CODEC_CLKIN_SHIFT   (0)
0126 #define AIC31XX_CODEC_CLKIN_MCLK    0x00
0127 #define AIC31XX_CODEC_CLKIN_BCLK    0x01
0128 #define AIC31XX_CODEC_CLKIN_GPIO1   0x02
0129 #define AIC31XX_CODEC_CLKIN_PLL     0x03
0130
0131 /* AIC31XX_PLLPR */
0132 /* AIC31XX_NDAC */
0133 /* AIC31XX_MDAC */
0134 /* AIC31XX_NADC */
0135 /* AIC31XX_MADC */
0136 /* AIC31XX_BCLKN */
0137 #define AIC31XX_PLL_MASK        GENMASK(6, 0)
0138 #define AIC31XX_PM_MASK         BIT(7)
0139
0140 /* AIC31XX_IFACE1 */
0141 #define AIC31XX_IFACE1_DATATYPE_MASK    GENMASK(7, 6)
0142 #define AIC31XX_IFACE1_DATATYPE_SHIFT   (6)
0143 #define AIC31XX_I2S_MODE        0x00
0144 #define AIC31XX_DSP_MODE        0x01
0145 #define AIC31XX_RIGHT_JUSTIFIED_MODE    0x02
0146 #define AIC31XX_LEFT_JUSTIFIED_MODE 0x03
0147 #define AIC31XX_IFACE1_DATALEN_MASK GENMASK(5, 4)
0148 #define AIC31XX_IFACE1_DATALEN_SHIFT    (4)
0149 #define AIC31XX_WORD_LEN_16BITS     0x00
0150 #define AIC31XX_WORD_LEN_20BITS     0x01
0151 #define AIC31XX_WORD_LEN_24BITS     0x02
0152 #define AIC31XX_WORD_LEN_32BITS     0x03
0153 #define AIC31XX_IFACE1_MASTER_MASK  GENMASK(3, 2)
0154 #define AIC31XX_BCLK_MASTER     BIT(3)
0155 #define AIC31XX_WCLK_MASTER     BIT(2)
0156
0157 /* AIC31XX_DATA_OFFSET */
0158 #define AIC31XX_DATA_OFFSET_MASK    GENMASK(7, 0)
0159
0160 /* AIC31XX_IFACE2 */
0161 #define AIC31XX_BCLKINV_MASK        BIT(3)
0162 #define AIC31XX_BDIVCLK_MASK        GENMASK(1, 0)
0163 #define AIC31XX_DAC2BCLK        0x00
0164 #define AIC31XX_DACMOD2BCLK     0x01
0165 #define AIC31XX_ADC2BCLK        0x02
0166 #define AIC31XX_ADCMOD2BCLK     0x03
0167 #define AIC31XX_KEEP_I2SCLK     BIT(2)
0168
0169 /* AIC31XX_ADCFLAG */
0170 #define AIC31XX_ADCPWRSTATUS_MASK   BIT(6)
0171
0172 /* AIC31XX_DACFLAG1 */
0173 #define AIC31XX_LDACPWRSTATUS_MASK  BIT(7)
0174 #define AIC31XX_HPLDRVPWRSTATUS_MASK    BIT(5)
0175 #define AIC31XX_SPLDRVPWRSTATUS_MASK    BIT(4)
0176 #define AIC31XX_RDACPWRSTATUS_MASK  BIT(3)
0177 #define AIC31XX_HPRDRVPWRSTATUS_MASK    BIT(1)
0178 #define AIC31XX_SPRDRVPWRSTATUS_MASK    BIT(0)
0179
0180 /* AIC31XX_OFFLAG */
0181 #define AIC31XX_DAC_OF_LEFT     BIT(7)
0182 #define AIC31XX_DAC_OF_RIGHT        BIT(6)
0183 #define AIC31XX_DAC_OF_SHIFTER      BIT(5)
0184 #define AIC31XX_ADC_OF          BIT(3)
0185 #define AIC31XX_ADC_OF_SHIFTER      BIT(1)
0186
0187 /* AIC31XX_INTRDACFLAG */
0188 #define AIC31XX_HPLSCDETECT     BIT(7)
0189 #define AIC31XX_HPRSCDETECT     BIT(6)
0190 #define AIC31XX_BUTTONPRESS     BIT(5)
0191 #define AIC31XX_HSPLUG          BIT(4)
0192 #define AIC31XX_LDRCTHRES       BIT(3)
0193 #define AIC31XX_RDRCTHRES       BIT(2)
0194 #define AIC31XX_DACSINT         BIT(1)
0195 #define AIC31XX_DACAINT         BIT(0)
0196
0197 /* AIC31XX_INT1CTRL */
0198 #define AIC31XX_HSPLUGDET       BIT(7)
0199 #define AIC31XX_BUTTONPRESSDET      BIT(6)
0200 #define AIC31XX_DRCTHRES        BIT(5)
0201 #define AIC31XX_AGCNOISE        BIT(4)
0202 #define AIC31XX_SC          BIT(3)
0203 #define AIC31XX_ENGINE          BIT(2)
0204
0205 /* AIC31XX_GPIO1 */
0206 #define AIC31XX_GPIO1_FUNC_MASK     GENMASK(5, 2)
0207 #define AIC31XX_GPIO1_FUNC_SHIFT    2
0208 #define AIC31XX_GPIO1_DISABLED      0x00
0209 #define AIC31XX_GPIO1_INPUT     0x01
0210 #define AIC31XX_GPIO1_GPI       0x02
0211 #define AIC31XX_GPIO1_GPO       0x03
0212 #define AIC31XX_GPIO1_CLKOUT        0x04
0213 #define AIC31XX_GPIO1_INT1      0x05
0214 #define AIC31XX_GPIO1_INT2      0x06
0215 #define AIC31XX_GPIO1_ADC_WCLK      0x07
0216 #define AIC31XX_GPIO1_SBCLK     0x08
0217 #define AIC31XX_GPIO1_SWCLK     0x09
0218 #define AIC31XX_GPIO1_ADC_MOD_CLK   0x10
0219 #define AIC31XX_GPIO1_SDOUT     0x11
0220
0221 /* AIC31XX_DACMUTE */
0222 #define AIC31XX_DACMUTE_MASK        GENMASK(3, 2)
0223
0224 /* AIC31XX_HSDETECT */
0225 #define AIC31XX_HSD_ENABLE      BIT(7)
0226 #define AIC31XX_HSD_TYPE_MASK       GENMASK(6, 5)
0227 #define AIC31XX_HSD_TYPE_SHIFT      5
0228 #define AIC31XX_HSD_NONE        0x00
0229 #define AIC31XX_HSD_HP          0x01
0230 #define AIC31XX_HSD_HS          0x03
0231
0232 /* AIC31XX_HPDRIVER */
0233 #define AIC31XX_HPD_OCMV_MASK       GENMASK(4, 3)
0234 #define AIC31XX_HPD_OCMV_SHIFT      3
0235 #define AIC31XX_HPD_OCMV_1_35V      0x0
0236 #define AIC31XX_HPD_OCMV_1_5V       0x1
0237 #define AIC31XX_HPD_OCMV_1_65V      0x2
0238 #define AIC31XX_HPD_OCMV_1_8V       0x3
0239
0240 /* AIC31XX_MICBIAS */
0241 #define AIC31XX_MICBIAS_MASK        GENMASK(1, 0)
0242 #define AIC31XX_MICBIAS_SHIFT       0
0243
0244 #endif  /* _TLV320AIC31XX_H */