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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * ALSA SoC TLV320AIC31xx CODEC Driver
0004  *
0005  * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
0006  *  Jyri Sarha <jsarha@ti.com>
0007  *
0008  * Based on ground work by: Ajit Kulkarni <x0175765@ti.com>
0009  *
0010  * The TLV320AIC31xx series of audio codecs are low-power, highly integrated
0011  * high performance codecs which provides a stereo DAC, a mono ADC,
0012  * and mono/stereo Class-D speaker driver.
0013  */
0014 
0015 #include <linux/module.h>
0016 #include <linux/moduleparam.h>
0017 #include <linux/init.h>
0018 #include <linux/clk.h>
0019 #include <linux/delay.h>
0020 #include <linux/pm.h>
0021 #include <linux/i2c.h>
0022 #include <linux/gpio/consumer.h>
0023 #include <linux/regulator/consumer.h>
0024 #include <linux/acpi.h>
0025 #include <linux/of.h>
0026 #include <linux/of_gpio.h>
0027 #include <linux/slab.h>
0028 #include <sound/core.h>
0029 #include <sound/jack.h>
0030 #include <sound/pcm.h>
0031 #include <sound/pcm_params.h>
0032 #include <sound/soc.h>
0033 #include <sound/initval.h>
0034 #include <sound/tlv.h>
0035 #include <dt-bindings/sound/tlv320aic31xx.h>
0036 
0037 #include "tlv320aic31xx.h"
0038 
0039 static int aic31xx_set_jack(struct snd_soc_component *component,
0040                             struct snd_soc_jack *jack, void *data);
0041 
0042 static const struct reg_default aic31xx_reg_defaults[] = {
0043     { AIC31XX_CLKMUX, 0x00 },
0044     { AIC31XX_PLLPR, 0x11 },
0045     { AIC31XX_PLLJ, 0x04 },
0046     { AIC31XX_PLLDMSB, 0x00 },
0047     { AIC31XX_PLLDLSB, 0x00 },
0048     { AIC31XX_NDAC, 0x01 },
0049     { AIC31XX_MDAC, 0x01 },
0050     { AIC31XX_DOSRMSB, 0x00 },
0051     { AIC31XX_DOSRLSB, 0x80 },
0052     { AIC31XX_NADC, 0x01 },
0053     { AIC31XX_MADC, 0x01 },
0054     { AIC31XX_AOSR, 0x80 },
0055     { AIC31XX_IFACE1, 0x00 },
0056     { AIC31XX_DATA_OFFSET, 0x00 },
0057     { AIC31XX_IFACE2, 0x00 },
0058     { AIC31XX_BCLKN, 0x01 },
0059     { AIC31XX_DACSETUP, 0x14 },
0060     { AIC31XX_DACMUTE, 0x0c },
0061     { AIC31XX_LDACVOL, 0x00 },
0062     { AIC31XX_RDACVOL, 0x00 },
0063     { AIC31XX_ADCSETUP, 0x00 },
0064     { AIC31XX_ADCFGA, 0x80 },
0065     { AIC31XX_ADCVOL, 0x00 },
0066     { AIC31XX_HPDRIVER, 0x04 },
0067     { AIC31XX_SPKAMP, 0x06 },
0068     { AIC31XX_DACMIXERROUTE, 0x00 },
0069     { AIC31XX_LANALOGHPL, 0x7f },
0070     { AIC31XX_RANALOGHPR, 0x7f },
0071     { AIC31XX_LANALOGSPL, 0x7f },
0072     { AIC31XX_RANALOGSPR, 0x7f },
0073     { AIC31XX_HPLGAIN, 0x02 },
0074     { AIC31XX_HPRGAIN, 0x02 },
0075     { AIC31XX_SPLGAIN, 0x00 },
0076     { AIC31XX_SPRGAIN, 0x00 },
0077     { AIC31XX_MICBIAS, 0x00 },
0078     { AIC31XX_MICPGA, 0x80 },
0079     { AIC31XX_MICPGAPI, 0x00 },
0080     { AIC31XX_MICPGAMI, 0x00 },
0081 };
0082 
0083 static bool aic31xx_volatile(struct device *dev, unsigned int reg)
0084 {
0085     switch (reg) {
0086     case AIC31XX_PAGECTL: /* regmap implementation requires this */
0087     case AIC31XX_RESET: /* always clears after write */
0088     case AIC31XX_OT_FLAG:
0089     case AIC31XX_ADCFLAG:
0090     case AIC31XX_DACFLAG1:
0091     case AIC31XX_DACFLAG2:
0092     case AIC31XX_OFFLAG: /* Sticky interrupt flags */
0093     case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */
0094     case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */
0095     case AIC31XX_INTRDACFLAG2:
0096     case AIC31XX_INTRADCFLAG2:
0097     case AIC31XX_HSDETECT:
0098         return true;
0099     }
0100     return false;
0101 }
0102 
0103 static bool aic31xx_writeable(struct device *dev, unsigned int reg)
0104 {
0105     switch (reg) {
0106     case AIC31XX_OT_FLAG:
0107     case AIC31XX_ADCFLAG:
0108     case AIC31XX_DACFLAG1:
0109     case AIC31XX_DACFLAG2:
0110     case AIC31XX_OFFLAG: /* Sticky interrupt flags */
0111     case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */
0112     case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */
0113     case AIC31XX_INTRDACFLAG2:
0114     case AIC31XX_INTRADCFLAG2:
0115         return false;
0116     }
0117     return true;
0118 }
0119 
0120 static const struct regmap_range_cfg aic31xx_ranges[] = {
0121     {
0122         .range_min = 0,
0123         .range_max = 12 * 128,
0124         .selector_reg = AIC31XX_PAGECTL,
0125         .selector_mask = 0xff,
0126         .selector_shift = 0,
0127         .window_start = 0,
0128         .window_len = 128,
0129     },
0130 };
0131 
0132 static const struct regmap_config aic31xx_i2c_regmap = {
0133     .reg_bits = 8,
0134     .val_bits = 8,
0135     .writeable_reg = aic31xx_writeable,
0136     .volatile_reg = aic31xx_volatile,
0137     .reg_defaults = aic31xx_reg_defaults,
0138     .num_reg_defaults = ARRAY_SIZE(aic31xx_reg_defaults),
0139     .cache_type = REGCACHE_RBTREE,
0140     .ranges = aic31xx_ranges,
0141     .num_ranges = ARRAY_SIZE(aic31xx_ranges),
0142     .max_register = 12 * 128,
0143 };
0144 
0145 static const char * const aic31xx_supply_names[] = {
0146     "HPVDD",
0147     "SPRVDD",
0148     "SPLVDD",
0149     "AVDD",
0150     "IOVDD",
0151     "DVDD",
0152 };
0153 
0154 #define AIC31XX_NUM_SUPPLIES ARRAY_SIZE(aic31xx_supply_names)
0155 
0156 struct aic31xx_disable_nb {
0157     struct notifier_block nb;
0158     struct aic31xx_priv *aic31xx;
0159 };
0160 
0161 struct aic31xx_priv {
0162     struct snd_soc_component *component;
0163     u8 i2c_regs_status;
0164     struct device *dev;
0165     struct regmap *regmap;
0166     enum aic31xx_type codec_type;
0167     struct gpio_desc *gpio_reset;
0168     int micbias_vg;
0169     struct aic31xx_pdata pdata;
0170     struct regulator_bulk_data supplies[AIC31XX_NUM_SUPPLIES];
0171     struct aic31xx_disable_nb disable_nb[AIC31XX_NUM_SUPPLIES];
0172     struct snd_soc_jack *jack;
0173     u32 sysclk_id;
0174     unsigned int sysclk;
0175     u8 p_div;
0176     int rate_div_line;
0177     bool master_dapm_route_applied;
0178     int irq;
0179     u8 ocmv; /* output common-mode voltage */
0180 };
0181 
0182 struct aic31xx_rate_divs {
0183     u32 mclk_p;
0184     u32 rate;
0185     u8 pll_r;
0186     u8 pll_j;
0187     u16 pll_d;
0188     u16 dosr;
0189     u8 ndac;
0190     u8 mdac;
0191     u8 aosr;
0192     u8 nadc;
0193     u8 madc;
0194 };
0195 
0196 /* ADC dividers can be disabled by configuring them to 0 */
0197 static const struct aic31xx_rate_divs aic31xx_divs[] = {
0198     /* mclk/p    rate  pll: r  j     d     dosr ndac mdac  aors nadc madc */
0199     /* 8k rate */
0200     {  512000,   8000,  4, 48,   0, 128,  48,  2,   128,  48,  2},
0201     {12000000,   8000,  1, 8, 1920, 128,  48,  2,   128,  48,  2},
0202     {12000000,   8000,  1, 8, 1920, 128,  32,  3,   128,  32,  3},
0203     {12500000,   8000,  1, 7, 8643, 128,  48,  2,   128,  48,  2},
0204     /* 11.025k rate */
0205     {  705600,  11025,  3, 48,   0, 128,  24,  3,   128,  24,  3},
0206     {12000000,  11025,  1, 7, 5264, 128,  32,  2,   128,  32,  2},
0207     {12000000,  11025,  1, 8, 4672, 128,  24,  3,   128,  24,  3},
0208     {12500000,  11025,  1, 7, 2253, 128,  32,  2,   128,  32,  2},
0209     /* 16k rate */
0210     {  512000,  16000,  4, 48,   0, 128,  16,  3,   128,  16,  3},
0211     { 1024000,  16000,  2, 48,   0, 128,  16,  3,   128,  16,  3},
0212     {12000000,  16000,  1, 8, 1920, 128,  24,  2,   128,  24,  2},
0213     {12000000,  16000,  1, 8, 1920, 128,  16,  3,   128,  16,  3},
0214     {12500000,  16000,  1, 7, 8643, 128,  24,  2,   128,  24,  2},
0215     /* 22.05k rate */
0216     {  705600,  22050,  4, 36,   0, 128,  12,  3,   128,  12,  3},
0217     { 1411200,  22050,  2, 36,   0, 128,  12,  3,   128,  12,  3},
0218     {12000000,  22050,  1, 7, 5264, 128,  16,  2,   128,  16,  2},
0219     {12000000,  22050,  1, 8, 4672, 128,  12,  3,   128,  12,  3},
0220     {12500000,  22050,  1, 7, 2253, 128,  16,  2,   128,  16,  2},
0221     /* 32k rate */
0222     { 1024000,  32000,      2, 48,   0, 128,  12,  2,   128,  12,  2},
0223     { 2048000,  32000,      1, 48,   0, 128,  12,  2,   128,  12,  2},
0224     {12000000,  32000,  1, 8, 1920, 128,  12,  2,   128,  12,  2},
0225     {12000000,  32000,  1, 8, 1920, 128,   8,  3,   128,   8,  3},
0226     {12500000,  32000,  1, 7, 8643, 128,  12,  2,   128,  12,  2},
0227     /* 44.1k rate */
0228     { 1411200,  44100,  2, 32,   0, 128,   8,  2,   128,   8,  2},
0229     { 2822400,  44100,  1, 32,   0, 128,   8,  2,   128,   8,  2},
0230     {12000000,  44100,  1, 7, 5264, 128,   8,  2,   128,   8,  2},
0231     {12000000,  44100,  1, 8, 4672, 128,   6,  3,   128,   6,  3},
0232     {12500000,  44100,  1, 7, 2253, 128,   8,  2,   128,   8,  2},
0233     /* 48k rate */
0234     { 1536000,  48000,  2, 32,   0, 128,   8,  2,   128,   8,  2},
0235     { 3072000,  48000,  1, 32,   0, 128,   8,  2,   128,   8,  2},
0236     {12000000,  48000,  1, 8, 1920, 128,   8,  2,   128,   8,  2},
0237     {12000000,  48000,  1, 7, 6800,  96,   5,  4,    96,   5,  4},
0238     {12500000,  48000,  1, 7, 8643, 128,   8,  2,   128,   8,  2},
0239     /* 88.2k rate */
0240     { 2822400,  88200,  2, 16,   0,  64,   8,  2,    64,   8,  2},
0241     { 5644800,  88200,  1, 16,   0,  64,   8,  2,    64,   8,  2},
0242     {12000000,  88200,  1, 7, 5264,  64,   8,  2,    64,   8,  2},
0243     {12000000,  88200,  1, 8, 4672,  64,   6,  3,    64,   6,  3},
0244     {12500000,  88200,  1, 7, 2253,  64,   8,  2,    64,   8,  2},
0245     /* 96k rate */
0246     { 3072000,  96000,  2, 16,   0,  64,   8,  2,    64,   8,  2},
0247     { 6144000,  96000,  1, 16,   0,  64,   8,  2,    64,   8,  2},
0248     {12000000,  96000,  1, 8, 1920,  64,   8,  2,    64,   8,  2},
0249     {12000000,  96000,  1, 7, 6800,  48,   5,  4,    48,   5,  4},
0250     {12500000,  96000,  1, 7, 8643,  64,   8,  2,    64,   8,  2},
0251     /* 176.4k rate */
0252     { 5644800, 176400,  2, 8,    0,  32,   8,  2,    32,   8,  2},
0253     {11289600, 176400,  1, 8,    0,  32,   8,  2,    32,   8,  2},
0254     {12000000, 176400,  1, 7, 5264,  32,   8,  2,    32,   8,  2},
0255     {12000000, 176400,  1, 8, 4672,  32,   6,  3,    32,   6,  3},
0256     {12500000, 176400,  1, 7, 2253,  32,   8,  2,    32,   8,  2},
0257     /* 192k rate */
0258     { 6144000, 192000,  2, 8,    0,  32,   8,  2,    32,   8,  2},
0259     {12288000, 192000,  1, 8,    0,  32,   8,  2,    32,   8,  2},
0260     {12000000, 192000,  1, 8, 1920,  32,   8,  2,    32,   8,  2},
0261     {12000000, 192000,  1, 7, 6800,  24,   5,  4,    24,   5,  4},
0262     {12500000, 192000,  1, 7, 8643,  32,   8,  2,    32,   8,  2},
0263 };
0264 
0265 static const char * const ldac_in_text[] = {
0266     "Off", "Left Data", "Right Data", "Mono"
0267 };
0268 
0269 static const char * const rdac_in_text[] = {
0270     "Off", "Right Data", "Left Data", "Mono"
0271 };
0272 
0273 static SOC_ENUM_SINGLE_DECL(ldac_in_enum, AIC31XX_DACSETUP, 4, ldac_in_text);
0274 
0275 static SOC_ENUM_SINGLE_DECL(rdac_in_enum, AIC31XX_DACSETUP, 2, rdac_in_text);
0276 
0277 static const char * const mic_select_text[] = {
0278     "Off", "FFR 10 Ohm", "FFR 20 Ohm", "FFR 40 Ohm"
0279 };
0280 
0281 static SOC_ENUM_SINGLE_DECL(mic1lp_p_enum, AIC31XX_MICPGAPI, 6,
0282     mic_select_text);
0283 static SOC_ENUM_SINGLE_DECL(mic1rp_p_enum, AIC31XX_MICPGAPI, 4,
0284     mic_select_text);
0285 static SOC_ENUM_SINGLE_DECL(mic1lm_p_enum, AIC31XX_MICPGAPI, 2,
0286     mic_select_text);
0287 
0288 static SOC_ENUM_SINGLE_DECL(mic1lm_m_enum, AIC31XX_MICPGAMI, 4,
0289     mic_select_text);
0290 
0291 static const char * const hp_poweron_time_text[] = {
0292     "0us", "15.3us", "153us", "1.53ms", "15.3ms", "76.2ms",
0293     "153ms", "304ms", "610ms", "1.22s", "3.04s", "6.1s" };
0294 
0295 static SOC_ENUM_SINGLE_DECL(hp_poweron_time_enum, AIC31XX_HPPOP, 3,
0296     hp_poweron_time_text);
0297 
0298 static const char * const hp_rampup_step_text[] = {
0299     "0ms", "0.98ms", "1.95ms", "3.9ms" };
0300 
0301 static SOC_ENUM_SINGLE_DECL(hp_rampup_step_enum, AIC31XX_HPPOP, 1,
0302     hp_rampup_step_text);
0303 
0304 static const char * const vol_soft_step_mode_text[] = {
0305     "fast", "slow", "disabled" };
0306 
0307 static SOC_ENUM_SINGLE_DECL(vol_soft_step_mode_enum, AIC31XX_DACSETUP, 0,
0308     vol_soft_step_mode_text);
0309 
0310 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6350, 50, 0);
0311 static const DECLARE_TLV_DB_SCALE(adc_fgain_tlv, 0, 10, 0);
0312 static const DECLARE_TLV_DB_SCALE(adc_cgain_tlv, -2000, 50, 0);
0313 static const DECLARE_TLV_DB_SCALE(mic_pga_tlv, 0, 50, 0);
0314 static const DECLARE_TLV_DB_SCALE(hp_drv_tlv, 0, 100, 0);
0315 static const DECLARE_TLV_DB_SCALE(class_D_drv_tlv, 600, 600, 0);
0316 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -6350, 50, 0);
0317 static const DECLARE_TLV_DB_SCALE(sp_vol_tlv, -6350, 50, 0);
0318 
0319 /*
0320  * controls to be exported to the user space
0321  */
0322 static const struct snd_kcontrol_new common31xx_snd_controls[] = {
0323     SOC_DOUBLE_R_S_TLV("DAC Playback Volume", AIC31XX_LDACVOL,
0324                AIC31XX_RDACVOL, 0, -127, 48, 7, 0, dac_vol_tlv),
0325 
0326     SOC_DOUBLE_R("HP Driver Playback Switch", AIC31XX_HPLGAIN,
0327              AIC31XX_HPRGAIN, 2, 1, 0),
0328     SOC_DOUBLE_R_TLV("HP Driver Playback Volume", AIC31XX_HPLGAIN,
0329              AIC31XX_HPRGAIN, 3, 0x09, 0, hp_drv_tlv),
0330 
0331     SOC_DOUBLE_R_TLV("HP Analog Playback Volume", AIC31XX_LANALOGHPL,
0332              AIC31XX_RANALOGHPR, 0, 0x7F, 1, hp_vol_tlv),
0333 
0334     /* HP de-pop control: apply power not immediately but via ramp
0335      * function with these psarameters. Note that power up sequence
0336      * has to wait for this to complete; this is implemented by
0337      * polling HP driver status in aic31xx_dapm_power_event()
0338      */
0339     SOC_ENUM("HP Output Driver Power-On time", hp_poweron_time_enum),
0340     SOC_ENUM("HP Output Driver Ramp-up step", hp_rampup_step_enum),
0341 
0342     SOC_ENUM("Volume Soft Stepping", vol_soft_step_mode_enum),
0343 };
0344 
0345 static const struct snd_kcontrol_new aic31xx_snd_controls[] = {
0346     SOC_SINGLE_TLV("ADC Fine Capture Volume", AIC31XX_ADCFGA, 4, 4, 1,
0347                adc_fgain_tlv),
0348 
0349     SOC_SINGLE("ADC Capture Switch", AIC31XX_ADCFGA, 7, 1, 1),
0350     SOC_DOUBLE_R_S_TLV("ADC Capture Volume", AIC31XX_ADCVOL, AIC31XX_ADCVOL,
0351                0, -24, 40, 6, 0, adc_cgain_tlv),
0352 
0353     SOC_SINGLE_TLV("Mic PGA Capture Volume", AIC31XX_MICPGA, 0,
0354                119, 0, mic_pga_tlv),
0355 };
0356 
0357 static const struct snd_kcontrol_new aic311x_snd_controls[] = {
0358     SOC_DOUBLE_R("Speaker Driver Playback Switch", AIC31XX_SPLGAIN,
0359              AIC31XX_SPRGAIN, 2, 1, 0),
0360     SOC_DOUBLE_R_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN,
0361              AIC31XX_SPRGAIN, 3, 3, 0, class_D_drv_tlv),
0362 
0363     SOC_DOUBLE_R_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL,
0364              AIC31XX_RANALOGSPR, 0, 0x7F, 1, sp_vol_tlv),
0365 };
0366 
0367 static const struct snd_kcontrol_new aic310x_snd_controls[] = {
0368     SOC_SINGLE("Speaker Driver Playback Switch", AIC31XX_SPLGAIN,
0369            2, 1, 0),
0370     SOC_SINGLE_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN,
0371                3, 3, 0, class_D_drv_tlv),
0372 
0373     SOC_SINGLE_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL,
0374                0, 0x7F, 1, sp_vol_tlv),
0375 };
0376 
0377 static const struct snd_kcontrol_new ldac_in_control =
0378     SOC_DAPM_ENUM("DAC Left Input", ldac_in_enum);
0379 
0380 static const struct snd_kcontrol_new rdac_in_control =
0381     SOC_DAPM_ENUM("DAC Right Input", rdac_in_enum);
0382 
0383 static int aic31xx_wait_bits(struct aic31xx_priv *aic31xx, unsigned int reg,
0384                  unsigned int mask, unsigned int wbits, int sleep,
0385                  int count)
0386 {
0387     unsigned int bits;
0388     int counter = count;
0389     int ret = regmap_read(aic31xx->regmap, reg, &bits);
0390 
0391     while ((bits & mask) != wbits && counter && !ret) {
0392         usleep_range(sleep, sleep * 2);
0393         ret = regmap_read(aic31xx->regmap, reg, &bits);
0394         counter--;
0395     }
0396     if ((bits & mask) != wbits) {
0397         dev_err(aic31xx->dev,
0398             "%s: Failed! 0x%x was 0x%x expected 0x%x (%d, 0x%x, %d us)\n",
0399             __func__, reg, bits, wbits, ret, mask,
0400             (count - counter) * sleep);
0401         ret = -1;
0402     }
0403     return ret;
0404 }
0405 
0406 #define WIDGET_BIT(reg, shift) (((shift) << 8) | (reg))
0407 
0408 static int aic31xx_dapm_power_event(struct snd_soc_dapm_widget *w,
0409                     struct snd_kcontrol *kcontrol, int event)
0410 {
0411     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0412     struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
0413     unsigned int reg = AIC31XX_DACFLAG1;
0414     unsigned int mask;
0415     unsigned int timeout = 500 * USEC_PER_MSEC;
0416 
0417     switch (WIDGET_BIT(w->reg, w->shift)) {
0418     case WIDGET_BIT(AIC31XX_DACSETUP, 7):
0419         mask = AIC31XX_LDACPWRSTATUS_MASK;
0420         break;
0421     case WIDGET_BIT(AIC31XX_DACSETUP, 6):
0422         mask = AIC31XX_RDACPWRSTATUS_MASK;
0423         break;
0424     case WIDGET_BIT(AIC31XX_HPDRIVER, 7):
0425         mask = AIC31XX_HPLDRVPWRSTATUS_MASK;
0426         if (event == SND_SOC_DAPM_POST_PMU)
0427             timeout = 7 * USEC_PER_SEC;
0428         break;
0429     case WIDGET_BIT(AIC31XX_HPDRIVER, 6):
0430         mask = AIC31XX_HPRDRVPWRSTATUS_MASK;
0431         if (event == SND_SOC_DAPM_POST_PMU)
0432             timeout = 7 * USEC_PER_SEC;
0433         break;
0434     case WIDGET_BIT(AIC31XX_SPKAMP, 7):
0435         mask = AIC31XX_SPLDRVPWRSTATUS_MASK;
0436         break;
0437     case WIDGET_BIT(AIC31XX_SPKAMP, 6):
0438         mask = AIC31XX_SPRDRVPWRSTATUS_MASK;
0439         break;
0440     case WIDGET_BIT(AIC31XX_ADCSETUP, 7):
0441         mask = AIC31XX_ADCPWRSTATUS_MASK;
0442         reg = AIC31XX_ADCFLAG;
0443         break;
0444     default:
0445         dev_err(component->dev, "Unknown widget '%s' calling %s\n",
0446             w->name, __func__);
0447         return -EINVAL;
0448     }
0449 
0450     switch (event) {
0451     case SND_SOC_DAPM_POST_PMU:
0452         return aic31xx_wait_bits(aic31xx, reg, mask, mask,
0453                 5000, timeout / 5000);
0454     case SND_SOC_DAPM_POST_PMD:
0455         return aic31xx_wait_bits(aic31xx, reg, mask, 0,
0456                 5000, timeout / 5000);
0457     default:
0458         dev_dbg(component->dev,
0459             "Unhandled dapm widget event %d from %s\n",
0460             event, w->name);
0461     }
0462     return 0;
0463 }
0464 
0465 static const struct snd_kcontrol_new aic31xx_left_output_switches[] = {
0466     SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE, 6, 1, 0),
0467     SOC_DAPM_SINGLE("From MIC1LP", AIC31XX_DACMIXERROUTE, 5, 1, 0),
0468     SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 4, 1, 0),
0469 };
0470 
0471 static const struct snd_kcontrol_new aic31xx_right_output_switches[] = {
0472     SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE, 2, 1, 0),
0473     SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 1, 1, 0),
0474 };
0475 
0476 static const struct snd_kcontrol_new dac31xx_left_output_switches[] = {
0477     SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE, 6, 1, 0),
0478     SOC_DAPM_SINGLE("From AIN1", AIC31XX_DACMIXERROUTE, 5, 1, 0),
0479     SOC_DAPM_SINGLE("From AIN2", AIC31XX_DACMIXERROUTE, 4, 1, 0),
0480 };
0481 
0482 static const struct snd_kcontrol_new dac31xx_right_output_switches[] = {
0483     SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE, 2, 1, 0),
0484     SOC_DAPM_SINGLE("From AIN2", AIC31XX_DACMIXERROUTE, 1, 1, 0),
0485 };
0486 
0487 static const struct snd_kcontrol_new p_term_mic1lp =
0488     SOC_DAPM_ENUM("MIC1LP P-Terminal", mic1lp_p_enum);
0489 
0490 static const struct snd_kcontrol_new p_term_mic1rp =
0491     SOC_DAPM_ENUM("MIC1RP P-Terminal", mic1rp_p_enum);
0492 
0493 static const struct snd_kcontrol_new p_term_mic1lm =
0494     SOC_DAPM_ENUM("MIC1LM P-Terminal", mic1lm_p_enum);
0495 
0496 static const struct snd_kcontrol_new m_term_mic1lm =
0497     SOC_DAPM_ENUM("MIC1LM M-Terminal", mic1lm_m_enum);
0498 
0499 static const struct snd_kcontrol_new aic31xx_dapm_hpl_switch =
0500     SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGHPL, 7, 1, 0);
0501 
0502 static const struct snd_kcontrol_new aic31xx_dapm_hpr_switch =
0503     SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGHPR, 7, 1, 0);
0504 
0505 static const struct snd_kcontrol_new aic31xx_dapm_spl_switch =
0506     SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGSPL, 7, 1, 0);
0507 
0508 static const struct snd_kcontrol_new aic31xx_dapm_spr_switch =
0509     SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGSPR, 7, 1, 0);
0510 
0511 static int mic_bias_event(struct snd_soc_dapm_widget *w,
0512               struct snd_kcontrol *kcontrol, int event)
0513 {
0514     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0515     struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
0516 
0517     switch (event) {
0518     case SND_SOC_DAPM_POST_PMU:
0519         /* change mic bias voltage to user defined */
0520         snd_soc_component_update_bits(component, AIC31XX_MICBIAS,
0521                     AIC31XX_MICBIAS_MASK,
0522                     aic31xx->micbias_vg <<
0523                     AIC31XX_MICBIAS_SHIFT);
0524         dev_dbg(component->dev, "%s: turned on\n", __func__);
0525         break;
0526     case SND_SOC_DAPM_PRE_PMD:
0527         /* turn mic bias off */
0528         snd_soc_component_update_bits(component, AIC31XX_MICBIAS,
0529                     AIC31XX_MICBIAS_MASK, 0);
0530         dev_dbg(component->dev, "%s: turned off\n", __func__);
0531         break;
0532     }
0533     return 0;
0534 }
0535 
0536 static const struct snd_soc_dapm_widget common31xx_dapm_widgets[] = {
0537     SND_SOC_DAPM_AIF_IN("AIF IN", "Playback", 0, SND_SOC_NOPM, 0, 0),
0538 
0539     SND_SOC_DAPM_MUX("DAC Left Input",
0540              SND_SOC_NOPM, 0, 0, &ldac_in_control),
0541     SND_SOC_DAPM_MUX("DAC Right Input",
0542              SND_SOC_NOPM, 0, 0, &rdac_in_control),
0543     /* DACs */
0544     SND_SOC_DAPM_DAC_E("DAC Left", "Left Playback",
0545                AIC31XX_DACSETUP, 7, 0, aic31xx_dapm_power_event,
0546                SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
0547 
0548     SND_SOC_DAPM_DAC_E("DAC Right", "Right Playback",
0549                AIC31XX_DACSETUP, 6, 0, aic31xx_dapm_power_event,
0550                SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
0551 
0552     /* HP */
0553     SND_SOC_DAPM_SWITCH("HP Left", SND_SOC_NOPM, 0, 0,
0554                 &aic31xx_dapm_hpl_switch),
0555     SND_SOC_DAPM_SWITCH("HP Right", SND_SOC_NOPM, 0, 0,
0556                 &aic31xx_dapm_hpr_switch),
0557 
0558     /* Output drivers */
0559     SND_SOC_DAPM_OUT_DRV_E("HPL Driver", AIC31XX_HPDRIVER, 7, 0,
0560                    NULL, 0, aic31xx_dapm_power_event,
0561                    SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
0562     SND_SOC_DAPM_OUT_DRV_E("HPR Driver", AIC31XX_HPDRIVER, 6, 0,
0563                    NULL, 0, aic31xx_dapm_power_event,
0564                    SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
0565 
0566     /* Mic Bias */
0567     SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, mic_bias_event,
0568                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
0569 
0570     /* Keep BCLK/WCLK enabled even if DAC/ADC is powered down */
0571     SND_SOC_DAPM_SUPPLY("Activate I2S clocks", AIC31XX_IFACE2, 2, 0,
0572                 NULL, 0),
0573 
0574     /* Outputs */
0575     SND_SOC_DAPM_OUTPUT("HPL"),
0576     SND_SOC_DAPM_OUTPUT("HPR"),
0577 };
0578 
0579 static const struct snd_soc_dapm_widget dac31xx_dapm_widgets[] = {
0580     /* Inputs */
0581     SND_SOC_DAPM_INPUT("AIN1"),
0582     SND_SOC_DAPM_INPUT("AIN2"),
0583 
0584     /* Output Mixers */
0585     SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM, 0, 0,
0586                dac31xx_left_output_switches,
0587                ARRAY_SIZE(dac31xx_left_output_switches)),
0588     SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM, 0, 0,
0589                dac31xx_right_output_switches,
0590                ARRAY_SIZE(dac31xx_right_output_switches)),
0591 };
0592 
0593 static const struct snd_soc_dapm_widget aic31xx_dapm_widgets[] = {
0594     /* Inputs */
0595     SND_SOC_DAPM_INPUT("MIC1LP"),
0596     SND_SOC_DAPM_INPUT("MIC1RP"),
0597     SND_SOC_DAPM_INPUT("MIC1LM"),
0598 
0599     /* Input Selection to MIC_PGA */
0600     SND_SOC_DAPM_MUX("MIC1LP P-Terminal", SND_SOC_NOPM, 0, 0,
0601              &p_term_mic1lp),
0602     SND_SOC_DAPM_MUX("MIC1RP P-Terminal", SND_SOC_NOPM, 0, 0,
0603              &p_term_mic1rp),
0604     SND_SOC_DAPM_MUX("MIC1LM P-Terminal", SND_SOC_NOPM, 0, 0,
0605              &p_term_mic1lm),
0606 
0607     /* ADC */
0608     SND_SOC_DAPM_ADC_E("ADC", "Capture", AIC31XX_ADCSETUP, 7, 0,
0609                aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
0610                SND_SOC_DAPM_POST_PMD),
0611 
0612     SND_SOC_DAPM_MUX("MIC1LM M-Terminal", SND_SOC_NOPM, 0, 0,
0613              &m_term_mic1lm),
0614 
0615     /* Enabling & Disabling MIC Gain Ctl */
0616     SND_SOC_DAPM_PGA("MIC_GAIN_CTL", AIC31XX_MICPGA,
0617              7, 1, NULL, 0),
0618 
0619     /* Output Mixers */
0620     SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM, 0, 0,
0621                aic31xx_left_output_switches,
0622                ARRAY_SIZE(aic31xx_left_output_switches)),
0623     SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM, 0, 0,
0624                aic31xx_right_output_switches,
0625                ARRAY_SIZE(aic31xx_right_output_switches)),
0626 
0627     SND_SOC_DAPM_AIF_OUT("AIF OUT", "Capture", 0, SND_SOC_NOPM, 0, 0),
0628 };
0629 
0630 static const struct snd_soc_dapm_widget aic311x_dapm_widgets[] = {
0631     /* AIC3111 and AIC3110 have stereo class-D amplifier */
0632     SND_SOC_DAPM_OUT_DRV_E("SPL ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0,
0633                    aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
0634                    SND_SOC_DAPM_POST_PMD),
0635     SND_SOC_DAPM_OUT_DRV_E("SPR ClassD", AIC31XX_SPKAMP, 6, 0, NULL, 0,
0636                    aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
0637                    SND_SOC_DAPM_POST_PMD),
0638     SND_SOC_DAPM_SWITCH("Speaker Left", SND_SOC_NOPM, 0, 0,
0639                 &aic31xx_dapm_spl_switch),
0640     SND_SOC_DAPM_SWITCH("Speaker Right", SND_SOC_NOPM, 0, 0,
0641                 &aic31xx_dapm_spr_switch),
0642     SND_SOC_DAPM_OUTPUT("SPL"),
0643     SND_SOC_DAPM_OUTPUT("SPR"),
0644 };
0645 
0646 /* AIC3100 and AIC3120 have only mono class-D amplifier */
0647 static const struct snd_soc_dapm_widget aic310x_dapm_widgets[] = {
0648     SND_SOC_DAPM_OUT_DRV_E("SPK ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0,
0649                    aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
0650                    SND_SOC_DAPM_POST_PMD),
0651     SND_SOC_DAPM_SWITCH("Speaker", SND_SOC_NOPM, 0, 0,
0652                 &aic31xx_dapm_spl_switch),
0653     SND_SOC_DAPM_OUTPUT("SPK"),
0654 };
0655 
0656 static const struct snd_soc_dapm_route
0657 common31xx_audio_map[] = {
0658     /* DAC Input Routing */
0659     {"DAC Left Input", "Left Data", "AIF IN"},
0660     {"DAC Left Input", "Right Data", "AIF IN"},
0661     {"DAC Left Input", "Mono", "AIF IN"},
0662     {"DAC Right Input", "Left Data", "AIF IN"},
0663     {"DAC Right Input", "Right Data", "AIF IN"},
0664     {"DAC Right Input", "Mono", "AIF IN"},
0665     {"DAC Left", NULL, "DAC Left Input"},
0666     {"DAC Right", NULL, "DAC Right Input"},
0667 
0668     /* HPL path */
0669     {"HP Left", "Switch", "Output Left"},
0670     {"HPL Driver", NULL, "HP Left"},
0671     {"HPL", NULL, "HPL Driver"},
0672 
0673     /* HPR path */
0674     {"HP Right", "Switch", "Output Right"},
0675     {"HPR Driver", NULL, "HP Right"},
0676     {"HPR", NULL, "HPR Driver"},
0677 };
0678 
0679 static const struct snd_soc_dapm_route
0680 dac31xx_audio_map[] = {
0681     /* Left Output */
0682     {"Output Left", "From Left DAC", "DAC Left"},
0683     {"Output Left", "From AIN1", "AIN1"},
0684     {"Output Left", "From AIN2", "AIN2"},
0685 
0686     /* Right Output */
0687     {"Output Right", "From Right DAC", "DAC Right"},
0688     {"Output Right", "From AIN2", "AIN2"},
0689 };
0690 
0691 static const struct snd_soc_dapm_route
0692 aic31xx_audio_map[] = {
0693     /* Mic input */
0694     {"MIC1LP P-Terminal", "FFR 10 Ohm", "MIC1LP"},
0695     {"MIC1LP P-Terminal", "FFR 20 Ohm", "MIC1LP"},
0696     {"MIC1LP P-Terminal", "FFR 40 Ohm", "MIC1LP"},
0697     {"MIC1RP P-Terminal", "FFR 10 Ohm", "MIC1RP"},
0698     {"MIC1RP P-Terminal", "FFR 20 Ohm", "MIC1RP"},
0699     {"MIC1RP P-Terminal", "FFR 40 Ohm", "MIC1RP"},
0700     {"MIC1LM P-Terminal", "FFR 10 Ohm", "MIC1LM"},
0701     {"MIC1LM P-Terminal", "FFR 20 Ohm", "MIC1LM"},
0702     {"MIC1LM P-Terminal", "FFR 40 Ohm", "MIC1LM"},
0703 
0704     {"MIC1LM M-Terminal", "FFR 10 Ohm", "MIC1LM"},
0705     {"MIC1LM M-Terminal", "FFR 20 Ohm", "MIC1LM"},
0706     {"MIC1LM M-Terminal", "FFR 40 Ohm", "MIC1LM"},
0707 
0708     {"MIC_GAIN_CTL", NULL, "MIC1LP P-Terminal"},
0709     {"MIC_GAIN_CTL", NULL, "MIC1RP P-Terminal"},
0710     {"MIC_GAIN_CTL", NULL, "MIC1LM P-Terminal"},
0711     {"MIC_GAIN_CTL", NULL, "MIC1LM M-Terminal"},
0712 
0713     {"ADC", NULL, "MIC_GAIN_CTL"},
0714 
0715     {"AIF OUT", NULL, "ADC"},
0716 
0717     /* Left Output */
0718     {"Output Left", "From Left DAC", "DAC Left"},
0719     {"Output Left", "From MIC1LP", "MIC1LP"},
0720     {"Output Left", "From MIC1RP", "MIC1RP"},
0721 
0722     /* Right Output */
0723     {"Output Right", "From Right DAC", "DAC Right"},
0724     {"Output Right", "From MIC1RP", "MIC1RP"},
0725 };
0726 
0727 static const struct snd_soc_dapm_route
0728 aic311x_audio_map[] = {
0729     /* SP L path */
0730     {"Speaker Left", "Switch", "Output Left"},
0731     {"SPL ClassD", NULL, "Speaker Left"},
0732     {"SPL", NULL, "SPL ClassD"},
0733 
0734     /* SP R path */
0735     {"Speaker Right", "Switch", "Output Right"},
0736     {"SPR ClassD", NULL, "Speaker Right"},
0737     {"SPR", NULL, "SPR ClassD"},
0738 };
0739 
0740 static const struct snd_soc_dapm_route
0741 aic310x_audio_map[] = {
0742     /* SP L path */
0743     {"Speaker", "Switch", "Output Left"},
0744     {"SPK ClassD", NULL, "Speaker"},
0745     {"SPK", NULL, "SPK ClassD"},
0746 };
0747 
0748 /*
0749  * Always connected DAPM routes for codec clock master modes.
0750  * If the codec is the master on the I2S bus, we need to power up components
0751  * to have valid DAC_CLK.
0752  *
0753  * In order to have the I2S clocks on the bus either the DACs/ADC need to be
0754  * enabled, or the P0/R29/D2 (Keep bclk/wclk in power down) need to be set.
0755  *
0756  * Otherwise the codec will not generate clocks on the bus.
0757  */
0758 static const struct snd_soc_dapm_route
0759 common31xx_cm_audio_map[] = {
0760     {"HPL", NULL, "AIF IN"},
0761     {"HPR", NULL, "AIF IN"},
0762 
0763     {"AIF IN", NULL, "Activate I2S clocks"},
0764 };
0765 
0766 static const struct snd_soc_dapm_route
0767 aic31xx_cm_audio_map[] = {
0768     {"AIF OUT", NULL, "MIC1LP"},
0769     {"AIF OUT", NULL, "MIC1RP"},
0770     {"AIF OUT", NULL, "MIC1LM"},
0771 
0772     {"AIF OUT", NULL, "Activate I2S clocks"},
0773 };
0774 
0775 static int aic31xx_add_controls(struct snd_soc_component *component)
0776 {
0777     int ret = 0;
0778     struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
0779 
0780     if (!(aic31xx->codec_type & DAC31XX_BIT))
0781         ret = snd_soc_add_component_controls(
0782             component, aic31xx_snd_controls,
0783             ARRAY_SIZE(aic31xx_snd_controls));
0784     if (ret)
0785         return ret;
0786 
0787     if (aic31xx->codec_type & AIC31XX_STEREO_CLASS_D_BIT)
0788         ret = snd_soc_add_component_controls(
0789             component, aic311x_snd_controls,
0790             ARRAY_SIZE(aic311x_snd_controls));
0791     else
0792         ret = snd_soc_add_component_controls(
0793             component, aic310x_snd_controls,
0794             ARRAY_SIZE(aic310x_snd_controls));
0795 
0796     return ret;
0797 }
0798 
0799 static int aic31xx_add_widgets(struct snd_soc_component *component)
0800 {
0801     struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
0802     struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
0803     int ret = 0;
0804 
0805     if (aic31xx->codec_type & DAC31XX_BIT) {
0806         ret = snd_soc_dapm_new_controls(
0807             dapm, dac31xx_dapm_widgets,
0808             ARRAY_SIZE(dac31xx_dapm_widgets));
0809         if (ret)
0810             return ret;
0811 
0812         ret = snd_soc_dapm_add_routes(dapm, dac31xx_audio_map,
0813                           ARRAY_SIZE(dac31xx_audio_map));
0814         if (ret)
0815             return ret;
0816     } else {
0817         ret = snd_soc_dapm_new_controls(
0818             dapm, aic31xx_dapm_widgets,
0819             ARRAY_SIZE(aic31xx_dapm_widgets));
0820         if (ret)
0821             return ret;
0822 
0823         ret = snd_soc_dapm_add_routes(dapm, aic31xx_audio_map,
0824                           ARRAY_SIZE(aic31xx_audio_map));
0825         if (ret)
0826             return ret;
0827     }
0828 
0829     if (aic31xx->codec_type & AIC31XX_STEREO_CLASS_D_BIT) {
0830         ret = snd_soc_dapm_new_controls(
0831             dapm, aic311x_dapm_widgets,
0832             ARRAY_SIZE(aic311x_dapm_widgets));
0833         if (ret)
0834             return ret;
0835 
0836         ret = snd_soc_dapm_add_routes(dapm, aic311x_audio_map,
0837                           ARRAY_SIZE(aic311x_audio_map));
0838         if (ret)
0839             return ret;
0840     } else {
0841         ret = snd_soc_dapm_new_controls(
0842             dapm, aic310x_dapm_widgets,
0843             ARRAY_SIZE(aic310x_dapm_widgets));
0844         if (ret)
0845             return ret;
0846 
0847         ret = snd_soc_dapm_add_routes(dapm, aic310x_audio_map,
0848                           ARRAY_SIZE(aic310x_audio_map));
0849         if (ret)
0850             return ret;
0851     }
0852 
0853     return 0;
0854 }
0855 
0856 static int aic31xx_setup_pll(struct snd_soc_component *component,
0857                  struct snd_pcm_hw_params *params)
0858 {
0859     struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
0860     int bclk_score = snd_soc_params_to_frame_size(params);
0861     int mclk_p;
0862     int bclk_n = 0;
0863     int match = -1;
0864     int i;
0865 
0866     if (!aic31xx->sysclk || !aic31xx->p_div) {
0867         dev_err(component->dev, "Master clock not supplied\n");
0868         return -EINVAL;
0869     }
0870     mclk_p = aic31xx->sysclk / aic31xx->p_div;
0871 
0872     /* Use PLL as CODEC_CLKIN and DAC_CLK as BDIV_CLKIN */
0873     snd_soc_component_update_bits(component, AIC31XX_CLKMUX,
0874                 AIC31XX_CODEC_CLKIN_MASK, AIC31XX_CODEC_CLKIN_PLL);
0875     snd_soc_component_update_bits(component, AIC31XX_IFACE2,
0876                 AIC31XX_BDIVCLK_MASK, AIC31XX_DAC2BCLK);
0877 
0878     for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++) {
0879         if (aic31xx_divs[i].rate == params_rate(params) &&
0880             aic31xx_divs[i].mclk_p == mclk_p) {
0881             int s = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) %
0882                 snd_soc_params_to_frame_size(params);
0883             int bn = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) /
0884                 snd_soc_params_to_frame_size(params);
0885             if (s < bclk_score && bn > 0) {
0886                 match = i;
0887                 bclk_n = bn;
0888                 bclk_score = s;
0889             }
0890         }
0891     }
0892 
0893     if (match == -1) {
0894         dev_err(component->dev,
0895             "%s: Sample rate (%u) and format not supported\n",
0896             __func__, params_rate(params));
0897         /* See bellow for details how fix this. */
0898         return -EINVAL;
0899     }
0900     if (bclk_score != 0) {
0901         dev_warn(component->dev, "Can not produce exact bitclock");
0902         /* This is fine if using dsp format, but if using i2s
0903            there may be trouble. To fix the issue edit the
0904            aic31xx_divs table for your mclk and sample
0905            rate. Details can be found from:
0906            https://www.ti.com/lit/ds/symlink/tlv320aic3100.pdf
0907            Section: 5.6 CLOCK Generation and PLL
0908         */
0909     }
0910     i = match;
0911 
0912     /* PLL configuration */
0913     snd_soc_component_update_bits(component, AIC31XX_PLLPR, AIC31XX_PLL_MASK,
0914                 (aic31xx->p_div << 4) | aic31xx_divs[i].pll_r);
0915     snd_soc_component_write(component, AIC31XX_PLLJ, aic31xx_divs[i].pll_j);
0916 
0917     snd_soc_component_write(component, AIC31XX_PLLDMSB,
0918               aic31xx_divs[i].pll_d >> 8);
0919     snd_soc_component_write(component, AIC31XX_PLLDLSB,
0920               aic31xx_divs[i].pll_d & 0xff);
0921 
0922     /* DAC dividers configuration */
0923     snd_soc_component_update_bits(component, AIC31XX_NDAC, AIC31XX_PLL_MASK,
0924                 aic31xx_divs[i].ndac);
0925     snd_soc_component_update_bits(component, AIC31XX_MDAC, AIC31XX_PLL_MASK,
0926                 aic31xx_divs[i].mdac);
0927 
0928     snd_soc_component_write(component, AIC31XX_DOSRMSB, aic31xx_divs[i].dosr >> 8);
0929     snd_soc_component_write(component, AIC31XX_DOSRLSB, aic31xx_divs[i].dosr & 0xff);
0930 
0931     /* ADC dividers configuration. Write reset value 1 if not used. */
0932     snd_soc_component_update_bits(component, AIC31XX_NADC, AIC31XX_PLL_MASK,
0933                 aic31xx_divs[i].nadc ? aic31xx_divs[i].nadc : 1);
0934     snd_soc_component_update_bits(component, AIC31XX_MADC, AIC31XX_PLL_MASK,
0935                 aic31xx_divs[i].madc ? aic31xx_divs[i].madc : 1);
0936 
0937     snd_soc_component_write(component, AIC31XX_AOSR, aic31xx_divs[i].aosr);
0938 
0939     /* Bit clock divider configuration. */
0940     snd_soc_component_update_bits(component, AIC31XX_BCLKN,
0941                 AIC31XX_PLL_MASK, bclk_n);
0942 
0943     aic31xx->rate_div_line = i;
0944 
0945     dev_dbg(component->dev,
0946         "pll %d.%04d/%d dosr %d n %d m %d aosr %d n %d m %d bclk_n %d\n",
0947         aic31xx_divs[i].pll_j,
0948         aic31xx_divs[i].pll_d,
0949         aic31xx->p_div,
0950         aic31xx_divs[i].dosr,
0951         aic31xx_divs[i].ndac,
0952         aic31xx_divs[i].mdac,
0953         aic31xx_divs[i].aosr,
0954         aic31xx_divs[i].nadc,
0955         aic31xx_divs[i].madc,
0956         bclk_n
0957     );
0958 
0959     return 0;
0960 }
0961 
0962 static int aic31xx_hw_params(struct snd_pcm_substream *substream,
0963                  struct snd_pcm_hw_params *params,
0964                  struct snd_soc_dai *dai)
0965 {
0966     struct snd_soc_component *component = dai->component;
0967     struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
0968     u8 data = 0;
0969 
0970     dev_dbg(component->dev, "## %s: width %d rate %d\n",
0971         __func__, params_width(params),
0972         params_rate(params));
0973 
0974     switch (params_width(params)) {
0975     case 16:
0976         break;
0977     case 20:
0978         data = (AIC31XX_WORD_LEN_20BITS <<
0979             AIC31XX_IFACE1_DATALEN_SHIFT);
0980         break;
0981     case 24:
0982         data = (AIC31XX_WORD_LEN_24BITS <<
0983             AIC31XX_IFACE1_DATALEN_SHIFT);
0984         break;
0985     case 32:
0986         data = (AIC31XX_WORD_LEN_32BITS <<
0987             AIC31XX_IFACE1_DATALEN_SHIFT);
0988         break;
0989     default:
0990         dev_err(component->dev, "%s: Unsupported width %d\n",
0991             __func__, params_width(params));
0992         return -EINVAL;
0993     }
0994 
0995     snd_soc_component_update_bits(component, AIC31XX_IFACE1,
0996                 AIC31XX_IFACE1_DATALEN_MASK,
0997                 data);
0998 
0999     /*
1000      * If BCLK is used as PLL input, the sysclk is determined by the hw
1001      * params. So it must be updated here to match the input frequency.
1002      */
1003     if (aic31xx->sysclk_id == AIC31XX_PLL_CLKIN_BCLK) {
1004         aic31xx->sysclk = params_rate(params) * params_width(params) *
1005                   params_channels(params);
1006         aic31xx->p_div = 1;
1007     }
1008 
1009     return aic31xx_setup_pll(component, params);
1010 }
1011 
1012 static int aic31xx_dac_mute(struct snd_soc_dai *codec_dai, int mute,
1013                 int direction)
1014 {
1015     struct snd_soc_component *component = codec_dai->component;
1016 
1017     if (mute) {
1018         snd_soc_component_update_bits(component, AIC31XX_DACMUTE,
1019                     AIC31XX_DACMUTE_MASK,
1020                     AIC31XX_DACMUTE_MASK);
1021     } else {
1022         snd_soc_component_update_bits(component, AIC31XX_DACMUTE,
1023                     AIC31XX_DACMUTE_MASK, 0x0);
1024     }
1025 
1026     return 0;
1027 }
1028 
1029 static int aic31xx_clock_master_routes(struct snd_soc_component *component,
1030                        unsigned int fmt)
1031 {
1032     struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1033     struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
1034     int ret;
1035 
1036     fmt &= SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK;
1037     if (fmt == SND_SOC_DAIFMT_CBC_CFC &&
1038         aic31xx->master_dapm_route_applied) {
1039         /*
1040          * Remove the DAPM route(s) for codec clock master modes,
1041          * if applied
1042          */
1043         ret = snd_soc_dapm_del_routes(dapm, common31xx_cm_audio_map,
1044                     ARRAY_SIZE(common31xx_cm_audio_map));
1045         if (!ret && !(aic31xx->codec_type & DAC31XX_BIT))
1046             ret = snd_soc_dapm_del_routes(dapm,
1047                     aic31xx_cm_audio_map,
1048                     ARRAY_SIZE(aic31xx_cm_audio_map));
1049 
1050         if (ret)
1051             return ret;
1052 
1053         aic31xx->master_dapm_route_applied = false;
1054     } else if (fmt != SND_SOC_DAIFMT_CBC_CFC &&
1055            !aic31xx->master_dapm_route_applied) {
1056         /*
1057          * Add the needed DAPM route(s) for codec clock master modes,
1058          * if it is not done already
1059          */
1060         ret = snd_soc_dapm_add_routes(dapm, common31xx_cm_audio_map,
1061                     ARRAY_SIZE(common31xx_cm_audio_map));
1062         if (!ret && !(aic31xx->codec_type & DAC31XX_BIT))
1063             ret = snd_soc_dapm_add_routes(dapm,
1064                     aic31xx_cm_audio_map,
1065                     ARRAY_SIZE(aic31xx_cm_audio_map));
1066 
1067         if (ret)
1068             return ret;
1069 
1070         aic31xx->master_dapm_route_applied = true;
1071     }
1072 
1073     return 0;
1074 }
1075 
1076 static int aic31xx_set_dai_fmt(struct snd_soc_dai *codec_dai,
1077                    unsigned int fmt)
1078 {
1079     struct snd_soc_component *component = codec_dai->component;
1080     u8 iface_reg1 = 0;
1081     u8 iface_reg2 = 0;
1082     u8 dsp_a_val = 0;
1083 
1084     dev_dbg(component->dev, "## %s: fmt = 0x%x\n", __func__, fmt);
1085 
1086     switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
1087     case SND_SOC_DAIFMT_CBP_CFP:
1088         iface_reg1 |= AIC31XX_BCLK_MASTER | AIC31XX_WCLK_MASTER;
1089         break;
1090     case SND_SOC_DAIFMT_CBC_CFP:
1091         iface_reg1 |= AIC31XX_WCLK_MASTER;
1092         break;
1093     case SND_SOC_DAIFMT_CBP_CFC:
1094         iface_reg1 |= AIC31XX_BCLK_MASTER;
1095         break;
1096     case SND_SOC_DAIFMT_CBC_CFC:
1097         break;
1098     default:
1099         dev_err(component->dev, "Invalid DAI clock provider\n");
1100         return -EINVAL;
1101     }
1102 
1103     /* signal polarity */
1104     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1105     case SND_SOC_DAIFMT_NB_NF:
1106         break;
1107     case SND_SOC_DAIFMT_IB_NF:
1108         iface_reg2 |= AIC31XX_BCLKINV_MASK;
1109         break;
1110     default:
1111         dev_err(component->dev, "Invalid DAI clock signal polarity\n");
1112         return -EINVAL;
1113     }
1114 
1115     /* interface format */
1116     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1117     case SND_SOC_DAIFMT_I2S:
1118         break;
1119     case SND_SOC_DAIFMT_DSP_A:
1120         dsp_a_val = 0x1;
1121         fallthrough;
1122     case SND_SOC_DAIFMT_DSP_B:
1123         /*
1124          * NOTE: This CODEC samples on the falling edge of BCLK in
1125          * DSP mode, this is inverted compared to what most DAIs
1126          * expect, so we invert for this mode
1127          */
1128         iface_reg2 ^= AIC31XX_BCLKINV_MASK;
1129         iface_reg1 |= (AIC31XX_DSP_MODE <<
1130                    AIC31XX_IFACE1_DATATYPE_SHIFT);
1131         break;
1132     case SND_SOC_DAIFMT_RIGHT_J:
1133         iface_reg1 |= (AIC31XX_RIGHT_JUSTIFIED_MODE <<
1134                    AIC31XX_IFACE1_DATATYPE_SHIFT);
1135         break;
1136     case SND_SOC_DAIFMT_LEFT_J:
1137         iface_reg1 |= (AIC31XX_LEFT_JUSTIFIED_MODE <<
1138                    AIC31XX_IFACE1_DATATYPE_SHIFT);
1139         break;
1140     default:
1141         dev_err(component->dev, "Invalid DAI interface format\n");
1142         return -EINVAL;
1143     }
1144 
1145     snd_soc_component_update_bits(component, AIC31XX_IFACE1,
1146                 AIC31XX_IFACE1_DATATYPE_MASK |
1147                 AIC31XX_IFACE1_MASTER_MASK,
1148                 iface_reg1);
1149     snd_soc_component_update_bits(component, AIC31XX_DATA_OFFSET,
1150                 AIC31XX_DATA_OFFSET_MASK,
1151                 dsp_a_val);
1152     snd_soc_component_update_bits(component, AIC31XX_IFACE2,
1153                 AIC31XX_BCLKINV_MASK,
1154                 iface_reg2);
1155 
1156     return aic31xx_clock_master_routes(component, fmt);
1157 }
1158 
1159 static int aic31xx_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1160                   int clk_id, unsigned int freq, int dir)
1161 {
1162     struct snd_soc_component *component = codec_dai->component;
1163     struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
1164     int i;
1165 
1166     dev_dbg(component->dev, "## %s: clk_id = %d, freq = %d, dir = %d\n",
1167         __func__, clk_id, freq, dir);
1168 
1169     for (i = 1; i < 8; i++)
1170         if (freq / i <= 20000000)
1171             break;
1172     if (freq/i > 20000000) {
1173         dev_err(aic31xx->dev, "%s: Too high mclk frequency %u\n",
1174             __func__, freq);
1175         return -EINVAL;
1176     }
1177     aic31xx->p_div = i;
1178 
1179     for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++)
1180         if (aic31xx_divs[i].mclk_p == freq / aic31xx->p_div)
1181             break;
1182     if (i == ARRAY_SIZE(aic31xx_divs)) {
1183         dev_err(aic31xx->dev, "%s: Unsupported frequency %d\n",
1184             __func__, freq);
1185         return -EINVAL;
1186     }
1187 
1188     /* set clock on MCLK, BCLK, or GPIO1 as PLL input */
1189     snd_soc_component_update_bits(component, AIC31XX_CLKMUX, AIC31XX_PLL_CLKIN_MASK,
1190                 clk_id << AIC31XX_PLL_CLKIN_SHIFT);
1191 
1192     aic31xx->sysclk_id = clk_id;
1193     aic31xx->sysclk = freq;
1194 
1195     return 0;
1196 }
1197 
1198 static int aic31xx_regulator_event(struct notifier_block *nb,
1199                    unsigned long event, void *data)
1200 {
1201     struct aic31xx_disable_nb *disable_nb =
1202         container_of(nb, struct aic31xx_disable_nb, nb);
1203     struct aic31xx_priv *aic31xx = disable_nb->aic31xx;
1204 
1205     if (event & REGULATOR_EVENT_DISABLE) {
1206         /*
1207          * Put codec to reset and as at least one of the
1208          * supplies was disabled.
1209          */
1210         if (aic31xx->gpio_reset)
1211             gpiod_set_value(aic31xx->gpio_reset, 1);
1212 
1213         regcache_mark_dirty(aic31xx->regmap);
1214         dev_dbg(aic31xx->dev, "## %s: DISABLE received\n", __func__);
1215     }
1216 
1217     return 0;
1218 }
1219 
1220 static int aic31xx_reset(struct aic31xx_priv *aic31xx)
1221 {
1222     int ret = 0;
1223 
1224     if (aic31xx->gpio_reset) {
1225         gpiod_set_value(aic31xx->gpio_reset, 1);
1226         ndelay(10); /* At least 10ns */
1227         gpiod_set_value(aic31xx->gpio_reset, 0);
1228     } else {
1229         ret = regmap_write(aic31xx->regmap, AIC31XX_RESET, 1);
1230     }
1231     mdelay(1); /* At least 1ms */
1232 
1233     return ret;
1234 }
1235 
1236 static void aic31xx_clk_on(struct snd_soc_component *component)
1237 {
1238     struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
1239     u8 mask = AIC31XX_PM_MASK;
1240     u8 on = AIC31XX_PM_MASK;
1241 
1242     dev_dbg(component->dev, "codec clock -> on (rate %d)\n",
1243         aic31xx_divs[aic31xx->rate_div_line].rate);
1244     snd_soc_component_update_bits(component, AIC31XX_PLLPR, mask, on);
1245     mdelay(10);
1246     snd_soc_component_update_bits(component, AIC31XX_NDAC, mask, on);
1247     snd_soc_component_update_bits(component, AIC31XX_MDAC, mask, on);
1248     if (aic31xx_divs[aic31xx->rate_div_line].nadc)
1249         snd_soc_component_update_bits(component, AIC31XX_NADC, mask, on);
1250     if (aic31xx_divs[aic31xx->rate_div_line].madc)
1251         snd_soc_component_update_bits(component, AIC31XX_MADC, mask, on);
1252     snd_soc_component_update_bits(component, AIC31XX_BCLKN, mask, on);
1253 }
1254 
1255 static void aic31xx_clk_off(struct snd_soc_component *component)
1256 {
1257     u8 mask = AIC31XX_PM_MASK;
1258     u8 off = 0;
1259 
1260     dev_dbg(component->dev, "codec clock -> off\n");
1261     snd_soc_component_update_bits(component, AIC31XX_BCLKN, mask, off);
1262     snd_soc_component_update_bits(component, AIC31XX_MADC, mask, off);
1263     snd_soc_component_update_bits(component, AIC31XX_NADC, mask, off);
1264     snd_soc_component_update_bits(component, AIC31XX_MDAC, mask, off);
1265     snd_soc_component_update_bits(component, AIC31XX_NDAC, mask, off);
1266     snd_soc_component_update_bits(component, AIC31XX_PLLPR, mask, off);
1267 }
1268 
1269 static int aic31xx_power_on(struct snd_soc_component *component)
1270 {
1271     struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
1272     int ret;
1273 
1274     ret = regulator_bulk_enable(ARRAY_SIZE(aic31xx->supplies),
1275                     aic31xx->supplies);
1276     if (ret)
1277         return ret;
1278 
1279     regcache_cache_only(aic31xx->regmap, false);
1280 
1281     /* Reset device registers for a consistent power-on like state */
1282     ret = aic31xx_reset(aic31xx);
1283     if (ret < 0)
1284         dev_err(aic31xx->dev, "Could not reset device: %d\n", ret);
1285 
1286     ret = regcache_sync(aic31xx->regmap);
1287     if (ret) {
1288         dev_err(component->dev,
1289             "Failed to restore cache: %d\n", ret);
1290         regcache_cache_only(aic31xx->regmap, true);
1291         regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies),
1292                        aic31xx->supplies);
1293         return ret;
1294     }
1295 
1296     /*
1297      * The jack detection configuration is in the same register
1298      * that is used to report jack detect status so is volatile
1299      * and not covered by the cache sync, restore it separately.
1300      */
1301     aic31xx_set_jack(component, aic31xx->jack, NULL);
1302 
1303     return 0;
1304 }
1305 
1306 static void aic31xx_power_off(struct snd_soc_component *component)
1307 {
1308     struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
1309 
1310     regcache_cache_only(aic31xx->regmap, true);
1311     regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies),
1312                    aic31xx->supplies);
1313 }
1314 
1315 static int aic31xx_set_bias_level(struct snd_soc_component *component,
1316                   enum snd_soc_bias_level level)
1317 {
1318     dev_dbg(component->dev, "## %s: %d -> %d\n", __func__,
1319         snd_soc_component_get_bias_level(component), level);
1320 
1321     switch (level) {
1322     case SND_SOC_BIAS_ON:
1323         break;
1324     case SND_SOC_BIAS_PREPARE:
1325         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY)
1326             aic31xx_clk_on(component);
1327         break;
1328     case SND_SOC_BIAS_STANDBY:
1329         switch (snd_soc_component_get_bias_level(component)) {
1330         case SND_SOC_BIAS_OFF:
1331             aic31xx_power_on(component);
1332             break;
1333         case SND_SOC_BIAS_PREPARE:
1334             aic31xx_clk_off(component);
1335             break;
1336         default:
1337             BUG();
1338         }
1339         break;
1340     case SND_SOC_BIAS_OFF:
1341         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY)
1342             aic31xx_power_off(component);
1343         break;
1344     }
1345 
1346     return 0;
1347 }
1348 
1349 static int aic31xx_set_jack(struct snd_soc_component *component,
1350                 struct snd_soc_jack *jack, void *data)
1351 {
1352     struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
1353 
1354     aic31xx->jack = jack;
1355 
1356     /* Enable/Disable jack detection */
1357     regmap_write(aic31xx->regmap, AIC31XX_HSDETECT,
1358              jack ? AIC31XX_HSD_ENABLE : 0);
1359 
1360     return 0;
1361 }
1362 
1363 static int aic31xx_codec_probe(struct snd_soc_component *component)
1364 {
1365     struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
1366     int i, ret;
1367 
1368     dev_dbg(aic31xx->dev, "## %s\n", __func__);
1369 
1370     aic31xx->component = component;
1371 
1372     for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++) {
1373         aic31xx->disable_nb[i].nb.notifier_call =
1374             aic31xx_regulator_event;
1375         aic31xx->disable_nb[i].aic31xx = aic31xx;
1376         ret = devm_regulator_register_notifier(
1377                         aic31xx->supplies[i].consumer,
1378                         &aic31xx->disable_nb[i].nb);
1379         if (ret) {
1380             dev_err(component->dev,
1381                 "Failed to request regulator notifier: %d\n",
1382                 ret);
1383             return ret;
1384         }
1385     }
1386 
1387     regcache_cache_only(aic31xx->regmap, true);
1388     regcache_mark_dirty(aic31xx->regmap);
1389 
1390     ret = aic31xx_add_controls(component);
1391     if (ret)
1392         return ret;
1393 
1394     ret = aic31xx_add_widgets(component);
1395     if (ret)
1396         return ret;
1397 
1398     /* set output common-mode voltage */
1399     snd_soc_component_update_bits(component, AIC31XX_HPDRIVER,
1400                       AIC31XX_HPD_OCMV_MASK,
1401                       aic31xx->ocmv << AIC31XX_HPD_OCMV_SHIFT);
1402 
1403     return 0;
1404 }
1405 
1406 static const struct snd_soc_component_driver soc_codec_driver_aic31xx = {
1407     .probe          = aic31xx_codec_probe,
1408     .set_jack       = aic31xx_set_jack,
1409     .set_bias_level     = aic31xx_set_bias_level,
1410     .controls       = common31xx_snd_controls,
1411     .num_controls       = ARRAY_SIZE(common31xx_snd_controls),
1412     .dapm_widgets       = common31xx_dapm_widgets,
1413     .num_dapm_widgets   = ARRAY_SIZE(common31xx_dapm_widgets),
1414     .dapm_routes        = common31xx_audio_map,
1415     .num_dapm_routes    = ARRAY_SIZE(common31xx_audio_map),
1416     .suspend_bias_off   = 1,
1417     .idle_bias_on       = 1,
1418     .use_pmdown_time    = 1,
1419     .endianness     = 1,
1420 };
1421 
1422 static const struct snd_soc_dai_ops aic31xx_dai_ops = {
1423     .hw_params  = aic31xx_hw_params,
1424     .set_sysclk = aic31xx_set_dai_sysclk,
1425     .set_fmt    = aic31xx_set_dai_fmt,
1426     .mute_stream    = aic31xx_dac_mute,
1427     .no_capture_mute = 1,
1428 };
1429 
1430 static struct snd_soc_dai_driver dac31xx_dai_driver[] = {
1431     {
1432         .name = "tlv320dac31xx-hifi",
1433         .playback = {
1434             .stream_name     = "Playback",
1435             .channels_min    = 2,
1436             .channels_max    = 2,
1437             .rates       = AIC31XX_RATES,
1438             .formats     = AIC31XX_FORMATS,
1439         },
1440         .ops = &aic31xx_dai_ops,
1441         .symmetric_rate = 1,
1442     }
1443 };
1444 
1445 static struct snd_soc_dai_driver aic31xx_dai_driver[] = {
1446     {
1447         .name = "tlv320aic31xx-hifi",
1448         .playback = {
1449             .stream_name     = "Playback",
1450             .channels_min    = 2,
1451             .channels_max    = 2,
1452             .rates       = AIC31XX_RATES,
1453             .formats     = AIC31XX_FORMATS,
1454         },
1455         .capture = {
1456             .stream_name     = "Capture",
1457             .channels_min    = 2,
1458             .channels_max    = 2,
1459             .rates       = AIC31XX_RATES,
1460             .formats     = AIC31XX_FORMATS,
1461         },
1462         .ops = &aic31xx_dai_ops,
1463         .symmetric_rate = 1,
1464     }
1465 };
1466 
1467 #if defined(CONFIG_OF)
1468 static const struct of_device_id tlv320aic31xx_of_match[] = {
1469     { .compatible = "ti,tlv320aic310x" },
1470     { .compatible = "ti,tlv320aic311x" },
1471     { .compatible = "ti,tlv320aic3100" },
1472     { .compatible = "ti,tlv320aic3110" },
1473     { .compatible = "ti,tlv320aic3120" },
1474     { .compatible = "ti,tlv320aic3111" },
1475     { .compatible = "ti,tlv320dac3100" },
1476     { .compatible = "ti,tlv320dac3101" },
1477     {},
1478 };
1479 MODULE_DEVICE_TABLE(of, tlv320aic31xx_of_match);
1480 #endif /* CONFIG_OF */
1481 
1482 #ifdef CONFIG_ACPI
1483 static const struct acpi_device_id aic31xx_acpi_match[] = {
1484     { "10TI3100", 0 },
1485     { }
1486 };
1487 MODULE_DEVICE_TABLE(acpi, aic31xx_acpi_match);
1488 #endif
1489 
1490 static irqreturn_t aic31xx_irq(int irq, void *data)
1491 {
1492     struct aic31xx_priv *aic31xx = data;
1493     struct device *dev = aic31xx->dev;
1494     unsigned int value;
1495     bool handled = false;
1496     int ret;
1497 
1498     ret = regmap_read(aic31xx->regmap, AIC31XX_INTRDACFLAG, &value);
1499     if (ret) {
1500         dev_err(dev, "Failed to read interrupt mask: %d\n", ret);
1501         goto exit;
1502     }
1503 
1504     if (value)
1505         handled = true;
1506     else
1507         goto read_overflow;
1508 
1509     if (value & AIC31XX_HPLSCDETECT)
1510         dev_err(dev, "Short circuit on Left output is detected\n");
1511     if (value & AIC31XX_HPRSCDETECT)
1512         dev_err(dev, "Short circuit on Right output is detected\n");
1513     if (value & (AIC31XX_HSPLUG | AIC31XX_BUTTONPRESS)) {
1514         unsigned int val;
1515         int status = 0;
1516 
1517         ret = regmap_read(aic31xx->regmap, AIC31XX_INTRDACFLAG2,
1518                   &val);
1519         if (ret) {
1520             dev_err(dev, "Failed to read interrupt mask: %d\n",
1521                 ret);
1522             goto exit;
1523         }
1524 
1525         if (val & AIC31XX_BUTTONPRESS)
1526             status |= SND_JACK_BTN_0;
1527 
1528         ret = regmap_read(aic31xx->regmap, AIC31XX_HSDETECT, &val);
1529         if (ret) {
1530             dev_err(dev, "Failed to read headset type: %d\n", ret);
1531             goto exit;
1532         }
1533 
1534         switch ((val & AIC31XX_HSD_TYPE_MASK) >>
1535             AIC31XX_HSD_TYPE_SHIFT) {
1536         case AIC31XX_HSD_HP:
1537             status |= SND_JACK_HEADPHONE;
1538             break;
1539         case AIC31XX_HSD_HS:
1540             status |= SND_JACK_HEADSET;
1541             break;
1542         default:
1543             break;
1544         }
1545 
1546         if (aic31xx->jack)
1547             snd_soc_jack_report(aic31xx->jack, status,
1548                         AIC31XX_JACK_MASK);
1549     }
1550     if (value & ~(AIC31XX_HPLSCDETECT |
1551               AIC31XX_HPRSCDETECT |
1552               AIC31XX_HSPLUG |
1553               AIC31XX_BUTTONPRESS))
1554         dev_err(dev, "Unknown DAC interrupt flags: 0x%08x\n", value);
1555 
1556 read_overflow:
1557     ret = regmap_read(aic31xx->regmap, AIC31XX_OFFLAG, &value);
1558     if (ret) {
1559         dev_err(dev, "Failed to read overflow flag: %d\n", ret);
1560         goto exit;
1561     }
1562 
1563     if (value)
1564         handled = true;
1565     else
1566         goto exit;
1567 
1568     if (value & AIC31XX_DAC_OF_LEFT)
1569         dev_warn(dev, "Left-channel DAC overflow has occurred\n");
1570     if (value & AIC31XX_DAC_OF_RIGHT)
1571         dev_warn(dev, "Right-channel DAC overflow has occurred\n");
1572     if (value & AIC31XX_DAC_OF_SHIFTER)
1573         dev_warn(dev, "DAC barrel shifter overflow has occurred\n");
1574     if (value & AIC31XX_ADC_OF)
1575         dev_warn(dev, "ADC overflow has occurred\n");
1576     if (value & AIC31XX_ADC_OF_SHIFTER)
1577         dev_warn(dev, "ADC barrel shifter overflow has occurred\n");
1578     if (value & ~(AIC31XX_DAC_OF_LEFT |
1579               AIC31XX_DAC_OF_RIGHT |
1580               AIC31XX_DAC_OF_SHIFTER |
1581               AIC31XX_ADC_OF |
1582               AIC31XX_ADC_OF_SHIFTER))
1583         dev_warn(dev, "Unknown overflow interrupt flags: 0x%08x\n", value);
1584 
1585 exit:
1586     if (handled)
1587         return IRQ_HANDLED;
1588     else
1589         return IRQ_NONE;
1590 }
1591 
1592 static void aic31xx_configure_ocmv(struct aic31xx_priv *priv)
1593 {
1594     struct device *dev = priv->dev;
1595     int dvdd, avdd;
1596     u32 value;
1597 
1598     if (dev->fwnode &&
1599         fwnode_property_read_u32(dev->fwnode, "ai31xx-ocmv", &value)) {
1600         /* OCMV setting is forced by DT */
1601         if (value <= 3) {
1602             priv->ocmv = value;
1603             return;
1604         }
1605     }
1606 
1607     avdd = regulator_get_voltage(priv->supplies[3].consumer);
1608     dvdd = regulator_get_voltage(priv->supplies[5].consumer);
1609 
1610     if (avdd > 3600000 || dvdd > 1950000) {
1611         dev_warn(dev,
1612              "Too high supply voltage(s) AVDD: %d, DVDD: %d\n",
1613              avdd, dvdd);
1614     } else if (avdd == 3600000 && dvdd == 1950000) {
1615         priv->ocmv = AIC31XX_HPD_OCMV_1_8V;
1616     } else if (avdd >= 3300000 && dvdd >= 1800000) {
1617         priv->ocmv = AIC31XX_HPD_OCMV_1_65V;
1618     } else if (avdd >= 3000000 && dvdd >= 1650000) {
1619         priv->ocmv = AIC31XX_HPD_OCMV_1_5V;
1620     } else if (avdd >= 2700000 && dvdd >= 1525000) {
1621         priv->ocmv = AIC31XX_HPD_OCMV_1_35V;
1622     } else {
1623         dev_warn(dev,
1624              "Invalid supply voltage(s) AVDD: %d, DVDD: %d\n",
1625              avdd, dvdd);
1626     }
1627 }
1628 
1629 static const struct i2c_device_id aic31xx_i2c_id[] = {
1630     { "tlv320aic310x", AIC3100 },
1631     { "tlv320aic311x", AIC3110 },
1632     { "tlv320aic3100", AIC3100 },
1633     { "tlv320aic3110", AIC3110 },
1634     { "tlv320aic3120", AIC3120 },
1635     { "tlv320aic3111", AIC3111 },
1636     { "tlv320dac3100", DAC3100 },
1637     { "tlv320dac3101", DAC3101 },
1638     { }
1639 };
1640 MODULE_DEVICE_TABLE(i2c, aic31xx_i2c_id);
1641 
1642 static int aic31xx_i2c_probe(struct i2c_client *i2c)
1643 {
1644     struct aic31xx_priv *aic31xx;
1645     unsigned int micbias_value = MICBIAS_2_0V;
1646     const struct i2c_device_id *id = i2c_match_id(aic31xx_i2c_id, i2c);
1647     int i, ret;
1648 
1649     dev_dbg(&i2c->dev, "## %s: %s codec_type = %d\n", __func__,
1650         id->name, (int)id->driver_data);
1651 
1652     aic31xx = devm_kzalloc(&i2c->dev, sizeof(*aic31xx), GFP_KERNEL);
1653     if (!aic31xx)
1654         return -ENOMEM;
1655 
1656     aic31xx->regmap = devm_regmap_init_i2c(i2c, &aic31xx_i2c_regmap);
1657     if (IS_ERR(aic31xx->regmap)) {
1658         ret = PTR_ERR(aic31xx->regmap);
1659         dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1660             ret);
1661         return ret;
1662     }
1663     regcache_cache_only(aic31xx->regmap, true);
1664 
1665     aic31xx->dev = &i2c->dev;
1666     aic31xx->irq = i2c->irq;
1667 
1668     aic31xx->codec_type = id->driver_data;
1669 
1670     dev_set_drvdata(aic31xx->dev, aic31xx);
1671 
1672     fwnode_property_read_u32(aic31xx->dev->fwnode, "ai31xx-micbias-vg",
1673                  &micbias_value);
1674     switch (micbias_value) {
1675     case MICBIAS_2_0V:
1676     case MICBIAS_2_5V:
1677     case MICBIAS_AVDDV:
1678         aic31xx->micbias_vg = micbias_value;
1679         break;
1680     default:
1681         dev_err(aic31xx->dev, "Bad ai31xx-micbias-vg value %d\n",
1682             micbias_value);
1683         aic31xx->micbias_vg = MICBIAS_2_0V;
1684     }
1685 
1686     if (dev_get_platdata(aic31xx->dev)) {
1687         memcpy(&aic31xx->pdata, dev_get_platdata(aic31xx->dev), sizeof(aic31xx->pdata));
1688         aic31xx->codec_type = aic31xx->pdata.codec_type;
1689         aic31xx->micbias_vg = aic31xx->pdata.micbias_vg;
1690     }
1691 
1692     aic31xx->gpio_reset = devm_gpiod_get_optional(aic31xx->dev, "reset",
1693                               GPIOD_OUT_LOW);
1694     if (IS_ERR(aic31xx->gpio_reset))
1695         return dev_err_probe(aic31xx->dev, PTR_ERR(aic31xx->gpio_reset),
1696                      "not able to acquire gpio\n");
1697 
1698     for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++)
1699         aic31xx->supplies[i].supply = aic31xx_supply_names[i];
1700 
1701     ret = devm_regulator_bulk_get(aic31xx->dev,
1702                       ARRAY_SIZE(aic31xx->supplies),
1703                       aic31xx->supplies);
1704     if (ret)
1705         return dev_err_probe(aic31xx->dev, ret, "Failed to request supplies\n");
1706 
1707     aic31xx_configure_ocmv(aic31xx);
1708 
1709     if (aic31xx->irq > 0) {
1710         regmap_update_bits(aic31xx->regmap, AIC31XX_GPIO1,
1711                    AIC31XX_GPIO1_FUNC_MASK,
1712                    AIC31XX_GPIO1_INT1 <<
1713                    AIC31XX_GPIO1_FUNC_SHIFT);
1714 
1715         regmap_write(aic31xx->regmap, AIC31XX_INT1CTRL,
1716                  AIC31XX_HSPLUGDET |
1717                  AIC31XX_BUTTONPRESSDET |
1718                  AIC31XX_SC |
1719                  AIC31XX_ENGINE);
1720 
1721         ret = devm_request_threaded_irq(aic31xx->dev, aic31xx->irq,
1722                         NULL, aic31xx_irq,
1723                         IRQF_ONESHOT, "aic31xx-irq",
1724                         aic31xx);
1725         if (ret) {
1726             dev_err(aic31xx->dev, "Unable to request IRQ\n");
1727             return ret;
1728         }
1729     }
1730 
1731     if (aic31xx->codec_type & DAC31XX_BIT)
1732         return devm_snd_soc_register_component(&i2c->dev,
1733                 &soc_codec_driver_aic31xx,
1734                 dac31xx_dai_driver,
1735                 ARRAY_SIZE(dac31xx_dai_driver));
1736     else
1737         return devm_snd_soc_register_component(&i2c->dev,
1738                 &soc_codec_driver_aic31xx,
1739                 aic31xx_dai_driver,
1740                 ARRAY_SIZE(aic31xx_dai_driver));
1741 }
1742 
1743 static struct i2c_driver aic31xx_i2c_driver = {
1744     .driver = {
1745         .name   = "tlv320aic31xx-codec",
1746         .of_match_table = of_match_ptr(tlv320aic31xx_of_match),
1747         .acpi_match_table = ACPI_PTR(aic31xx_acpi_match),
1748     },
1749     .probe_new  = aic31xx_i2c_probe,
1750     .id_table   = aic31xx_i2c_id,
1751 };
1752 module_i2c_driver(aic31xx_i2c_driver);
1753 
1754 MODULE_AUTHOR("Jyri Sarha <jsarha@ti.com>");
1755 MODULE_DESCRIPTION("ASoC TLV320AIC31xx CODEC Driver");
1756 MODULE_LICENSE("GPL v2");
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