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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 // TLV320ADCX140 Sound driver
0003 // Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
0004 
0005 #include <linux/module.h>
0006 #include <linux/moduleparam.h>
0007 #include <linux/init.h>
0008 #include <linux/delay.h>
0009 #include <linux/pm.h>
0010 #include <linux/i2c.h>
0011 #include <linux/gpio/consumer.h>
0012 #include <linux/regulator/consumer.h>
0013 #include <linux/acpi.h>
0014 #include <linux/of.h>
0015 #include <linux/of_gpio.h>
0016 #include <linux/slab.h>
0017 #include <sound/core.h>
0018 #include <sound/pcm.h>
0019 #include <sound/pcm_params.h>
0020 #include <sound/soc.h>
0021 #include <sound/initval.h>
0022 #include <sound/tlv.h>
0023 
0024 #include "tlv320adcx140.h"
0025 
0026 struct adcx140_priv {
0027     struct snd_soc_component *component;
0028     struct regulator *supply_areg;
0029     struct gpio_desc *gpio_reset;
0030     struct regmap *regmap;
0031     struct device *dev;
0032 
0033     bool micbias_vg;
0034 
0035     unsigned int dai_fmt;
0036     unsigned int slot_width;
0037 };
0038 
0039 static const char * const gpo_config_names[] = {
0040     "ti,gpo-config-1",
0041     "ti,gpo-config-2",
0042     "ti,gpo-config-3",
0043     "ti,gpo-config-4",
0044 };
0045 
0046 static const struct reg_default adcx140_reg_defaults[] = {
0047     { ADCX140_PAGE_SELECT, 0x00 },
0048     { ADCX140_SW_RESET, 0x00 },
0049     { ADCX140_SLEEP_CFG, 0x00 },
0050     { ADCX140_SHDN_CFG, 0x05 },
0051     { ADCX140_ASI_CFG0, 0x30 },
0052     { ADCX140_ASI_CFG1, 0x00 },
0053     { ADCX140_ASI_CFG2, 0x00 },
0054     { ADCX140_ASI_CH1, 0x00 },
0055     { ADCX140_ASI_CH2, 0x01 },
0056     { ADCX140_ASI_CH3, 0x02 },
0057     { ADCX140_ASI_CH4, 0x03 },
0058     { ADCX140_ASI_CH5, 0x04 },
0059     { ADCX140_ASI_CH6, 0x05 },
0060     { ADCX140_ASI_CH7, 0x06 },
0061     { ADCX140_ASI_CH8, 0x07 },
0062     { ADCX140_MST_CFG0, 0x02 },
0063     { ADCX140_MST_CFG1, 0x48 },
0064     { ADCX140_ASI_STS, 0xff },
0065     { ADCX140_CLK_SRC, 0x10 },
0066     { ADCX140_PDMCLK_CFG, 0x40 },
0067     { ADCX140_PDM_CFG, 0x00 },
0068     { ADCX140_GPIO_CFG0, 0x22 },
0069     { ADCX140_GPO_CFG0, 0x00 },
0070     { ADCX140_GPO_CFG1, 0x00 },
0071     { ADCX140_GPO_CFG2, 0x00 },
0072     { ADCX140_GPO_CFG3, 0x00 },
0073     { ADCX140_GPO_VAL, 0x00 },
0074     { ADCX140_GPIO_MON, 0x00 },
0075     { ADCX140_GPI_CFG0, 0x00 },
0076     { ADCX140_GPI_CFG1, 0x00 },
0077     { ADCX140_GPI_MON, 0x00 },
0078     { ADCX140_INT_CFG, 0x00 },
0079     { ADCX140_INT_MASK0, 0xff },
0080     { ADCX140_INT_LTCH0, 0x00 },
0081     { ADCX140_BIAS_CFG, 0x00 },
0082     { ADCX140_CH1_CFG0, 0x00 },
0083     { ADCX140_CH1_CFG1, 0x00 },
0084     { ADCX140_CH1_CFG2, 0xc9 },
0085     { ADCX140_CH1_CFG3, 0x80 },
0086     { ADCX140_CH1_CFG4, 0x00 },
0087     { ADCX140_CH2_CFG0, 0x00 },
0088     { ADCX140_CH2_CFG1, 0x00 },
0089     { ADCX140_CH2_CFG2, 0xc9 },
0090     { ADCX140_CH2_CFG3, 0x80 },
0091     { ADCX140_CH2_CFG4, 0x00 },
0092     { ADCX140_CH3_CFG0, 0x00 },
0093     { ADCX140_CH3_CFG1, 0x00 },
0094     { ADCX140_CH3_CFG2, 0xc9 },
0095     { ADCX140_CH3_CFG3, 0x80 },
0096     { ADCX140_CH3_CFG4, 0x00 },
0097     { ADCX140_CH4_CFG0, 0x00 },
0098     { ADCX140_CH4_CFG1, 0x00 },
0099     { ADCX140_CH4_CFG2, 0xc9 },
0100     { ADCX140_CH4_CFG3, 0x80 },
0101     { ADCX140_CH4_CFG4, 0x00 },
0102     { ADCX140_CH5_CFG2, 0xc9 },
0103     { ADCX140_CH5_CFG3, 0x80 },
0104     { ADCX140_CH5_CFG4, 0x00 },
0105     { ADCX140_CH6_CFG2, 0xc9 },
0106     { ADCX140_CH6_CFG3, 0x80 },
0107     { ADCX140_CH6_CFG4, 0x00 },
0108     { ADCX140_CH7_CFG2, 0xc9 },
0109     { ADCX140_CH7_CFG3, 0x80 },
0110     { ADCX140_CH7_CFG4, 0x00 },
0111     { ADCX140_CH8_CFG2, 0xc9 },
0112     { ADCX140_CH8_CFG3, 0x80 },
0113     { ADCX140_CH8_CFG4, 0x00 },
0114     { ADCX140_DSP_CFG0, 0x01 },
0115     { ADCX140_DSP_CFG1, 0x40 },
0116     { ADCX140_DRE_CFG0, 0x7b },
0117     { ADCX140_AGC_CFG0, 0xe7 },
0118     { ADCX140_IN_CH_EN, 0xf0 },
0119     { ADCX140_ASI_OUT_CH_EN, 0x00 },
0120     { ADCX140_PWR_CFG, 0x00 },
0121     { ADCX140_DEV_STS0, 0x00 },
0122     { ADCX140_DEV_STS1, 0x80 },
0123 };
0124 
0125 static const struct regmap_range_cfg adcx140_ranges[] = {
0126     {
0127         .range_min = 0,
0128         .range_max = 12 * 128,
0129         .selector_reg = ADCX140_PAGE_SELECT,
0130         .selector_mask = 0xff,
0131         .selector_shift = 0,
0132         .window_start = 0,
0133         .window_len = 128,
0134     },
0135 };
0136 
0137 static bool adcx140_volatile(struct device *dev, unsigned int reg)
0138 {
0139     switch (reg) {
0140     case ADCX140_SW_RESET:
0141     case ADCX140_DEV_STS0:
0142     case ADCX140_DEV_STS1:
0143     case ADCX140_ASI_STS:
0144         return true;
0145     default:
0146         return false;
0147     }
0148 }
0149 
0150 static const struct regmap_config adcx140_i2c_regmap = {
0151     .reg_bits = 8,
0152     .val_bits = 8,
0153     .reg_defaults = adcx140_reg_defaults,
0154     .num_reg_defaults = ARRAY_SIZE(adcx140_reg_defaults),
0155     .cache_type = REGCACHE_FLAT,
0156     .ranges = adcx140_ranges,
0157     .num_ranges = ARRAY_SIZE(adcx140_ranges),
0158     .max_register = 12 * 128,
0159     .volatile_reg = adcx140_volatile,
0160 };
0161 
0162 /* Digital Volume control. From -100 to 27 dB in 0.5 dB steps */
0163 static DECLARE_TLV_DB_SCALE(dig_vol_tlv, -10050, 50, 0);
0164 
0165 /* ADC gain. From 0 to 42 dB in 1 dB steps */
0166 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 100, 0);
0167 
0168 /* DRE Level. From -12 dB to -66 dB in 1 dB steps */
0169 static DECLARE_TLV_DB_SCALE(dre_thresh_tlv, -6600, 100, 0);
0170 /* DRE Max Gain. From 2 dB to 26 dB in 2 dB steps */
0171 static DECLARE_TLV_DB_SCALE(dre_gain_tlv, 200, 200, 0);
0172 
0173 /* AGC Level. From -6 dB to -36 dB in 2 dB steps */
0174 static DECLARE_TLV_DB_SCALE(agc_thresh_tlv, -3600, 200, 0);
0175 /* AGC Max Gain. From 3 dB to 42 dB in 3 dB steps */
0176 static DECLARE_TLV_DB_SCALE(agc_gain_tlv, 300, 300, 0);
0177 
0178 static const char * const decimation_filter_text[] = {
0179     "Linear Phase", "Low Latency", "Ultra-low Latency"
0180 };
0181 
0182 static SOC_ENUM_SINGLE_DECL(decimation_filter_enum, ADCX140_DSP_CFG0, 4,
0183                 decimation_filter_text);
0184 
0185 static const struct snd_kcontrol_new decimation_filter_controls[] = {
0186     SOC_DAPM_ENUM("Decimation Filter", decimation_filter_enum),
0187 };
0188 
0189 static const char * const pdmclk_text[] = {
0190     "2.8224 MHz", "1.4112 MHz", "705.6 kHz", "5.6448 MHz"
0191 };
0192 
0193 static SOC_ENUM_SINGLE_DECL(pdmclk_select_enum, ADCX140_PDMCLK_CFG, 0,
0194                 pdmclk_text);
0195 
0196 static const struct snd_kcontrol_new pdmclk_div_controls[] = {
0197     SOC_DAPM_ENUM("PDM Clk Divider Select", pdmclk_select_enum),
0198 };
0199 
0200 static const char * const resistor_text[] = {
0201     "2.5 kOhm", "10 kOhm", "20 kOhm"
0202 };
0203 
0204 static SOC_ENUM_SINGLE_DECL(in1_resistor_enum, ADCX140_CH1_CFG0, 2,
0205                 resistor_text);
0206 static SOC_ENUM_SINGLE_DECL(in2_resistor_enum, ADCX140_CH2_CFG0, 2,
0207                 resistor_text);
0208 static SOC_ENUM_SINGLE_DECL(in3_resistor_enum, ADCX140_CH3_CFG0, 2,
0209                 resistor_text);
0210 static SOC_ENUM_SINGLE_DECL(in4_resistor_enum, ADCX140_CH4_CFG0, 2,
0211                 resistor_text);
0212 
0213 static const struct snd_kcontrol_new in1_resistor_controls[] = {
0214     SOC_DAPM_ENUM("CH1 Resistor Select", in1_resistor_enum),
0215 };
0216 static const struct snd_kcontrol_new in2_resistor_controls[] = {
0217     SOC_DAPM_ENUM("CH2 Resistor Select", in2_resistor_enum),
0218 };
0219 static const struct snd_kcontrol_new in3_resistor_controls[] = {
0220     SOC_DAPM_ENUM("CH3 Resistor Select", in3_resistor_enum),
0221 };
0222 static const struct snd_kcontrol_new in4_resistor_controls[] = {
0223     SOC_DAPM_ENUM("CH4 Resistor Select", in4_resistor_enum),
0224 };
0225 
0226 /* Analog/Digital Selection */
0227 static const char * const adcx140_mic_sel_text[] = {"Analog", "Line In", "Digital"};
0228 static const char * const adcx140_analog_sel_text[] = {"Analog", "Line In"};
0229 
0230 static SOC_ENUM_SINGLE_DECL(adcx140_mic1p_enum,
0231                 ADCX140_CH1_CFG0, 5,
0232                 adcx140_mic_sel_text);
0233 
0234 static const struct snd_kcontrol_new adcx140_dapm_mic1p_control =
0235 SOC_DAPM_ENUM("MIC1P MUX", adcx140_mic1p_enum);
0236 
0237 static SOC_ENUM_SINGLE_DECL(adcx140_mic1_analog_enum,
0238                 ADCX140_CH1_CFG0, 7,
0239                 adcx140_analog_sel_text);
0240 
0241 static const struct snd_kcontrol_new adcx140_dapm_mic1_analog_control =
0242 SOC_DAPM_ENUM("MIC1 Analog MUX", adcx140_mic1_analog_enum);
0243 
0244 static SOC_ENUM_SINGLE_DECL(adcx140_mic1m_enum,
0245                 ADCX140_CH1_CFG0, 5,
0246                 adcx140_mic_sel_text);
0247 
0248 static const struct snd_kcontrol_new adcx140_dapm_mic1m_control =
0249 SOC_DAPM_ENUM("MIC1M MUX", adcx140_mic1m_enum);
0250 
0251 static SOC_ENUM_SINGLE_DECL(adcx140_mic2p_enum,
0252                 ADCX140_CH2_CFG0, 5,
0253                 adcx140_mic_sel_text);
0254 
0255 static const struct snd_kcontrol_new adcx140_dapm_mic2p_control =
0256 SOC_DAPM_ENUM("MIC2P MUX", adcx140_mic2p_enum);
0257 
0258 static SOC_ENUM_SINGLE_DECL(adcx140_mic2_analog_enum,
0259                 ADCX140_CH2_CFG0, 7,
0260                 adcx140_analog_sel_text);
0261 
0262 static const struct snd_kcontrol_new adcx140_dapm_mic2_analog_control =
0263 SOC_DAPM_ENUM("MIC2 Analog MUX", adcx140_mic2_analog_enum);
0264 
0265 static SOC_ENUM_SINGLE_DECL(adcx140_mic2m_enum,
0266                 ADCX140_CH2_CFG0, 5,
0267                 adcx140_mic_sel_text);
0268 
0269 static const struct snd_kcontrol_new adcx140_dapm_mic2m_control =
0270 SOC_DAPM_ENUM("MIC2M MUX", adcx140_mic2m_enum);
0271 
0272 static SOC_ENUM_SINGLE_DECL(adcx140_mic3p_enum,
0273                 ADCX140_CH3_CFG0, 5,
0274                 adcx140_mic_sel_text);
0275 
0276 static const struct snd_kcontrol_new adcx140_dapm_mic3p_control =
0277 SOC_DAPM_ENUM("MIC3P MUX", adcx140_mic3p_enum);
0278 
0279 static SOC_ENUM_SINGLE_DECL(adcx140_mic3_analog_enum,
0280                 ADCX140_CH3_CFG0, 7,
0281                 adcx140_analog_sel_text);
0282 
0283 static const struct snd_kcontrol_new adcx140_dapm_mic3_analog_control =
0284 SOC_DAPM_ENUM("MIC3 Analog MUX", adcx140_mic3_analog_enum);
0285 
0286 static SOC_ENUM_SINGLE_DECL(adcx140_mic3m_enum,
0287                 ADCX140_CH3_CFG0, 5,
0288                 adcx140_mic_sel_text);
0289 
0290 static const struct snd_kcontrol_new adcx140_dapm_mic3m_control =
0291 SOC_DAPM_ENUM("MIC3M MUX", adcx140_mic3m_enum);
0292 
0293 static SOC_ENUM_SINGLE_DECL(adcx140_mic4p_enum,
0294                 ADCX140_CH4_CFG0, 5,
0295                 adcx140_mic_sel_text);
0296 
0297 static const struct snd_kcontrol_new adcx140_dapm_mic4p_control =
0298 SOC_DAPM_ENUM("MIC4P MUX", adcx140_mic4p_enum);
0299 
0300 static SOC_ENUM_SINGLE_DECL(adcx140_mic4_analog_enum,
0301                 ADCX140_CH4_CFG0, 7,
0302                 adcx140_analog_sel_text);
0303 
0304 static const struct snd_kcontrol_new adcx140_dapm_mic4_analog_control =
0305 SOC_DAPM_ENUM("MIC4 Analog MUX", adcx140_mic4_analog_enum);
0306 
0307 static SOC_ENUM_SINGLE_DECL(adcx140_mic4m_enum,
0308                 ADCX140_CH4_CFG0, 5,
0309                 adcx140_mic_sel_text);
0310 
0311 static const struct snd_kcontrol_new adcx140_dapm_mic4m_control =
0312 SOC_DAPM_ENUM("MIC4M MUX", adcx140_mic4m_enum);
0313 
0314 static const struct snd_kcontrol_new adcx140_dapm_ch1_en_switch =
0315     SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 7, 1, 0);
0316 static const struct snd_kcontrol_new adcx140_dapm_ch2_en_switch =
0317     SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 6, 1, 0);
0318 static const struct snd_kcontrol_new adcx140_dapm_ch3_en_switch =
0319     SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 5, 1, 0);
0320 static const struct snd_kcontrol_new adcx140_dapm_ch4_en_switch =
0321     SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 4, 1, 0);
0322 static const struct snd_kcontrol_new adcx140_dapm_ch5_en_switch =
0323     SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 3, 1, 0);
0324 static const struct snd_kcontrol_new adcx140_dapm_ch6_en_switch =
0325     SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 2, 1, 0);
0326 static const struct snd_kcontrol_new adcx140_dapm_ch7_en_switch =
0327     SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 1, 1, 0);
0328 static const struct snd_kcontrol_new adcx140_dapm_ch8_en_switch =
0329     SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 0, 1, 0);
0330 
0331 static const struct snd_kcontrol_new adcx140_dapm_ch1_dre_en_switch =
0332     SOC_DAPM_SINGLE("Switch", ADCX140_CH1_CFG0, 0, 1, 0);
0333 static const struct snd_kcontrol_new adcx140_dapm_ch2_dre_en_switch =
0334     SOC_DAPM_SINGLE("Switch", ADCX140_CH2_CFG0, 0, 1, 0);
0335 static const struct snd_kcontrol_new adcx140_dapm_ch3_dre_en_switch =
0336     SOC_DAPM_SINGLE("Switch", ADCX140_CH3_CFG0, 0, 1, 0);
0337 static const struct snd_kcontrol_new adcx140_dapm_ch4_dre_en_switch =
0338     SOC_DAPM_SINGLE("Switch", ADCX140_CH4_CFG0, 0, 1, 0);
0339 
0340 static const struct snd_kcontrol_new adcx140_dapm_dre_en_switch =
0341     SOC_DAPM_SINGLE("Switch", ADCX140_DSP_CFG1, 3, 1, 0);
0342 
0343 /* Output Mixer */
0344 static const struct snd_kcontrol_new adcx140_output_mixer_controls[] = {
0345     SOC_DAPM_SINGLE("Digital CH1 Switch", 0, 0, 0, 0),
0346     SOC_DAPM_SINGLE("Digital CH2 Switch", 0, 0, 0, 0),
0347     SOC_DAPM_SINGLE("Digital CH3 Switch", 0, 0, 0, 0),
0348     SOC_DAPM_SINGLE("Digital CH4 Switch", 0, 0, 0, 0),
0349 };
0350 
0351 static const struct snd_soc_dapm_widget adcx140_dapm_widgets[] = {
0352     /* Analog Differential Inputs */
0353     SND_SOC_DAPM_INPUT("MIC1P"),
0354     SND_SOC_DAPM_INPUT("MIC1M"),
0355     SND_SOC_DAPM_INPUT("MIC2P"),
0356     SND_SOC_DAPM_INPUT("MIC2M"),
0357     SND_SOC_DAPM_INPUT("MIC3P"),
0358     SND_SOC_DAPM_INPUT("MIC3M"),
0359     SND_SOC_DAPM_INPUT("MIC4P"),
0360     SND_SOC_DAPM_INPUT("MIC4M"),
0361 
0362     SND_SOC_DAPM_OUTPUT("CH1_OUT"),
0363     SND_SOC_DAPM_OUTPUT("CH2_OUT"),
0364     SND_SOC_DAPM_OUTPUT("CH3_OUT"),
0365     SND_SOC_DAPM_OUTPUT("CH4_OUT"),
0366     SND_SOC_DAPM_OUTPUT("CH5_OUT"),
0367     SND_SOC_DAPM_OUTPUT("CH6_OUT"),
0368     SND_SOC_DAPM_OUTPUT("CH7_OUT"),
0369     SND_SOC_DAPM_OUTPUT("CH8_OUT"),
0370 
0371     SND_SOC_DAPM_MIXER("Output Mixer", SND_SOC_NOPM, 0, 0,
0372         &adcx140_output_mixer_controls[0],
0373         ARRAY_SIZE(adcx140_output_mixer_controls)),
0374 
0375     /* Input Selection to MIC_PGA */
0376     SND_SOC_DAPM_MUX("MIC1P Input Mux", SND_SOC_NOPM, 0, 0,
0377              &adcx140_dapm_mic1p_control),
0378     SND_SOC_DAPM_MUX("MIC2P Input Mux", SND_SOC_NOPM, 0, 0,
0379              &adcx140_dapm_mic2p_control),
0380     SND_SOC_DAPM_MUX("MIC3P Input Mux", SND_SOC_NOPM, 0, 0,
0381              &adcx140_dapm_mic3p_control),
0382     SND_SOC_DAPM_MUX("MIC4P Input Mux", SND_SOC_NOPM, 0, 0,
0383              &adcx140_dapm_mic4p_control),
0384 
0385     /* Input Selection to MIC_PGA */
0386     SND_SOC_DAPM_MUX("MIC1 Analog Mux", SND_SOC_NOPM, 0, 0,
0387              &adcx140_dapm_mic1_analog_control),
0388     SND_SOC_DAPM_MUX("MIC2 Analog Mux", SND_SOC_NOPM, 0, 0,
0389              &adcx140_dapm_mic2_analog_control),
0390     SND_SOC_DAPM_MUX("MIC3 Analog Mux", SND_SOC_NOPM, 0, 0,
0391              &adcx140_dapm_mic3_analog_control),
0392     SND_SOC_DAPM_MUX("MIC4 Analog Mux", SND_SOC_NOPM, 0, 0,
0393              &adcx140_dapm_mic4_analog_control),
0394 
0395     SND_SOC_DAPM_MUX("MIC1M Input Mux", SND_SOC_NOPM, 0, 0,
0396              &adcx140_dapm_mic1m_control),
0397     SND_SOC_DAPM_MUX("MIC2M Input Mux", SND_SOC_NOPM, 0, 0,
0398              &adcx140_dapm_mic2m_control),
0399     SND_SOC_DAPM_MUX("MIC3M Input Mux", SND_SOC_NOPM, 0, 0,
0400              &adcx140_dapm_mic3m_control),
0401     SND_SOC_DAPM_MUX("MIC4M Input Mux", SND_SOC_NOPM, 0, 0,
0402              &adcx140_dapm_mic4m_control),
0403 
0404     SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH1", SND_SOC_NOPM, 0, 0, NULL, 0),
0405     SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH2", SND_SOC_NOPM, 0, 0, NULL, 0),
0406     SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH3", SND_SOC_NOPM, 0, 0, NULL, 0),
0407     SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH4", SND_SOC_NOPM, 0, 0, NULL, 0),
0408 
0409     SND_SOC_DAPM_ADC("CH1_ADC", "CH1 Capture", ADCX140_IN_CH_EN, 7, 0),
0410     SND_SOC_DAPM_ADC("CH2_ADC", "CH2 Capture", ADCX140_IN_CH_EN, 6, 0),
0411     SND_SOC_DAPM_ADC("CH3_ADC", "CH3 Capture", ADCX140_IN_CH_EN, 5, 0),
0412     SND_SOC_DAPM_ADC("CH4_ADC", "CH4 Capture", ADCX140_IN_CH_EN, 4, 0),
0413 
0414     SND_SOC_DAPM_ADC("CH1_DIG", "CH1 Capture", ADCX140_IN_CH_EN, 7, 0),
0415     SND_SOC_DAPM_ADC("CH2_DIG", "CH2 Capture", ADCX140_IN_CH_EN, 6, 0),
0416     SND_SOC_DAPM_ADC("CH3_DIG", "CH3 Capture", ADCX140_IN_CH_EN, 5, 0),
0417     SND_SOC_DAPM_ADC("CH4_DIG", "CH4 Capture", ADCX140_IN_CH_EN, 4, 0),
0418     SND_SOC_DAPM_ADC("CH5_DIG", "CH5 Capture", ADCX140_IN_CH_EN, 3, 0),
0419     SND_SOC_DAPM_ADC("CH6_DIG", "CH6 Capture", ADCX140_IN_CH_EN, 2, 0),
0420     SND_SOC_DAPM_ADC("CH7_DIG", "CH7 Capture", ADCX140_IN_CH_EN, 1, 0),
0421     SND_SOC_DAPM_ADC("CH8_DIG", "CH8 Capture", ADCX140_IN_CH_EN, 0, 0),
0422 
0423 
0424     SND_SOC_DAPM_SWITCH("CH1_ASI_EN", SND_SOC_NOPM, 0, 0,
0425                 &adcx140_dapm_ch1_en_switch),
0426     SND_SOC_DAPM_SWITCH("CH2_ASI_EN", SND_SOC_NOPM, 0, 0,
0427                 &adcx140_dapm_ch2_en_switch),
0428     SND_SOC_DAPM_SWITCH("CH3_ASI_EN", SND_SOC_NOPM, 0, 0,
0429                 &adcx140_dapm_ch3_en_switch),
0430     SND_SOC_DAPM_SWITCH("CH4_ASI_EN", SND_SOC_NOPM, 0, 0,
0431                 &adcx140_dapm_ch4_en_switch),
0432 
0433     SND_SOC_DAPM_SWITCH("CH5_ASI_EN", SND_SOC_NOPM, 0, 0,
0434                 &adcx140_dapm_ch5_en_switch),
0435     SND_SOC_DAPM_SWITCH("CH6_ASI_EN", SND_SOC_NOPM, 0, 0,
0436                 &adcx140_dapm_ch6_en_switch),
0437     SND_SOC_DAPM_SWITCH("CH7_ASI_EN", SND_SOC_NOPM, 0, 0,
0438                 &adcx140_dapm_ch7_en_switch),
0439     SND_SOC_DAPM_SWITCH("CH8_ASI_EN", SND_SOC_NOPM, 0, 0,
0440                 &adcx140_dapm_ch8_en_switch),
0441 
0442     SND_SOC_DAPM_SWITCH("DRE_ENABLE", SND_SOC_NOPM, 0, 0,
0443                 &adcx140_dapm_dre_en_switch),
0444 
0445     SND_SOC_DAPM_SWITCH("CH1_DRE_EN", SND_SOC_NOPM, 0, 0,
0446                 &adcx140_dapm_ch1_dre_en_switch),
0447     SND_SOC_DAPM_SWITCH("CH2_DRE_EN", SND_SOC_NOPM, 0, 0,
0448                 &adcx140_dapm_ch2_dre_en_switch),
0449     SND_SOC_DAPM_SWITCH("CH3_DRE_EN", SND_SOC_NOPM, 0, 0,
0450                 &adcx140_dapm_ch3_dre_en_switch),
0451     SND_SOC_DAPM_SWITCH("CH4_DRE_EN", SND_SOC_NOPM, 0, 0,
0452                 &adcx140_dapm_ch4_dre_en_switch),
0453 
0454     SND_SOC_DAPM_MUX("IN1 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
0455             in1_resistor_controls),
0456     SND_SOC_DAPM_MUX("IN2 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
0457             in2_resistor_controls),
0458     SND_SOC_DAPM_MUX("IN3 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
0459             in3_resistor_controls),
0460     SND_SOC_DAPM_MUX("IN4 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
0461             in4_resistor_controls),
0462 
0463     SND_SOC_DAPM_MUX("PDM Clk Div Select", SND_SOC_NOPM, 0, 0,
0464             pdmclk_div_controls),
0465 
0466     SND_SOC_DAPM_MUX("Decimation Filter", SND_SOC_NOPM, 0, 0,
0467             decimation_filter_controls),
0468 };
0469 
0470 static const struct snd_soc_dapm_route adcx140_audio_map[] = {
0471     /* Outputs */
0472     {"CH1_OUT", NULL, "Output Mixer"},
0473     {"CH2_OUT", NULL, "Output Mixer"},
0474     {"CH3_OUT", NULL, "Output Mixer"},
0475     {"CH4_OUT", NULL, "Output Mixer"},
0476 
0477     {"CH1_ASI_EN", "Switch", "CH1_ADC"},
0478     {"CH2_ASI_EN", "Switch", "CH2_ADC"},
0479     {"CH3_ASI_EN", "Switch", "CH3_ADC"},
0480     {"CH4_ASI_EN", "Switch", "CH4_ADC"},
0481 
0482     {"CH1_ASI_EN", "Switch", "CH1_DIG"},
0483     {"CH2_ASI_EN", "Switch", "CH2_DIG"},
0484     {"CH3_ASI_EN", "Switch", "CH3_DIG"},
0485     {"CH4_ASI_EN", "Switch", "CH4_DIG"},
0486     {"CH5_ASI_EN", "Switch", "CH5_DIG"},
0487     {"CH6_ASI_EN", "Switch", "CH6_DIG"},
0488     {"CH7_ASI_EN", "Switch", "CH7_DIG"},
0489     {"CH8_ASI_EN", "Switch", "CH8_DIG"},
0490 
0491     {"CH5_ASI_EN", "Switch", "CH5_OUT"},
0492     {"CH6_ASI_EN", "Switch", "CH6_OUT"},
0493     {"CH7_ASI_EN", "Switch", "CH7_OUT"},
0494     {"CH8_ASI_EN", "Switch", "CH8_OUT"},
0495 
0496     {"Decimation Filter", "Linear Phase", "DRE_ENABLE"},
0497     {"Decimation Filter", "Low Latency", "DRE_ENABLE"},
0498     {"Decimation Filter", "Ultra-low Latency", "DRE_ENABLE"},
0499 
0500     {"DRE_ENABLE", "Switch", "CH1_DRE_EN"},
0501     {"DRE_ENABLE", "Switch", "CH2_DRE_EN"},
0502     {"DRE_ENABLE", "Switch", "CH3_DRE_EN"},
0503     {"DRE_ENABLE", "Switch", "CH4_DRE_EN"},
0504 
0505     {"CH1_DRE_EN", "Switch", "CH1_ADC"},
0506     {"CH2_DRE_EN", "Switch", "CH2_ADC"},
0507     {"CH3_DRE_EN", "Switch", "CH3_ADC"},
0508     {"CH4_DRE_EN", "Switch", "CH4_ADC"},
0509 
0510     /* Mic input */
0511     {"CH1_ADC", NULL, "MIC_GAIN_CTL_CH1"},
0512     {"CH2_ADC", NULL, "MIC_GAIN_CTL_CH2"},
0513     {"CH3_ADC", NULL, "MIC_GAIN_CTL_CH3"},
0514     {"CH4_ADC", NULL, "MIC_GAIN_CTL_CH4"},
0515 
0516     {"MIC_GAIN_CTL_CH1", NULL, "IN1 Analog Mic Resistor"},
0517     {"MIC_GAIN_CTL_CH1", NULL, "IN1 Analog Mic Resistor"},
0518     {"MIC_GAIN_CTL_CH2", NULL, "IN2 Analog Mic Resistor"},
0519     {"MIC_GAIN_CTL_CH2", NULL, "IN2 Analog Mic Resistor"},
0520     {"MIC_GAIN_CTL_CH3", NULL, "IN3 Analog Mic Resistor"},
0521     {"MIC_GAIN_CTL_CH3", NULL, "IN3 Analog Mic Resistor"},
0522     {"MIC_GAIN_CTL_CH4", NULL, "IN4 Analog Mic Resistor"},
0523     {"MIC_GAIN_CTL_CH4", NULL, "IN4 Analog Mic Resistor"},
0524 
0525     {"IN1 Analog Mic Resistor", "2.5 kOhm", "MIC1P Input Mux"},
0526     {"IN1 Analog Mic Resistor", "10 kOhm", "MIC1P Input Mux"},
0527     {"IN1 Analog Mic Resistor", "20 kOhm", "MIC1P Input Mux"},
0528 
0529     {"IN1 Analog Mic Resistor", "2.5 kOhm", "MIC1M Input Mux"},
0530     {"IN1 Analog Mic Resistor", "10 kOhm", "MIC1M Input Mux"},
0531     {"IN1 Analog Mic Resistor", "20 kOhm", "MIC1M Input Mux"},
0532 
0533     {"IN2 Analog Mic Resistor", "2.5 kOhm", "MIC2P Input Mux"},
0534     {"IN2 Analog Mic Resistor", "10 kOhm", "MIC2P Input Mux"},
0535     {"IN2 Analog Mic Resistor", "20 kOhm", "MIC2P Input Mux"},
0536 
0537     {"IN2 Analog Mic Resistor", "2.5 kOhm", "MIC2M Input Mux"},
0538     {"IN2 Analog Mic Resistor", "10 kOhm", "MIC2M Input Mux"},
0539     {"IN2 Analog Mic Resistor", "20 kOhm", "MIC2M Input Mux"},
0540 
0541     {"IN3 Analog Mic Resistor", "2.5 kOhm", "MIC3P Input Mux"},
0542     {"IN3 Analog Mic Resistor", "10 kOhm", "MIC3P Input Mux"},
0543     {"IN3 Analog Mic Resistor", "20 kOhm", "MIC3P Input Mux"},
0544 
0545     {"IN3 Analog Mic Resistor", "2.5 kOhm", "MIC3M Input Mux"},
0546     {"IN3 Analog Mic Resistor", "10 kOhm", "MIC3M Input Mux"},
0547     {"IN3 Analog Mic Resistor", "20 kOhm", "MIC3M Input Mux"},
0548 
0549     {"IN4 Analog Mic Resistor", "2.5 kOhm", "MIC4P Input Mux"},
0550     {"IN4 Analog Mic Resistor", "10 kOhm", "MIC4P Input Mux"},
0551     {"IN4 Analog Mic Resistor", "20 kOhm", "MIC4P Input Mux"},
0552 
0553     {"IN4 Analog Mic Resistor", "2.5 kOhm", "MIC4M Input Mux"},
0554     {"IN4 Analog Mic Resistor", "10 kOhm", "MIC4M Input Mux"},
0555     {"IN4 Analog Mic Resistor", "20 kOhm", "MIC4M Input Mux"},
0556 
0557     {"PDM Clk Div Select", "2.8224 MHz", "MIC1P Input Mux"},
0558     {"PDM Clk Div Select", "1.4112 MHz", "MIC1P Input Mux"},
0559     {"PDM Clk Div Select", "705.6 kHz", "MIC1P Input Mux"},
0560     {"PDM Clk Div Select", "5.6448 MHz", "MIC1P Input Mux"},
0561 
0562     {"MIC1P Input Mux", NULL, "CH1_DIG"},
0563     {"MIC1M Input Mux", NULL, "CH2_DIG"},
0564     {"MIC2P Input Mux", NULL, "CH3_DIG"},
0565     {"MIC2M Input Mux", NULL, "CH4_DIG"},
0566     {"MIC3P Input Mux", NULL, "CH5_DIG"},
0567     {"MIC3M Input Mux", NULL, "CH6_DIG"},
0568     {"MIC4P Input Mux", NULL, "CH7_DIG"},
0569     {"MIC4M Input Mux", NULL, "CH8_DIG"},
0570 
0571     {"MIC1 Analog Mux", "Line In", "MIC1P"},
0572     {"MIC2 Analog Mux", "Line In", "MIC2P"},
0573     {"MIC3 Analog Mux", "Line In", "MIC3P"},
0574     {"MIC4 Analog Mux", "Line In", "MIC4P"},
0575 
0576     {"MIC1P Input Mux", "Analog", "MIC1P"},
0577     {"MIC1M Input Mux", "Analog", "MIC1M"},
0578     {"MIC2P Input Mux", "Analog", "MIC2P"},
0579     {"MIC2M Input Mux", "Analog", "MIC2M"},
0580     {"MIC3P Input Mux", "Analog", "MIC3P"},
0581     {"MIC3M Input Mux", "Analog", "MIC3M"},
0582     {"MIC4P Input Mux", "Analog", "MIC4P"},
0583     {"MIC4M Input Mux", "Analog", "MIC4M"},
0584 
0585     {"MIC1P Input Mux", "Digital", "MIC1P"},
0586     {"MIC1M Input Mux", "Digital", "MIC1M"},
0587     {"MIC2P Input Mux", "Digital", "MIC2P"},
0588     {"MIC2M Input Mux", "Digital", "MIC2M"},
0589     {"MIC3P Input Mux", "Digital", "MIC3P"},
0590     {"MIC3M Input Mux", "Digital", "MIC3M"},
0591     {"MIC4P Input Mux", "Digital", "MIC4P"},
0592     {"MIC4M Input Mux", "Digital", "MIC4M"},
0593 };
0594 
0595 static const struct snd_kcontrol_new adcx140_snd_controls[] = {
0596     SOC_SINGLE_TLV("Analog CH1 Mic Gain Volume", ADCX140_CH1_CFG1, 2, 42, 0,
0597             adc_tlv),
0598     SOC_SINGLE_TLV("Analog CH2 Mic Gain Volume", ADCX140_CH2_CFG1, 2, 42, 0,
0599             adc_tlv),
0600     SOC_SINGLE_TLV("Analog CH3 Mic Gain Volume", ADCX140_CH3_CFG1, 2, 42, 0,
0601             adc_tlv),
0602     SOC_SINGLE_TLV("Analog CH4 Mic Gain Volume", ADCX140_CH4_CFG1, 2, 42, 0,
0603             adc_tlv),
0604 
0605     SOC_SINGLE_TLV("DRE Threshold", ADCX140_DRE_CFG0, 4, 9, 0,
0606                dre_thresh_tlv),
0607     SOC_SINGLE_TLV("DRE Max Gain", ADCX140_DRE_CFG0, 0, 12, 0,
0608                dre_gain_tlv),
0609 
0610     SOC_SINGLE_TLV("AGC Threshold", ADCX140_AGC_CFG0, 4, 15, 0,
0611                agc_thresh_tlv),
0612     SOC_SINGLE_TLV("AGC Max Gain", ADCX140_AGC_CFG0, 0, 13, 0,
0613                agc_gain_tlv),
0614 
0615     SOC_SINGLE_TLV("Digital CH1 Out Volume", ADCX140_CH1_CFG2,
0616             0, 0xff, 0, dig_vol_tlv),
0617     SOC_SINGLE_TLV("Digital CH2 Out Volume", ADCX140_CH2_CFG2,
0618             0, 0xff, 0, dig_vol_tlv),
0619     SOC_SINGLE_TLV("Digital CH3 Out Volume", ADCX140_CH3_CFG2,
0620             0, 0xff, 0, dig_vol_tlv),
0621     SOC_SINGLE_TLV("Digital CH4 Out Volume", ADCX140_CH4_CFG2,
0622             0, 0xff, 0, dig_vol_tlv),
0623     SOC_SINGLE_TLV("Digital CH5 Out Volume", ADCX140_CH5_CFG2,
0624             0, 0xff, 0, dig_vol_tlv),
0625     SOC_SINGLE_TLV("Digital CH6 Out Volume", ADCX140_CH6_CFG2,
0626             0, 0xff, 0, dig_vol_tlv),
0627     SOC_SINGLE_TLV("Digital CH7 Out Volume", ADCX140_CH7_CFG2,
0628             0, 0xff, 0, dig_vol_tlv),
0629     SOC_SINGLE_TLV("Digital CH8 Out Volume", ADCX140_CH8_CFG2,
0630             0, 0xff, 0, dig_vol_tlv),
0631 };
0632 
0633 static int adcx140_reset(struct adcx140_priv *adcx140)
0634 {
0635     int ret = 0;
0636 
0637     if (adcx140->gpio_reset) {
0638         gpiod_direction_output(adcx140->gpio_reset, 0);
0639         /* 8.4.1: wait for hw shutdown (25ms) + >= 1ms */
0640         usleep_range(30000, 100000);
0641         gpiod_direction_output(adcx140->gpio_reset, 1);
0642     } else {
0643         ret = regmap_write(adcx140->regmap, ADCX140_SW_RESET,
0644                    ADCX140_RESET);
0645     }
0646 
0647     /* 8.4.2: wait >= 10 ms after entering sleep mode. */
0648     usleep_range(10000, 100000);
0649 
0650     return ret;
0651 }
0652 
0653 static void adcx140_pwr_ctrl(struct adcx140_priv *adcx140, bool power_state)
0654 {
0655     int pwr_ctrl = 0;
0656 
0657     if (power_state)
0658         pwr_ctrl = ADCX140_PWR_CFG_ADC_PDZ | ADCX140_PWR_CFG_PLL_PDZ;
0659 
0660     if (adcx140->micbias_vg && power_state)
0661         pwr_ctrl |= ADCX140_PWR_CFG_BIAS_PDZ;
0662 
0663     regmap_update_bits(adcx140->regmap, ADCX140_PWR_CFG,
0664                ADCX140_PWR_CTRL_MSK, pwr_ctrl);
0665 }
0666 
0667 static int adcx140_hw_params(struct snd_pcm_substream *substream,
0668                  struct snd_pcm_hw_params *params,
0669                  struct snd_soc_dai *dai)
0670 {
0671     struct snd_soc_component *component = dai->component;
0672     struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component);
0673     u8 data = 0;
0674 
0675     switch (params_width(params)) {
0676     case 16:
0677         data = ADCX140_16_BIT_WORD;
0678         break;
0679     case 20:
0680         data = ADCX140_20_BIT_WORD;
0681         break;
0682     case 24:
0683         data = ADCX140_24_BIT_WORD;
0684         break;
0685     case 32:
0686         data = ADCX140_32_BIT_WORD;
0687         break;
0688     default:
0689         dev_err(component->dev, "%s: Unsupported width %d\n",
0690             __func__, params_width(params));
0691         return -EINVAL;
0692     }
0693 
0694     adcx140_pwr_ctrl(adcx140, false);
0695 
0696     snd_soc_component_update_bits(component, ADCX140_ASI_CFG0,
0697                 ADCX140_WORD_LEN_MSK, data);
0698 
0699     adcx140_pwr_ctrl(adcx140, true);
0700 
0701     return 0;
0702 }
0703 
0704 static int adcx140_set_dai_fmt(struct snd_soc_dai *codec_dai,
0705                    unsigned int fmt)
0706 {
0707     struct snd_soc_component *component = codec_dai->component;
0708     struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component);
0709     u8 iface_reg1 = 0;
0710     u8 iface_reg2 = 0;
0711     int offset = 0;
0712     bool inverted_bclk = false;
0713 
0714     /* set master/slave audio interface */
0715     switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0716     case SND_SOC_DAIFMT_CBP_CFP:
0717         iface_reg2 |= ADCX140_BCLK_FSYNC_MASTER;
0718         break;
0719     case SND_SOC_DAIFMT_CBC_CFC:
0720         break;
0721     default:
0722         dev_err(component->dev, "Invalid DAI clock provider\n");
0723         return -EINVAL;
0724     }
0725 
0726     /* interface format */
0727     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0728     case SND_SOC_DAIFMT_I2S:
0729         iface_reg1 |= ADCX140_I2S_MODE_BIT;
0730         break;
0731     case SND_SOC_DAIFMT_LEFT_J:
0732         iface_reg1 |= ADCX140_LEFT_JUST_BIT;
0733         break;
0734     case SND_SOC_DAIFMT_DSP_A:
0735         offset = 1;
0736         inverted_bclk = true;
0737         break;
0738     case SND_SOC_DAIFMT_DSP_B:
0739         inverted_bclk = true;
0740         break;
0741     default:
0742         dev_err(component->dev, "Invalid DAI interface format\n");
0743         return -EINVAL;
0744     }
0745 
0746     /* signal polarity */
0747     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0748     case SND_SOC_DAIFMT_IB_NF:
0749     case SND_SOC_DAIFMT_IB_IF:
0750         inverted_bclk = !inverted_bclk;
0751         break;
0752     case SND_SOC_DAIFMT_NB_IF:
0753         iface_reg1 |= ADCX140_FSYNCINV_BIT;
0754         break;
0755     case SND_SOC_DAIFMT_NB_NF:
0756         break;
0757     default:
0758         dev_err(component->dev, "Invalid DAI clock signal polarity\n");
0759         return -EINVAL;
0760     }
0761 
0762     if (inverted_bclk)
0763         iface_reg1 |= ADCX140_BCLKINV_BIT;
0764 
0765     adcx140->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
0766 
0767     adcx140_pwr_ctrl(adcx140, false);
0768 
0769     snd_soc_component_update_bits(component, ADCX140_ASI_CFG0,
0770                       ADCX140_FSYNCINV_BIT |
0771                       ADCX140_BCLKINV_BIT |
0772                       ADCX140_ASI_FORMAT_MSK,
0773                       iface_reg1);
0774     snd_soc_component_update_bits(component, ADCX140_MST_CFG0,
0775                       ADCX140_BCLK_FSYNC_MASTER, iface_reg2);
0776 
0777     /* Configure data offset */
0778     snd_soc_component_update_bits(component, ADCX140_ASI_CFG1,
0779                       ADCX140_TX_OFFSET_MASK, offset);
0780 
0781     adcx140_pwr_ctrl(adcx140, true);
0782 
0783     return 0;
0784 }
0785 
0786 static int adcx140_set_dai_tdm_slot(struct snd_soc_dai *codec_dai,
0787                   unsigned int tx_mask, unsigned int rx_mask,
0788                   int slots, int slot_width)
0789 {
0790     struct snd_soc_component *component = codec_dai->component;
0791     struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component);
0792 
0793     /*
0794      * The chip itself supports arbitrary masks, but the driver currently
0795      * only supports adjacent slots beginning at the first slot.
0796      */
0797     if (tx_mask != GENMASK(__fls(tx_mask), 0)) {
0798         dev_err(component->dev, "Only lower adjacent slots are supported\n");
0799         return -EINVAL;
0800     }
0801 
0802     switch (slot_width) {
0803     case 16:
0804     case 20:
0805     case 24:
0806     case 32:
0807         break;
0808     default:
0809         dev_err(component->dev, "Unsupported slot width %d\n", slot_width);
0810         return -EINVAL;
0811     }
0812 
0813     adcx140->slot_width = slot_width;
0814 
0815     return 0;
0816 }
0817 
0818 static const struct snd_soc_dai_ops adcx140_dai_ops = {
0819     .hw_params  = adcx140_hw_params,
0820     .set_fmt    = adcx140_set_dai_fmt,
0821     .set_tdm_slot   = adcx140_set_dai_tdm_slot,
0822 };
0823 
0824 static int adcx140_configure_gpo(struct adcx140_priv *adcx140)
0825 {
0826     u32 gpo_outputs[ADCX140_NUM_GPOS];
0827     u32 gpo_output_val = 0;
0828     int ret;
0829     int i;
0830 
0831     for (i = 0; i < ADCX140_NUM_GPOS; i++) {
0832         ret = device_property_read_u32_array(adcx140->dev,
0833                              gpo_config_names[i],
0834                              gpo_outputs,
0835                              ADCX140_NUM_GPO_CFGS);
0836         if (ret)
0837             continue;
0838 
0839         if (gpo_outputs[0] > ADCX140_GPO_CFG_MAX) {
0840             dev_err(adcx140->dev, "GPO%d config out of range\n", i + 1);
0841             return -EINVAL;
0842         }
0843 
0844         if (gpo_outputs[1] > ADCX140_GPO_DRV_MAX) {
0845             dev_err(adcx140->dev, "GPO%d drive out of range\n", i + 1);
0846             return -EINVAL;
0847         }
0848 
0849         gpo_output_val = gpo_outputs[0] << ADCX140_GPO_SHIFT |
0850                  gpo_outputs[1];
0851         ret = regmap_write(adcx140->regmap, ADCX140_GPO_CFG0 + i,
0852                    gpo_output_val);
0853         if (ret)
0854             return ret;
0855     }
0856 
0857     return 0;
0858 
0859 }
0860 
0861 static int adcx140_configure_gpio(struct adcx140_priv *adcx140)
0862 {
0863     int gpio_count = 0;
0864     u32 gpio_outputs[ADCX140_NUM_GPIO_CFGS];
0865     u32 gpio_output_val = 0;
0866     int ret;
0867 
0868     gpio_count = device_property_count_u32(adcx140->dev,
0869             "ti,gpio-config");
0870     if (gpio_count == 0)
0871         return 0;
0872 
0873     if (gpio_count != ADCX140_NUM_GPIO_CFGS)
0874         return -EINVAL;
0875 
0876     ret = device_property_read_u32_array(adcx140->dev, "ti,gpio-config",
0877             gpio_outputs, gpio_count);
0878     if (ret)
0879         return ret;
0880 
0881     if (gpio_outputs[0] > ADCX140_GPIO_CFG_MAX) {
0882         dev_err(adcx140->dev, "GPIO config out of range\n");
0883         return -EINVAL;
0884     }
0885 
0886     if (gpio_outputs[1] > ADCX140_GPIO_DRV_MAX) {
0887         dev_err(adcx140->dev, "GPIO drive out of range\n");
0888         return -EINVAL;
0889     }
0890 
0891     gpio_output_val = gpio_outputs[0] << ADCX140_GPIO_SHIFT
0892         | gpio_outputs[1];
0893 
0894     return regmap_write(adcx140->regmap, ADCX140_GPIO_CFG0, gpio_output_val);
0895 }
0896 
0897 static int adcx140_codec_probe(struct snd_soc_component *component)
0898 {
0899     struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component);
0900     int sleep_cfg_val = ADCX140_WAKE_DEV;
0901     u32 bias_source;
0902     u32 vref_source;
0903     u8 bias_cfg;
0904     int pdm_count;
0905     u32 pdm_edges[ADCX140_NUM_PDM_EDGES];
0906     u32 pdm_edge_val = 0;
0907     int gpi_count;
0908     u32 gpi_inputs[ADCX140_NUM_GPI_PINS];
0909     u32 gpi_input_val = 0;
0910     int i;
0911     int ret;
0912     bool tx_high_z;
0913 
0914     ret = device_property_read_u32(adcx140->dev, "ti,mic-bias-source",
0915                       &bias_source);
0916     if (ret || bias_source > ADCX140_MIC_BIAS_VAL_AVDD) {
0917         bias_source = ADCX140_MIC_BIAS_VAL_VREF;
0918         adcx140->micbias_vg = false;
0919     } else {
0920         adcx140->micbias_vg = true;
0921     }
0922 
0923     ret = device_property_read_u32(adcx140->dev, "ti,vref-source",
0924                       &vref_source);
0925     if (ret)
0926         vref_source = ADCX140_MIC_BIAS_VREF_275V;
0927 
0928     if (vref_source > ADCX140_MIC_BIAS_VREF_1375V) {
0929         dev_err(adcx140->dev, "Mic Bias source value is invalid\n");
0930         return -EINVAL;
0931     }
0932 
0933     bias_cfg = bias_source << ADCX140_MIC_BIAS_SHIFT | vref_source;
0934 
0935     ret = adcx140_reset(adcx140);
0936     if (ret)
0937         goto out;
0938 
0939     if (adcx140->supply_areg == NULL)
0940         sleep_cfg_val |= ADCX140_AREG_INTERNAL;
0941 
0942     ret = regmap_write(adcx140->regmap, ADCX140_SLEEP_CFG, sleep_cfg_val);
0943     if (ret) {
0944         dev_err(adcx140->dev, "setting sleep config failed %d\n", ret);
0945         goto out;
0946     }
0947 
0948     /* 8.4.3: Wait >= 1ms after entering active mode. */
0949     usleep_range(1000, 100000);
0950 
0951     pdm_count = device_property_count_u32(adcx140->dev,
0952                           "ti,pdm-edge-select");
0953     if (pdm_count <= ADCX140_NUM_PDM_EDGES && pdm_count > 0) {
0954         ret = device_property_read_u32_array(adcx140->dev,
0955                              "ti,pdm-edge-select",
0956                              pdm_edges, pdm_count);
0957         if (ret)
0958             return ret;
0959 
0960         for (i = 0; i < pdm_count; i++)
0961             pdm_edge_val |= pdm_edges[i] << (ADCX140_PDM_EDGE_SHIFT - i);
0962 
0963         ret = regmap_write(adcx140->regmap, ADCX140_PDM_CFG,
0964                    pdm_edge_val);
0965         if (ret)
0966             return ret;
0967     }
0968 
0969     gpi_count = device_property_count_u32(adcx140->dev, "ti,gpi-config");
0970     if (gpi_count <= ADCX140_NUM_GPI_PINS && gpi_count > 0) {
0971         ret = device_property_read_u32_array(adcx140->dev,
0972                              "ti,gpi-config",
0973                              gpi_inputs, gpi_count);
0974         if (ret)
0975             return ret;
0976 
0977         gpi_input_val = gpi_inputs[ADCX140_GPI1_INDEX] << ADCX140_GPI_SHIFT |
0978                 gpi_inputs[ADCX140_GPI2_INDEX];
0979 
0980         ret = regmap_write(adcx140->regmap, ADCX140_GPI_CFG0,
0981                    gpi_input_val);
0982         if (ret)
0983             return ret;
0984 
0985         gpi_input_val = gpi_inputs[ADCX140_GPI3_INDEX] << ADCX140_GPI_SHIFT |
0986                 gpi_inputs[ADCX140_GPI4_INDEX];
0987 
0988         ret = regmap_write(adcx140->regmap, ADCX140_GPI_CFG1,
0989                    gpi_input_val);
0990         if (ret)
0991             return ret;
0992     }
0993 
0994     ret = adcx140_configure_gpio(adcx140);
0995     if (ret)
0996         return ret;
0997 
0998     ret = adcx140_configure_gpo(adcx140);
0999     if (ret)
1000         goto out;
1001 
1002     ret = regmap_update_bits(adcx140->regmap, ADCX140_BIAS_CFG,
1003                 ADCX140_MIC_BIAS_VAL_MSK |
1004                 ADCX140_MIC_BIAS_VREF_MSK, bias_cfg);
1005     if (ret)
1006         dev_err(adcx140->dev, "setting MIC bias failed %d\n", ret);
1007 
1008     tx_high_z = device_property_read_bool(adcx140->dev, "ti,asi-tx-drive");
1009     if (tx_high_z) {
1010         ret = regmap_update_bits(adcx140->regmap, ADCX140_ASI_CFG0,
1011                  ADCX140_TX_FILL, ADCX140_TX_FILL);
1012         if (ret) {
1013             dev_err(adcx140->dev, "Setting Tx drive failed %d\n", ret);
1014             goto out;
1015         }
1016     }
1017 
1018     adcx140_pwr_ctrl(adcx140, true);
1019 out:
1020     return ret;
1021 }
1022 
1023 static int adcx140_set_bias_level(struct snd_soc_component *component,
1024                   enum snd_soc_bias_level level)
1025 {
1026     struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component);
1027 
1028     switch (level) {
1029     case SND_SOC_BIAS_ON:
1030     case SND_SOC_BIAS_PREPARE:
1031     case SND_SOC_BIAS_STANDBY:
1032         adcx140_pwr_ctrl(adcx140, true);
1033         break;
1034     case SND_SOC_BIAS_OFF:
1035         adcx140_pwr_ctrl(adcx140, false);
1036         break;
1037     }
1038 
1039     return 0;
1040 }
1041 
1042 static const struct snd_soc_component_driver soc_codec_driver_adcx140 = {
1043     .probe          = adcx140_codec_probe,
1044     .set_bias_level     = adcx140_set_bias_level,
1045     .controls       = adcx140_snd_controls,
1046     .num_controls       = ARRAY_SIZE(adcx140_snd_controls),
1047     .dapm_widgets       = adcx140_dapm_widgets,
1048     .num_dapm_widgets   = ARRAY_SIZE(adcx140_dapm_widgets),
1049     .dapm_routes        = adcx140_audio_map,
1050     .num_dapm_routes    = ARRAY_SIZE(adcx140_audio_map),
1051     .suspend_bias_off   = 1,
1052     .idle_bias_on       = 0,
1053     .use_pmdown_time    = 1,
1054     .endianness     = 1,
1055 };
1056 
1057 static struct snd_soc_dai_driver adcx140_dai_driver[] = {
1058     {
1059         .name = "tlv320adcx140-codec",
1060         .capture = {
1061             .stream_name     = "Capture",
1062             .channels_min    = 2,
1063             .channels_max    = ADCX140_MAX_CHANNELS,
1064             .rates       = ADCX140_RATES,
1065             .formats     = ADCX140_FORMATS,
1066         },
1067         .ops = &adcx140_dai_ops,
1068         .symmetric_rate = 1,
1069     }
1070 };
1071 
1072 #ifdef CONFIG_OF
1073 static const struct of_device_id tlv320adcx140_of_match[] = {
1074     { .compatible = "ti,tlv320adc3140" },
1075     { .compatible = "ti,tlv320adc5140" },
1076     { .compatible = "ti,tlv320adc6140" },
1077     {},
1078 };
1079 MODULE_DEVICE_TABLE(of, tlv320adcx140_of_match);
1080 #endif
1081 
1082 static void adcx140_disable_regulator(void *arg)
1083 {
1084     struct adcx140_priv *adcx140 = arg;
1085 
1086     regulator_disable(adcx140->supply_areg);
1087 }
1088 
1089 static int adcx140_i2c_probe(struct i2c_client *i2c)
1090 {
1091     struct adcx140_priv *adcx140;
1092     int ret;
1093 
1094     adcx140 = devm_kzalloc(&i2c->dev, sizeof(*adcx140), GFP_KERNEL);
1095     if (!adcx140)
1096         return -ENOMEM;
1097 
1098     adcx140->dev = &i2c->dev;
1099 
1100     adcx140->gpio_reset = devm_gpiod_get_optional(adcx140->dev,
1101                               "reset", GPIOD_OUT_LOW);
1102     if (IS_ERR(adcx140->gpio_reset))
1103         dev_info(&i2c->dev, "Reset GPIO not defined\n");
1104 
1105     adcx140->supply_areg = devm_regulator_get_optional(adcx140->dev,
1106                                "areg");
1107     if (IS_ERR(adcx140->supply_areg)) {
1108         if (PTR_ERR(adcx140->supply_areg) == -EPROBE_DEFER)
1109             return -EPROBE_DEFER;
1110 
1111         adcx140->supply_areg = NULL;
1112     } else {
1113         ret = regulator_enable(adcx140->supply_areg);
1114         if (ret) {
1115             dev_err(adcx140->dev, "Failed to enable areg\n");
1116             return ret;
1117         }
1118 
1119         ret = devm_add_action_or_reset(&i2c->dev, adcx140_disable_regulator, adcx140);
1120         if (ret)
1121             return ret;
1122     }
1123 
1124     adcx140->regmap = devm_regmap_init_i2c(i2c, &adcx140_i2c_regmap);
1125     if (IS_ERR(adcx140->regmap)) {
1126         ret = PTR_ERR(adcx140->regmap);
1127         dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1128             ret);
1129         return ret;
1130     }
1131 
1132     i2c_set_clientdata(i2c, adcx140);
1133 
1134     return devm_snd_soc_register_component(&i2c->dev,
1135                            &soc_codec_driver_adcx140,
1136                            adcx140_dai_driver, 1);
1137 }
1138 
1139 static const struct i2c_device_id adcx140_i2c_id[] = {
1140     { "tlv320adc3140", 0 },
1141     { "tlv320adc5140", 1 },
1142     { "tlv320adc6140", 2 },
1143     {}
1144 };
1145 MODULE_DEVICE_TABLE(i2c, adcx140_i2c_id);
1146 
1147 static struct i2c_driver adcx140_i2c_driver = {
1148     .driver = {
1149         .name   = "tlv320adcx140-codec",
1150         .of_match_table = of_match_ptr(tlv320adcx140_of_match),
1151     },
1152     .probe_new  = adcx140_i2c_probe,
1153     .id_table   = adcx140_i2c_id,
1154 };
1155 module_i2c_driver(adcx140_i2c_driver);
1156 
1157 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>");
1158 MODULE_DESCRIPTION("ASoC TLV320ADCX140 CODEC Driver");
1159 MODULE_LICENSE("GPL v2");
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