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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 //
0003 // Based on sound/soc/codecs/tlv320aic3x.c by  Vladimir Barinov
0004 //
0005 // Copyright (C) 2010 Mistral Solutions Pvt Ltd.
0006 // Author: Shahina Shaik <shahina.s@mistralsolutions.com>
0007 //
0008 // Copyright (C) 2014-2018, Ambarella, Inc.
0009 // Author: Dongge wu <dgwu@ambarella.com>
0010 //
0011 // Copyright (C) 2021 Axis Communications AB
0012 // Author: Ricard Wanderlof <ricardw@axis.com>
0013 //
0014 
0015 #include <dt-bindings/sound/tlv320adc3xxx.h>
0016 #include <linux/clk.h>
0017 #include <linux/module.h>
0018 #include <linux/moduleparam.h>
0019 #include <linux/io.h>
0020 #include <linux/init.h>
0021 #include <linux/delay.h>
0022 #include <linux/gpio/driver.h>
0023 #include <linux/pm.h>
0024 #include <linux/i2c.h>
0025 #include <linux/platform_device.h>
0026 #include <linux/cdev.h>
0027 #include <linux/of_gpio.h>
0028 #include <linux/slab.h>
0029 #include <sound/core.h>
0030 #include <sound/pcm.h>
0031 #include <sound/pcm_params.h>
0032 #include <sound/soc.h>
0033 #include <sound/soc-dapm.h>
0034 #include <sound/tlv.h>
0035 #include <sound/initval.h>
0036 
0037 /*
0038  * General definitions defining exported functionality.
0039  */
0040 
0041 #define ADC3XXX_MICBIAS_PINS        2
0042 
0043 /* Number of GPIO pins exposed via the gpiolib interface */
0044 #define ADC3XXX_GPIOS_MAX       2
0045 
0046 #define ADC3XXX_RATES       SNDRV_PCM_RATE_8000_96000
0047 #define ADC3XXX_FORMATS     (SNDRV_PCM_FMTBIT_S16_LE | \
0048                  SNDRV_PCM_FMTBIT_S20_3LE | \
0049                  SNDRV_PCM_FMTBIT_S24_3LE | \
0050                  SNDRV_PCM_FMTBIT_S32_LE)
0051 
0052 /*
0053  * PLL modes, to be used for clk_id for set_sysclk callback.
0054  *
0055  * The default behavior (AUTO) is to take the first matching entry in the clock
0056  * table, which is intended to be the PLL based one if there is more than one.
0057  *
0058  * Setting the clock source using simple-card (clocks or
0059  * system-clock-frequency property) sets clk_id = 0 = ADC3XXX_PLL_AUTO.
0060  */
0061 #define ADC3XXX_PLL_AUTO    0 /* Use first available mode */
0062 #define ADC3XXX_PLL_ENABLE  1 /* Use PLL for clock generation */
0063 #define ADC3XXX_PLL_BYPASS  2 /* Don't use PLL for clock generation */
0064 
0065 /* Register definitions. */
0066 
0067 #define ADC3XXX_PAGE_SIZE       128
0068 #define ADC3XXX_REG(page, reg)      ((page * ADC3XXX_PAGE_SIZE) + reg)
0069 
0070 /*
0071  * Page 0 registers.
0072  */
0073 
0074 #define ADC3XXX_PAGE_SELECT         ADC3XXX_REG(0, 0)
0075 #define ADC3XXX_RESET               ADC3XXX_REG(0, 1)
0076 
0077 /* 2-3 Reserved */
0078 
0079 #define ADC3XXX_CLKGEN_MUX          ADC3XXX_REG(0, 4)
0080 #define ADC3XXX_PLL_PROG_PR         ADC3XXX_REG(0, 5)
0081 #define ADC3XXX_PLL_PROG_J          ADC3XXX_REG(0, 6)
0082 #define ADC3XXX_PLL_PROG_D_MSB          ADC3XXX_REG(0, 7)
0083 #define ADC3XXX_PLL_PROG_D_LSB          ADC3XXX_REG(0, 8)
0084 
0085 /* 9-17 Reserved */
0086 
0087 #define ADC3XXX_ADC_NADC            ADC3XXX_REG(0, 18)
0088 #define ADC3XXX_ADC_MADC            ADC3XXX_REG(0, 19)
0089 #define ADC3XXX_ADC_AOSR            ADC3XXX_REG(0, 20)
0090 #define ADC3XXX_ADC_IADC            ADC3XXX_REG(0, 21)
0091 
0092 /* 23-24 Reserved */
0093 
0094 #define ADC3XXX_CLKOUT_MUX          ADC3XXX_REG(0, 25)
0095 #define ADC3XXX_CLKOUT_M_DIV            ADC3XXX_REG(0, 26)
0096 #define ADC3XXX_INTERFACE_CTRL_1        ADC3XXX_REG(0, 27)
0097 #define ADC3XXX_CH_OFFSET_1         ADC3XXX_REG(0, 28)
0098 #define ADC3XXX_INTERFACE_CTRL_2        ADC3XXX_REG(0, 29)
0099 #define ADC3XXX_BCLK_N_DIV          ADC3XXX_REG(0, 30)
0100 #define ADC3XXX_INTERFACE_CTRL_3        ADC3XXX_REG(0, 31)
0101 #define ADC3XXX_INTERFACE_CTRL_4        ADC3XXX_REG(0, 32)
0102 #define ADC3XXX_INTERFACE_CTRL_5        ADC3XXX_REG(0, 33)
0103 #define ADC3XXX_I2S_SYNC            ADC3XXX_REG(0, 34)
0104 /* 35 Reserved */
0105 #define ADC3XXX_ADC_FLAG            ADC3XXX_REG(0, 36)
0106 #define ADC3XXX_CH_OFFSET_2         ADC3XXX_REG(0, 37)
0107 #define ADC3XXX_I2S_TDM_CTRL            ADC3XXX_REG(0, 38)
0108 /* 39-41 Reserved */
0109 #define ADC3XXX_INTR_FLAG_1         ADC3XXX_REG(0, 42)
0110 #define ADC3XXX_INTR_FLAG_2         ADC3XXX_REG(0, 43)
0111 /* 44 Reserved */
0112 #define ADC3XXX_INTR_FLAG_ADC1          ADC3XXX_REG(0, 45)
0113 /* 46 Reserved */
0114 #define ADC3XXX_INTR_FLAG_ADC2          ADC3XXX_REG(0, 47)
0115 #define ADC3XXX_INT1_CTRL           ADC3XXX_REG(0, 48)
0116 #define ADC3XXX_INT2_CTRL           ADC3XXX_REG(0, 49)
0117 /* 50 Reserved */
0118 #define ADC3XXX_GPIO2_CTRL          ADC3XXX_REG(0, 51)
0119 #define ADC3XXX_GPIO1_CTRL          ADC3XXX_REG(0, 52)
0120 #define ADC3XXX_DOUT_CTRL           ADC3XXX_REG(0, 53)
0121 /* 54-56 Reserved */
0122 #define ADC3XXX_SYNC_CTRL_1         ADC3XXX_REG(0, 57)
0123 #define ADC3XXX_SYNC_CTRL_2         ADC3XXX_REG(0, 58)
0124 #define ADC3XXX_CIC_GAIN_CTRL           ADC3XXX_REG(0, 59)
0125 /* 60 Reserved */
0126 #define ADC3XXX_PRB_SELECT          ADC3XXX_REG(0, 61)
0127 #define ADC3XXX_INST_MODE_CTRL          ADC3XXX_REG(0, 62)
0128 /* 63-79 Reserved */
0129 #define ADC3XXX_MIC_POLARITY_CTRL       ADC3XXX_REG(0, 80)
0130 #define ADC3XXX_ADC_DIGITAL         ADC3XXX_REG(0, 81)
0131 #define ADC3XXX_ADC_FGA             ADC3XXX_REG(0, 82)
0132 #define ADC3XXX_LADC_VOL            ADC3XXX_REG(0, 83)
0133 #define ADC3XXX_RADC_VOL            ADC3XXX_REG(0, 84)
0134 #define ADC3XXX_ADC_PHASE_COMP          ADC3XXX_REG(0, 85)
0135 #define ADC3XXX_LEFT_CHN_AGC_1          ADC3XXX_REG(0, 86)
0136 #define ADC3XXX_LEFT_CHN_AGC_2          ADC3XXX_REG(0, 87)
0137 #define ADC3XXX_LEFT_CHN_AGC_3          ADC3XXX_REG(0, 88)
0138 #define ADC3XXX_LEFT_CHN_AGC_4          ADC3XXX_REG(0, 89)
0139 #define ADC3XXX_LEFT_CHN_AGC_5          ADC3XXX_REG(0, 90)
0140 #define ADC3XXX_LEFT_CHN_AGC_6          ADC3XXX_REG(0, 91)
0141 #define ADC3XXX_LEFT_CHN_AGC_7          ADC3XXX_REG(0, 92)
0142 #define ADC3XXX_LEFT_AGC_GAIN           ADC3XXX_REG(0, 93)
0143 #define ADC3XXX_RIGHT_CHN_AGC_1         ADC3XXX_REG(0, 94)
0144 #define ADC3XXX_RIGHT_CHN_AGC_2         ADC3XXX_REG(0, 95)
0145 #define ADC3XXX_RIGHT_CHN_AGC_3         ADC3XXX_REG(0, 96)
0146 #define ADC3XXX_RIGHT_CHN_AGC_4         ADC3XXX_REG(0, 97)
0147 #define ADC3XXX_RIGHT_CHN_AGC_5         ADC3XXX_REG(0, 98)
0148 #define ADC3XXX_RIGHT_CHN_AGC_6         ADC3XXX_REG(0, 99)
0149 #define ADC3XXX_RIGHT_CHN_AGC_7         ADC3XXX_REG(0, 100)
0150 #define ADC3XXX_RIGHT_AGC_GAIN          ADC3XXX_REG(0, 101)
0151 /* 102-127 Reserved */
0152 
0153 /*
0154  * Page 1 registers.
0155  */
0156 
0157 /* 1-25 Reserved */
0158 #define ADC3XXX_DITHER_CTRL         ADC3XXX_REG(1, 26)
0159 /* 27-50 Reserved */
0160 #define ADC3XXX_MICBIAS_CTRL            ADC3XXX_REG(1, 51)
0161 #define ADC3XXX_LEFT_PGA_SEL_1          ADC3XXX_REG(1, 52)
0162 /* 53 Reserved */
0163 #define ADC3XXX_LEFT_PGA_SEL_2          ADC3XXX_REG(1, 54)
0164 #define ADC3XXX_RIGHT_PGA_SEL_1         ADC3XXX_REG(1, 55)
0165 #define ADC3XXX_RIGHT_PGA_SEL_2         ADC3XXX_REG(1, 57)
0166 #define ADC3XXX_LEFT_APGA_CTRL          ADC3XXX_REG(1, 59)
0167 #define ADC3XXX_RIGHT_APGA_CTRL         ADC3XXX_REG(1, 60)
0168 #define ADC3XXX_LOW_CURRENT_MODES       ADC3XXX_REG(1, 61)
0169 #define ADC3XXX_ANALOG_PGA_FLAGS        ADC3XXX_REG(1, 62)
0170 /* 63-127 Reserved */
0171 
0172 /*
0173  * Page 4 registers. First page of coefficient memory for the miniDSP.
0174  */
0175 #define ADC3XXX_LEFT_ADC_IIR_COEFF_N0_MSB   ADC3XXX_REG(4, 8)
0176 #define ADC3XXX_LEFT_ADC_IIR_COEFF_N0_LSB   ADC3XXX_REG(4, 9)
0177 #define ADC3XXX_LEFT_ADC_IIR_COEFF_N1_MSB   ADC3XXX_REG(4, 10)
0178 #define ADC3XXX_LEFT_ADC_IIR_COEFF_N1_LSB   ADC3XXX_REG(4, 11)
0179 #define ADC3XXX_LEFT_ADC_IIR_COEFF_D1_MSB   ADC3XXX_REG(4, 12)
0180 #define ADC3XXX_LEFT_ADC_IIR_COEFF_D1_LSB   ADC3XXX_REG(4, 13)
0181 
0182 #define ADC3XXX_RIGHT_ADC_IIR_COEFF_N0_MSB  ADC3XXX_REG(4, 72)
0183 #define ADC3XXX_RIGHT_ADC_IIR_COEFF_N0_LSB  ADC3XXX_REG(4, 73)
0184 #define ADC3XXX_RIGHT_ADC_IIR_COEFF_N1_MSB  ADC3XXX_REG(4, 74)
0185 #define ADC3XXX_RIGHT_ADC_IIR_COEFF_N1_LSB  ADC3XXX_REG(4, 75)
0186 #define ADC3XXX_RIGHT_ADC_IIR_COEFF_D1_MSB  ADC3XXX_REG(4, 76)
0187 #define ADC3XXX_RIGHT_ADC_IIR_COEFF_D1_LSB  ADC3XXX_REG(4, 77)
0188 
0189 /*
0190  * Register bits.
0191  */
0192 
0193 /* PLL Enable bits */
0194 #define ADC3XXX_ENABLE_PLL_SHIFT    7
0195 #define ADC3XXX_ENABLE_PLL      (1 << ADC3XXX_ENABLE_PLL_SHIFT)
0196 #define ADC3XXX_ENABLE_NADC_SHIFT   7
0197 #define ADC3XXX_ENABLE_NADC     (1 << ADC3XXX_ENABLE_NADC_SHIFT)
0198 #define ADC3XXX_ENABLE_MADC_SHIFT   7
0199 #define ADC3XXX_ENABLE_MADC     (1 << ADC3XXX_ENABLE_MADC_SHIFT)
0200 #define ADC3XXX_ENABLE_BCLK_SHIFT   7
0201 #define ADC3XXX_ENABLE_BCLK     (1 << ADC3XXX_ENABLE_BCLK_SHIFT)
0202 
0203 /* Power bits */
0204 #define ADC3XXX_LADC_PWR_ON     0x80
0205 #define ADC3XXX_RADC_PWR_ON     0x40
0206 
0207 #define ADC3XXX_SOFT_RESET      0x01
0208 #define ADC3XXX_BCLK_MASTER     0x08
0209 #define ADC3XXX_WCLK_MASTER     0x04
0210 
0211 /* Interface register masks */
0212 #define ADC3XXX_FORMAT_MASK     0xc0
0213 #define ADC3XXX_FORMAT_SHIFT        6
0214 #define ADC3XXX_WLENGTH_MASK        0x30
0215 #define ADC3XXX_WLENGTH_SHIFT       4
0216 #define ADC3XXX_CLKDIR_MASK     0x0c
0217 #define ADC3XXX_CLKDIR_SHIFT        2
0218 
0219 /* Interface register bit patterns */
0220 #define ADC3XXX_FORMAT_I2S      (0 << ADC3XXX_FORMAT_SHIFT)
0221 #define ADC3XXX_FORMAT_DSP      (1 << ADC3XXX_FORMAT_SHIFT)
0222 #define ADC3XXX_FORMAT_RJF      (2 << ADC3XXX_FORMAT_SHIFT)
0223 #define ADC3XXX_FORMAT_LJF      (3 << ADC3XXX_FORMAT_SHIFT)
0224 
0225 #define ADC3XXX_IFACE_16BITS        (0 << ADC3XXX_WLENGTH_SHIFT)
0226 #define ADC3XXX_IFACE_20BITS        (1 << ADC3XXX_WLENGTH_SHIFT)
0227 #define ADC3XXX_IFACE_24BITS        (2 << ADC3XXX_WLENGTH_SHIFT)
0228 #define ADC3XXX_IFACE_32BITS        (3 << ADC3XXX_WLENGTH_SHIFT)
0229 
0230 /* PLL P/R bit offsets */
0231 #define ADC3XXX_PLLP_SHIFT      4
0232 #define ADC3XXX_PLLR_SHIFT      0
0233 #define ADC3XXX_PLL_PR_MASK     0x7f
0234 #define ADC3XXX_PLLJ_MASK       0x3f
0235 #define ADC3XXX_PLLD_MSB_MASK       0x3f
0236 #define ADC3XXX_PLLD_LSB_MASK       0xff
0237 #define ADC3XXX_NADC_MASK       0x7f
0238 #define ADC3XXX_MADC_MASK       0x7f
0239 #define ADC3XXX_AOSR_MASK       0xff
0240 #define ADC3XXX_IADC_MASK       0xff
0241 #define ADC3XXX_BDIV_MASK       0x7f
0242 
0243 /* PLL_CLKIN bits */
0244 #define ADC3XXX_PLL_CLKIN_SHIFT     2
0245 #define ADC3XXX_PLL_CLKIN_MCLK      0x0
0246 #define ADC3XXX_PLL_CLKIN_BCLK      0x1
0247 #define ADC3XXX_PLL_CLKIN_ZERO      0x3
0248 
0249 /* CODEC_CLKIN bits */
0250 #define ADC3XXX_CODEC_CLKIN_SHIFT   0
0251 #define ADC3XXX_CODEC_CLKIN_MCLK    0x0
0252 #define ADC3XXX_CODEC_CLKIN_BCLK    0x1
0253 #define ADC3XXX_CODEC_CLKIN_PLL_CLK 0x3
0254 
0255 #define ADC3XXX_USE_PLL ((ADC3XXX_PLL_CLKIN_MCLK << ADC3XXX_PLL_CLKIN_SHIFT) | \
0256              (ADC3XXX_CODEC_CLKIN_PLL_CLK << ADC3XXX_CODEC_CLKIN_SHIFT))
0257 #define ADC3XXX_NO_PLL  ((ADC3XXX_PLL_CLKIN_ZERO << ADC3XXX_PLL_CLKIN_SHIFT) | \
0258              (ADC3XXX_CODEC_CLKIN_MCLK << ADC3XXX_CODEC_CLKIN_SHIFT))
0259 
0260 /*  Analog PGA control bits */
0261 #define ADC3XXX_LPGA_MUTE       0x80
0262 #define ADC3XXX_RPGA_MUTE       0x80
0263 
0264 #define ADC3XXX_LPGA_GAIN_MASK      0x7f
0265 #define ADC3XXX_RPGA_GAIN_MASK      0x7f
0266 
0267 /* ADC current modes */
0268 #define ADC3XXX_ADC_LOW_CURR_MODE   0x01
0269 
0270 /* Left ADC Input selection bits */
0271 #define ADC3XXX_LCH_SEL1_SHIFT      0
0272 #define ADC3XXX_LCH_SEL2_SHIFT      2
0273 #define ADC3XXX_LCH_SEL3_SHIFT      4
0274 #define ADC3XXX_LCH_SEL4_SHIFT      6
0275 
0276 #define ADC3XXX_LCH_SEL1X_SHIFT     0
0277 #define ADC3XXX_LCH_SEL2X_SHIFT     2
0278 #define ADC3XXX_LCH_SEL3X_SHIFT     4
0279 #define ADC3XXX_LCH_COMMON_MODE     0x40
0280 #define ADC3XXX_BYPASS_LPGA     0x80
0281 
0282 /* Right ADC Input selection bits */
0283 #define ADC3XXX_RCH_SEL1_SHIFT      0
0284 #define ADC3XXX_RCH_SEL2_SHIFT      2
0285 #define ADC3XXX_RCH_SEL3_SHIFT      4
0286 #define ADC3XXX_RCH_SEL4_SHIFT      6
0287 
0288 #define ADC3XXX_RCH_SEL1X_SHIFT     0
0289 #define ADC3XXX_RCH_SEL2X_SHIFT     2
0290 #define ADC3XXX_RCH_SEL3X_SHIFT     4
0291 #define ADC3XXX_RCH_COMMON_MODE     0x40
0292 #define ADC3XXX_BYPASS_RPGA     0x80
0293 
0294 /* MICBIAS control bits */
0295 #define ADC3XXX_MICBIAS_MASK        0x2
0296 #define ADC3XXX_MICBIAS1_SHIFT      5
0297 #define ADC3XXX_MICBIAS2_SHIFT      3
0298 
0299 #define ADC3XXX_ADC_MAX_VOLUME      64
0300 #define ADC3XXX_ADC_POS_VOL     24
0301 
0302 /* GPIO control bits (GPIO1_CTRL and GPIO2_CTRL) */
0303 #define ADC3XXX_GPIO_CTRL_CFG_MASK      0x3c
0304 #define ADC3XXX_GPIO_CTRL_CFG_SHIFT     2
0305 #define ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_MASK  0x01
0306 #define ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_SHIFT 0
0307 #define ADC3XXX_GPIO_CTRL_INPUT_VALUE_MASK  0x02
0308 #define ADC3XXX_GPIO_CTRL_INPUT_VALUE_SHIFT 1
0309 
0310 enum adc3xxx_type {
0311     ADC3001 = 0,
0312     ADC3101
0313 };
0314 
0315 struct adc3xxx {
0316     struct device *dev;
0317     enum adc3xxx_type type;
0318     struct clk *mclk;
0319     struct regmap *regmap;
0320     struct gpio_desc *rst_pin;
0321     unsigned int pll_mode;
0322     unsigned int sysclk;
0323     unsigned int gpio_cfg[ADC3XXX_GPIOS_MAX]; /* value+1 (0 => not set)  */
0324     unsigned int micbias_vg[ADC3XXX_MICBIAS_PINS];
0325     int master;
0326     u8 page_no;
0327     int use_pll;
0328     struct gpio_chip gpio_chip;
0329 };
0330 
0331 static const unsigned int adc3xxx_gpio_ctrl_reg[ADC3XXX_GPIOS_MAX] = {
0332     ADC3XXX_GPIO1_CTRL,
0333     ADC3XXX_GPIO2_CTRL
0334 };
0335 
0336 static const unsigned int adc3xxx_micbias_shift[ADC3XXX_MICBIAS_PINS] = {
0337     ADC3XXX_MICBIAS1_SHIFT,
0338     ADC3XXX_MICBIAS2_SHIFT
0339 };
0340 
0341 static const struct reg_default adc3xxx_defaults[] = {
0342     /* Page 0 */
0343     { 0, 0x00 },    { 1, 0x00 },    { 2, 0x00 },    { 3, 0x00 },
0344     { 4, 0x00 },    { 5, 0x11 },    { 6, 0x04 },    { 7, 0x00 },
0345     { 8, 0x00 },    { 9, 0x00 },    { 10, 0x00 },   { 11, 0x00 },
0346     { 12, 0x00 },   { 13, 0x00 },   { 14, 0x00 },   { 15, 0x00 },
0347     { 16, 0x00 },   { 17, 0x00 },   { 18, 0x01 },   { 19, 0x01 },
0348     { 20, 0x80 },   { 21, 0x80 },   { 22, 0x04 },   { 23, 0x00 },
0349     { 24, 0x00 },   { 25, 0x00 },   { 26, 0x01 },   { 27, 0x00 },
0350     { 28, 0x00 },   { 29, 0x02 },   { 30, 0x01 },   { 31, 0x00 },
0351     { 32, 0x00 },   { 33, 0x10 },   { 34, 0x00 },   { 35, 0x00 },
0352     { 36, 0x00 },   { 37, 0x00 },   { 38, 0x02 },   { 39, 0x00 },
0353     { 40, 0x00 },   { 41, 0x00 },   { 42, 0x00 },   { 43, 0x00 },
0354     { 44, 0x00 },   { 45, 0x00 },   { 46, 0x00 },   { 47, 0x00 },
0355     { 48, 0x00 },   { 49, 0x00 },   { 50, 0x00 },   { 51, 0x00 },
0356     { 52, 0x00 },   { 53, 0x12 },   { 54, 0x00 },   { 55, 0x00 },
0357     { 56, 0x00 },   { 57, 0x00 },   { 58, 0x00 },   { 59, 0x44 },
0358     { 60, 0x00 },   { 61, 0x01 },   { 62, 0x00 },   { 63, 0x00 },
0359     { 64, 0x00 },   { 65, 0x00 },   { 66, 0x00 },   { 67, 0x00 },
0360     { 68, 0x00 },   { 69, 0x00 },   { 70, 0x00 },   { 71, 0x00 },
0361     { 72, 0x00 },   { 73, 0x00 },   { 74, 0x00 },   { 75, 0x00 },
0362     { 76, 0x00 },   { 77, 0x00 },   { 78, 0x00 },   { 79, 0x00 },
0363     { 80, 0x00 },   { 81, 0x00 },   { 82, 0x88 },   { 83, 0x00 },
0364     { 84, 0x00 },   { 85, 0x00 },   { 86, 0x00 },   { 87, 0x00 },
0365     { 88, 0x7f },   { 89, 0x00 },   { 90, 0x00 },   { 91, 0x00 },
0366     { 92, 0x00 },   { 93, 0x00 },   { 94, 0x00 },   { 95, 0x00 },
0367     { 96, 0x7f },   { 97, 0x00 },   { 98, 0x00 },   { 99, 0x00 },
0368     { 100, 0x00 },  { 101, 0x00 },  { 102, 0x00 },  { 103, 0x00 },
0369     { 104, 0x00 },  { 105, 0x00 },  { 106, 0x00 },  { 107, 0x00 },
0370     { 108, 0x00 },  { 109, 0x00 },  { 110, 0x00 },  { 111, 0x00 },
0371     { 112, 0x00 },  { 113, 0x00 },  { 114, 0x00 },  { 115, 0x00 },
0372     { 116, 0x00 },  { 117, 0x00 },  { 118, 0x00 },  { 119, 0x00 },
0373     { 120, 0x00 },  { 121, 0x00 },  { 122, 0x00 },  { 123, 0x00 },
0374     { 124, 0x00 },  { 125, 0x00 },  { 126, 0x00 },  { 127, 0x00 },
0375 
0376     /* Page 1 */
0377     { 128, 0x00 },  { 129, 0x00 },  { 130, 0x00 },  { 131, 0x00 },
0378     { 132, 0x00 },  { 133, 0x00 },  { 134, 0x00 },  { 135, 0x00 },
0379     { 136, 0x00 },  { 137, 0x00 },  { 138, 0x00 },  { 139, 0x00 },
0380     { 140, 0x00 },  { 141, 0x00 },  { 142, 0x00 },  { 143, 0x00 },
0381     { 144, 0x00 },  { 145, 0x00 },  { 146, 0x00 },  { 147, 0x00 },
0382     { 148, 0x00 },  { 149, 0x00 },  { 150, 0x00 },  { 151, 0x00 },
0383     { 152, 0x00 },  { 153, 0x00 },  { 154, 0x00 },  { 155, 0x00 },
0384     { 156, 0x00 },  { 157, 0x00 },  { 158, 0x00 },  { 159, 0x00 },
0385     { 160, 0x00 },  { 161, 0x00 },  { 162, 0x00 },  { 163, 0x00 },
0386     { 164, 0x00 },  { 165, 0x00 },  { 166, 0x00 },  { 167, 0x00 },
0387     { 168, 0x00 },  { 169, 0x00 },  { 170, 0x00 },  { 171, 0x00 },
0388     { 172, 0x00 },  { 173, 0x00 },  { 174, 0x00 },  { 175, 0x00 },
0389     { 176, 0x00 },  { 177, 0x00 },  { 178, 0x00 },  { 179, 0x00 },
0390     { 180, 0xff },  { 181, 0x00 },  { 182, 0x3f },  { 183, 0xff },
0391     { 184, 0x00 },  { 185, 0x3f },  { 186, 0x00 },  { 187, 0x80 },
0392     { 188, 0x80 },  { 189, 0x00 },  { 190, 0x00 },  { 191, 0x00 },
0393 
0394     /* Page 4 */
0395     { 1024, 0x00 },         { 1026, 0x01 }, { 1027, 0x17 },
0396     { 1028, 0x01 }, { 1029, 0x17 }, { 1030, 0x7d }, { 1031, 0xd3 },
0397     { 1032, 0x7f }, { 1033, 0xff }, { 1034, 0x00 }, { 1035, 0x00 },
0398     { 1036, 0x00 }, { 1037, 0x00 }, { 1038, 0x7f }, { 1039, 0xff },
0399     { 1040, 0x00 }, { 1041, 0x00 }, { 1042, 0x00 }, { 1043, 0x00 },
0400     { 1044, 0x00 }, { 1045, 0x00 }, { 1046, 0x00 }, { 1047, 0x00 },
0401     { 1048, 0x7f }, { 1049, 0xff }, { 1050, 0x00 }, { 1051, 0x00 },
0402     { 1052, 0x00 }, { 1053, 0x00 }, { 1054, 0x00 }, { 1055, 0x00 },
0403     { 1056, 0x00 }, { 1057, 0x00 }, { 1058, 0x7f }, { 1059, 0xff },
0404     { 1060, 0x00 }, { 1061, 0x00 }, { 1062, 0x00 }, { 1063, 0x00 },
0405     { 1064, 0x00 }, { 1065, 0x00 }, { 1066, 0x00 }, { 1067, 0x00 },
0406     { 1068, 0x7f }, { 1069, 0xff }, { 1070, 0x00 }, { 1071, 0x00 },
0407     { 1072, 0x00 }, { 1073, 0x00 }, { 1074, 0x00 }, { 1075, 0x00 },
0408     { 1076, 0x00 }, { 1077, 0x00 }, { 1078, 0x7f }, { 1079, 0xff },
0409     { 1080, 0x00 }, { 1081, 0x00 }, { 1082, 0x00 }, { 1083, 0x00 },
0410     { 1084, 0x00 }, { 1085, 0x00 }, { 1086, 0x00 }, { 1087, 0x00 },
0411     { 1088, 0x00 }, { 1089, 0x00 }, { 1090, 0x00 }, { 1091, 0x00 },
0412     { 1092, 0x00 }, { 1093, 0x00 }, { 1094, 0x00 }, { 1095, 0x00 },
0413     { 1096, 0x00 }, { 1097, 0x00 }, { 1098, 0x00 }, { 1099, 0x00 },
0414     { 1100, 0x00 }, { 1101, 0x00 }, { 1102, 0x00 }, { 1103, 0x00 },
0415     { 1104, 0x00 }, { 1105, 0x00 }, { 1106, 0x00 }, { 1107, 0x00 },
0416     { 1108, 0x00 }, { 1109, 0x00 }, { 1110, 0x00 }, { 1111, 0x00 },
0417     { 1112, 0x00 }, { 1113, 0x00 }, { 1114, 0x00 }, { 1115, 0x00 },
0418     { 1116, 0x00 }, { 1117, 0x00 }, { 1118, 0x00 }, { 1119, 0x00 },
0419     { 1120, 0x00 }, { 1121, 0x00 }, { 1122, 0x00 }, { 1123, 0x00 },
0420     { 1124, 0x00 }, { 1125, 0x00 }, { 1126, 0x00 }, { 1127, 0x00 },
0421     { 1128, 0x00 }, { 1129, 0x00 }, { 1130, 0x00 }, { 1131, 0x00 },
0422     { 1132, 0x00 }, { 1133, 0x00 }, { 1134, 0x00 }, { 1135, 0x00 },
0423     { 1136, 0x00 }, { 1137, 0x00 }, { 1138, 0x00 }, { 1139, 0x00 },
0424     { 1140, 0x00 }, { 1141, 0x00 }, { 1142, 0x00 }, { 1143, 0x00 },
0425     { 1144, 0x00 }, { 1145, 0x00 }, { 1146, 0x00 }, { 1147, 0x00 },
0426     { 1148, 0x00 }, { 1149, 0x00 }, { 1150, 0x00 }, { 1151, 0x00 },
0427 };
0428 
0429 static bool adc3xxx_volatile_reg(struct device *dev, unsigned int reg)
0430 {
0431     switch (reg) {
0432     case ADC3XXX_RESET:
0433         return true;
0434     default:
0435         return false;
0436     }
0437 }
0438 
0439 static const struct regmap_range_cfg adc3xxx_ranges[] = {
0440     {
0441         .range_min = 0,
0442         .range_max = 5 * ADC3XXX_PAGE_SIZE,
0443         .selector_reg = ADC3XXX_PAGE_SELECT,
0444         .selector_mask = 0xff,
0445         .selector_shift = 0,
0446         .window_start = 0,
0447         .window_len = ADC3XXX_PAGE_SIZE,
0448     }
0449 };
0450 
0451 static const struct regmap_config adc3xxx_regmap = {
0452     .reg_bits = 8,
0453     .val_bits = 8,
0454 
0455     .reg_defaults = adc3xxx_defaults,
0456     .num_reg_defaults = ARRAY_SIZE(adc3xxx_defaults),
0457 
0458     .volatile_reg = adc3xxx_volatile_reg,
0459 
0460     .cache_type = REGCACHE_RBTREE,
0461 
0462     .ranges = adc3xxx_ranges,
0463     .num_ranges = ARRAY_SIZE(adc3xxx_ranges),
0464     .max_register = 5 * ADC3XXX_PAGE_SIZE,
0465 };
0466 
0467 struct adc3xxx_rate_divs {
0468     u32 mclk;
0469     u32 rate;
0470     u8 pll_p;
0471     u8 pll_r;
0472     u8 pll_j;
0473     u16 pll_d;
0474     u8 nadc;
0475     u8 madc;
0476     u8 aosr;
0477 };
0478 
0479 /*
0480  * PLL and Clock settings.
0481  * If p member is 0, PLL is not used.
0482  * The order of the entries in this table have the PLL entries before
0483  * the non-PLL entries, so that the PLL modes are preferred unless
0484  * the PLL mode setting says otherwise.
0485  */
0486 static const struct adc3xxx_rate_divs adc3xxx_divs[] = {
0487     /* mclk, rate, p, r, j, d, nadc, madc, aosr */
0488     /* 8k rate */
0489     { 12000000, 8000, 1, 1, 7, 1680, 42, 2, 128 },
0490     { 12288000, 8000, 1, 1, 7, 0000, 42, 2, 128 },
0491     /* 11.025k rate */
0492     { 12000000, 11025, 1, 1, 6, 8208, 29, 2, 128 },
0493     /* 16k rate */
0494     { 12000000, 16000, 1, 1, 7, 1680, 21, 2, 128 },
0495     { 12288000, 16000, 1, 1, 7, 0000, 21, 2, 128 },
0496     /* 22.05k rate */
0497     { 12000000, 22050, 1, 1, 7, 560, 15, 2, 128 },
0498     /* 32k rate */
0499     { 12000000, 32000, 1, 1, 8, 1920, 12, 2, 128 },
0500     { 12288000, 32000, 1, 1, 8, 0000, 12, 2, 128 },
0501     /* 44.1k rate */
0502     { 12000000, 44100, 1, 1, 7, 5264, 8, 2, 128 },
0503     /* 48k rate */
0504     { 12000000, 48000, 1, 1, 7, 1680, 7, 2, 128 },
0505     { 12288000, 48000, 1, 1, 7, 0000, 7, 2, 128 },
0506     { 24576000, 48000, 1, 1, 3, 5000, 7, 2, 128 }, /* With PLL */
0507     { 24576000, 48000, 0, 0, 0, 0000, 2, 2, 128 }, /* Without PLL */
0508     /* 88.2k rate */
0509     { 12000000, 88200, 1, 1, 7, 5264, 4, 4, 64 },
0510     /* 96k rate */
0511     { 12000000, 96000, 1, 1, 8, 1920, 4, 4, 64 },
0512 };
0513 
0514 static int adc3xxx_get_divs(struct device *dev, int mclk, int rate, int pll_mode)
0515 {
0516     int i;
0517 
0518     dev_dbg(dev, "mclk = %d, rate = %d, clock mode %u\n",
0519         mclk, rate, pll_mode);
0520     for (i = 0; i < ARRAY_SIZE(adc3xxx_divs); i++) {
0521         const struct adc3xxx_rate_divs *mode = &adc3xxx_divs[i];
0522 
0523         /* Skip this entry if it doesn't fulfill the intended clock
0524          * mode requirement. We consider anything besides the two
0525          * modes below to be the same as ADC3XXX_PLL_AUTO.
0526          */
0527         if ((pll_mode == ADC3XXX_PLL_BYPASS && mode->pll_p) ||
0528             (pll_mode == ADC3XXX_PLL_ENABLE && !mode->pll_p))
0529             continue;
0530 
0531         if (mode->rate == rate && mode->mclk == mclk)
0532             return i;
0533     }
0534 
0535     dev_info(dev, "Master clock rate %d and sample rate %d is not supported\n",
0536          mclk, rate);
0537     return -EINVAL;
0538 }
0539 
0540 static int adc3xxx_pll_delay(struct snd_soc_dapm_widget *w,
0541                  struct snd_kcontrol *kcontrol, int event)
0542 {
0543     /* 10msec delay needed after PLL power-up to allow
0544      * PLL and dividers to stabilize (datasheet p13).
0545      */
0546     usleep_range(10000, 20000);
0547 
0548     return 0;
0549 }
0550 
0551 static int adc3xxx_coefficient_info(struct snd_kcontrol *kcontrol,
0552                     struct snd_ctl_elem_info *uinfo)
0553 {
0554     int numcoeff = kcontrol->private_value >> 16;
0555 
0556     uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
0557     uinfo->count = numcoeff;
0558     uinfo->value.integer.min = 0;
0559     uinfo->value.integer.max = 0xffff; /* all coefficients are 16 bit */
0560     return 0;
0561 }
0562 
0563 static int adc3xxx_coefficient_get(struct snd_kcontrol *kcontrol,
0564                    struct snd_ctl_elem_value *ucontrol)
0565 {
0566     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0567     int numcoeff  = kcontrol->private_value >> 16;
0568     int reg = kcontrol->private_value & 0xffff;
0569     int index = 0;
0570 
0571     for (index = 0; index < numcoeff; index++) {
0572         unsigned int value_msb, value_lsb, value;
0573 
0574         value_msb = snd_soc_component_read(component, reg++);
0575         if ((int)value_msb < 0)
0576             return (int)value_msb;
0577 
0578         value_lsb = snd_soc_component_read(component, reg++);
0579         if ((int)value_lsb < 0)
0580             return (int)value_lsb;
0581 
0582         value = (value_msb << 8) | value_lsb;
0583         ucontrol->value.integer.value[index] = value;
0584     }
0585 
0586     return 0;
0587 }
0588 
0589 static int adc3xxx_coefficient_put(struct snd_kcontrol *kcontrol,
0590                    struct snd_ctl_elem_value *ucontrol)
0591 {
0592     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0593     int numcoeff  = kcontrol->private_value >> 16;
0594     int reg = kcontrol->private_value & 0xffff;
0595     int index = 0;
0596     int ret;
0597 
0598     for (index = 0; index < numcoeff; index++) {
0599         unsigned int value = ucontrol->value.integer.value[index];
0600         unsigned int value_msb = (value >> 8) & 0xff;
0601         unsigned int value_lsb = value & 0xff;
0602 
0603         ret = snd_soc_component_write(component, reg++, value_msb);
0604         if (ret)
0605             return ret;
0606 
0607         ret = snd_soc_component_write(component, reg++, value_lsb);
0608         if (ret)
0609             return ret;
0610     }
0611 
0612     return 0;
0613 }
0614 
0615 /* All on-chip filters have coefficients which are expressed in terms of
0616  * 16 bit values, so represent them as strings of 16-bit integers.
0617  */
0618 #define TI_COEFFICIENTS(xname, reg, numcoeffs) { \
0619     .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
0620     .name = xname, \
0621     .info = adc3xxx_coefficient_info, \
0622     .get = adc3xxx_coefficient_get,\
0623     .put = adc3xxx_coefficient_put, \
0624     .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \
0625     .private_value = reg | (numcoeffs << 16) \
0626 }
0627 
0628 static const char * const adc_softstepping_text[] = { "1 step", "2 step", "off" };
0629 static SOC_ENUM_SINGLE_DECL(adc_softstepping_enum, ADC3XXX_ADC_DIGITAL, 0,
0630                 adc_softstepping_text);
0631 
0632 static const char * const multiplier_text[] = { "1", "2", "4", "8", "16", "32", "64", "128" };
0633 static SOC_ENUM_SINGLE_DECL(left_agc_attack_mult_enum,
0634                 ADC3XXX_LEFT_CHN_AGC_4, 0, multiplier_text);
0635 static SOC_ENUM_SINGLE_DECL(right_agc_attack_mult_enum,
0636                 ADC3XXX_RIGHT_CHN_AGC_4, 0, multiplier_text);
0637 static SOC_ENUM_SINGLE_DECL(left_agc_decay_mult_enum,
0638                 ADC3XXX_LEFT_CHN_AGC_5, 0, multiplier_text);
0639 static SOC_ENUM_SINGLE_DECL(right_agc_decay_mult_enum,
0640                 ADC3XXX_RIGHT_CHN_AGC_5, 0, multiplier_text);
0641 
0642 static const char * const dither_dc_offset_text[] = {
0643     "0mV", "15mV", "30mV", "45mV", "60mV", "75mV", "90mV", "105mV",
0644     "-15mV", "-30mV", "-45mV", "-60mV", "-75mV", "-90mV", "-105mV"
0645 };
0646 static const unsigned int dither_dc_offset_values[] = {
0647     0, 1, 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15
0648 };
0649 static SOC_VALUE_ENUM_DOUBLE_DECL(dither_dc_offset_enum,
0650                   ADC3XXX_DITHER_CTRL,
0651                   4, 0, 0xf, dither_dc_offset_text,
0652                   dither_dc_offset_values);
0653 
0654 static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 50, 0);
0655 static const DECLARE_TLV_DB_SCALE(adc_tlv, -1200, 50, 0);
0656 static const DECLARE_TLV_DB_SCALE(adc_fine_tlv, -40, 10, 0);
0657 /* AGC target: 8 values: -5.5, -8, -10, -12, -14, -17, -20, -24 dB */
0658 /* It would be nice to declare these in the order above, but empirically
0659  * TLV_DB_SCALE_ITEM doesn't take lightly to the increment (second) parameter
0660  * being negative, despite there being examples to the contrary in other
0661  * drivers. So declare these in the order from lowest to highest, and
0662  * set the invert flag in the SOC_DOUBLE_R_TLV declaration instead.
0663  */
0664 static const DECLARE_TLV_DB_RANGE(agc_target_tlv,
0665     0, 0, TLV_DB_SCALE_ITEM(-2400, 0, 0),
0666     1, 3, TLV_DB_SCALE_ITEM(-2000, 300, 0),
0667     4, 6, TLV_DB_SCALE_ITEM(-1200, 200, 0),
0668     7, 7, TLV_DB_SCALE_ITEM(-550, 0, 0));
0669 /* Since the 'disabled' value (mute) is at the highest value in the dB
0670  * range (i.e. just before -32 dB) rather than the lowest, we need to resort
0671  * to using a TLV_DB_RANGE in order to get the mute value in the right place.
0672  */
0673 static const DECLARE_TLV_DB_RANGE(agc_thresh_tlv,
0674     0, 30, TLV_DB_SCALE_ITEM(-9000, 200, 0),
0675     31, 31, TLV_DB_SCALE_ITEM(0, 0, 1)); /* disabled = mute */
0676 /* AGC hysteresis: 4 values: 1, 2, 4 dB, disabled (= mute) */
0677 static const DECLARE_TLV_DB_RANGE(agc_hysteresis_tlv,
0678     0, 1, TLV_DB_SCALE_ITEM(100, 100, 0),
0679     2, 2, TLV_DB_SCALE_ITEM(400, 0, 0),
0680     3, 3, TLV_DB_SCALE_ITEM(0, 0, 1)); /* disabled = mute */
0681 static const DECLARE_TLV_DB_SCALE(agc_max_tlv, 0, 50, 0);
0682 /* Input attenuation: -6 dB or 0 dB */
0683 static const DECLARE_TLV_DB_SCALE(input_attenuation_tlv, -600, 600, 0);
0684 
0685 static const struct snd_kcontrol_new adc3xxx_snd_controls[] = {
0686     SOC_DOUBLE_R_TLV("PGA Capture Volume", ADC3XXX_LEFT_APGA_CTRL,
0687              ADC3XXX_RIGHT_APGA_CTRL, 0, 80, 0, pga_tlv),
0688     SOC_DOUBLE("PGA Capture Switch", ADC3XXX_ADC_FGA, 7, 3, 1, 1),
0689     SOC_DOUBLE_R("AGC Capture Switch", ADC3XXX_LEFT_CHN_AGC_1,
0690              ADC3XXX_RIGHT_CHN_AGC_1, 7, 1, 0),
0691     SOC_DOUBLE_R_TLV("AGC Target Level Capture Volume", ADC3XXX_LEFT_CHN_AGC_1,
0692              ADC3XXX_RIGHT_CHN_AGC_2, 4, 0x07, 1, agc_target_tlv),
0693     SOC_DOUBLE_R_TLV("AGC Noise Threshold Capture Volume", ADC3XXX_LEFT_CHN_AGC_2,
0694              ADC3XXX_RIGHT_CHN_AGC_2, 1, 0x1f, 1, agc_thresh_tlv),
0695     SOC_DOUBLE_R_TLV("AGC Hysteresis Capture Volume", ADC3XXX_LEFT_CHN_AGC_2,
0696              ADC3XXX_RIGHT_CHN_AGC_2, 6, 3, 0, agc_hysteresis_tlv),
0697     SOC_DOUBLE_R("AGC Clip Stepping Capture Switch", ADC3XXX_LEFT_CHN_AGC_2,
0698              ADC3XXX_RIGHT_CHN_AGC_2, 0, 1, 0),
0699     /*
0700      * Oddly enough, the data sheet says the default value
0701      * for the left/right AGC maximum gain register field
0702      * (ADC3XXX_LEFT/RIGHT_CHN_AGC_3 bits 0..6) is 0x7f = 127
0703      * (verified empirically) even though this value (indeed, above
0704      * 0x50) is specified as 'Reserved. Do not use.' in the accompanying
0705      * table in the data sheet.
0706      */
0707     SOC_DOUBLE_R_TLV("AGC Maximum Capture Volume", ADC3XXX_LEFT_CHN_AGC_3,
0708              ADC3XXX_RIGHT_CHN_AGC_3, 0, 0x50, 0, agc_max_tlv),
0709     SOC_DOUBLE_R("AGC Attack Time", ADC3XXX_LEFT_CHN_AGC_4,
0710              ADC3XXX_RIGHT_CHN_AGC_4, 3, 0x1f, 0),
0711     /* Would like to have the multipliers as LR pairs, but there is
0712      * no SOC_ENUM_foo which accepts two values in separate registers.
0713      */
0714     SOC_ENUM("AGC Left Attack Time Multiplier", left_agc_attack_mult_enum),
0715     SOC_ENUM("AGC Right Attack Time Multiplier", right_agc_attack_mult_enum),
0716     SOC_DOUBLE_R("AGC Decay Time", ADC3XXX_LEFT_CHN_AGC_5,
0717              ADC3XXX_RIGHT_CHN_AGC_5, 3, 0x1f, 0),
0718     SOC_ENUM("AGC Left Decay Time Multiplier", left_agc_decay_mult_enum),
0719     SOC_ENUM("AGC Right Decay Time Multiplier", right_agc_decay_mult_enum),
0720     SOC_DOUBLE_R("AGC Noise Debounce", ADC3XXX_LEFT_CHN_AGC_6,
0721              ADC3XXX_RIGHT_CHN_AGC_6, 0, 0x1f, 0),
0722     SOC_DOUBLE_R("AGC Signal Debounce", ADC3XXX_LEFT_CHN_AGC_7,
0723              ADC3XXX_RIGHT_CHN_AGC_7, 0, 0x0f, 0),
0724     /* Read only register */
0725     SOC_DOUBLE_R_S_TLV("AGC Applied Capture Volume", ADC3XXX_LEFT_AGC_GAIN,
0726                ADC3XXX_RIGHT_AGC_GAIN, 0, -24, 40, 6, 0, adc_tlv),
0727     /* ADC soft stepping */
0728     SOC_ENUM("ADC Soft Stepping", adc_softstepping_enum),
0729     /* Left/Right Input attenuation */
0730     SOC_SINGLE_TLV("Left Input IN_1L Capture Volume",
0731                ADC3XXX_LEFT_PGA_SEL_1, 0, 1, 1, input_attenuation_tlv),
0732     SOC_SINGLE_TLV("Left Input IN_2L Capture Volume",
0733                ADC3XXX_LEFT_PGA_SEL_1, 2, 1, 1, input_attenuation_tlv),
0734     SOC_SINGLE_TLV("Left Input IN_3L Capture Volume",
0735                ADC3XXX_LEFT_PGA_SEL_1, 4, 1, 1, input_attenuation_tlv),
0736     SOC_SINGLE_TLV("Left Input IN_1R Capture Volume",
0737                ADC3XXX_LEFT_PGA_SEL_2, 0, 1, 1, input_attenuation_tlv),
0738     SOC_SINGLE_TLV("Left Input DIF_2L_3L Capture Volume",
0739                ADC3XXX_LEFT_PGA_SEL_1, 6, 1, 1, input_attenuation_tlv),
0740     SOC_SINGLE_TLV("Left Input DIF_1L_1R Capture Volume",
0741                ADC3XXX_LEFT_PGA_SEL_2, 4, 1, 1, input_attenuation_tlv),
0742     SOC_SINGLE_TLV("Left Input DIF_2R_3R Capture Volume",
0743                ADC3XXX_LEFT_PGA_SEL_2, 2, 1, 1, input_attenuation_tlv),
0744     SOC_SINGLE_TLV("Right Input IN_1R Capture Volume",
0745                ADC3XXX_RIGHT_PGA_SEL_1, 0, 1, 1, input_attenuation_tlv),
0746     SOC_SINGLE_TLV("Right Input IN_2R Capture Volume",
0747                ADC3XXX_RIGHT_PGA_SEL_1, 2, 1, 1, input_attenuation_tlv),
0748     SOC_SINGLE_TLV("Right Input IN_3R Capture Volume",
0749                ADC3XXX_RIGHT_PGA_SEL_1, 4, 1, 1, input_attenuation_tlv),
0750     SOC_SINGLE_TLV("Right Input IN_1L Capture Volume",
0751                ADC3XXX_RIGHT_PGA_SEL_2, 0, 1, 1, input_attenuation_tlv),
0752     SOC_SINGLE_TLV("Right Input DIF_2R_3R Capture Volume",
0753                ADC3XXX_RIGHT_PGA_SEL_1, 6, 1, 1, input_attenuation_tlv),
0754     SOC_SINGLE_TLV("Right Input DIF_1L_1R Capture Volume",
0755                ADC3XXX_RIGHT_PGA_SEL_2, 4, 1, 1, input_attenuation_tlv),
0756     SOC_SINGLE_TLV("Right Input DIF_2L_3L Capture Volume",
0757                ADC3XXX_RIGHT_PGA_SEL_2, 2, 1, 1, input_attenuation_tlv),
0758     SOC_DOUBLE_R_S_TLV("ADC Volume Control Capture Volume", ADC3XXX_LADC_VOL,
0759                ADC3XXX_RADC_VOL, 0, -24, 40, 6, 0, adc_tlv),
0760     /* Empirically, the following doesn't work the way it's supposed
0761      * to. Values 0, -0.1, -0.2 and -0.3 dB result in the same level, and
0762      * -0.4 dB drops about 0.12 dB on a specific chip.
0763      */
0764     SOC_DOUBLE_TLV("ADC Fine Volume Control Capture Volume", ADC3XXX_ADC_FGA,
0765                4, 0, 4, 1, adc_fine_tlv),
0766     SOC_SINGLE("Left ADC Unselected CM Bias Capture Switch",
0767            ADC3XXX_LEFT_PGA_SEL_2, 6, 1, 0),
0768     SOC_SINGLE("Right ADC Unselected CM Bias Capture Switch",
0769            ADC3XXX_RIGHT_PGA_SEL_2, 6, 1, 0),
0770     SOC_ENUM("Dither Control DC Offset", dither_dc_offset_enum),
0771 
0772     /* Coefficient memory for miniDSP. */
0773     /* For the default PRB_R1 processing block, the only available
0774      * filter is the first order IIR.
0775      */
0776 
0777     TI_COEFFICIENTS("Left ADC IIR Coefficients N0 N1 D1",
0778             ADC3XXX_LEFT_ADC_IIR_COEFF_N0_MSB, 3),
0779 
0780     TI_COEFFICIENTS("Right ADC IIR Coefficients N0 N1 D1",
0781             ADC3XXX_RIGHT_ADC_IIR_COEFF_N0_MSB, 3),
0782 };
0783 
0784 /* Left input selection, Single Ended inputs and Differential inputs */
0785 static const struct snd_kcontrol_new left_input_mixer_controls[] = {
0786     SOC_DAPM_SINGLE("IN_1L Capture Switch",
0787             ADC3XXX_LEFT_PGA_SEL_1, 1, 0x1, 1),
0788     SOC_DAPM_SINGLE("IN_2L Capture Switch",
0789             ADC3XXX_LEFT_PGA_SEL_1, 3, 0x1, 1),
0790     SOC_DAPM_SINGLE("IN_3L Capture Switch",
0791             ADC3XXX_LEFT_PGA_SEL_1, 5, 0x1, 1),
0792     SOC_DAPM_SINGLE("DIF_2L_3L Capture Switch",
0793             ADC3XXX_LEFT_PGA_SEL_1, 7, 0x1, 1),
0794     SOC_DAPM_SINGLE("DIF_1L_1R Capture Switch",
0795             ADC3XXX_LEFT_PGA_SEL_2, 5, 0x1, 1),
0796     SOC_DAPM_SINGLE("DIF_2R_3R Capture Switch",
0797             ADC3XXX_LEFT_PGA_SEL_2, 3, 0x1, 1),
0798     SOC_DAPM_SINGLE("IN_1R Capture Switch",
0799             ADC3XXX_LEFT_PGA_SEL_2, 1, 0x1, 1),
0800 };
0801 
0802 /* Right input selection, Single Ended inputs and Differential inputs */
0803 static const struct snd_kcontrol_new right_input_mixer_controls[] = {
0804     SOC_DAPM_SINGLE("IN_1R Capture Switch",
0805             ADC3XXX_RIGHT_PGA_SEL_1, 1, 0x1, 1),
0806     SOC_DAPM_SINGLE("IN_2R Capture Switch",
0807             ADC3XXX_RIGHT_PGA_SEL_1, 3, 0x1, 1),
0808     SOC_DAPM_SINGLE("IN_3R Capture Switch",
0809              ADC3XXX_RIGHT_PGA_SEL_1, 5, 0x1, 1),
0810     SOC_DAPM_SINGLE("DIF_2R_3R Capture Switch",
0811              ADC3XXX_RIGHT_PGA_SEL_1, 7, 0x1, 1),
0812     SOC_DAPM_SINGLE("DIF_1L_1R Capture Switch",
0813              ADC3XXX_RIGHT_PGA_SEL_2, 5, 0x1, 1),
0814     SOC_DAPM_SINGLE("DIF_2L_3L Capture Switch",
0815              ADC3XXX_RIGHT_PGA_SEL_2, 3, 0x1, 1),
0816     SOC_DAPM_SINGLE("IN_1L Capture Switch",
0817              ADC3XXX_RIGHT_PGA_SEL_2, 1, 0x1, 1),
0818 };
0819 
0820 /* Left Digital Mic input for left ADC */
0821 static const struct snd_kcontrol_new left_input_dmic_controls[] = {
0822     SOC_DAPM_SINGLE("Left ADC Capture Switch",
0823             ADC3XXX_ADC_DIGITAL, 3, 0x1, 0),
0824 };
0825 
0826 /* Right Digital Mic input for Right ADC */
0827 static const struct snd_kcontrol_new right_input_dmic_controls[] = {
0828     SOC_DAPM_SINGLE("Right ADC Capture Switch",
0829             ADC3XXX_ADC_DIGITAL, 2, 0x1, 0),
0830 };
0831 
0832 /* DAPM widgets */
0833 static const struct snd_soc_dapm_widget adc3xxx_dapm_widgets[] = {
0834 
0835     /* Left Input Selection */
0836     SND_SOC_DAPM_MIXER("Left Input", SND_SOC_NOPM, 0, 0,
0837                &left_input_mixer_controls[0],
0838                ARRAY_SIZE(left_input_mixer_controls)),
0839     /* Right Input Selection */
0840     SND_SOC_DAPM_MIXER("Right Input", SND_SOC_NOPM, 0, 0,
0841                &right_input_mixer_controls[0],
0842                ARRAY_SIZE(right_input_mixer_controls)),
0843     /* PGA selection */
0844     SND_SOC_DAPM_PGA("Left PGA", ADC3XXX_LEFT_APGA_CTRL, 7, 1, NULL, 0),
0845     SND_SOC_DAPM_PGA("Right PGA", ADC3XXX_RIGHT_APGA_CTRL, 7, 1, NULL, 0),
0846 
0847     /* Digital Microphone Input Control for Left/Right ADC */
0848     SND_SOC_DAPM_MIXER("Left DMic Input", SND_SOC_NOPM, 0, 0,
0849             &left_input_dmic_controls[0],
0850             ARRAY_SIZE(left_input_dmic_controls)),
0851     SND_SOC_DAPM_MIXER("Right DMic Input", SND_SOC_NOPM, 0, 0,
0852             &right_input_dmic_controls[0],
0853             ARRAY_SIZE(right_input_dmic_controls)),
0854 
0855     /* Left/Right ADC */
0856     SND_SOC_DAPM_ADC("Left ADC", "Left Capture", ADC3XXX_ADC_DIGITAL, 7, 0),
0857     SND_SOC_DAPM_ADC("Right ADC", "Right Capture", ADC3XXX_ADC_DIGITAL, 6, 0),
0858 
0859     /* Inputs */
0860     SND_SOC_DAPM_INPUT("IN_1L"),
0861     SND_SOC_DAPM_INPUT("IN_1R"),
0862     SND_SOC_DAPM_INPUT("IN_2L"),
0863     SND_SOC_DAPM_INPUT("IN_2R"),
0864     SND_SOC_DAPM_INPUT("IN_3L"),
0865     SND_SOC_DAPM_INPUT("IN_3R"),
0866     SND_SOC_DAPM_INPUT("DIFL_1L_1R"),
0867     SND_SOC_DAPM_INPUT("DIFL_2L_3L"),
0868     SND_SOC_DAPM_INPUT("DIFL_2R_3R"),
0869     SND_SOC_DAPM_INPUT("DIFR_1L_1R"),
0870     SND_SOC_DAPM_INPUT("DIFR_2L_3L"),
0871     SND_SOC_DAPM_INPUT("DIFR_2R_3R"),
0872     SND_SOC_DAPM_INPUT("DMic_L"),
0873     SND_SOC_DAPM_INPUT("DMic_R"),
0874 
0875     /* Digital audio interface output */
0876     SND_SOC_DAPM_AIF_OUT("AIF_OUT", "Capture", 0, SND_SOC_NOPM, 0, 0),
0877 
0878     /* Clocks */
0879     SND_SOC_DAPM_SUPPLY("PLL_CLK", ADC3XXX_PLL_PROG_PR, ADC3XXX_ENABLE_PLL_SHIFT,
0880                 0, adc3xxx_pll_delay, SND_SOC_DAPM_POST_PMU),
0881 
0882     SND_SOC_DAPM_SUPPLY("ADC_CLK", ADC3XXX_ADC_NADC, ADC3XXX_ENABLE_NADC_SHIFT,
0883                 0, NULL, 0),
0884     SND_SOC_DAPM_SUPPLY("ADC_MOD_CLK", ADC3XXX_ADC_MADC, ADC3XXX_ENABLE_MADC_SHIFT,
0885                 0, NULL, 0),
0886 
0887     /* This refers to the generated BCLK in master mode. */
0888     SND_SOC_DAPM_SUPPLY("BCLK", ADC3XXX_BCLK_N_DIV, ADC3XXX_ENABLE_BCLK_SHIFT,
0889                 0, NULL, 0),
0890 };
0891 
0892 static const struct snd_soc_dapm_route adc3xxx_intercon[] = {
0893     /* Left input selection from switches */
0894     { "Left Input", "IN_1L Capture Switch", "IN_1L" },
0895     { "Left Input", "IN_2L Capture Switch", "IN_2L" },
0896     { "Left Input", "IN_3L Capture Switch", "IN_3L" },
0897     { "Left Input", "DIF_2L_3L Capture Switch", "DIFL_2L_3L" },
0898     { "Left Input", "DIF_1L_1R Capture Switch", "DIFL_1L_1R" },
0899     { "Left Input", "DIF_2R_3R Capture Switch", "DIFL_2R_3R" },
0900     { "Left Input", "IN_1R Capture Switch", "IN_1R" },
0901 
0902     /* Left input selection to left PGA */
0903     { "Left PGA", NULL, "Left Input" },
0904 
0905     /* Left PGA to left ADC */
0906     { "Left ADC", NULL, "Left PGA" },
0907 
0908     /* Right input selection from switches */
0909     { "Right Input", "IN_1R Capture Switch", "IN_1R" },
0910     { "Right Input", "IN_2R Capture Switch", "IN_2R" },
0911     { "Right Input", "IN_3R Capture Switch", "IN_3R" },
0912     { "Right Input", "DIF_2R_3R Capture Switch", "DIFR_2R_3R" },
0913     { "Right Input", "DIF_1L_1R Capture Switch", "DIFR_1L_1R" },
0914     { "Right Input", "DIF_2L_3L Capture Switch", "DIFR_2L_3L" },
0915     { "Right Input", "IN_1L Capture Switch", "IN_1L" },
0916 
0917     /* Right input selection to right PGA */
0918     { "Right PGA", NULL, "Right Input" },
0919 
0920     /* Right PGA to right ADC */
0921     { "Right ADC", NULL, "Right PGA" },
0922 
0923     /* Left DMic Input selection from switch */
0924     { "Left DMic Input", "Left ADC Capture Switch", "DMic_L" },
0925 
0926     /* Left DMic to left ADC */
0927     { "Left ADC", NULL, "Left DMic Input" },
0928 
0929     /* Right DMic Input selection from switch */
0930     { "Right DMic Input", "Right ADC Capture Switch", "DMic_R" },
0931 
0932     /* Right DMic to right ADC */
0933     { "Right ADC", NULL, "Right DMic Input" },
0934 
0935     /* ADC to AIF output */
0936     { "AIF_OUT", NULL, "Left ADC" },
0937     { "AIF_OUT", NULL, "Right ADC" },
0938 
0939     /* Clocking */
0940     { "ADC_MOD_CLK", NULL, "ADC_CLK" },
0941     { "Left ADC", NULL, "ADC_MOD_CLK" },
0942     { "Right ADC", NULL, "ADC_MOD_CLK" },
0943 
0944     { "BCLK", NULL, "ADC_CLK" },
0945 };
0946 
0947 static const struct snd_soc_dapm_route adc3xxx_pll_intercon[] = {
0948     { "ADC_CLK", NULL, "PLL_CLK" },
0949 };
0950 
0951 static const struct snd_soc_dapm_route adc3xxx_bclk_out_intercon[] = {
0952     { "AIF_OUT", NULL, "BCLK" }
0953 };
0954 
0955 static int adc3xxx_gpio_request(struct gpio_chip *chip, unsigned int offset)
0956 {
0957     struct adc3xxx *adc3xxx = gpiochip_get_data(chip);
0958 
0959     if (offset >= ADC3XXX_GPIOS_MAX)
0960         return -EINVAL;
0961 
0962     /* GPIO1 is offset 0, GPIO2 is offset 1 */
0963     /* We check here that the GPIO pins are either not configured in the
0964      * DT, or that they purposely are set as outputs.
0965      * (Input mode not yet implemented).
0966      */
0967     if (adc3xxx->gpio_cfg[offset] != 0 &&
0968         adc3xxx->gpio_cfg[offset] != ADC3XXX_GPIO_GPO + 1)
0969         return -EINVAL;
0970 
0971     return 0;
0972 }
0973 
0974 static int adc3xxx_gpio_direction_out(struct gpio_chip *chip,
0975                       unsigned int offset, int value)
0976 {
0977     struct adc3xxx *adc3xxx = gpiochip_get_data(chip);
0978 
0979     /* Set GPIO output function. */
0980     return regmap_update_bits(adc3xxx->regmap,
0981                   adc3xxx_gpio_ctrl_reg[offset],
0982                   ADC3XXX_GPIO_CTRL_CFG_MASK |
0983                   ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_MASK,
0984                   ADC3XXX_GPIO_GPO << ADC3XXX_GPIO_CTRL_CFG_SHIFT |
0985                   !!value << ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_SHIFT);
0986 }
0987 
0988 /* With only GPIO outputs configured, we never get the .direction_out call,
0989  * so we set the output mode and output value in the same call. Hence
0990  * .set in practice does the same thing as .direction_out .
0991  */
0992 static void adc3xxx_gpio_set(struct gpio_chip *chip, unsigned int offset,
0993                  int value)
0994 {
0995     (void) adc3xxx_gpio_direction_out(chip, offset, value);
0996 }
0997 
0998 /* Even though we only support GPIO output for now, some GPIO clients
0999  * want to read the current pin state using the .get callback.
1000  */
1001 static int adc3xxx_gpio_get(struct gpio_chip *chip, unsigned int offset)
1002 {
1003     struct adc3xxx *adc3xxx = gpiochip_get_data(chip);
1004     unsigned int regval;
1005     int ret;
1006 
1007     /* We only allow output pins, so just read the value set in the output
1008      * pin register field.
1009      */
1010     ret = regmap_read(adc3xxx->regmap, adc3xxx_gpio_ctrl_reg[offset], &regval);
1011     if (ret)
1012         return ret;
1013     return !!(regval & ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_MASK);
1014 }
1015 
1016 static const struct gpio_chip adc3xxx_gpio_chip = {
1017     .label          = "adc3xxx",
1018     .owner          = THIS_MODULE,
1019     .request        = adc3xxx_gpio_request,
1020     .direction_output   = adc3xxx_gpio_direction_out,
1021     .set            = adc3xxx_gpio_set,
1022     .get            = adc3xxx_gpio_get,
1023     .can_sleep      = 1,
1024 };
1025 
1026 static void adc3xxx_free_gpio(struct adc3xxx *adc3xxx)
1027 {
1028     gpiochip_remove(&adc3xxx->gpio_chip);
1029 }
1030 
1031 static void adc3xxx_init_gpio(struct adc3xxx *adc3xxx)
1032 {
1033     int gpio, micbias;
1034     int ret;
1035 
1036     adc3xxx->gpio_chip = adc3xxx_gpio_chip;
1037     adc3xxx->gpio_chip.ngpio = ADC3XXX_GPIOS_MAX;
1038     adc3xxx->gpio_chip.parent = adc3xxx->dev;
1039     adc3xxx->gpio_chip.base = -1;
1040 
1041     ret = gpiochip_add_data(&adc3xxx->gpio_chip, adc3xxx);
1042     if (ret)
1043         dev_err(adc3xxx->dev, "Failed to add gpios: %d\n", ret);
1044 
1045     /* Set up potential GPIO configuration from the devicetree.
1046      * This allows us to set up things which are not software
1047      * controllable GPIOs, such as PDM microphone I/O,
1048      */
1049     for (gpio = 0; gpio < ADC3XXX_GPIOS_MAX; gpio++) {
1050         unsigned int cfg = adc3xxx->gpio_cfg[gpio];
1051 
1052         if (cfg) {
1053             cfg--; /* actual value to use is stored +1 */
1054             regmap_update_bits(adc3xxx->regmap,
1055                        adc3xxx_gpio_ctrl_reg[gpio],
1056                        ADC3XXX_GPIO_CTRL_CFG_MASK,
1057                        cfg << ADC3XXX_GPIO_CTRL_CFG_SHIFT);
1058         }
1059     }
1060 
1061     /* Set up micbias voltage */
1062     for (micbias = 0; micbias < ADC3XXX_MICBIAS_PINS; micbias++) {
1063         unsigned int vg = adc3xxx->micbias_vg[micbias];
1064 
1065         regmap_update_bits(adc3xxx->regmap,
1066                    ADC3XXX_MICBIAS_CTRL,
1067                    ADC3XXX_MICBIAS_MASK << adc3xxx_micbias_shift[micbias],
1068                    vg << adc3xxx_micbias_shift[micbias]);
1069     }
1070 }
1071 
1072 static int adc3xxx_parse_dt_gpio(struct adc3xxx *adc3xxx,
1073                  const char *propname, unsigned int *cfg)
1074 {
1075     struct device *dev = adc3xxx->dev;
1076     struct device_node *np = dev->of_node;
1077     unsigned int val;
1078 
1079     if (!of_property_read_u32(np, propname, &val)) {
1080         if (val & ~15 || val == 7 || val >= 11) {
1081             dev_err(dev, "Invalid property value for '%s'\n", propname);
1082             return -EINVAL;
1083         }
1084         if (val == ADC3XXX_GPIO_GPI)
1085             dev_warn(dev, "GPIO Input read not yet implemented\n");
1086         *cfg = val + 1; /* 0 => not set up, all others shifted +1 */
1087     }
1088     return 0;
1089 }
1090 
1091 static int adc3xxx_parse_dt_micbias(struct adc3xxx *adc3xxx,
1092                     const char *propname, unsigned int *vg)
1093 {
1094     struct device *dev = adc3xxx->dev;
1095     struct device_node *np = dev->of_node;
1096     unsigned int val;
1097 
1098     if (!of_property_read_u32(np, propname, &val)) {
1099         if (val >= ADC3XXX_MICBIAS_AVDD) {
1100             dev_err(dev, "Invalid property value for '%s'\n", propname);
1101             return -EINVAL;
1102         }
1103         *vg = val;
1104     }
1105     return 0;
1106 }
1107 
1108 static int adc3xxx_parse_pll_mode(uint32_t val, unsigned int *pll_mode)
1109 {
1110     if (val != ADC3XXX_PLL_ENABLE && val != ADC3XXX_PLL_BYPASS &&
1111         val != ADC3XXX_PLL_AUTO)
1112         return -EINVAL;
1113 
1114     *pll_mode = val;
1115 
1116     return 0;
1117 }
1118 
1119 static void adc3xxx_setup_pll(struct snd_soc_component *component,
1120                   int div_entry)
1121 {
1122     int i = div_entry;
1123 
1124     /* P & R values */
1125     snd_soc_component_write(component, ADC3XXX_PLL_PROG_PR,
1126                 (adc3xxx_divs[i].pll_p << ADC3XXX_PLLP_SHIFT) |
1127                 (adc3xxx_divs[i].pll_r << ADC3XXX_PLLR_SHIFT));
1128     /* J value */
1129     snd_soc_component_write(component, ADC3XXX_PLL_PROG_J,
1130                 adc3xxx_divs[i].pll_j & ADC3XXX_PLLJ_MASK);
1131     /* D value */
1132     snd_soc_component_write(component, ADC3XXX_PLL_PROG_D_LSB,
1133                 adc3xxx_divs[i].pll_d & ADC3XXX_PLLD_LSB_MASK);
1134     snd_soc_component_write(component, ADC3XXX_PLL_PROG_D_MSB,
1135                 (adc3xxx_divs[i].pll_d >> 8) & ADC3XXX_PLLD_MSB_MASK);
1136 }
1137 
1138 static int adc3xxx_hw_params(struct snd_pcm_substream *substream,
1139                  struct snd_pcm_hw_params *params,
1140                  struct snd_soc_dai *dai)
1141 {
1142     struct snd_soc_component *component = dai->component;
1143     struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(dai->component);
1144     struct adc3xxx *adc3xxx = snd_soc_component_get_drvdata(component);
1145     int i, width = 16;
1146     u8 iface_len, bdiv;
1147 
1148     i = adc3xxx_get_divs(component->dev, adc3xxx->sysclk,
1149                  params_rate(params), adc3xxx->pll_mode);
1150 
1151     if (i < 0)
1152         return i;
1153 
1154     /* select data word length */
1155     switch (params_width(params)) {
1156     case 16:
1157         iface_len = ADC3XXX_IFACE_16BITS;
1158         width = 16;
1159         break;
1160     case 20:
1161         iface_len = ADC3XXX_IFACE_20BITS;
1162         width = 20;
1163         break;
1164     case 24:
1165         iface_len = ADC3XXX_IFACE_24BITS;
1166         width = 24;
1167         break;
1168     case 32:
1169         iface_len = ADC3XXX_IFACE_32BITS;
1170         width = 32;
1171         break;
1172     default:
1173         dev_err(component->dev, "Unsupported serial data format\n");
1174         return -EINVAL;
1175     }
1176     snd_soc_component_update_bits(component, ADC3XXX_INTERFACE_CTRL_1,
1177                       ADC3XXX_WLENGTH_MASK, iface_len);
1178     if (adc3xxx_divs[i].pll_p) { /* If PLL used for this mode */
1179         adc3xxx_setup_pll(component, i);
1180         snd_soc_component_write(component, ADC3XXX_CLKGEN_MUX, ADC3XXX_USE_PLL);
1181         if (!adc3xxx->use_pll) {
1182             snd_soc_dapm_add_routes(dapm, adc3xxx_pll_intercon,
1183                         ARRAY_SIZE(adc3xxx_pll_intercon));
1184             adc3xxx->use_pll = 1;
1185         }
1186     } else {
1187         snd_soc_component_write(component, ADC3XXX_CLKGEN_MUX, ADC3XXX_NO_PLL);
1188         if (adc3xxx->use_pll) {
1189             snd_soc_dapm_del_routes(dapm, adc3xxx_pll_intercon,
1190                         ARRAY_SIZE(adc3xxx_pll_intercon));
1191             adc3xxx->use_pll = 0;
1192         }
1193     }
1194 
1195     /* NADC */
1196     snd_soc_component_update_bits(component, ADC3XXX_ADC_NADC,
1197                       ADC3XXX_NADC_MASK, adc3xxx_divs[i].nadc);
1198     /* MADC */
1199     snd_soc_component_update_bits(component, ADC3XXX_ADC_MADC,
1200                       ADC3XXX_MADC_MASK, adc3xxx_divs[i].madc);
1201     /* AOSR */
1202     snd_soc_component_update_bits(component, ADC3XXX_ADC_AOSR,
1203                       ADC3XXX_AOSR_MASK, adc3xxx_divs[i].aosr);
1204     /* BDIV N Value */
1205     /* BCLK is (by default) set up to be derived from ADC_CLK */
1206     bdiv = (adc3xxx_divs[i].aosr * adc3xxx_divs[i].madc) / (2 * width);
1207     snd_soc_component_update_bits(component, ADC3XXX_BCLK_N_DIV,
1208                       ADC3XXX_BDIV_MASK, bdiv);
1209 
1210     return 0;
1211 }
1212 
1213 static const char *adc3xxx_pll_mode_text(int pll_mode)
1214 {
1215     switch (pll_mode) {
1216     case ADC3XXX_PLL_AUTO:
1217         return "PLL auto";
1218     case ADC3XXX_PLL_ENABLE:
1219         return "PLL enable";
1220     case ADC3XXX_PLL_BYPASS:
1221         return "PLL bypass";
1222     default:
1223         break;
1224     }
1225 
1226     return "PLL unknown";
1227 }
1228 
1229 static int adc3xxx_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1230                   int clk_id, unsigned int freq, int dir)
1231 {
1232     struct snd_soc_component *component = codec_dai->component;
1233     struct adc3xxx *adc3xxx = snd_soc_component_get_drvdata(component);
1234     int ret;
1235 
1236     ret = adc3xxx_parse_pll_mode(clk_id, &adc3xxx->pll_mode);
1237     if (ret < 0)
1238         return ret;
1239 
1240     adc3xxx->sysclk = freq;
1241     dev_dbg(component->dev, "Set sysclk to %u Hz, %s\n",
1242         freq, adc3xxx_pll_mode_text(adc3xxx->pll_mode));
1243     return 0;
1244 }
1245 
1246 static int adc3xxx_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
1247 {
1248     struct snd_soc_component *component = codec_dai->component;
1249     struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1250     struct adc3xxx *adc3xxx = snd_soc_component_get_drvdata(component);
1251     u8 clkdir = 0, format = 0;
1252     int master = 0;
1253     int ret;
1254 
1255     switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
1256     case SND_SOC_DAIFMT_CBP_CFP:
1257         master = 1;
1258         clkdir = ADC3XXX_BCLK_MASTER | ADC3XXX_WCLK_MASTER;
1259         break;
1260     case SND_SOC_DAIFMT_CBC_CFC:
1261         master = 0;
1262         break;
1263     default:
1264         dev_err(component->dev, "Invalid DAI clock setup\n");
1265         return -EINVAL;
1266     }
1267 
1268     /*
1269      * match both interface format and signal polarities since they
1270      * are fixed
1271      */
1272     switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_INV_MASK)) {
1273     case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF:
1274         format = ADC3XXX_FORMAT_I2S;
1275         break;
1276     case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF:
1277         format = ADC3XXX_FORMAT_DSP;
1278         break;
1279     case SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF:
1280         format = ADC3XXX_FORMAT_DSP;
1281         break;
1282     case SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF:
1283         format = ADC3XXX_FORMAT_RJF;
1284         break;
1285     case SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF:
1286         format = ADC3XXX_FORMAT_LJF;
1287         break;
1288     default:
1289         dev_err(component->dev, "Invalid DAI format\n");
1290         return -EINVAL;
1291     }
1292 
1293     /* Add/del route enabling BCLK output as applicable */
1294     if (master && !adc3xxx->master)
1295         snd_soc_dapm_add_routes(dapm, adc3xxx_bclk_out_intercon,
1296                     ARRAY_SIZE(adc3xxx_bclk_out_intercon));
1297     else if (!master && adc3xxx->master)
1298         snd_soc_dapm_del_routes(dapm, adc3xxx_bclk_out_intercon,
1299                     ARRAY_SIZE(adc3xxx_bclk_out_intercon));
1300     adc3xxx->master = master;
1301 
1302     /* set clock direction and format */
1303     ret = snd_soc_component_update_bits(component,
1304                         ADC3XXX_INTERFACE_CTRL_1,
1305                         ADC3XXX_CLKDIR_MASK | ADC3XXX_FORMAT_MASK,
1306                         clkdir | format);
1307     if (ret < 0)
1308         return ret;
1309     return 0;
1310 }
1311 
1312 static const struct snd_soc_dai_ops adc3xxx_dai_ops = {
1313     .hw_params  = adc3xxx_hw_params,
1314     .set_sysclk = adc3xxx_set_dai_sysclk,
1315     .set_fmt    = adc3xxx_set_dai_fmt,
1316 };
1317 
1318 static struct snd_soc_dai_driver adc3xxx_dai = {
1319     .name = "tlv320adc3xxx-hifi",
1320     .capture = {
1321             .stream_name = "Capture",
1322             .channels_min = 1,
1323             .channels_max = 2,
1324             .rates = ADC3XXX_RATES,
1325             .formats = ADC3XXX_FORMATS,
1326            },
1327     .ops = &adc3xxx_dai_ops,
1328 };
1329 
1330 static const struct snd_soc_component_driver soc_component_dev_adc3xxx = {
1331     .controls       = adc3xxx_snd_controls,
1332     .num_controls       = ARRAY_SIZE(adc3xxx_snd_controls),
1333     .dapm_widgets       = adc3xxx_dapm_widgets,
1334     .num_dapm_widgets   = ARRAY_SIZE(adc3xxx_dapm_widgets),
1335     .dapm_routes        = adc3xxx_intercon,
1336     .num_dapm_routes    = ARRAY_SIZE(adc3xxx_intercon),
1337     .endianness     = 1,
1338 };
1339 
1340 static const struct i2c_device_id adc3xxx_i2c_id[] = {
1341     { "tlv320adc3001", ADC3001 },
1342     { "tlv320adc3101", ADC3101 },
1343     {}
1344 };
1345 MODULE_DEVICE_TABLE(i2c, adc3xxx_i2c_id);
1346 
1347 static int adc3xxx_i2c_probe(struct i2c_client *i2c)
1348 {
1349     struct device *dev = &i2c->dev;
1350     struct adc3xxx *adc3xxx = NULL;
1351     const struct i2c_device_id *id;
1352     int ret;
1353 
1354     adc3xxx = devm_kzalloc(dev, sizeof(struct adc3xxx), GFP_KERNEL);
1355     if (!adc3xxx)
1356         return -ENOMEM;
1357     adc3xxx->dev = dev;
1358 
1359     adc3xxx->rst_pin = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1360     if (IS_ERR(adc3xxx->rst_pin)) {
1361         return dev_err_probe(dev, PTR_ERR(adc3xxx->rst_pin),
1362                      "Failed to request rst_pin\n");
1363     }
1364 
1365     adc3xxx->mclk = devm_clk_get(dev, NULL);
1366     if (IS_ERR(adc3xxx->mclk)) {
1367         /*
1368          * The chip itself supports running off the BCLK either
1369          * directly or via the PLL, but the driver does not (yet), so
1370          * having a specified mclk is required. Otherwise, we could
1371          * use the lack of a clocks property to indicate when BCLK is
1372          * intended as the clock source.
1373          */
1374         return dev_err_probe(dev, PTR_ERR(adc3xxx->mclk),
1375                      "Failed to acquire MCLK\n");
1376     } else if (adc3xxx->mclk) {
1377         ret = clk_prepare_enable(adc3xxx->mclk);
1378         if (ret < 0)
1379             return ret;
1380         dev_dbg(dev, "Enabled MCLK, freq %lu Hz\n", clk_get_rate(adc3xxx->mclk));
1381     }
1382 
1383     ret = adc3xxx_parse_dt_gpio(adc3xxx, "ti,dmdin-gpio1", &adc3xxx->gpio_cfg[0]);
1384     if (ret < 0)
1385         goto err_unprepare_mclk;
1386     ret = adc3xxx_parse_dt_gpio(adc3xxx, "ti,dmclk-gpio2", &adc3xxx->gpio_cfg[1]);
1387     if (ret < 0)
1388         goto err_unprepare_mclk;
1389     ret = adc3xxx_parse_dt_micbias(adc3xxx, "ti,micbias1-vg", &adc3xxx->micbias_vg[0]);
1390     if (ret < 0)
1391         goto err_unprepare_mclk;
1392     ret = adc3xxx_parse_dt_micbias(adc3xxx, "ti,micbias2-vg", &adc3xxx->micbias_vg[1]);
1393     if (ret < 0)
1394         goto err_unprepare_mclk;
1395 
1396     adc3xxx->regmap = devm_regmap_init_i2c(i2c, &adc3xxx_regmap);
1397     if (IS_ERR(adc3xxx->regmap)) {
1398         ret = PTR_ERR(adc3xxx->regmap);
1399         goto err_unprepare_mclk;
1400     }
1401 
1402     i2c_set_clientdata(i2c, adc3xxx);
1403 
1404     id = i2c_match_id(adc3xxx_i2c_id, i2c);
1405     adc3xxx->type = id->driver_data;
1406 
1407     /* Reset codec chip */
1408     gpiod_set_value_cansleep(adc3xxx->rst_pin, 1);
1409     usleep_range(2000, 100000); /* Requirement: > 10 ns (datasheet p13) */
1410     gpiod_set_value_cansleep(adc3xxx->rst_pin, 0);
1411 
1412     /* Potentially set up pins used as GPIOs */
1413     adc3xxx_init_gpio(adc3xxx);
1414 
1415     ret = snd_soc_register_component(dev,
1416             &soc_component_dev_adc3xxx, &adc3xxx_dai, 1);
1417     if (ret < 0) {
1418         dev_err(dev, "Failed to register codec: %d\n", ret);
1419         goto err_unprepare_mclk;
1420     }
1421 
1422     return 0;
1423 
1424 err_unprepare_mclk:
1425     clk_disable_unprepare(adc3xxx->mclk);
1426     return ret;
1427 }
1428 
1429 static int __exit adc3xxx_i2c_remove(struct i2c_client *client)
1430 {
1431     struct adc3xxx *adc3xxx = i2c_get_clientdata(client);
1432 
1433     if (adc3xxx->mclk)
1434         clk_disable_unprepare(adc3xxx->mclk);
1435     adc3xxx_free_gpio(adc3xxx);
1436     snd_soc_unregister_component(&client->dev);
1437     return 0;
1438 }
1439 
1440 static const struct of_device_id tlv320adc3xxx_of_match[] = {
1441     { .compatible = "ti,tlv320adc3001", },
1442     { .compatible = "ti,tlv320adc3101", },
1443     {},
1444 };
1445 MODULE_DEVICE_TABLE(of, tlv320adc3xxx_of_match);
1446 
1447 static struct i2c_driver adc3xxx_i2c_driver = {
1448     .driver = {
1449            .name = "tlv320adc3xxx-codec",
1450            .of_match_table = tlv320adc3xxx_of_match,
1451           },
1452     .probe_new = adc3xxx_i2c_probe,
1453     .remove = adc3xxx_i2c_remove,
1454     .id_table = adc3xxx_i2c_id,
1455 };
1456 
1457 module_i2c_driver(adc3xxx_i2c_driver);
1458 
1459 MODULE_DESCRIPTION("ASoC TLV320ADC3xxx codec driver");
1460 MODULE_AUTHOR("shahina.s@mistralsolutions.com");
1461 MODULE_LICENSE("GPL v2");
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