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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * TAS5086 ASoC codec driver
0004  *
0005  * Copyright (c) 2013 Daniel Mack <zonque@gmail.com>
0006  *
0007  * TODO:
0008  *  - implement DAPM and input muxing
0009  *  - implement modulation limit
0010  *  - implement non-default PWM start
0011  *
0012  * Note that this chip has a very unusual register layout, specifically
0013  * because the registers are of unequal size, and multi-byte registers
0014  * require bulk writes to take effect. Regmap does not support that kind
0015  * of devices.
0016  *
0017  * Currently, the driver does not touch any of the registers >= 0x20, so
0018  * it doesn't matter because the entire map can be accessed as 8-bit
0019  * array. In case more features will be added in the future
0020  * that require access to higher registers, the entire regmap H/W I/O
0021  * routines have to be open-coded.
0022  */
0023 
0024 #include <linux/module.h>
0025 #include <linux/slab.h>
0026 #include <linux/delay.h>
0027 #include <linux/gpio.h>
0028 #include <linux/i2c.h>
0029 #include <linux/regmap.h>
0030 #include <linux/regulator/consumer.h>
0031 #include <linux/spi/spi.h>
0032 #include <linux/of.h>
0033 #include <linux/of_device.h>
0034 #include <linux/of_gpio.h>
0035 #include <sound/pcm.h>
0036 #include <sound/pcm_params.h>
0037 #include <sound/soc.h>
0038 #include <sound/tlv.h>
0039 #include <sound/tas5086.h>
0040 
0041 #define TAS5086_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE  |     \
0042                  SNDRV_PCM_FMTBIT_S20_3LE |     \
0043                  SNDRV_PCM_FMTBIT_S24_3LE)
0044 
0045 #define TAS5086_PCM_RATES   (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100  | \
0046                  SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200  | \
0047                  SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | \
0048                  SNDRV_PCM_RATE_192000)
0049 
0050 /*
0051  * TAS5086 registers
0052  */
0053 #define TAS5086_CLOCK_CONTROL       0x00    /* Clock control register  */
0054 #define TAS5086_CLOCK_RATE(val)     (val << 5)
0055 #define TAS5086_CLOCK_RATE_MASK     (0x7 << 5)
0056 #define TAS5086_CLOCK_RATIO(val)    (val << 2)
0057 #define TAS5086_CLOCK_RATIO_MASK    (0x7 << 2)
0058 #define TAS5086_CLOCK_SCLK_RATIO_48 (1 << 1)
0059 #define TAS5086_CLOCK_VALID     (1 << 0)
0060 
0061 #define TAS5086_DEEMPH_MASK     0x03
0062 #define TAS5086_SOFT_MUTE_ALL       0x3f
0063 
0064 #define TAS5086_DEV_ID          0x01    /* Device ID register */
0065 #define TAS5086_ERROR_STATUS        0x02    /* Error status register */
0066 #define TAS5086_SYS_CONTROL_1       0x03    /* System control register 1 */
0067 #define TAS5086_SERIAL_DATA_IF      0x04    /* Serial data interface register  */
0068 #define TAS5086_SYS_CONTROL_2       0x05    /* System control register 2 */
0069 #define TAS5086_SOFT_MUTE       0x06    /* Soft mute register */
0070 #define TAS5086_MASTER_VOL      0x07    /* Master volume  */
0071 #define TAS5086_CHANNEL_VOL(X)      (0x08 + (X))    /* Channel 1-6 volume */
0072 #define TAS5086_VOLUME_CONTROL      0x09    /* Volume control register */
0073 #define TAS5086_MOD_LIMIT       0x10    /* Modulation limit register */
0074 #define TAS5086_PWM_START       0x18    /* PWM start register */
0075 #define TAS5086_SURROUND        0x19    /* Surround register */
0076 #define TAS5086_SPLIT_CAP_CHARGE    0x1a    /* Split cap charge period register */
0077 #define TAS5086_OSC_TRIM        0x1b    /* Oscillator trim register */
0078 #define TAS5086_BKNDERR         0x1c
0079 #define TAS5086_INPUT_MUX       0x20
0080 #define TAS5086_PWM_OUTPUT_MUX      0x25
0081 
0082 #define TAS5086_MAX_REGISTER        TAS5086_PWM_OUTPUT_MUX
0083 
0084 #define TAS5086_PWM_START_MIDZ_FOR_START_1  (1 << 7)
0085 #define TAS5086_PWM_START_MIDZ_FOR_START_2  (1 << 6)
0086 #define TAS5086_PWM_START_CHANNEL_MASK      (0x3f)
0087 
0088 /*
0089  * Default TAS5086 power-up configuration
0090  */
0091 static const struct reg_default tas5086_reg_defaults[] = {
0092     { 0x00, 0x6c },
0093     { 0x01, 0x03 },
0094     { 0x02, 0x00 },
0095     { 0x03, 0xa0 },
0096     { 0x04, 0x05 },
0097     { 0x05, 0x60 },
0098     { 0x06, 0x00 },
0099     { 0x07, 0xff },
0100     { 0x08, 0x30 },
0101     { 0x09, 0x30 },
0102     { 0x0a, 0x30 },
0103     { 0x0b, 0x30 },
0104     { 0x0c, 0x30 },
0105     { 0x0d, 0x30 },
0106     { 0x0e, 0xb1 },
0107     { 0x0f, 0x00 },
0108     { 0x10, 0x02 },
0109     { 0x11, 0x00 },
0110     { 0x12, 0x00 },
0111     { 0x13, 0x00 },
0112     { 0x14, 0x00 },
0113     { 0x15, 0x00 },
0114     { 0x16, 0x00 },
0115     { 0x17, 0x00 },
0116     { 0x18, 0x3f },
0117     { 0x19, 0x00 },
0118     { 0x1a, 0x18 },
0119     { 0x1b, 0x82 },
0120     { 0x1c, 0x05 },
0121 };
0122 
0123 static int tas5086_register_size(struct device *dev, unsigned int reg)
0124 {
0125     switch (reg) {
0126     case TAS5086_CLOCK_CONTROL ... TAS5086_BKNDERR:
0127         return 1;
0128     case TAS5086_INPUT_MUX:
0129     case TAS5086_PWM_OUTPUT_MUX:
0130         return 4;
0131     }
0132 
0133     dev_err(dev, "Unsupported register address: %d\n", reg);
0134     return 0;
0135 }
0136 
0137 static bool tas5086_accessible_reg(struct device *dev, unsigned int reg)
0138 {
0139     switch (reg) {
0140     case 0x0f:
0141     case 0x11 ... 0x17:
0142     case 0x1d ... 0x1f:
0143         return false;
0144     default:
0145         return true;
0146     }
0147 }
0148 
0149 static bool tas5086_volatile_reg(struct device *dev, unsigned int reg)
0150 {
0151     switch (reg) {
0152     case TAS5086_DEV_ID:
0153     case TAS5086_ERROR_STATUS:
0154         return true;
0155     }
0156 
0157     return false;
0158 }
0159 
0160 static bool tas5086_writeable_reg(struct device *dev, unsigned int reg)
0161 {
0162     return tas5086_accessible_reg(dev, reg) && (reg != TAS5086_DEV_ID);
0163 }
0164 
0165 static int tas5086_reg_write(void *context, unsigned int reg,
0166                   unsigned int value)
0167 {
0168     struct i2c_client *client = context;
0169     unsigned int i, size;
0170     uint8_t buf[5];
0171     int ret;
0172 
0173     size = tas5086_register_size(&client->dev, reg);
0174     if (size == 0)
0175         return -EINVAL;
0176 
0177     buf[0] = reg;
0178 
0179     for (i = size; i >= 1; --i) {
0180         buf[i] = value;
0181         value >>= 8;
0182     }
0183 
0184     ret = i2c_master_send(client, buf, size + 1);
0185     if (ret == size + 1)
0186         return 0;
0187     else if (ret < 0)
0188         return ret;
0189     else
0190         return -EIO;
0191 }
0192 
0193 static int tas5086_reg_read(void *context, unsigned int reg,
0194                  unsigned int *value)
0195 {
0196     struct i2c_client *client = context;
0197     uint8_t send_buf, recv_buf[4];
0198     struct i2c_msg msgs[2];
0199     unsigned int size;
0200     unsigned int i;
0201     int ret;
0202 
0203     size = tas5086_register_size(&client->dev, reg);
0204     if (size == 0)
0205         return -EINVAL;
0206 
0207     send_buf = reg;
0208 
0209     msgs[0].addr = client->addr;
0210     msgs[0].len = sizeof(send_buf);
0211     msgs[0].buf = &send_buf;
0212     msgs[0].flags = 0;
0213 
0214     msgs[1].addr = client->addr;
0215     msgs[1].len = size;
0216     msgs[1].buf = recv_buf;
0217     msgs[1].flags = I2C_M_RD;
0218 
0219     ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
0220     if (ret < 0)
0221         return ret;
0222     else if (ret != ARRAY_SIZE(msgs))
0223         return -EIO;
0224 
0225     *value = 0;
0226 
0227     for (i = 0; i < size; i++) {
0228         *value <<= 8;
0229         *value |= recv_buf[i];
0230     }
0231 
0232     return 0;
0233 }
0234 
0235 static const char * const supply_names[] = {
0236     "dvdd", "avdd"
0237 };
0238 
0239 struct tas5086_private {
0240     struct regmap   *regmap;
0241     unsigned int    mclk, sclk;
0242     unsigned int    format;
0243     bool        deemph;
0244     unsigned int    charge_period;
0245     unsigned int    pwm_start_mid_z;
0246     /* Current sample rate for de-emphasis control */
0247     int     rate;
0248     /* GPIO driving Reset pin, if any */
0249     int     gpio_nreset;
0250     struct      regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
0251 };
0252 
0253 static int tas5086_deemph[] = { 0, 32000, 44100, 48000 };
0254 
0255 static int tas5086_set_deemph(struct snd_soc_component *component)
0256 {
0257     struct tas5086_private *priv = snd_soc_component_get_drvdata(component);
0258     int i, val = 0;
0259 
0260     if (priv->deemph) {
0261         for (i = 0; i < ARRAY_SIZE(tas5086_deemph); i++) {
0262             if (tas5086_deemph[i] == priv->rate) {
0263                 val = i;
0264                 break;
0265             }
0266         }
0267     }
0268 
0269     return regmap_update_bits(priv->regmap, TAS5086_SYS_CONTROL_1,
0270                   TAS5086_DEEMPH_MASK, val);
0271 }
0272 
0273 static int tas5086_get_deemph(struct snd_kcontrol *kcontrol,
0274                   struct snd_ctl_elem_value *ucontrol)
0275 {
0276     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0277     struct tas5086_private *priv = snd_soc_component_get_drvdata(component);
0278 
0279     ucontrol->value.integer.value[0] = priv->deemph;
0280 
0281     return 0;
0282 }
0283 
0284 static int tas5086_put_deemph(struct snd_kcontrol *kcontrol,
0285                   struct snd_ctl_elem_value *ucontrol)
0286 {
0287     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0288     struct tas5086_private *priv = snd_soc_component_get_drvdata(component);
0289 
0290     priv->deemph = ucontrol->value.integer.value[0];
0291 
0292     return tas5086_set_deemph(component);
0293 }
0294 
0295 
0296 static int tas5086_set_dai_sysclk(struct snd_soc_dai *codec_dai,
0297                   int clk_id, unsigned int freq, int dir)
0298 {
0299     struct snd_soc_component *component = codec_dai->component;
0300     struct tas5086_private *priv = snd_soc_component_get_drvdata(component);
0301 
0302     switch (clk_id) {
0303     case TAS5086_CLK_IDX_MCLK:
0304         priv->mclk = freq;
0305         break;
0306     case TAS5086_CLK_IDX_SCLK:
0307         priv->sclk = freq;
0308         break;
0309     }
0310 
0311     return 0;
0312 }
0313 
0314 static int tas5086_set_dai_fmt(struct snd_soc_dai *codec_dai,
0315                    unsigned int format)
0316 {
0317     struct snd_soc_component *component = codec_dai->component;
0318     struct tas5086_private *priv = snd_soc_component_get_drvdata(component);
0319 
0320     /* The TAS5086 can only be slave to all clocks */
0321     if ((format & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) != SND_SOC_DAIFMT_CBC_CFC) {
0322         dev_err(component->dev, "Invalid clocking mode\n");
0323         return -EINVAL;
0324     }
0325 
0326     /* we need to refer to the data format from hw_params() */
0327     priv->format = format;
0328 
0329     return 0;
0330 }
0331 
0332 static const int tas5086_sample_rates[] = {
0333     32000, 38000, 44100, 48000, 88200, 96000, 176400, 192000
0334 };
0335 
0336 static const int tas5086_ratios[] = {
0337     64, 128, 192, 256, 384, 512
0338 };
0339 
0340 static int index_in_array(const int *array, int len, int needle)
0341 {
0342     int i;
0343 
0344     for (i = 0; i < len; i++)
0345         if (array[i] == needle)
0346             return i;
0347 
0348     return -ENOENT;
0349 }
0350 
0351 static int tas5086_hw_params(struct snd_pcm_substream *substream,
0352                  struct snd_pcm_hw_params *params,
0353                  struct snd_soc_dai *dai)
0354 {
0355     struct snd_soc_component *component = dai->component;
0356     struct tas5086_private *priv = snd_soc_component_get_drvdata(component);
0357     int val;
0358     int ret;
0359 
0360     priv->rate = params_rate(params);
0361 
0362     /* Look up the sample rate and refer to the offset in the list */
0363     val = index_in_array(tas5086_sample_rates,
0364                  ARRAY_SIZE(tas5086_sample_rates), priv->rate);
0365 
0366     if (val < 0) {
0367         dev_err(component->dev, "Invalid sample rate\n");
0368         return -EINVAL;
0369     }
0370 
0371     ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL,
0372                  TAS5086_CLOCK_RATE_MASK,
0373                  TAS5086_CLOCK_RATE(val));
0374     if (ret < 0)
0375         return ret;
0376 
0377     /* MCLK / Fs ratio */
0378     val = index_in_array(tas5086_ratios, ARRAY_SIZE(tas5086_ratios),
0379                  priv->mclk / priv->rate);
0380     if (val < 0) {
0381         dev_err(component->dev, "Invalid MCLK / Fs ratio\n");
0382         return -EINVAL;
0383     }
0384 
0385     ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL,
0386                  TAS5086_CLOCK_RATIO_MASK,
0387                  TAS5086_CLOCK_RATIO(val));
0388     if (ret < 0)
0389         return ret;
0390 
0391 
0392     ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL,
0393                  TAS5086_CLOCK_SCLK_RATIO_48,
0394                  (priv->sclk == 48 * priv->rate) ? 
0395                     TAS5086_CLOCK_SCLK_RATIO_48 : 0);
0396     if (ret < 0)
0397         return ret;
0398 
0399     /*
0400      * The chip has a very unituitive register mapping and muxes information
0401      * about data format and sample depth into the same register, but not on
0402      * a logical bit-boundary. Hence, we have to refer to the format passed
0403      * in the set_dai_fmt() callback and set up everything from here.
0404      *
0405      * First, determine the 'base' value, using the format ...
0406      */
0407     switch (priv->format & SND_SOC_DAIFMT_FORMAT_MASK) {
0408     case SND_SOC_DAIFMT_RIGHT_J:
0409         val = 0x00;
0410         break;
0411     case SND_SOC_DAIFMT_I2S:
0412         val = 0x03;
0413         break;
0414     case SND_SOC_DAIFMT_LEFT_J:
0415         val = 0x06;
0416         break;
0417     default:
0418         dev_err(component->dev, "Invalid DAI format\n");
0419         return -EINVAL;
0420     }
0421 
0422     /* ... then add the offset for the sample bit depth. */
0423     switch (params_width(params)) {
0424         case 16:
0425         val += 0;
0426                 break;
0427     case 20:
0428         val += 1;
0429         break;
0430     case 24:
0431         val += 2;
0432         break;
0433     default:
0434         dev_err(component->dev, "Invalid bit width\n");
0435         return -EINVAL;
0436     }
0437 
0438     ret = regmap_write(priv->regmap, TAS5086_SERIAL_DATA_IF, val);
0439     if (ret < 0)
0440         return ret;
0441 
0442     /* clock is considered valid now */
0443     ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL,
0444                  TAS5086_CLOCK_VALID, TAS5086_CLOCK_VALID);
0445     if (ret < 0)
0446         return ret;
0447 
0448     return tas5086_set_deemph(component);
0449 }
0450 
0451 static int tas5086_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
0452 {
0453     struct snd_soc_component *component = dai->component;
0454     struct tas5086_private *priv = snd_soc_component_get_drvdata(component);
0455     unsigned int val = 0;
0456 
0457     if (mute)
0458         val = TAS5086_SOFT_MUTE_ALL;
0459 
0460     return regmap_write(priv->regmap, TAS5086_SOFT_MUTE, val);
0461 }
0462 
0463 static void tas5086_reset(struct tas5086_private *priv)
0464 {
0465     if (gpio_is_valid(priv->gpio_nreset)) {
0466         /* Reset codec - minimum assertion time is 400ns */
0467         gpio_direction_output(priv->gpio_nreset, 0);
0468         udelay(1);
0469         gpio_set_value(priv->gpio_nreset, 1);
0470 
0471         /* Codec needs ~15ms to wake up */
0472         msleep(15);
0473     }
0474 }
0475 
0476 /* charge period values in microseconds */
0477 static const int tas5086_charge_period[] = {
0478       13000,  16900,   23400,   31200,   41600,   54600,   72800,   96200,
0479      130000, 156000,  234000,  312000,  416000,  546000,  728000,  962000,
0480     1300000, 169000, 2340000, 3120000, 4160000, 5460000, 7280000, 9620000,
0481 };
0482 
0483 static int tas5086_init(struct device *dev, struct tas5086_private *priv)
0484 {
0485     int ret, i;
0486 
0487     /*
0488      * If any of the channels is configured to start in Mid-Z mode,
0489      * configure 'part 1' of the PWM starts to use Mid-Z, and tell
0490      * all configured mid-z channels to start under 'part 1'.
0491      */
0492     if (priv->pwm_start_mid_z)
0493         regmap_write(priv->regmap, TAS5086_PWM_START,
0494                  TAS5086_PWM_START_MIDZ_FOR_START_1 |
0495                 priv->pwm_start_mid_z);
0496 
0497     /* lookup and set split-capacitor charge period */
0498     if (priv->charge_period == 0) {
0499         regmap_write(priv->regmap, TAS5086_SPLIT_CAP_CHARGE, 0);
0500     } else {
0501         i = index_in_array(tas5086_charge_period,
0502                    ARRAY_SIZE(tas5086_charge_period),
0503                    priv->charge_period);
0504         if (i >= 0)
0505             regmap_write(priv->regmap, TAS5086_SPLIT_CAP_CHARGE,
0506                      i + 0x08);
0507         else
0508             dev_warn(dev,
0509                  "Invalid split-cap charge period of %d ns.\n",
0510                  priv->charge_period);
0511     }
0512 
0513     /* enable factory trim */
0514     ret = regmap_write(priv->regmap, TAS5086_OSC_TRIM, 0x00);
0515     if (ret < 0)
0516         return ret;
0517 
0518     /* start all channels */
0519     ret = regmap_write(priv->regmap, TAS5086_SYS_CONTROL_2, 0x20);
0520     if (ret < 0)
0521         return ret;
0522 
0523     /* mute all channels for now */
0524     ret = regmap_write(priv->regmap, TAS5086_SOFT_MUTE,
0525                TAS5086_SOFT_MUTE_ALL);
0526     if (ret < 0)
0527         return ret;
0528 
0529     return 0;
0530 }
0531 
0532 /* TAS5086 controls */
0533 static const DECLARE_TLV_DB_SCALE(tas5086_dac_tlv, -10350, 50, 1);
0534 
0535 static const struct snd_kcontrol_new tas5086_controls[] = {
0536     SOC_SINGLE_TLV("Master Playback Volume", TAS5086_MASTER_VOL,
0537                0, 0xff, 1, tas5086_dac_tlv),
0538     SOC_DOUBLE_R_TLV("Channel 1/2 Playback Volume",
0539              TAS5086_CHANNEL_VOL(0), TAS5086_CHANNEL_VOL(1),
0540              0, 0xff, 1, tas5086_dac_tlv),
0541     SOC_DOUBLE_R_TLV("Channel 3/4 Playback Volume",
0542              TAS5086_CHANNEL_VOL(2), TAS5086_CHANNEL_VOL(3),
0543              0, 0xff, 1, tas5086_dac_tlv),
0544     SOC_DOUBLE_R_TLV("Channel 5/6 Playback Volume",
0545              TAS5086_CHANNEL_VOL(4), TAS5086_CHANNEL_VOL(5),
0546              0, 0xff, 1, tas5086_dac_tlv),
0547     SOC_SINGLE_BOOL_EXT("De-emphasis Switch", 0,
0548                 tas5086_get_deemph, tas5086_put_deemph),
0549 };
0550 
0551 /* Input mux controls */
0552 static const char *tas5086_dapm_sdin_texts[] =
0553 {
0554     "SDIN1-L", "SDIN1-R", "SDIN2-L", "SDIN2-R",
0555     "SDIN3-L", "SDIN3-R", "Ground (0)", "nc"
0556 };
0557 
0558 static const struct soc_enum tas5086_dapm_input_mux_enum[] = {
0559     SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 20, 8, tas5086_dapm_sdin_texts),
0560     SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 16, 8, tas5086_dapm_sdin_texts),
0561     SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 12, 8, tas5086_dapm_sdin_texts),
0562     SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 8,  8, tas5086_dapm_sdin_texts),
0563     SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 4,  8, tas5086_dapm_sdin_texts),
0564     SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 0,  8, tas5086_dapm_sdin_texts),
0565 };
0566 
0567 static const struct snd_kcontrol_new tas5086_dapm_input_mux_controls[] = {
0568     SOC_DAPM_ENUM("Channel 1 input", tas5086_dapm_input_mux_enum[0]),
0569     SOC_DAPM_ENUM("Channel 2 input", tas5086_dapm_input_mux_enum[1]),
0570     SOC_DAPM_ENUM("Channel 3 input", tas5086_dapm_input_mux_enum[2]),
0571     SOC_DAPM_ENUM("Channel 4 input", tas5086_dapm_input_mux_enum[3]),
0572     SOC_DAPM_ENUM("Channel 5 input", tas5086_dapm_input_mux_enum[4]),
0573     SOC_DAPM_ENUM("Channel 6 input", tas5086_dapm_input_mux_enum[5]),
0574 };
0575 
0576 /* Output mux controls */
0577 static const char *tas5086_dapm_channel_texts[] =
0578     { "Channel 1 Mux", "Channel 2 Mux", "Channel 3 Mux",
0579       "Channel 4 Mux", "Channel 5 Mux", "Channel 6 Mux" };
0580 
0581 static const struct soc_enum tas5086_dapm_output_mux_enum[] = {
0582     SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 20, 6, tas5086_dapm_channel_texts),
0583     SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 16, 6, tas5086_dapm_channel_texts),
0584     SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 12, 6, tas5086_dapm_channel_texts),
0585     SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 8,  6, tas5086_dapm_channel_texts),
0586     SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 4,  6, tas5086_dapm_channel_texts),
0587     SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 0,  6, tas5086_dapm_channel_texts),
0588 };
0589 
0590 static const struct snd_kcontrol_new tas5086_dapm_output_mux_controls[] = {
0591     SOC_DAPM_ENUM("PWM1 Output", tas5086_dapm_output_mux_enum[0]),
0592     SOC_DAPM_ENUM("PWM2 Output", tas5086_dapm_output_mux_enum[1]),
0593     SOC_DAPM_ENUM("PWM3 Output", tas5086_dapm_output_mux_enum[2]),
0594     SOC_DAPM_ENUM("PWM4 Output", tas5086_dapm_output_mux_enum[3]),
0595     SOC_DAPM_ENUM("PWM5 Output", tas5086_dapm_output_mux_enum[4]),
0596     SOC_DAPM_ENUM("PWM6 Output", tas5086_dapm_output_mux_enum[5]),
0597 };
0598 
0599 static const struct snd_soc_dapm_widget tas5086_dapm_widgets[] = {
0600     SND_SOC_DAPM_INPUT("SDIN1-L"),
0601     SND_SOC_DAPM_INPUT("SDIN1-R"),
0602     SND_SOC_DAPM_INPUT("SDIN2-L"),
0603     SND_SOC_DAPM_INPUT("SDIN2-R"),
0604     SND_SOC_DAPM_INPUT("SDIN3-L"),
0605     SND_SOC_DAPM_INPUT("SDIN3-R"),
0606     SND_SOC_DAPM_INPUT("SDIN4-L"),
0607     SND_SOC_DAPM_INPUT("SDIN4-R"),
0608 
0609     SND_SOC_DAPM_OUTPUT("PWM1"),
0610     SND_SOC_DAPM_OUTPUT("PWM2"),
0611     SND_SOC_DAPM_OUTPUT("PWM3"),
0612     SND_SOC_DAPM_OUTPUT("PWM4"),
0613     SND_SOC_DAPM_OUTPUT("PWM5"),
0614     SND_SOC_DAPM_OUTPUT("PWM6"),
0615 
0616     SND_SOC_DAPM_MUX("Channel 1 Mux", SND_SOC_NOPM, 0, 0,
0617              &tas5086_dapm_input_mux_controls[0]),
0618     SND_SOC_DAPM_MUX("Channel 2 Mux", SND_SOC_NOPM, 0, 0,
0619              &tas5086_dapm_input_mux_controls[1]),
0620     SND_SOC_DAPM_MUX("Channel 3 Mux", SND_SOC_NOPM, 0, 0,
0621              &tas5086_dapm_input_mux_controls[2]),
0622     SND_SOC_DAPM_MUX("Channel 4 Mux", SND_SOC_NOPM, 0, 0,
0623              &tas5086_dapm_input_mux_controls[3]),
0624     SND_SOC_DAPM_MUX("Channel 5 Mux", SND_SOC_NOPM, 0, 0,
0625              &tas5086_dapm_input_mux_controls[4]),
0626     SND_SOC_DAPM_MUX("Channel 6 Mux", SND_SOC_NOPM, 0, 0,
0627              &tas5086_dapm_input_mux_controls[5]),
0628 
0629     SND_SOC_DAPM_MUX("PWM1 Mux", SND_SOC_NOPM, 0, 0,
0630              &tas5086_dapm_output_mux_controls[0]),
0631     SND_SOC_DAPM_MUX("PWM2 Mux", SND_SOC_NOPM, 0, 0,
0632              &tas5086_dapm_output_mux_controls[1]),
0633     SND_SOC_DAPM_MUX("PWM3 Mux", SND_SOC_NOPM, 0, 0,
0634              &tas5086_dapm_output_mux_controls[2]),
0635     SND_SOC_DAPM_MUX("PWM4 Mux", SND_SOC_NOPM, 0, 0,
0636              &tas5086_dapm_output_mux_controls[3]),
0637     SND_SOC_DAPM_MUX("PWM5 Mux", SND_SOC_NOPM, 0, 0,
0638              &tas5086_dapm_output_mux_controls[4]),
0639     SND_SOC_DAPM_MUX("PWM6 Mux", SND_SOC_NOPM, 0, 0,
0640              &tas5086_dapm_output_mux_controls[5]),
0641 };
0642 
0643 static const struct snd_soc_dapm_route tas5086_dapm_routes[] = {
0644     /* SDIN inputs -> channel muxes */
0645     { "Channel 1 Mux", "SDIN1-L", "SDIN1-L" },
0646     { "Channel 1 Mux", "SDIN1-R", "SDIN1-R" },
0647     { "Channel 1 Mux", "SDIN2-L", "SDIN2-L" },
0648     { "Channel 1 Mux", "SDIN2-R", "SDIN2-R" },
0649     { "Channel 1 Mux", "SDIN3-L", "SDIN3-L" },
0650     { "Channel 1 Mux", "SDIN3-R", "SDIN3-R" },
0651 
0652     { "Channel 2 Mux", "SDIN1-L", "SDIN1-L" },
0653     { "Channel 2 Mux", "SDIN1-R", "SDIN1-R" },
0654     { "Channel 2 Mux", "SDIN2-L", "SDIN2-L" },
0655     { "Channel 2 Mux", "SDIN2-R", "SDIN2-R" },
0656     { "Channel 2 Mux", "SDIN3-L", "SDIN3-L" },
0657     { "Channel 2 Mux", "SDIN3-R", "SDIN3-R" },
0658 
0659     { "Channel 2 Mux", "SDIN1-L", "SDIN1-L" },
0660     { "Channel 2 Mux", "SDIN1-R", "SDIN1-R" },
0661     { "Channel 2 Mux", "SDIN2-L", "SDIN2-L" },
0662     { "Channel 2 Mux", "SDIN2-R", "SDIN2-R" },
0663     { "Channel 2 Mux", "SDIN3-L", "SDIN3-L" },
0664     { "Channel 2 Mux", "SDIN3-R", "SDIN3-R" },
0665 
0666     { "Channel 3 Mux", "SDIN1-L", "SDIN1-L" },
0667     { "Channel 3 Mux", "SDIN1-R", "SDIN1-R" },
0668     { "Channel 3 Mux", "SDIN2-L", "SDIN2-L" },
0669     { "Channel 3 Mux", "SDIN2-R", "SDIN2-R" },
0670     { "Channel 3 Mux", "SDIN3-L", "SDIN3-L" },
0671     { "Channel 3 Mux", "SDIN3-R", "SDIN3-R" },
0672 
0673     { "Channel 4 Mux", "SDIN1-L", "SDIN1-L" },
0674     { "Channel 4 Mux", "SDIN1-R", "SDIN1-R" },
0675     { "Channel 4 Mux", "SDIN2-L", "SDIN2-L" },
0676     { "Channel 4 Mux", "SDIN2-R", "SDIN2-R" },
0677     { "Channel 4 Mux", "SDIN3-L", "SDIN3-L" },
0678     { "Channel 4 Mux", "SDIN3-R", "SDIN3-R" },
0679 
0680     { "Channel 5 Mux", "SDIN1-L", "SDIN1-L" },
0681     { "Channel 5 Mux", "SDIN1-R", "SDIN1-R" },
0682     { "Channel 5 Mux", "SDIN2-L", "SDIN2-L" },
0683     { "Channel 5 Mux", "SDIN2-R", "SDIN2-R" },
0684     { "Channel 5 Mux", "SDIN3-L", "SDIN3-L" },
0685     { "Channel 5 Mux", "SDIN3-R", "SDIN3-R" },
0686 
0687     { "Channel 6 Mux", "SDIN1-L", "SDIN1-L" },
0688     { "Channel 6 Mux", "SDIN1-R", "SDIN1-R" },
0689     { "Channel 6 Mux", "SDIN2-L", "SDIN2-L" },
0690     { "Channel 6 Mux", "SDIN2-R", "SDIN2-R" },
0691     { "Channel 6 Mux", "SDIN3-L", "SDIN3-L" },
0692     { "Channel 6 Mux", "SDIN3-R", "SDIN3-R" },
0693 
0694     /* Channel muxes -> PWM muxes */
0695     { "PWM1 Mux", "Channel 1 Mux", "Channel 1 Mux" },
0696     { "PWM2 Mux", "Channel 1 Mux", "Channel 1 Mux" },
0697     { "PWM3 Mux", "Channel 1 Mux", "Channel 1 Mux" },
0698     { "PWM4 Mux", "Channel 1 Mux", "Channel 1 Mux" },
0699     { "PWM5 Mux", "Channel 1 Mux", "Channel 1 Mux" },
0700     { "PWM6 Mux", "Channel 1 Mux", "Channel 1 Mux" },
0701 
0702     { "PWM1 Mux", "Channel 2 Mux", "Channel 2 Mux" },
0703     { "PWM2 Mux", "Channel 2 Mux", "Channel 2 Mux" },
0704     { "PWM3 Mux", "Channel 2 Mux", "Channel 2 Mux" },
0705     { "PWM4 Mux", "Channel 2 Mux", "Channel 2 Mux" },
0706     { "PWM5 Mux", "Channel 2 Mux", "Channel 2 Mux" },
0707     { "PWM6 Mux", "Channel 2 Mux", "Channel 2 Mux" },
0708 
0709     { "PWM1 Mux", "Channel 3 Mux", "Channel 3 Mux" },
0710     { "PWM2 Mux", "Channel 3 Mux", "Channel 3 Mux" },
0711     { "PWM3 Mux", "Channel 3 Mux", "Channel 3 Mux" },
0712     { "PWM4 Mux", "Channel 3 Mux", "Channel 3 Mux" },
0713     { "PWM5 Mux", "Channel 3 Mux", "Channel 3 Mux" },
0714     { "PWM6 Mux", "Channel 3 Mux", "Channel 3 Mux" },
0715 
0716     { "PWM1 Mux", "Channel 4 Mux", "Channel 4 Mux" },
0717     { "PWM2 Mux", "Channel 4 Mux", "Channel 4 Mux" },
0718     { "PWM3 Mux", "Channel 4 Mux", "Channel 4 Mux" },
0719     { "PWM4 Mux", "Channel 4 Mux", "Channel 4 Mux" },
0720     { "PWM5 Mux", "Channel 4 Mux", "Channel 4 Mux" },
0721     { "PWM6 Mux", "Channel 4 Mux", "Channel 4 Mux" },
0722 
0723     { "PWM1 Mux", "Channel 5 Mux", "Channel 5 Mux" },
0724     { "PWM2 Mux", "Channel 5 Mux", "Channel 5 Mux" },
0725     { "PWM3 Mux", "Channel 5 Mux", "Channel 5 Mux" },
0726     { "PWM4 Mux", "Channel 5 Mux", "Channel 5 Mux" },
0727     { "PWM5 Mux", "Channel 5 Mux", "Channel 5 Mux" },
0728     { "PWM6 Mux", "Channel 5 Mux", "Channel 5 Mux" },
0729 
0730     { "PWM1 Mux", "Channel 6 Mux", "Channel 6 Mux" },
0731     { "PWM2 Mux", "Channel 6 Mux", "Channel 6 Mux" },
0732     { "PWM3 Mux", "Channel 6 Mux", "Channel 6 Mux" },
0733     { "PWM4 Mux", "Channel 6 Mux", "Channel 6 Mux" },
0734     { "PWM5 Mux", "Channel 6 Mux", "Channel 6 Mux" },
0735     { "PWM6 Mux", "Channel 6 Mux", "Channel 6 Mux" },
0736 
0737     /* The PWM muxes are directly connected to the PWM outputs */
0738     { "PWM1", NULL, "PWM1 Mux" },
0739     { "PWM2", NULL, "PWM2 Mux" },
0740     { "PWM3", NULL, "PWM3 Mux" },
0741     { "PWM4", NULL, "PWM4 Mux" },
0742     { "PWM5", NULL, "PWM5 Mux" },
0743     { "PWM6", NULL, "PWM6 Mux" },
0744 
0745 };
0746 
0747 static const struct snd_soc_dai_ops tas5086_dai_ops = {
0748     .hw_params  = tas5086_hw_params,
0749     .set_sysclk = tas5086_set_dai_sysclk,
0750     .set_fmt    = tas5086_set_dai_fmt,
0751     .mute_stream    = tas5086_mute_stream,
0752 };
0753 
0754 static struct snd_soc_dai_driver tas5086_dai = {
0755     .name = "tas5086-hifi",
0756     .playback = {
0757         .stream_name    = "Playback",
0758         .channels_min   = 2,
0759         .channels_max   = 6,
0760         .rates      = TAS5086_PCM_RATES,
0761         .formats    = TAS5086_PCM_FORMATS,
0762     },
0763     .ops = &tas5086_dai_ops,
0764 };
0765 
0766 #ifdef CONFIG_PM
0767 static int tas5086_soc_suspend(struct snd_soc_component *component)
0768 {
0769     struct tas5086_private *priv = snd_soc_component_get_drvdata(component);
0770     int ret;
0771 
0772     /* Shut down all channels */
0773     ret = regmap_write(priv->regmap, TAS5086_SYS_CONTROL_2, 0x60);
0774     if (ret < 0)
0775         return ret;
0776 
0777     regulator_bulk_disable(ARRAY_SIZE(priv->supplies), priv->supplies);
0778 
0779     return 0;
0780 }
0781 
0782 static int tas5086_soc_resume(struct snd_soc_component *component)
0783 {
0784     struct tas5086_private *priv = snd_soc_component_get_drvdata(component);
0785     int ret;
0786 
0787     ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
0788     if (ret < 0)
0789         return ret;
0790 
0791     tas5086_reset(priv);
0792     regcache_mark_dirty(priv->regmap);
0793 
0794     ret = tas5086_init(component->dev, priv);
0795     if (ret < 0)
0796         return ret;
0797 
0798     ret = regcache_sync(priv->regmap);
0799     if (ret < 0)
0800         return ret;
0801 
0802     return 0;
0803 }
0804 #else
0805 #define tas5086_soc_suspend NULL
0806 #define tas5086_soc_resume  NULL
0807 #endif /* CONFIG_PM */
0808 
0809 #ifdef CONFIG_OF
0810 static const struct of_device_id tas5086_dt_ids[] = {
0811     { .compatible = "ti,tas5086", },
0812     { }
0813 };
0814 MODULE_DEVICE_TABLE(of, tas5086_dt_ids);
0815 #endif
0816 
0817 static int tas5086_probe(struct snd_soc_component *component)
0818 {
0819     struct tas5086_private *priv = snd_soc_component_get_drvdata(component);
0820     int i, ret;
0821 
0822     ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
0823     if (ret < 0) {
0824         dev_err(component->dev, "Failed to enable regulators: %d\n", ret);
0825         return ret;
0826     }
0827 
0828     priv->pwm_start_mid_z = 0;
0829     priv->charge_period = 1300000; /* hardware default is 1300 ms */
0830 
0831     if (of_match_device(of_match_ptr(tas5086_dt_ids), component->dev)) {
0832         struct device_node *of_node = component->dev->of_node;
0833 
0834         of_property_read_u32(of_node, "ti,charge-period",
0835                      &priv->charge_period);
0836 
0837         for (i = 0; i < 6; i++) {
0838             char name[25];
0839 
0840             snprintf(name, sizeof(name),
0841                  "ti,mid-z-channel-%d", i + 1);
0842 
0843             if (of_get_property(of_node, name, NULL) != NULL)
0844                 priv->pwm_start_mid_z |= 1 << i;
0845         }
0846     }
0847 
0848     tas5086_reset(priv);
0849     ret = tas5086_init(component->dev, priv);
0850     if (ret < 0)
0851         goto exit_disable_regulators;
0852 
0853     /* set master volume to 0 dB */
0854     ret = regmap_write(priv->regmap, TAS5086_MASTER_VOL, 0x30);
0855     if (ret < 0)
0856         goto exit_disable_regulators;
0857 
0858     return 0;
0859 
0860 exit_disable_regulators:
0861     regulator_bulk_disable(ARRAY_SIZE(priv->supplies), priv->supplies);
0862 
0863     return ret;
0864 }
0865 
0866 static void tas5086_remove(struct snd_soc_component *component)
0867 {
0868     struct tas5086_private *priv = snd_soc_component_get_drvdata(component);
0869 
0870     if (gpio_is_valid(priv->gpio_nreset))
0871         /* Set codec to the reset state */
0872         gpio_set_value(priv->gpio_nreset, 0);
0873 
0874     regulator_bulk_disable(ARRAY_SIZE(priv->supplies), priv->supplies);
0875 };
0876 
0877 static const struct snd_soc_component_driver soc_component_dev_tas5086 = {
0878     .probe          = tas5086_probe,
0879     .remove         = tas5086_remove,
0880     .suspend        = tas5086_soc_suspend,
0881     .resume         = tas5086_soc_resume,
0882     .controls       = tas5086_controls,
0883     .num_controls       = ARRAY_SIZE(tas5086_controls),
0884     .dapm_widgets       = tas5086_dapm_widgets,
0885     .num_dapm_widgets   = ARRAY_SIZE(tas5086_dapm_widgets),
0886     .dapm_routes        = tas5086_dapm_routes,
0887     .num_dapm_routes    = ARRAY_SIZE(tas5086_dapm_routes),
0888     .idle_bias_on       = 1,
0889     .use_pmdown_time    = 1,
0890     .endianness     = 1,
0891 };
0892 
0893 static const struct i2c_device_id tas5086_i2c_id[] = {
0894     { "tas5086", 0 },
0895     { }
0896 };
0897 MODULE_DEVICE_TABLE(i2c, tas5086_i2c_id);
0898 
0899 static const struct regmap_config tas5086_regmap = {
0900     .reg_bits       = 8,
0901     .val_bits       = 32,
0902     .max_register       = TAS5086_MAX_REGISTER,
0903     .reg_defaults       = tas5086_reg_defaults,
0904     .num_reg_defaults   = ARRAY_SIZE(tas5086_reg_defaults),
0905     .cache_type     = REGCACHE_RBTREE,
0906     .volatile_reg       = tas5086_volatile_reg,
0907     .writeable_reg      = tas5086_writeable_reg,
0908     .readable_reg       = tas5086_accessible_reg,
0909     .reg_read       = tas5086_reg_read,
0910     .reg_write      = tas5086_reg_write,
0911 };
0912 
0913 static int tas5086_i2c_probe(struct i2c_client *i2c)
0914 {
0915     struct tas5086_private *priv;
0916     struct device *dev = &i2c->dev;
0917     int gpio_nreset = -EINVAL;
0918     int i, ret;
0919 
0920     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0921     if (!priv)
0922         return -ENOMEM;
0923 
0924     for (i = 0; i < ARRAY_SIZE(supply_names); i++)
0925         priv->supplies[i].supply = supply_names[i];
0926 
0927     ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(priv->supplies),
0928                       priv->supplies);
0929     if (ret < 0) {
0930         dev_err(dev, "Failed to get regulators: %d\n", ret);
0931         return ret;
0932     }
0933 
0934     priv->regmap = devm_regmap_init(dev, NULL, i2c, &tas5086_regmap);
0935     if (IS_ERR(priv->regmap)) {
0936         ret = PTR_ERR(priv->regmap);
0937         dev_err(&i2c->dev, "Failed to create regmap: %d\n", ret);
0938         return ret;
0939     }
0940 
0941     i2c_set_clientdata(i2c, priv);
0942 
0943     if (of_match_device(of_match_ptr(tas5086_dt_ids), dev)) {
0944         struct device_node *of_node = dev->of_node;
0945         gpio_nreset = of_get_named_gpio(of_node, "reset-gpio", 0);
0946     }
0947 
0948     if (gpio_is_valid(gpio_nreset))
0949         if (devm_gpio_request(dev, gpio_nreset, "TAS5086 Reset"))
0950             gpio_nreset = -EINVAL;
0951 
0952     priv->gpio_nreset = gpio_nreset;
0953 
0954     ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
0955     if (ret < 0) {
0956         dev_err(dev, "Failed to enable regulators: %d\n", ret);
0957         return ret;
0958     }
0959 
0960     tas5086_reset(priv);
0961 
0962     /* The TAS5086 always returns 0x03 in its TAS5086_DEV_ID register */
0963     ret = regmap_read(priv->regmap, TAS5086_DEV_ID, &i);
0964     if (ret == 0 && i != 0x3) {
0965         dev_err(dev,
0966             "Failed to identify TAS5086 codec (got %02x)\n", i);
0967         ret = -ENODEV;
0968     }
0969 
0970     /*
0971      * The chip has been identified, so we can turn off the power
0972      * again until the dai link is set up.
0973      */
0974     regulator_bulk_disable(ARRAY_SIZE(priv->supplies), priv->supplies);
0975 
0976     if (ret == 0)
0977         ret = devm_snd_soc_register_component(&i2c->dev,
0978                          &soc_component_dev_tas5086,
0979                          &tas5086_dai, 1);
0980 
0981     return ret;
0982 }
0983 
0984 static int tas5086_i2c_remove(struct i2c_client *i2c)
0985 {
0986     return 0;
0987 }
0988 
0989 static struct i2c_driver tas5086_i2c_driver = {
0990     .driver = {
0991         .name   = "tas5086",
0992         .of_match_table = of_match_ptr(tas5086_dt_ids),
0993     },
0994     .id_table   = tas5086_i2c_id,
0995     .probe_new  = tas5086_i2c_probe,
0996     .remove     = tas5086_i2c_remove,
0997 };
0998 
0999 module_i2c_driver(tas5086_i2c_driver);
1000 
1001 MODULE_AUTHOR("Daniel Mack <zonque@gmail.com>");
1002 MODULE_DESCRIPTION("Texas Instruments TAS5086 ALSA SoC Codec Driver");
1003 MODULE_LICENSE("GPL");
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