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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Codec driver for ST STA350 2.1-channel high-efficiency digital audio system
0004  *
0005  * Copyright: 2014 Raumfeld GmbH
0006  * Author: Sven Brandau <info@brandau.biz>
0007  *
0008  * based on code from:
0009  *  Raumfeld GmbH
0010  *    Johannes Stezenbach <js@sig21.net>
0011  *  Wolfson Microelectronics PLC.
0012  *    Mark Brown <broonie@opensource.wolfsonmicro.com>
0013  *  Freescale Semiconductor, Inc.
0014  *    Timur Tabi <timur@freescale.com>
0015  */
0016 
0017 #define pr_fmt(fmt) KBUILD_MODNAME ":%s:%d: " fmt, __func__, __LINE__
0018 
0019 #include <linux/module.h>
0020 #include <linux/moduleparam.h>
0021 #include <linux/init.h>
0022 #include <linux/delay.h>
0023 #include <linux/pm.h>
0024 #include <linux/i2c.h>
0025 #include <linux/of_device.h>
0026 #include <linux/of_gpio.h>
0027 #include <linux/regmap.h>
0028 #include <linux/regulator/consumer.h>
0029 #include <linux/gpio/consumer.h>
0030 #include <linux/slab.h>
0031 #include <sound/core.h>
0032 #include <sound/pcm.h>
0033 #include <sound/pcm_params.h>
0034 #include <sound/soc.h>
0035 #include <sound/soc-dapm.h>
0036 #include <sound/initval.h>
0037 #include <sound/tlv.h>
0038 
0039 #include <sound/sta350.h>
0040 #include "sta350.h"
0041 
0042 #define STA350_RATES (SNDRV_PCM_RATE_32000 | \
0043               SNDRV_PCM_RATE_44100 | \
0044               SNDRV_PCM_RATE_48000 | \
0045               SNDRV_PCM_RATE_88200 | \
0046               SNDRV_PCM_RATE_96000 | \
0047               SNDRV_PCM_RATE_176400 | \
0048               SNDRV_PCM_RATE_192000)
0049 
0050 #define STA350_FORMATS \
0051     (SNDRV_PCM_FMTBIT_S16_LE  | SNDRV_PCM_FMTBIT_S18_3LE | \
0052      SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_3LE | \
0053      SNDRV_PCM_FMTBIT_S24_LE  | SNDRV_PCM_FMTBIT_S32_LE)
0054 
0055 /* Power-up register defaults */
0056 static const struct reg_default sta350_regs[] = {
0057     {  0x0, 0x63 },
0058     {  0x1, 0x80 },
0059     {  0x2, 0xdf },
0060     {  0x3, 0x40 },
0061     {  0x4, 0xc2 },
0062     {  0x5, 0x5c },
0063     {  0x6, 0x00 },
0064     {  0x7, 0xff },
0065     {  0x8, 0x60 },
0066     {  0x9, 0x60 },
0067     {  0xa, 0x60 },
0068     {  0xb, 0x00 },
0069     {  0xc, 0x00 },
0070     {  0xd, 0x00 },
0071     {  0xe, 0x00 },
0072     {  0xf, 0x40 },
0073     { 0x10, 0x80 },
0074     { 0x11, 0x77 },
0075     { 0x12, 0x6a },
0076     { 0x13, 0x69 },
0077     { 0x14, 0x6a },
0078     { 0x15, 0x69 },
0079     { 0x16, 0x00 },
0080     { 0x17, 0x00 },
0081     { 0x18, 0x00 },
0082     { 0x19, 0x00 },
0083     { 0x1a, 0x00 },
0084     { 0x1b, 0x00 },
0085     { 0x1c, 0x00 },
0086     { 0x1d, 0x00 },
0087     { 0x1e, 0x00 },
0088     { 0x1f, 0x00 },
0089     { 0x20, 0x00 },
0090     { 0x21, 0x00 },
0091     { 0x22, 0x00 },
0092     { 0x23, 0x00 },
0093     { 0x24, 0x00 },
0094     { 0x25, 0x00 },
0095     { 0x26, 0x00 },
0096     { 0x27, 0x2a },
0097     { 0x28, 0xc0 },
0098     { 0x29, 0xf3 },
0099     { 0x2a, 0x33 },
0100     { 0x2b, 0x00 },
0101     { 0x2c, 0x0c },
0102     { 0x31, 0x00 },
0103     { 0x36, 0x00 },
0104     { 0x37, 0x00 },
0105     { 0x38, 0x00 },
0106     { 0x39, 0x01 },
0107     { 0x3a, 0xee },
0108     { 0x3b, 0xff },
0109     { 0x3c, 0x7e },
0110     { 0x3d, 0xc0 },
0111     { 0x3e, 0x26 },
0112     { 0x3f, 0x00 },
0113     { 0x48, 0x00 },
0114     { 0x49, 0x00 },
0115     { 0x4a, 0x00 },
0116     { 0x4b, 0x04 },
0117     { 0x4c, 0x00 },
0118 };
0119 
0120 static const struct regmap_range sta350_write_regs_range[] = {
0121     regmap_reg_range(STA350_CONFA,  STA350_AUTO2),
0122     regmap_reg_range(STA350_C1CFG,  STA350_FDRC2),
0123     regmap_reg_range(STA350_EQCFG,  STA350_EVOLRES),
0124     regmap_reg_range(STA350_NSHAPE, STA350_MISC2),
0125 };
0126 
0127 static const struct regmap_range sta350_read_regs_range[] = {
0128     regmap_reg_range(STA350_CONFA,  STA350_AUTO2),
0129     regmap_reg_range(STA350_C1CFG,  STA350_STATUS),
0130     regmap_reg_range(STA350_EQCFG,  STA350_EVOLRES),
0131     regmap_reg_range(STA350_NSHAPE, STA350_MISC2),
0132 };
0133 
0134 static const struct regmap_range sta350_volatile_regs_range[] = {
0135     regmap_reg_range(STA350_CFADDR2, STA350_CFUD),
0136     regmap_reg_range(STA350_STATUS,  STA350_STATUS),
0137 };
0138 
0139 static const struct regmap_access_table sta350_write_regs = {
0140     .yes_ranges =   sta350_write_regs_range,
0141     .n_yes_ranges = ARRAY_SIZE(sta350_write_regs_range),
0142 };
0143 
0144 static const struct regmap_access_table sta350_read_regs = {
0145     .yes_ranges =   sta350_read_regs_range,
0146     .n_yes_ranges = ARRAY_SIZE(sta350_read_regs_range),
0147 };
0148 
0149 static const struct regmap_access_table sta350_volatile_regs = {
0150     .yes_ranges =   sta350_volatile_regs_range,
0151     .n_yes_ranges = ARRAY_SIZE(sta350_volatile_regs_range),
0152 };
0153 
0154 /* regulator power supply names */
0155 static const char * const sta350_supply_names[] = {
0156     "vdd-dig",  /* digital supply, 3.3V */
0157     "vdd-pll",  /* pll supply, 3.3V */
0158     "vcc"       /* power amp supply, 5V - 26V */
0159 };
0160 
0161 /* codec private data */
0162 struct sta350_priv {
0163     struct regmap *regmap;
0164     struct regulator_bulk_data supplies[ARRAY_SIZE(sta350_supply_names)];
0165     struct sta350_platform_data *pdata;
0166 
0167     unsigned int mclk;
0168     unsigned int format;
0169 
0170     u32 coef_shadow[STA350_COEF_COUNT];
0171     int shutdown;
0172 
0173     struct gpio_desc *gpiod_nreset;
0174     struct gpio_desc *gpiod_power_down;
0175 
0176     struct mutex coeff_lock;
0177 };
0178 
0179 static const DECLARE_TLV_DB_SCALE(mvol_tlv, -12750, 50, 1);
0180 static const DECLARE_TLV_DB_SCALE(chvol_tlv, -7950, 50, 1);
0181 static const DECLARE_TLV_DB_SCALE(tone_tlv, -1200, 200, 0);
0182 
0183 static const char * const sta350_drc_ac[] = {
0184     "Anti-Clipping", "Dynamic Range Compression"
0185 };
0186 static const char * const sta350_auto_gc_mode[] = {
0187     "User", "AC no clipping", "AC limited clipping (10%)",
0188     "DRC nighttime listening mode"
0189 };
0190 static const char * const sta350_auto_xo_mode[] = {
0191     "User", "80Hz", "100Hz", "120Hz", "140Hz", "160Hz", "180Hz",
0192     "200Hz", "220Hz", "240Hz", "260Hz", "280Hz", "300Hz", "320Hz",
0193     "340Hz", "360Hz"
0194 };
0195 static const char * const sta350_binary_output[] = {
0196     "FFX 3-state output - normal operation", "Binary output"
0197 };
0198 static const char * const sta350_limiter_select[] = {
0199     "Limiter Disabled", "Limiter #1", "Limiter #2"
0200 };
0201 static const char * const sta350_limiter_attack_rate[] = {
0202     "3.1584", "2.7072", "2.2560", "1.8048", "1.3536", "0.9024",
0203     "0.4512", "0.2256", "0.1504", "0.1123", "0.0902", "0.0752",
0204     "0.0645", "0.0564", "0.0501", "0.0451"
0205 };
0206 static const char * const sta350_limiter_release_rate[] = {
0207     "0.5116", "0.1370", "0.0744", "0.0499", "0.0360", "0.0299",
0208     "0.0264", "0.0208", "0.0198", "0.0172", "0.0147", "0.0137",
0209     "0.0134", "0.0117", "0.0110", "0.0104"
0210 };
0211 static const char * const sta350_noise_shaper_type[] = {
0212     "Third order", "Fourth order"
0213 };
0214 
0215 static DECLARE_TLV_DB_RANGE(sta350_limiter_ac_attack_tlv,
0216     0, 7, TLV_DB_SCALE_ITEM(-1200, 200, 0),
0217     8, 16, TLV_DB_SCALE_ITEM(300, 100, 0),
0218 );
0219 
0220 static DECLARE_TLV_DB_RANGE(sta350_limiter_ac_release_tlv,
0221     0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0),
0222     1, 1, TLV_DB_SCALE_ITEM(-2900, 0, 0),
0223     2, 2, TLV_DB_SCALE_ITEM(-2000, 0, 0),
0224     3, 8, TLV_DB_SCALE_ITEM(-1400, 200, 0),
0225     8, 16, TLV_DB_SCALE_ITEM(-700, 100, 0),
0226 );
0227 
0228 static DECLARE_TLV_DB_RANGE(sta350_limiter_drc_attack_tlv,
0229     0, 7, TLV_DB_SCALE_ITEM(-3100, 200, 0),
0230     8, 13, TLV_DB_SCALE_ITEM(-1600, 100, 0),
0231     14, 16, TLV_DB_SCALE_ITEM(-1000, 300, 0),
0232 );
0233 
0234 static DECLARE_TLV_DB_RANGE(sta350_limiter_drc_release_tlv,
0235     0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0),
0236     1, 2, TLV_DB_SCALE_ITEM(-3800, 200, 0),
0237     3, 4, TLV_DB_SCALE_ITEM(-3300, 200, 0),
0238     5, 12, TLV_DB_SCALE_ITEM(-3000, 200, 0),
0239     13, 16, TLV_DB_SCALE_ITEM(-1500, 300, 0),
0240 );
0241 
0242 static SOC_ENUM_SINGLE_DECL(sta350_drc_ac_enum,
0243                 STA350_CONFD, STA350_CONFD_DRC_SHIFT,
0244                 sta350_drc_ac);
0245 static SOC_ENUM_SINGLE_DECL(sta350_noise_shaper_enum,
0246                 STA350_CONFE, STA350_CONFE_NSBW_SHIFT,
0247                 sta350_noise_shaper_type);
0248 static SOC_ENUM_SINGLE_DECL(sta350_auto_gc_enum,
0249                 STA350_AUTO1, STA350_AUTO1_AMGC_SHIFT,
0250                 sta350_auto_gc_mode);
0251 static SOC_ENUM_SINGLE_DECL(sta350_auto_xo_enum,
0252                 STA350_AUTO2, STA350_AUTO2_XO_SHIFT,
0253                 sta350_auto_xo_mode);
0254 static SOC_ENUM_SINGLE_DECL(sta350_binary_output_ch1_enum,
0255                 STA350_C1CFG, STA350_CxCFG_BO_SHIFT,
0256                 sta350_binary_output);
0257 static SOC_ENUM_SINGLE_DECL(sta350_binary_output_ch2_enum,
0258                 STA350_C2CFG, STA350_CxCFG_BO_SHIFT,
0259                 sta350_binary_output);
0260 static SOC_ENUM_SINGLE_DECL(sta350_binary_output_ch3_enum,
0261                 STA350_C3CFG, STA350_CxCFG_BO_SHIFT,
0262                 sta350_binary_output);
0263 static SOC_ENUM_SINGLE_DECL(sta350_limiter_ch1_enum,
0264                 STA350_C1CFG, STA350_CxCFG_LS_SHIFT,
0265                 sta350_limiter_select);
0266 static SOC_ENUM_SINGLE_DECL(sta350_limiter_ch2_enum,
0267                 STA350_C2CFG, STA350_CxCFG_LS_SHIFT,
0268                 sta350_limiter_select);
0269 static SOC_ENUM_SINGLE_DECL(sta350_limiter_ch3_enum,
0270                 STA350_C3CFG, STA350_CxCFG_LS_SHIFT,
0271                 sta350_limiter_select);
0272 static SOC_ENUM_SINGLE_DECL(sta350_limiter1_attack_rate_enum,
0273                 STA350_L1AR, STA350_LxA_SHIFT,
0274                 sta350_limiter_attack_rate);
0275 static SOC_ENUM_SINGLE_DECL(sta350_limiter2_attack_rate_enum,
0276                 STA350_L2AR, STA350_LxA_SHIFT,
0277                 sta350_limiter_attack_rate);
0278 static SOC_ENUM_SINGLE_DECL(sta350_limiter1_release_rate_enum,
0279                 STA350_L1AR, STA350_LxR_SHIFT,
0280                 sta350_limiter_release_rate);
0281 static SOC_ENUM_SINGLE_DECL(sta350_limiter2_release_rate_enum,
0282                 STA350_L2AR, STA350_LxR_SHIFT,
0283                 sta350_limiter_release_rate);
0284 
0285 /*
0286  * byte array controls for setting biquad, mixer, scaling coefficients;
0287  * for biquads all five coefficients need to be set in one go,
0288  * mixer and pre/postscale coefs can be set individually;
0289  * each coef is 24bit, the bytes are ordered in the same way
0290  * as given in the STA350 data sheet (big endian; b1, b2, a1, a2, b0)
0291  */
0292 
0293 static int sta350_coefficient_info(struct snd_kcontrol *kcontrol,
0294                    struct snd_ctl_elem_info *uinfo)
0295 {
0296     int numcoef = kcontrol->private_value >> 16;
0297     uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
0298     uinfo->count = 3 * numcoef;
0299     return 0;
0300 }
0301 
0302 static int sta350_coefficient_get(struct snd_kcontrol *kcontrol,
0303                   struct snd_ctl_elem_value *ucontrol)
0304 {
0305     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0306     struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component);
0307     int numcoef = kcontrol->private_value >> 16;
0308     int index = kcontrol->private_value & 0xffff;
0309     unsigned int cfud, val;
0310     int i, ret = 0;
0311 
0312     mutex_lock(&sta350->coeff_lock);
0313 
0314     /* preserve reserved bits in STA350_CFUD */
0315     regmap_read(sta350->regmap, STA350_CFUD, &cfud);
0316     cfud &= 0xf0;
0317     /*
0318      * chip documentation does not say if the bits are self clearing,
0319      * so do it explicitly
0320      */
0321     regmap_write(sta350->regmap, STA350_CFUD, cfud);
0322 
0323     regmap_write(sta350->regmap, STA350_CFADDR2, index);
0324     if (numcoef == 1) {
0325         regmap_write(sta350->regmap, STA350_CFUD, cfud | 0x04);
0326     } else if (numcoef == 5) {
0327         regmap_write(sta350->regmap, STA350_CFUD, cfud | 0x08);
0328     } else {
0329         ret = -EINVAL;
0330         goto exit_unlock;
0331     }
0332 
0333     for (i = 0; i < 3 * numcoef; i++) {
0334         regmap_read(sta350->regmap, STA350_B1CF1 + i, &val);
0335         ucontrol->value.bytes.data[i] = val;
0336     }
0337 
0338 exit_unlock:
0339     mutex_unlock(&sta350->coeff_lock);
0340 
0341     return ret;
0342 }
0343 
0344 static int sta350_coefficient_put(struct snd_kcontrol *kcontrol,
0345                   struct snd_ctl_elem_value *ucontrol)
0346 {
0347     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0348     struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component);
0349     int numcoef = kcontrol->private_value >> 16;
0350     int index = kcontrol->private_value & 0xffff;
0351     unsigned int cfud;
0352     int i;
0353 
0354     /* preserve reserved bits in STA350_CFUD */
0355     regmap_read(sta350->regmap, STA350_CFUD, &cfud);
0356     cfud &= 0xf0;
0357     /*
0358      * chip documentation does not say if the bits are self clearing,
0359      * so do it explicitly
0360      */
0361     regmap_write(sta350->regmap, STA350_CFUD, cfud);
0362 
0363     regmap_write(sta350->regmap, STA350_CFADDR2, index);
0364     for (i = 0; i < numcoef && (index + i < STA350_COEF_COUNT); i++)
0365         sta350->coef_shadow[index + i] =
0366               (ucontrol->value.bytes.data[3 * i] << 16)
0367             | (ucontrol->value.bytes.data[3 * i + 1] << 8)
0368             | (ucontrol->value.bytes.data[3 * i + 2]);
0369     for (i = 0; i < 3 * numcoef; i++)
0370         regmap_write(sta350->regmap, STA350_B1CF1 + i,
0371                  ucontrol->value.bytes.data[i]);
0372     if (numcoef == 1)
0373         regmap_write(sta350->regmap, STA350_CFUD, cfud | 0x01);
0374     else if (numcoef == 5)
0375         regmap_write(sta350->regmap, STA350_CFUD, cfud | 0x02);
0376     else
0377         return -EINVAL;
0378 
0379     return 0;
0380 }
0381 
0382 static int sta350_sync_coef_shadow(struct snd_soc_component *component)
0383 {
0384     struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component);
0385     unsigned int cfud;
0386     int i;
0387 
0388     /* preserve reserved bits in STA350_CFUD */
0389     regmap_read(sta350->regmap, STA350_CFUD, &cfud);
0390     cfud &= 0xf0;
0391 
0392     for (i = 0; i < STA350_COEF_COUNT; i++) {
0393         regmap_write(sta350->regmap, STA350_CFADDR2, i);
0394         regmap_write(sta350->regmap, STA350_B1CF1,
0395                  (sta350->coef_shadow[i] >> 16) & 0xff);
0396         regmap_write(sta350->regmap, STA350_B1CF2,
0397                  (sta350->coef_shadow[i] >> 8) & 0xff);
0398         regmap_write(sta350->regmap, STA350_B1CF3,
0399                  (sta350->coef_shadow[i]) & 0xff);
0400         /*
0401          * chip documentation does not say if the bits are
0402          * self-clearing, so do it explicitly
0403          */
0404         regmap_write(sta350->regmap, STA350_CFUD, cfud);
0405         regmap_write(sta350->regmap, STA350_CFUD, cfud | 0x01);
0406     }
0407     return 0;
0408 }
0409 
0410 static int sta350_cache_sync(struct snd_soc_component *component)
0411 {
0412     struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component);
0413     unsigned int mute;
0414     int rc;
0415 
0416     /* mute during register sync */
0417     regmap_read(sta350->regmap, STA350_CFUD, &mute);
0418     regmap_write(sta350->regmap, STA350_MMUTE, mute | STA350_MMUTE_MMUTE);
0419     sta350_sync_coef_shadow(component);
0420     rc = regcache_sync(sta350->regmap);
0421     regmap_write(sta350->regmap, STA350_MMUTE, mute);
0422     return rc;
0423 }
0424 
0425 #define SINGLE_COEF(xname, index) \
0426 {   .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
0427     .info = sta350_coefficient_info, \
0428     .get = sta350_coefficient_get,\
0429     .put = sta350_coefficient_put, \
0430     .private_value = index | (1 << 16) }
0431 
0432 #define BIQUAD_COEFS(xname, index) \
0433 {   .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
0434     .info = sta350_coefficient_info, \
0435     .get = sta350_coefficient_get,\
0436     .put = sta350_coefficient_put, \
0437     .private_value = index | (5 << 16) }
0438 
0439 static const struct snd_kcontrol_new sta350_snd_controls[] = {
0440 SOC_SINGLE_TLV("Master Volume", STA350_MVOL, 0, 0xff, 1, mvol_tlv),
0441 /* VOL */
0442 SOC_SINGLE_TLV("Ch1 Volume", STA350_C1VOL, 0, 0xff, 1, chvol_tlv),
0443 SOC_SINGLE_TLV("Ch2 Volume", STA350_C2VOL, 0, 0xff, 1, chvol_tlv),
0444 SOC_SINGLE_TLV("Ch3 Volume", STA350_C3VOL, 0, 0xff, 1, chvol_tlv),
0445 /* CONFD */
0446 SOC_SINGLE("High Pass Filter Bypass Switch",
0447        STA350_CONFD, STA350_CONFD_HPB_SHIFT, 1, 1),
0448 SOC_SINGLE("De-emphasis Filter Switch",
0449        STA350_CONFD, STA350_CONFD_DEMP_SHIFT, 1, 0),
0450 SOC_SINGLE("DSP Bypass Switch",
0451        STA350_CONFD, STA350_CONFD_DSPB_SHIFT, 1, 0),
0452 SOC_SINGLE("Post-scale Link Switch",
0453        STA350_CONFD, STA350_CONFD_PSL_SHIFT, 1, 0),
0454 SOC_SINGLE("Biquad Coefficient Link Switch",
0455        STA350_CONFD, STA350_CONFD_BQL_SHIFT, 1, 0),
0456 SOC_ENUM("Compressor/Limiter Switch", sta350_drc_ac_enum),
0457 SOC_ENUM("Noise Shaper Bandwidth", sta350_noise_shaper_enum),
0458 SOC_SINGLE("Zero-detect Mute Enable Switch",
0459        STA350_CONFD, STA350_CONFD_ZDE_SHIFT, 1, 0),
0460 SOC_SINGLE("Submix Mode Switch",
0461        STA350_CONFD, STA350_CONFD_SME_SHIFT, 1, 0),
0462 /* CONFE */
0463 SOC_SINGLE("Zero Cross Switch", STA350_CONFE, STA350_CONFE_ZCE_SHIFT, 1, 0),
0464 SOC_SINGLE("Soft Ramp Switch", STA350_CONFE, STA350_CONFE_SVE_SHIFT, 1, 0),
0465 /* MUTE */
0466 SOC_SINGLE("Master Switch", STA350_MMUTE, STA350_MMUTE_MMUTE_SHIFT, 1, 1),
0467 SOC_SINGLE("Ch1 Switch", STA350_MMUTE, STA350_MMUTE_C1M_SHIFT, 1, 1),
0468 SOC_SINGLE("Ch2 Switch", STA350_MMUTE, STA350_MMUTE_C2M_SHIFT, 1, 1),
0469 SOC_SINGLE("Ch3 Switch", STA350_MMUTE, STA350_MMUTE_C3M_SHIFT, 1, 1),
0470 /* AUTOx */
0471 SOC_ENUM("Automode GC", sta350_auto_gc_enum),
0472 SOC_ENUM("Automode XO", sta350_auto_xo_enum),
0473 /* CxCFG */
0474 SOC_SINGLE("Ch1 Tone Control Bypass Switch",
0475        STA350_C1CFG, STA350_CxCFG_TCB_SHIFT, 1, 0),
0476 SOC_SINGLE("Ch2 Tone Control Bypass Switch",
0477        STA350_C2CFG, STA350_CxCFG_TCB_SHIFT, 1, 0),
0478 SOC_SINGLE("Ch1 EQ Bypass Switch",
0479        STA350_C1CFG, STA350_CxCFG_EQBP_SHIFT, 1, 0),
0480 SOC_SINGLE("Ch2 EQ Bypass Switch",
0481        STA350_C2CFG, STA350_CxCFG_EQBP_SHIFT, 1, 0),
0482 SOC_SINGLE("Ch1 Master Volume Bypass Switch",
0483        STA350_C1CFG, STA350_CxCFG_VBP_SHIFT, 1, 0),
0484 SOC_SINGLE("Ch2 Master Volume Bypass Switch",
0485        STA350_C1CFG, STA350_CxCFG_VBP_SHIFT, 1, 0),
0486 SOC_SINGLE("Ch3 Master Volume Bypass Switch",
0487        STA350_C1CFG, STA350_CxCFG_VBP_SHIFT, 1, 0),
0488 SOC_ENUM("Ch1 Binary Output Select", sta350_binary_output_ch1_enum),
0489 SOC_ENUM("Ch2 Binary Output Select", sta350_binary_output_ch2_enum),
0490 SOC_ENUM("Ch3 Binary Output Select", sta350_binary_output_ch3_enum),
0491 SOC_ENUM("Ch1 Limiter Select", sta350_limiter_ch1_enum),
0492 SOC_ENUM("Ch2 Limiter Select", sta350_limiter_ch2_enum),
0493 SOC_ENUM("Ch3 Limiter Select", sta350_limiter_ch3_enum),
0494 /* TONE */
0495 SOC_SINGLE_RANGE_TLV("Bass Tone Control Volume",
0496              STA350_TONE, STA350_TONE_BTC_SHIFT, 1, 13, 0, tone_tlv),
0497 SOC_SINGLE_RANGE_TLV("Treble Tone Control Volume",
0498              STA350_TONE, STA350_TONE_TTC_SHIFT, 1, 13, 0, tone_tlv),
0499 SOC_ENUM("Limiter1 Attack Rate (dB/ms)", sta350_limiter1_attack_rate_enum),
0500 SOC_ENUM("Limiter2 Attack Rate (dB/ms)", sta350_limiter2_attack_rate_enum),
0501 SOC_ENUM("Limiter1 Release Rate (dB/ms)", sta350_limiter1_release_rate_enum),
0502 SOC_ENUM("Limiter2 Release Rate (dB/ms)", sta350_limiter2_release_rate_enum),
0503 
0504 /*
0505  * depending on mode, the attack/release thresholds have
0506  * two different enum definitions; provide both
0507  */
0508 SOC_SINGLE_TLV("Limiter1 Attack Threshold (AC Mode)",
0509            STA350_L1ATRT, STA350_LxA_SHIFT,
0510            16, 0, sta350_limiter_ac_attack_tlv),
0511 SOC_SINGLE_TLV("Limiter2 Attack Threshold (AC Mode)",
0512            STA350_L2ATRT, STA350_LxA_SHIFT,
0513            16, 0, sta350_limiter_ac_attack_tlv),
0514 SOC_SINGLE_TLV("Limiter1 Release Threshold (AC Mode)",
0515            STA350_L1ATRT, STA350_LxR_SHIFT,
0516            16, 0, sta350_limiter_ac_release_tlv),
0517 SOC_SINGLE_TLV("Limiter2 Release Threshold (AC Mode)",
0518            STA350_L2ATRT, STA350_LxR_SHIFT,
0519            16, 0, sta350_limiter_ac_release_tlv),
0520 SOC_SINGLE_TLV("Limiter1 Attack Threshold (DRC Mode)",
0521            STA350_L1ATRT, STA350_LxA_SHIFT,
0522            16, 0, sta350_limiter_drc_attack_tlv),
0523 SOC_SINGLE_TLV("Limiter2 Attack Threshold (DRC Mode)",
0524            STA350_L2ATRT, STA350_LxA_SHIFT,
0525            16, 0, sta350_limiter_drc_attack_tlv),
0526 SOC_SINGLE_TLV("Limiter1 Release Threshold (DRC Mode)",
0527            STA350_L1ATRT, STA350_LxR_SHIFT,
0528            16, 0, sta350_limiter_drc_release_tlv),
0529 SOC_SINGLE_TLV("Limiter2 Release Threshold (DRC Mode)",
0530            STA350_L2ATRT, STA350_LxR_SHIFT,
0531            16, 0, sta350_limiter_drc_release_tlv),
0532 
0533 BIQUAD_COEFS("Ch1 - Biquad 1", 0),
0534 BIQUAD_COEFS("Ch1 - Biquad 2", 5),
0535 BIQUAD_COEFS("Ch1 - Biquad 3", 10),
0536 BIQUAD_COEFS("Ch1 - Biquad 4", 15),
0537 BIQUAD_COEFS("Ch2 - Biquad 1", 20),
0538 BIQUAD_COEFS("Ch2 - Biquad 2", 25),
0539 BIQUAD_COEFS("Ch2 - Biquad 3", 30),
0540 BIQUAD_COEFS("Ch2 - Biquad 4", 35),
0541 BIQUAD_COEFS("High-pass", 40),
0542 BIQUAD_COEFS("Low-pass", 45),
0543 SINGLE_COEF("Ch1 - Prescale", 50),
0544 SINGLE_COEF("Ch2 - Prescale", 51),
0545 SINGLE_COEF("Ch1 - Postscale", 52),
0546 SINGLE_COEF("Ch2 - Postscale", 53),
0547 SINGLE_COEF("Ch3 - Postscale", 54),
0548 SINGLE_COEF("Thermal warning - Postscale", 55),
0549 SINGLE_COEF("Ch1 - Mix 1", 56),
0550 SINGLE_COEF("Ch1 - Mix 2", 57),
0551 SINGLE_COEF("Ch2 - Mix 1", 58),
0552 SINGLE_COEF("Ch2 - Mix 2", 59),
0553 SINGLE_COEF("Ch3 - Mix 1", 60),
0554 SINGLE_COEF("Ch3 - Mix 2", 61),
0555 };
0556 
0557 static const struct snd_soc_dapm_widget sta350_dapm_widgets[] = {
0558 SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
0559 SND_SOC_DAPM_OUTPUT("LEFT"),
0560 SND_SOC_DAPM_OUTPUT("RIGHT"),
0561 SND_SOC_DAPM_OUTPUT("SUB"),
0562 };
0563 
0564 static const struct snd_soc_dapm_route sta350_dapm_routes[] = {
0565     { "LEFT", NULL, "DAC" },
0566     { "RIGHT", NULL, "DAC" },
0567     { "SUB", NULL, "DAC" },
0568     { "DAC", NULL, "Playback" },
0569 };
0570 
0571 /* MCLK interpolation ratio per fs */
0572 static struct {
0573     int fs;
0574     int ir;
0575 } interpolation_ratios[] = {
0576     { 32000, 0 },
0577     { 44100, 0 },
0578     { 48000, 0 },
0579     { 88200, 1 },
0580     { 96000, 1 },
0581     { 176400, 2 },
0582     { 192000, 2 },
0583 };
0584 
0585 /* MCLK to fs clock ratios */
0586 static int mcs_ratio_table[3][6] = {
0587     { 768, 512, 384, 256, 128, 576 },
0588     { 384, 256, 192, 128,  64,   0 },
0589     { 192, 128,  96,  64,  32,   0 },
0590 };
0591 
0592 /**
0593  * sta350_set_dai_sysclk - configure MCLK
0594  * @codec_dai: the codec DAI
0595  * @clk_id: the clock ID (ignored)
0596  * @freq: the MCLK input frequency
0597  * @dir: the clock direction (ignored)
0598  *
0599  * The value of MCLK is used to determine which sample rates are supported
0600  * by the STA350, based on the mcs_ratio_table.
0601  *
0602  * This function must be called by the machine driver's 'startup' function,
0603  * otherwise the list of supported sample rates will not be available in
0604  * time for ALSA.
0605  */
0606 static int sta350_set_dai_sysclk(struct snd_soc_dai *codec_dai,
0607                  int clk_id, unsigned int freq, int dir)
0608 {
0609     struct snd_soc_component *component = codec_dai->component;
0610     struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component);
0611 
0612     dev_dbg(component->dev, "mclk=%u\n", freq);
0613     sta350->mclk = freq;
0614 
0615     return 0;
0616 }
0617 
0618 /**
0619  * sta350_set_dai_fmt - configure the codec for the selected audio format
0620  * @codec_dai: the codec DAI
0621  * @fmt: a SND_SOC_DAIFMT_x value indicating the data format
0622  *
0623  * This function takes a bitmask of SND_SOC_DAIFMT_x bits and programs the
0624  * codec accordingly.
0625  */
0626 static int sta350_set_dai_fmt(struct snd_soc_dai *codec_dai,
0627                   unsigned int fmt)
0628 {
0629     struct snd_soc_component *component = codec_dai->component;
0630     struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component);
0631     unsigned int confb = 0;
0632 
0633     switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0634     case SND_SOC_DAIFMT_CBC_CFC:
0635         break;
0636     default:
0637         return -EINVAL;
0638     }
0639 
0640     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0641     case SND_SOC_DAIFMT_I2S:
0642     case SND_SOC_DAIFMT_RIGHT_J:
0643     case SND_SOC_DAIFMT_LEFT_J:
0644         sta350->format = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
0645         break;
0646     default:
0647         return -EINVAL;
0648     }
0649 
0650     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0651     case SND_SOC_DAIFMT_NB_NF:
0652         confb |= STA350_CONFB_C2IM;
0653         break;
0654     case SND_SOC_DAIFMT_NB_IF:
0655         confb |= STA350_CONFB_C1IM;
0656         break;
0657     default:
0658         return -EINVAL;
0659     }
0660 
0661     return regmap_update_bits(sta350->regmap, STA350_CONFB,
0662                   STA350_CONFB_C1IM | STA350_CONFB_C2IM, confb);
0663 }
0664 
0665 /**
0666  * sta350_hw_params - program the STA350 with the given hardware parameters.
0667  * @substream: the audio stream
0668  * @params: the hardware parameters to set
0669  * @dai: the SOC DAI (ignored)
0670  *
0671  * This function programs the hardware with the values provided.
0672  * Specifically, the sample rate and the data format.
0673  */
0674 static int sta350_hw_params(struct snd_pcm_substream *substream,
0675                 struct snd_pcm_hw_params *params,
0676                 struct snd_soc_dai *dai)
0677 {
0678     struct snd_soc_component *component = dai->component;
0679     struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component);
0680     int i, mcs = -EINVAL, ir = -EINVAL;
0681     unsigned int confa, confb;
0682     unsigned int rate, ratio;
0683     int ret;
0684 
0685     if (!sta350->mclk) {
0686         dev_err(component->dev,
0687             "sta350->mclk is unset. Unable to determine ratio\n");
0688         return -EIO;
0689     }
0690 
0691     rate = params_rate(params);
0692     ratio = sta350->mclk / rate;
0693     dev_dbg(component->dev, "rate: %u, ratio: %u\n", rate, ratio);
0694 
0695     for (i = 0; i < ARRAY_SIZE(interpolation_ratios); i++) {
0696         if (interpolation_ratios[i].fs == rate) {
0697             ir = interpolation_ratios[i].ir;
0698             break;
0699         }
0700     }
0701 
0702     if (ir < 0) {
0703         dev_err(component->dev, "Unsupported samplerate: %u\n", rate);
0704         return -EINVAL;
0705     }
0706 
0707     for (i = 0; i < 6; i++) {
0708         if (mcs_ratio_table[ir][i] == ratio) {
0709             mcs = i;
0710             break;
0711         }
0712     }
0713 
0714     if (mcs < 0) {
0715         dev_err(component->dev, "Unresolvable ratio: %u\n", ratio);
0716         return -EINVAL;
0717     }
0718 
0719     confa = (ir << STA350_CONFA_IR_SHIFT) |
0720         (mcs << STA350_CONFA_MCS_SHIFT);
0721     confb = 0;
0722 
0723     switch (params_width(params)) {
0724     case 24:
0725         dev_dbg(component->dev, "24bit\n");
0726         fallthrough;
0727     case 32:
0728         dev_dbg(component->dev, "24bit or 32bit\n");
0729         switch (sta350->format) {
0730         case SND_SOC_DAIFMT_I2S:
0731             confb |= 0x0;
0732             break;
0733         case SND_SOC_DAIFMT_LEFT_J:
0734             confb |= 0x1;
0735             break;
0736         case SND_SOC_DAIFMT_RIGHT_J:
0737             confb |= 0x2;
0738             break;
0739         }
0740 
0741         break;
0742     case 20:
0743         dev_dbg(component->dev, "20bit\n");
0744         switch (sta350->format) {
0745         case SND_SOC_DAIFMT_I2S:
0746             confb |= 0x4;
0747             break;
0748         case SND_SOC_DAIFMT_LEFT_J:
0749             confb |= 0x5;
0750             break;
0751         case SND_SOC_DAIFMT_RIGHT_J:
0752             confb |= 0x6;
0753             break;
0754         }
0755 
0756         break;
0757     case 18:
0758         dev_dbg(component->dev, "18bit\n");
0759         switch (sta350->format) {
0760         case SND_SOC_DAIFMT_I2S:
0761             confb |= 0x8;
0762             break;
0763         case SND_SOC_DAIFMT_LEFT_J:
0764             confb |= 0x9;
0765             break;
0766         case SND_SOC_DAIFMT_RIGHT_J:
0767             confb |= 0xa;
0768             break;
0769         }
0770 
0771         break;
0772     case 16:
0773         dev_dbg(component->dev, "16bit\n");
0774         switch (sta350->format) {
0775         case SND_SOC_DAIFMT_I2S:
0776             confb |= 0x0;
0777             break;
0778         case SND_SOC_DAIFMT_LEFT_J:
0779             confb |= 0xd;
0780             break;
0781         case SND_SOC_DAIFMT_RIGHT_J:
0782             confb |= 0xe;
0783             break;
0784         }
0785 
0786         break;
0787     default:
0788         return -EINVAL;
0789     }
0790 
0791     ret = regmap_update_bits(sta350->regmap, STA350_CONFA,
0792                  STA350_CONFA_MCS_MASK | STA350_CONFA_IR_MASK,
0793                  confa);
0794     if (ret < 0)
0795         return ret;
0796 
0797     ret = regmap_update_bits(sta350->regmap, STA350_CONFB,
0798                  STA350_CONFB_SAI_MASK | STA350_CONFB_SAIFB,
0799                  confb);
0800     if (ret < 0)
0801         return ret;
0802 
0803     return 0;
0804 }
0805 
0806 static int sta350_startup_sequence(struct sta350_priv *sta350)
0807 {
0808     if (sta350->gpiod_power_down)
0809         gpiod_set_value(sta350->gpiod_power_down, 1);
0810 
0811     if (sta350->gpiod_nreset) {
0812         gpiod_set_value(sta350->gpiod_nreset, 0);
0813         mdelay(1);
0814         gpiod_set_value(sta350->gpiod_nreset, 1);
0815         mdelay(1);
0816     }
0817 
0818     return 0;
0819 }
0820 
0821 /**
0822  * sta350_set_bias_level - DAPM callback
0823  * @component: the component device
0824  * @level: DAPM power level
0825  *
0826  * This is called by ALSA to put the component into low power mode
0827  * or to wake it up.  If the component is powered off completely
0828  * all registers must be restored after power on.
0829  */
0830 static int sta350_set_bias_level(struct snd_soc_component *component,
0831                  enum snd_soc_bias_level level)
0832 {
0833     struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component);
0834     int ret;
0835 
0836     dev_dbg(component->dev, "level = %d\n", level);
0837     switch (level) {
0838     case SND_SOC_BIAS_ON:
0839         break;
0840 
0841     case SND_SOC_BIAS_PREPARE:
0842         /* Full power on */
0843         regmap_update_bits(sta350->regmap, STA350_CONFF,
0844                    STA350_CONFF_PWDN | STA350_CONFF_EAPD,
0845                    STA350_CONFF_PWDN | STA350_CONFF_EAPD);
0846         break;
0847 
0848     case SND_SOC_BIAS_STANDBY:
0849         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
0850             ret = regulator_bulk_enable(
0851                 ARRAY_SIZE(sta350->supplies),
0852                 sta350->supplies);
0853             if (ret < 0) {
0854                 dev_err(component->dev,
0855                     "Failed to enable supplies: %d\n",
0856                     ret);
0857                 return ret;
0858             }
0859             sta350_startup_sequence(sta350);
0860             sta350_cache_sync(component);
0861         }
0862 
0863         /* Power down */
0864         regmap_update_bits(sta350->regmap, STA350_CONFF,
0865                    STA350_CONFF_PWDN | STA350_CONFF_EAPD,
0866                    0);
0867 
0868         break;
0869 
0870     case SND_SOC_BIAS_OFF:
0871         /* The chip runs through the power down sequence for us */
0872         regmap_update_bits(sta350->regmap, STA350_CONFF,
0873                    STA350_CONFF_PWDN | STA350_CONFF_EAPD, 0);
0874 
0875         /* power down: low */
0876         if (sta350->gpiod_power_down)
0877             gpiod_set_value(sta350->gpiod_power_down, 0);
0878 
0879         if (sta350->gpiod_nreset)
0880             gpiod_set_value(sta350->gpiod_nreset, 0);
0881 
0882         regulator_bulk_disable(ARRAY_SIZE(sta350->supplies),
0883                        sta350->supplies);
0884         break;
0885     }
0886     return 0;
0887 }
0888 
0889 static const struct snd_soc_dai_ops sta350_dai_ops = {
0890     .hw_params  = sta350_hw_params,
0891     .set_sysclk = sta350_set_dai_sysclk,
0892     .set_fmt    = sta350_set_dai_fmt,
0893 };
0894 
0895 static struct snd_soc_dai_driver sta350_dai = {
0896     .name = "sta350-hifi",
0897     .playback = {
0898         .stream_name = "Playback",
0899         .channels_min = 2,
0900         .channels_max = 2,
0901         .rates = STA350_RATES,
0902         .formats = STA350_FORMATS,
0903     },
0904     .ops = &sta350_dai_ops,
0905 };
0906 
0907 static int sta350_probe(struct snd_soc_component *component)
0908 {
0909     struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component);
0910     struct sta350_platform_data *pdata = sta350->pdata;
0911     int i, ret = 0, thermal = 0;
0912 
0913     ret = regulator_bulk_enable(ARRAY_SIZE(sta350->supplies),
0914                     sta350->supplies);
0915     if (ret < 0) {
0916         dev_err(component->dev, "Failed to enable supplies: %d\n", ret);
0917         return ret;
0918     }
0919 
0920     ret = sta350_startup_sequence(sta350);
0921     if (ret < 0) {
0922         dev_err(component->dev, "Failed to startup device\n");
0923         return ret;
0924     }
0925 
0926     /* CONFA */
0927     if (!pdata->thermal_warning_recovery)
0928         thermal |= STA350_CONFA_TWAB;
0929     if (!pdata->thermal_warning_adjustment)
0930         thermal |= STA350_CONFA_TWRB;
0931     if (!pdata->fault_detect_recovery)
0932         thermal |= STA350_CONFA_FDRB;
0933     regmap_update_bits(sta350->regmap, STA350_CONFA,
0934                STA350_CONFA_TWAB | STA350_CONFA_TWRB |
0935                STA350_CONFA_FDRB,
0936                thermal);
0937 
0938     /* CONFC */
0939     regmap_update_bits(sta350->regmap, STA350_CONFC,
0940                STA350_CONFC_OM_MASK,
0941                pdata->ffx_power_output_mode
0942                 << STA350_CONFC_OM_SHIFT);
0943     regmap_update_bits(sta350->regmap, STA350_CONFC,
0944                STA350_CONFC_CSZ_MASK,
0945                pdata->drop_compensation_ns
0946                 << STA350_CONFC_CSZ_SHIFT);
0947     regmap_update_bits(sta350->regmap,
0948                STA350_CONFC,
0949                STA350_CONFC_OCRB,
0950                pdata->oc_warning_adjustment ?
0951                 STA350_CONFC_OCRB : 0);
0952 
0953     /* CONFE */
0954     regmap_update_bits(sta350->regmap, STA350_CONFE,
0955                STA350_CONFE_MPCV,
0956                pdata->max_power_use_mpcc ?
0957                 STA350_CONFE_MPCV : 0);
0958     regmap_update_bits(sta350->regmap, STA350_CONFE,
0959                STA350_CONFE_MPC,
0960                pdata->max_power_correction ?
0961                 STA350_CONFE_MPC : 0);
0962     regmap_update_bits(sta350->regmap, STA350_CONFE,
0963                STA350_CONFE_AME,
0964                pdata->am_reduction_mode ?
0965                 STA350_CONFE_AME : 0);
0966     regmap_update_bits(sta350->regmap, STA350_CONFE,
0967                STA350_CONFE_PWMS,
0968                pdata->odd_pwm_speed_mode ?
0969                 STA350_CONFE_PWMS : 0);
0970     regmap_update_bits(sta350->regmap, STA350_CONFE,
0971                STA350_CONFE_DCCV,
0972                pdata->distortion_compensation ?
0973                 STA350_CONFE_DCCV : 0);
0974     /*  CONFF */
0975     regmap_update_bits(sta350->regmap, STA350_CONFF,
0976                STA350_CONFF_IDE,
0977                pdata->invalid_input_detect_mute ?
0978                 STA350_CONFF_IDE : 0);
0979     regmap_update_bits(sta350->regmap, STA350_CONFF,
0980                STA350_CONFF_OCFG_MASK,
0981                pdata->output_conf
0982                 << STA350_CONFF_OCFG_SHIFT);
0983 
0984     /* channel to output mapping */
0985     regmap_update_bits(sta350->regmap, STA350_C1CFG,
0986                STA350_CxCFG_OM_MASK,
0987                pdata->ch1_output_mapping
0988                 << STA350_CxCFG_OM_SHIFT);
0989     regmap_update_bits(sta350->regmap, STA350_C2CFG,
0990                STA350_CxCFG_OM_MASK,
0991                pdata->ch2_output_mapping
0992                 << STA350_CxCFG_OM_SHIFT);
0993     regmap_update_bits(sta350->regmap, STA350_C3CFG,
0994                STA350_CxCFG_OM_MASK,
0995                pdata->ch3_output_mapping
0996                 << STA350_CxCFG_OM_SHIFT);
0997 
0998     /* miscellaneous registers */
0999     regmap_update_bits(sta350->regmap, STA350_MISC1,
1000                STA350_MISC1_CPWMEN,
1001                pdata->activate_mute_output ?
1002                 STA350_MISC1_CPWMEN : 0);
1003     regmap_update_bits(sta350->regmap, STA350_MISC1,
1004                STA350_MISC1_BRIDGOFF,
1005                pdata->bridge_immediate_off ?
1006                 STA350_MISC1_BRIDGOFF : 0);
1007     regmap_update_bits(sta350->regmap, STA350_MISC1,
1008                STA350_MISC1_NSHHPEN,
1009                pdata->noise_shape_dc_cut ?
1010                 STA350_MISC1_NSHHPEN : 0);
1011     regmap_update_bits(sta350->regmap, STA350_MISC1,
1012                STA350_MISC1_RPDNEN,
1013                pdata->powerdown_master_vol ?
1014                 STA350_MISC1_RPDNEN: 0);
1015 
1016     regmap_update_bits(sta350->regmap, STA350_MISC2,
1017                STA350_MISC2_PNDLSL_MASK,
1018                pdata->powerdown_delay_divider
1019                 << STA350_MISC2_PNDLSL_SHIFT);
1020 
1021     /* initialize coefficient shadow RAM with reset values */
1022     for (i = 4; i <= 49; i += 5)
1023         sta350->coef_shadow[i] = 0x400000;
1024     for (i = 50; i <= 54; i++)
1025         sta350->coef_shadow[i] = 0x7fffff;
1026     sta350->coef_shadow[55] = 0x5a9df7;
1027     sta350->coef_shadow[56] = 0x7fffff;
1028     sta350->coef_shadow[59] = 0x7fffff;
1029     sta350->coef_shadow[60] = 0x400000;
1030     sta350->coef_shadow[61] = 0x400000;
1031 
1032     snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
1033     /* Bias level configuration will have done an extra enable */
1034     regulator_bulk_disable(ARRAY_SIZE(sta350->supplies), sta350->supplies);
1035 
1036     return 0;
1037 }
1038 
1039 static void sta350_remove(struct snd_soc_component *component)
1040 {
1041     struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component);
1042 
1043     regulator_bulk_disable(ARRAY_SIZE(sta350->supplies), sta350->supplies);
1044 }
1045 
1046 static const struct snd_soc_component_driver sta350_component = {
1047     .probe          = sta350_probe,
1048     .remove         = sta350_remove,
1049     .set_bias_level     = sta350_set_bias_level,
1050     .controls       = sta350_snd_controls,
1051     .num_controls       = ARRAY_SIZE(sta350_snd_controls),
1052     .dapm_widgets       = sta350_dapm_widgets,
1053     .num_dapm_widgets   = ARRAY_SIZE(sta350_dapm_widgets),
1054     .dapm_routes        = sta350_dapm_routes,
1055     .num_dapm_routes    = ARRAY_SIZE(sta350_dapm_routes),
1056     .suspend_bias_off   = 1,
1057     .idle_bias_on       = 1,
1058     .use_pmdown_time    = 1,
1059     .endianness     = 1,
1060 };
1061 
1062 static const struct regmap_config sta350_regmap = {
1063     .reg_bits =     8,
1064     .val_bits =     8,
1065     .max_register =     STA350_MISC2,
1066     .reg_defaults =     sta350_regs,
1067     .num_reg_defaults = ARRAY_SIZE(sta350_regs),
1068     .cache_type =       REGCACHE_RBTREE,
1069     .wr_table =     &sta350_write_regs,
1070     .rd_table =     &sta350_read_regs,
1071     .volatile_table =   &sta350_volatile_regs,
1072 };
1073 
1074 #ifdef CONFIG_OF
1075 static const struct of_device_id st350_dt_ids[] = {
1076     { .compatible = "st,sta350", },
1077     { }
1078 };
1079 MODULE_DEVICE_TABLE(of, st350_dt_ids);
1080 
1081 static const char * const sta350_ffx_modes[] = {
1082     [STA350_FFX_PM_DROP_COMP]       = "drop-compensation",
1083     [STA350_FFX_PM_TAPERED_COMP]        = "tapered-compensation",
1084     [STA350_FFX_PM_FULL_POWER]      = "full-power-mode",
1085     [STA350_FFX_PM_VARIABLE_DROP_COMP]  = "variable-drop-compensation",
1086 };
1087 
1088 static int sta350_probe_dt(struct device *dev, struct sta350_priv *sta350)
1089 {
1090     struct device_node *np = dev->of_node;
1091     struct sta350_platform_data *pdata;
1092     const char *ffx_power_mode;
1093     u16 tmp;
1094     u8 tmp8;
1095 
1096     pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1097     if (!pdata)
1098         return -ENOMEM;
1099 
1100     of_property_read_u8(np, "st,output-conf",
1101                 &pdata->output_conf);
1102     of_property_read_u8(np, "st,ch1-output-mapping",
1103                 &pdata->ch1_output_mapping);
1104     of_property_read_u8(np, "st,ch2-output-mapping",
1105                 &pdata->ch2_output_mapping);
1106     of_property_read_u8(np, "st,ch3-output-mapping",
1107                 &pdata->ch3_output_mapping);
1108 
1109     if (of_get_property(np, "st,thermal-warning-recovery", NULL))
1110         pdata->thermal_warning_recovery = 1;
1111     if (of_get_property(np, "st,thermal-warning-adjustment", NULL))
1112         pdata->thermal_warning_adjustment = 1;
1113     if (of_get_property(np, "st,fault-detect-recovery", NULL))
1114         pdata->fault_detect_recovery = 1;
1115 
1116     pdata->ffx_power_output_mode = STA350_FFX_PM_VARIABLE_DROP_COMP;
1117     if (!of_property_read_string(np, "st,ffx-power-output-mode",
1118                      &ffx_power_mode)) {
1119         int i, mode = -EINVAL;
1120 
1121         for (i = 0; i < ARRAY_SIZE(sta350_ffx_modes); i++)
1122             if (!strcasecmp(ffx_power_mode, sta350_ffx_modes[i]))
1123                 mode = i;
1124 
1125         if (mode < 0)
1126             dev_warn(dev, "Unsupported ffx output mode: %s\n",
1127                  ffx_power_mode);
1128         else
1129             pdata->ffx_power_output_mode = mode;
1130     }
1131 
1132     tmp = 140;
1133     of_property_read_u16(np, "st,drop-compensation-ns", &tmp);
1134     pdata->drop_compensation_ns = clamp_t(u16, tmp, 0, 300) / 20;
1135 
1136     if (of_get_property(np, "st,overcurrent-warning-adjustment", NULL))
1137         pdata->oc_warning_adjustment = 1;
1138 
1139     /* CONFE */
1140     if (of_get_property(np, "st,max-power-use-mpcc", NULL))
1141         pdata->max_power_use_mpcc = 1;
1142 
1143     if (of_get_property(np, "st,max-power-correction", NULL))
1144         pdata->max_power_correction = 1;
1145 
1146     if (of_get_property(np, "st,am-reduction-mode", NULL))
1147         pdata->am_reduction_mode = 1;
1148 
1149     if (of_get_property(np, "st,odd-pwm-speed-mode", NULL))
1150         pdata->odd_pwm_speed_mode = 1;
1151 
1152     if (of_get_property(np, "st,distortion-compensation", NULL))
1153         pdata->distortion_compensation = 1;
1154 
1155     /* CONFF */
1156     if (of_get_property(np, "st,invalid-input-detect-mute", NULL))
1157         pdata->invalid_input_detect_mute = 1;
1158 
1159     /* MISC */
1160     if (of_get_property(np, "st,activate-mute-output", NULL))
1161         pdata->activate_mute_output = 1;
1162 
1163     if (of_get_property(np, "st,bridge-immediate-off", NULL))
1164         pdata->bridge_immediate_off = 1;
1165 
1166     if (of_get_property(np, "st,noise-shape-dc-cut", NULL))
1167         pdata->noise_shape_dc_cut = 1;
1168 
1169     if (of_get_property(np, "st,powerdown-master-volume", NULL))
1170         pdata->powerdown_master_vol = 1;
1171 
1172     if (!of_property_read_u8(np, "st,powerdown-delay-divider", &tmp8)) {
1173         if (is_power_of_2(tmp8) && tmp8 >= 1 && tmp8 <= 128)
1174             pdata->powerdown_delay_divider = ilog2(tmp8);
1175         else
1176             dev_warn(dev, "Unsupported powerdown delay divider %d\n",
1177                  tmp8);
1178     }
1179 
1180     sta350->pdata = pdata;
1181 
1182     return 0;
1183 }
1184 #endif
1185 
1186 static int sta350_i2c_probe(struct i2c_client *i2c)
1187 {
1188     struct device *dev = &i2c->dev;
1189     struct sta350_priv *sta350;
1190     int ret, i;
1191 
1192     sta350 = devm_kzalloc(dev, sizeof(struct sta350_priv), GFP_KERNEL);
1193     if (!sta350)
1194         return -ENOMEM;
1195 
1196     mutex_init(&sta350->coeff_lock);
1197     sta350->pdata = dev_get_platdata(dev);
1198 
1199 #ifdef CONFIG_OF
1200     if (dev->of_node) {
1201         ret = sta350_probe_dt(dev, sta350);
1202         if (ret < 0)
1203             return ret;
1204     }
1205 #endif
1206 
1207     /* GPIOs */
1208     sta350->gpiod_nreset = devm_gpiod_get_optional(dev, "reset",
1209                                GPIOD_OUT_LOW);
1210     if (IS_ERR(sta350->gpiod_nreset))
1211         return PTR_ERR(sta350->gpiod_nreset);
1212 
1213     sta350->gpiod_power_down = devm_gpiod_get_optional(dev, "power-down",
1214                                GPIOD_OUT_LOW);
1215     if (IS_ERR(sta350->gpiod_power_down))
1216         return PTR_ERR(sta350->gpiod_power_down);
1217 
1218     /* regulators */
1219     for (i = 0; i < ARRAY_SIZE(sta350->supplies); i++)
1220         sta350->supplies[i].supply = sta350_supply_names[i];
1221 
1222     ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(sta350->supplies),
1223                       sta350->supplies);
1224     if (ret < 0) {
1225         dev_err(dev, "Failed to request supplies: %d\n", ret);
1226         return ret;
1227     }
1228 
1229     sta350->regmap = devm_regmap_init_i2c(i2c, &sta350_regmap);
1230     if (IS_ERR(sta350->regmap)) {
1231         ret = PTR_ERR(sta350->regmap);
1232         dev_err(dev, "Failed to init regmap: %d\n", ret);
1233         return ret;
1234     }
1235 
1236     i2c_set_clientdata(i2c, sta350);
1237 
1238     ret = devm_snd_soc_register_component(dev, &sta350_component, &sta350_dai, 1);
1239     if (ret < 0)
1240         dev_err(dev, "Failed to register component (%d)\n", ret);
1241 
1242     return ret;
1243 }
1244 
1245 static int sta350_i2c_remove(struct i2c_client *client)
1246 {
1247     return 0;
1248 }
1249 
1250 static const struct i2c_device_id sta350_i2c_id[] = {
1251     { "sta350", 0 },
1252     { }
1253 };
1254 MODULE_DEVICE_TABLE(i2c, sta350_i2c_id);
1255 
1256 static struct i2c_driver sta350_i2c_driver = {
1257     .driver = {
1258         .name = "sta350",
1259         .of_match_table = of_match_ptr(st350_dt_ids),
1260     },
1261     .probe_new = sta350_i2c_probe,
1262     .remove =   sta350_i2c_remove,
1263     .id_table = sta350_i2c_id,
1264 };
1265 
1266 module_i2c_driver(sta350_i2c_driver);
1267 
1268 MODULE_DESCRIPTION("ASoC STA350 driver");
1269 MODULE_AUTHOR("Sven Brandau <info@brandau.biz>");
1270 MODULE_LICENSE("GPL");
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