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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Codec driver for ST STA32x 2.1-channel high-efficiency digital audio system
0004  *
0005  * Copyright: 2011 Raumfeld GmbH
0006  * Author: Johannes Stezenbach <js@sig21.net>
0007  *
0008  * based on code from:
0009  *  Wolfson Microelectronics PLC.
0010  *    Mark Brown <broonie@opensource.wolfsonmicro.com>
0011  *  Freescale Semiconductor, Inc.
0012  *    Timur Tabi <timur@freescale.com>
0013  */
0014 
0015 #define pr_fmt(fmt) KBUILD_MODNAME ":%s:%d: " fmt, __func__, __LINE__
0016 
0017 #include <linux/module.h>
0018 #include <linux/moduleparam.h>
0019 #include <linux/init.h>
0020 #include <linux/clk.h>
0021 #include <linux/delay.h>
0022 #include <linux/pm.h>
0023 #include <linux/i2c.h>
0024 #include <linux/of_device.h>
0025 #include <linux/of_gpio.h>
0026 #include <linux/regmap.h>
0027 #include <linux/regulator/consumer.h>
0028 #include <linux/gpio/consumer.h>
0029 #include <linux/slab.h>
0030 #include <linux/workqueue.h>
0031 #include <sound/core.h>
0032 #include <sound/pcm.h>
0033 #include <sound/pcm_params.h>
0034 #include <sound/soc.h>
0035 #include <sound/soc-dapm.h>
0036 #include <sound/initval.h>
0037 #include <sound/tlv.h>
0038 
0039 #include <sound/sta32x.h>
0040 #include "sta32x.h"
0041 
0042 #define STA32X_RATES (SNDRV_PCM_RATE_32000 | \
0043               SNDRV_PCM_RATE_44100 | \
0044               SNDRV_PCM_RATE_48000 | \
0045               SNDRV_PCM_RATE_88200 | \
0046               SNDRV_PCM_RATE_96000 | \
0047               SNDRV_PCM_RATE_176400 | \
0048               SNDRV_PCM_RATE_192000)
0049 
0050 #define STA32X_FORMATS \
0051     (SNDRV_PCM_FMTBIT_S16_LE  | SNDRV_PCM_FMTBIT_S18_3LE | \
0052      SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_3LE | \
0053      SNDRV_PCM_FMTBIT_S24_LE  | SNDRV_PCM_FMTBIT_S32_LE)
0054 
0055 /* Power-up register defaults */
0056 static const struct reg_default sta32x_regs[] = {
0057     {  0x0, 0x63 },
0058     {  0x1, 0x80 },
0059     {  0x2, 0xc2 },
0060     {  0x3, 0x40 },
0061     {  0x4, 0xc2 },
0062     {  0x5, 0x5c },
0063     {  0x6, 0x10 },
0064     {  0x7, 0xff },
0065     {  0x8, 0x60 },
0066     {  0x9, 0x60 },
0067     {  0xa, 0x60 },
0068     {  0xb, 0x80 },
0069     {  0xc, 0x00 },
0070     {  0xd, 0x00 },
0071     {  0xe, 0x00 },
0072     {  0xf, 0x40 },
0073     { 0x10, 0x80 },
0074     { 0x11, 0x77 },
0075     { 0x12, 0x6a },
0076     { 0x13, 0x69 },
0077     { 0x14, 0x6a },
0078     { 0x15, 0x69 },
0079     { 0x16, 0x00 },
0080     { 0x17, 0x00 },
0081     { 0x18, 0x00 },
0082     { 0x19, 0x00 },
0083     { 0x1a, 0x00 },
0084     { 0x1b, 0x00 },
0085     { 0x1c, 0x00 },
0086     { 0x1d, 0x00 },
0087     { 0x1e, 0x00 },
0088     { 0x1f, 0x00 },
0089     { 0x20, 0x00 },
0090     { 0x21, 0x00 },
0091     { 0x22, 0x00 },
0092     { 0x23, 0x00 },
0093     { 0x24, 0x00 },
0094     { 0x25, 0x00 },
0095     { 0x26, 0x00 },
0096     { 0x27, 0x2d },
0097     { 0x28, 0xc0 },
0098     { 0x2b, 0x00 },
0099     { 0x2c, 0x0c },
0100 };
0101 
0102 static const struct regmap_range sta32x_write_regs_range[] = {
0103     regmap_reg_range(STA32X_CONFA,  STA32X_FDRC2),
0104 };
0105 
0106 static const struct regmap_range sta32x_read_regs_range[] = {
0107     regmap_reg_range(STA32X_CONFA,  STA32X_FDRC2),
0108 };
0109 
0110 static const struct regmap_range sta32x_volatile_regs_range[] = {
0111     regmap_reg_range(STA32X_CFADDR2, STA32X_CFUD),
0112 };
0113 
0114 static const struct regmap_access_table sta32x_write_regs = {
0115     .yes_ranges =   sta32x_write_regs_range,
0116     .n_yes_ranges = ARRAY_SIZE(sta32x_write_regs_range),
0117 };
0118 
0119 static const struct regmap_access_table sta32x_read_regs = {
0120     .yes_ranges =   sta32x_read_regs_range,
0121     .n_yes_ranges = ARRAY_SIZE(sta32x_read_regs_range),
0122 };
0123 
0124 static const struct regmap_access_table sta32x_volatile_regs = {
0125     .yes_ranges =   sta32x_volatile_regs_range,
0126     .n_yes_ranges = ARRAY_SIZE(sta32x_volatile_regs_range),
0127 };
0128 
0129 /* regulator power supply names */
0130 static const char *sta32x_supply_names[] = {
0131     "Vdda", /* analog supply, 3.3VV */
0132     "Vdd3", /* digital supply, 3.3V */
0133     "Vcc"   /* power amp spply, 10V - 36V */
0134 };
0135 
0136 /* codec private data */
0137 struct sta32x_priv {
0138     struct regmap *regmap;
0139     struct clk *xti_clk;
0140     struct regulator_bulk_data supplies[ARRAY_SIZE(sta32x_supply_names)];
0141     struct snd_soc_component *component;
0142     struct sta32x_platform_data *pdata;
0143 
0144     unsigned int mclk;
0145     unsigned int format;
0146 
0147     u32 coef_shadow[STA32X_COEF_COUNT];
0148     struct delayed_work watchdog_work;
0149     int shutdown;
0150     struct gpio_desc *gpiod_nreset;
0151     struct mutex coeff_lock;
0152 };
0153 
0154 static const DECLARE_TLV_DB_SCALE(mvol_tlv, -12700, 50, 1);
0155 static const DECLARE_TLV_DB_SCALE(chvol_tlv, -7950, 50, 1);
0156 static const DECLARE_TLV_DB_SCALE(tone_tlv, -120, 200, 0);
0157 
0158 static const char *sta32x_drc_ac[] = {
0159     "Anti-Clipping", "Dynamic Range Compression" };
0160 static const char *sta32x_auto_eq_mode[] = {
0161     "User", "Preset", "Loudness" };
0162 static const char *sta32x_auto_gc_mode[] = {
0163     "User", "AC no clipping", "AC limited clipping (10%)",
0164     "DRC nighttime listening mode" };
0165 static const char *sta32x_auto_xo_mode[] = {
0166     "User", "80Hz", "100Hz", "120Hz", "140Hz", "160Hz", "180Hz", "200Hz",
0167     "220Hz", "240Hz", "260Hz", "280Hz", "300Hz", "320Hz", "340Hz", "360Hz" };
0168 static const char *sta32x_preset_eq_mode[] = {
0169     "Flat", "Rock", "Soft Rock", "Jazz", "Classical", "Dance", "Pop", "Soft",
0170     "Hard", "Party", "Vocal", "Hip-Hop", "Dialog", "Bass-boost #1",
0171     "Bass-boost #2", "Bass-boost #3", "Loudness 1", "Loudness 2",
0172     "Loudness 3", "Loudness 4", "Loudness 5", "Loudness 6", "Loudness 7",
0173     "Loudness 8", "Loudness 9", "Loudness 10", "Loudness 11", "Loudness 12",
0174     "Loudness 13", "Loudness 14", "Loudness 15", "Loudness 16" };
0175 static const char *sta32x_limiter_select[] = {
0176     "Limiter Disabled", "Limiter #1", "Limiter #2" };
0177 static const char *sta32x_limiter_attack_rate[] = {
0178     "3.1584", "2.7072", "2.2560", "1.8048", "1.3536", "0.9024",
0179     "0.4512", "0.2256", "0.1504", "0.1123", "0.0902", "0.0752",
0180     "0.0645", "0.0564", "0.0501", "0.0451" };
0181 static const char *sta32x_limiter_release_rate[] = {
0182     "0.5116", "0.1370", "0.0744", "0.0499", "0.0360", "0.0299",
0183     "0.0264", "0.0208", "0.0198", "0.0172", "0.0147", "0.0137",
0184     "0.0134", "0.0117", "0.0110", "0.0104" };
0185 static DECLARE_TLV_DB_RANGE(sta32x_limiter_ac_attack_tlv,
0186     0, 7, TLV_DB_SCALE_ITEM(-1200, 200, 0),
0187     8, 16, TLV_DB_SCALE_ITEM(300, 100, 0),
0188 );
0189 
0190 static DECLARE_TLV_DB_RANGE(sta32x_limiter_ac_release_tlv,
0191     0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0),
0192     1, 1, TLV_DB_SCALE_ITEM(-2900, 0, 0),
0193     2, 2, TLV_DB_SCALE_ITEM(-2000, 0, 0),
0194     3, 8, TLV_DB_SCALE_ITEM(-1400, 200, 0),
0195     8, 16, TLV_DB_SCALE_ITEM(-700, 100, 0),
0196 );
0197 
0198 static DECLARE_TLV_DB_RANGE(sta32x_limiter_drc_attack_tlv,
0199     0, 7, TLV_DB_SCALE_ITEM(-3100, 200, 0),
0200     8, 13, TLV_DB_SCALE_ITEM(-1600, 100, 0),
0201     14, 16, TLV_DB_SCALE_ITEM(-1000, 300, 0),
0202 );
0203 
0204 static DECLARE_TLV_DB_RANGE(sta32x_limiter_drc_release_tlv,
0205     0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0),
0206     1, 2, TLV_DB_SCALE_ITEM(-3800, 200, 0),
0207     3, 4, TLV_DB_SCALE_ITEM(-3300, 200, 0),
0208     5, 12, TLV_DB_SCALE_ITEM(-3000, 200, 0),
0209     13, 16, TLV_DB_SCALE_ITEM(-1500, 300, 0),
0210 );
0211 
0212 static SOC_ENUM_SINGLE_DECL(sta32x_drc_ac_enum,
0213                 STA32X_CONFD, STA32X_CONFD_DRC_SHIFT,
0214                 sta32x_drc_ac);
0215 static SOC_ENUM_SINGLE_DECL(sta32x_auto_eq_enum,
0216                 STA32X_AUTO1, STA32X_AUTO1_AMEQ_SHIFT,
0217                 sta32x_auto_eq_mode);
0218 static SOC_ENUM_SINGLE_DECL(sta32x_auto_gc_enum,
0219                 STA32X_AUTO1, STA32X_AUTO1_AMGC_SHIFT,
0220                 sta32x_auto_gc_mode);
0221 static SOC_ENUM_SINGLE_DECL(sta32x_auto_xo_enum,
0222                 STA32X_AUTO2, STA32X_AUTO2_XO_SHIFT,
0223                 sta32x_auto_xo_mode);
0224 static SOC_ENUM_SINGLE_DECL(sta32x_preset_eq_enum,
0225                 STA32X_AUTO3, STA32X_AUTO3_PEQ_SHIFT,
0226                 sta32x_preset_eq_mode);
0227 static SOC_ENUM_SINGLE_DECL(sta32x_limiter_ch1_enum,
0228                 STA32X_C1CFG, STA32X_CxCFG_LS_SHIFT,
0229                 sta32x_limiter_select);
0230 static SOC_ENUM_SINGLE_DECL(sta32x_limiter_ch2_enum,
0231                 STA32X_C2CFG, STA32X_CxCFG_LS_SHIFT,
0232                 sta32x_limiter_select);
0233 static SOC_ENUM_SINGLE_DECL(sta32x_limiter_ch3_enum,
0234                 STA32X_C3CFG, STA32X_CxCFG_LS_SHIFT,
0235                 sta32x_limiter_select);
0236 static SOC_ENUM_SINGLE_DECL(sta32x_limiter1_attack_rate_enum,
0237                 STA32X_L1AR, STA32X_LxA_SHIFT,
0238                 sta32x_limiter_attack_rate);
0239 static SOC_ENUM_SINGLE_DECL(sta32x_limiter2_attack_rate_enum,
0240                 STA32X_L2AR, STA32X_LxA_SHIFT,
0241                 sta32x_limiter_attack_rate);
0242 static SOC_ENUM_SINGLE_DECL(sta32x_limiter1_release_rate_enum,
0243                 STA32X_L1AR, STA32X_LxR_SHIFT,
0244                 sta32x_limiter_release_rate);
0245 static SOC_ENUM_SINGLE_DECL(sta32x_limiter2_release_rate_enum,
0246                 STA32X_L2AR, STA32X_LxR_SHIFT,
0247                 sta32x_limiter_release_rate);
0248 
0249 /* byte array controls for setting biquad, mixer, scaling coefficients;
0250  * for biquads all five coefficients need to be set in one go,
0251  * mixer and pre/postscale coefs can be set individually;
0252  * each coef is 24bit, the bytes are ordered in the same way
0253  * as given in the STA32x data sheet (big endian; b1, b2, a1, a2, b0)
0254  */
0255 
0256 static int sta32x_coefficient_info(struct snd_kcontrol *kcontrol,
0257                    struct snd_ctl_elem_info *uinfo)
0258 {
0259     int numcoef = kcontrol->private_value >> 16;
0260     uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
0261     uinfo->count = 3 * numcoef;
0262     return 0;
0263 }
0264 
0265 static int sta32x_coefficient_get(struct snd_kcontrol *kcontrol,
0266                   struct snd_ctl_elem_value *ucontrol)
0267 {
0268     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0269     struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
0270     int numcoef = kcontrol->private_value >> 16;
0271     int index = kcontrol->private_value & 0xffff;
0272     unsigned int cfud, val;
0273     int i, ret = 0;
0274 
0275     mutex_lock(&sta32x->coeff_lock);
0276 
0277     /* preserve reserved bits in STA32X_CFUD */
0278     regmap_read(sta32x->regmap, STA32X_CFUD, &cfud);
0279     cfud &= 0xf0;
0280     /*
0281      * chip documentation does not say if the bits are self clearing,
0282      * so do it explicitly
0283      */
0284     regmap_write(sta32x->regmap, STA32X_CFUD, cfud);
0285 
0286     regmap_write(sta32x->regmap, STA32X_CFADDR2, index);
0287     if (numcoef == 1) {
0288         regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x04);
0289     } else if (numcoef == 5) {
0290         regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x08);
0291     } else {
0292         ret = -EINVAL;
0293         goto exit_unlock;
0294     }
0295 
0296     for (i = 0; i < 3 * numcoef; i++) {
0297         regmap_read(sta32x->regmap, STA32X_B1CF1 + i, &val);
0298         ucontrol->value.bytes.data[i] = val;
0299     }
0300 
0301 exit_unlock:
0302     mutex_unlock(&sta32x->coeff_lock);
0303 
0304     return ret;
0305 }
0306 
0307 static int sta32x_coefficient_put(struct snd_kcontrol *kcontrol,
0308                   struct snd_ctl_elem_value *ucontrol)
0309 {
0310     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0311     struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
0312     int numcoef = kcontrol->private_value >> 16;
0313     int index = kcontrol->private_value & 0xffff;
0314     unsigned int cfud;
0315     int i;
0316 
0317     /* preserve reserved bits in STA32X_CFUD */
0318     regmap_read(sta32x->regmap, STA32X_CFUD, &cfud);
0319     cfud &= 0xf0;
0320     /*
0321      * chip documentation does not say if the bits are self clearing,
0322      * so do it explicitly
0323      */
0324     regmap_write(sta32x->regmap, STA32X_CFUD, cfud);
0325 
0326     regmap_write(sta32x->regmap, STA32X_CFADDR2, index);
0327     for (i = 0; i < numcoef && (index + i < STA32X_COEF_COUNT); i++)
0328         sta32x->coef_shadow[index + i] =
0329               (ucontrol->value.bytes.data[3 * i] << 16)
0330             | (ucontrol->value.bytes.data[3 * i + 1] << 8)
0331             | (ucontrol->value.bytes.data[3 * i + 2]);
0332     for (i = 0; i < 3 * numcoef; i++)
0333         regmap_write(sta32x->regmap, STA32X_B1CF1 + i,
0334                  ucontrol->value.bytes.data[i]);
0335     if (numcoef == 1)
0336         regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x01);
0337     else if (numcoef == 5)
0338         regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x02);
0339     else
0340         return -EINVAL;
0341 
0342     return 0;
0343 }
0344 
0345 static int sta32x_sync_coef_shadow(struct snd_soc_component *component)
0346 {
0347     struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
0348     unsigned int cfud;
0349     int i;
0350 
0351     /* preserve reserved bits in STA32X_CFUD */
0352     regmap_read(sta32x->regmap, STA32X_CFUD, &cfud);
0353     cfud &= 0xf0;
0354 
0355     for (i = 0; i < STA32X_COEF_COUNT; i++) {
0356         regmap_write(sta32x->regmap, STA32X_CFADDR2, i);
0357         regmap_write(sta32x->regmap, STA32X_B1CF1,
0358                  (sta32x->coef_shadow[i] >> 16) & 0xff);
0359         regmap_write(sta32x->regmap, STA32X_B1CF2,
0360                  (sta32x->coef_shadow[i] >> 8) & 0xff);
0361         regmap_write(sta32x->regmap, STA32X_B1CF3,
0362                  (sta32x->coef_shadow[i]) & 0xff);
0363         /*
0364          * chip documentation does not say if the bits are
0365          * self-clearing, so do it explicitly
0366          */
0367         regmap_write(sta32x->regmap, STA32X_CFUD, cfud);
0368         regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x01);
0369     }
0370     return 0;
0371 }
0372 
0373 static int sta32x_cache_sync(struct snd_soc_component *component)
0374 {
0375     struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
0376     unsigned int mute;
0377     int rc;
0378 
0379     /* mute during register sync */
0380     regmap_read(sta32x->regmap, STA32X_MMUTE, &mute);
0381     regmap_write(sta32x->regmap, STA32X_MMUTE, mute | STA32X_MMUTE_MMUTE);
0382     sta32x_sync_coef_shadow(component);
0383     rc = regcache_sync(sta32x->regmap);
0384     regmap_write(sta32x->regmap, STA32X_MMUTE, mute);
0385     return rc;
0386 }
0387 
0388 /* work around ESD issue where sta32x resets and loses all configuration */
0389 static void sta32x_watchdog(struct work_struct *work)
0390 {
0391     struct sta32x_priv *sta32x = container_of(work, struct sta32x_priv,
0392                           watchdog_work.work);
0393     struct snd_soc_component *component = sta32x->component;
0394     unsigned int confa, confa_cached;
0395 
0396     /* check if sta32x has reset itself */
0397     confa_cached = snd_soc_component_read(component, STA32X_CONFA);
0398     regcache_cache_bypass(sta32x->regmap, true);
0399     confa = snd_soc_component_read(component, STA32X_CONFA);
0400     regcache_cache_bypass(sta32x->regmap, false);
0401     if (confa != confa_cached) {
0402         regcache_mark_dirty(sta32x->regmap);
0403         sta32x_cache_sync(component);
0404     }
0405 
0406     if (!sta32x->shutdown)
0407         queue_delayed_work(system_power_efficient_wq,
0408                    &sta32x->watchdog_work,
0409                    round_jiffies_relative(HZ));
0410 }
0411 
0412 static void sta32x_watchdog_start(struct sta32x_priv *sta32x)
0413 {
0414     if (sta32x->pdata->needs_esd_watchdog) {
0415         sta32x->shutdown = 0;
0416         queue_delayed_work(system_power_efficient_wq,
0417                    &sta32x->watchdog_work,
0418                    round_jiffies_relative(HZ));
0419     }
0420 }
0421 
0422 static void sta32x_watchdog_stop(struct sta32x_priv *sta32x)
0423 {
0424     if (sta32x->pdata->needs_esd_watchdog) {
0425         sta32x->shutdown = 1;
0426         cancel_delayed_work_sync(&sta32x->watchdog_work);
0427     }
0428 }
0429 
0430 #define SINGLE_COEF(xname, index) \
0431 {   .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
0432     .info = sta32x_coefficient_info, \
0433     .get = sta32x_coefficient_get,\
0434     .put = sta32x_coefficient_put, \
0435     .private_value = index | (1 << 16) }
0436 
0437 #define BIQUAD_COEFS(xname, index) \
0438 {   .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
0439     .info = sta32x_coefficient_info, \
0440     .get = sta32x_coefficient_get,\
0441     .put = sta32x_coefficient_put, \
0442     .private_value = index | (5 << 16) }
0443 
0444 static const struct snd_kcontrol_new sta32x_snd_controls[] = {
0445 SOC_SINGLE_TLV("Master Volume", STA32X_MVOL, 0, 0xff, 1, mvol_tlv),
0446 SOC_SINGLE("Master Switch", STA32X_MMUTE, 0, 1, 1),
0447 SOC_SINGLE("Ch1 Switch", STA32X_MMUTE, 1, 1, 1),
0448 SOC_SINGLE("Ch2 Switch", STA32X_MMUTE, 2, 1, 1),
0449 SOC_SINGLE("Ch3 Switch", STA32X_MMUTE, 3, 1, 1),
0450 SOC_SINGLE_TLV("Ch1 Volume", STA32X_C1VOL, 0, 0xff, 1, chvol_tlv),
0451 SOC_SINGLE_TLV("Ch2 Volume", STA32X_C2VOL, 0, 0xff, 1, chvol_tlv),
0452 SOC_SINGLE_TLV("Ch3 Volume", STA32X_C3VOL, 0, 0xff, 1, chvol_tlv),
0453 SOC_SINGLE("De-emphasis Filter Switch", STA32X_CONFD, STA32X_CONFD_DEMP_SHIFT, 1, 0),
0454 SOC_ENUM("Compressor/Limiter Switch", sta32x_drc_ac_enum),
0455 SOC_SINGLE("Miami Mode Switch", STA32X_CONFD, STA32X_CONFD_MME_SHIFT, 1, 0),
0456 SOC_SINGLE("Zero Cross Switch", STA32X_CONFE, STA32X_CONFE_ZCE_SHIFT, 1, 0),
0457 SOC_SINGLE("Soft Ramp Switch", STA32X_CONFE, STA32X_CONFE_SVE_SHIFT, 1, 0),
0458 SOC_SINGLE("Auto-Mute Switch", STA32X_CONFF, STA32X_CONFF_IDE_SHIFT, 1, 0),
0459 SOC_ENUM("Automode EQ", sta32x_auto_eq_enum),
0460 SOC_ENUM("Automode GC", sta32x_auto_gc_enum),
0461 SOC_ENUM("Automode XO", sta32x_auto_xo_enum),
0462 SOC_ENUM("Preset EQ", sta32x_preset_eq_enum),
0463 SOC_SINGLE("Ch1 Tone Control Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_TCB_SHIFT, 1, 0),
0464 SOC_SINGLE("Ch2 Tone Control Bypass Switch", STA32X_C2CFG, STA32X_CxCFG_TCB_SHIFT, 1, 0),
0465 SOC_SINGLE("Ch1 EQ Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_EQBP_SHIFT, 1, 0),
0466 SOC_SINGLE("Ch2 EQ Bypass Switch", STA32X_C2CFG, STA32X_CxCFG_EQBP_SHIFT, 1, 0),
0467 SOC_SINGLE("Ch1 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0),
0468 SOC_SINGLE("Ch2 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0),
0469 SOC_SINGLE("Ch3 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0),
0470 SOC_ENUM("Ch1 Limiter Select", sta32x_limiter_ch1_enum),
0471 SOC_ENUM("Ch2 Limiter Select", sta32x_limiter_ch2_enum),
0472 SOC_ENUM("Ch3 Limiter Select", sta32x_limiter_ch3_enum),
0473 SOC_SINGLE_TLV("Bass Tone Control", STA32X_TONE, STA32X_TONE_BTC_SHIFT, 15, 0, tone_tlv),
0474 SOC_SINGLE_TLV("Treble Tone Control", STA32X_TONE, STA32X_TONE_TTC_SHIFT, 15, 0, tone_tlv),
0475 SOC_ENUM("Limiter1 Attack Rate (dB/ms)", sta32x_limiter1_attack_rate_enum),
0476 SOC_ENUM("Limiter2 Attack Rate (dB/ms)", sta32x_limiter2_attack_rate_enum),
0477 SOC_ENUM("Limiter1 Release Rate (dB/ms)", sta32x_limiter1_release_rate_enum),
0478 SOC_ENUM("Limiter2 Release Rate (dB/ms)", sta32x_limiter2_release_rate_enum),
0479 
0480 /* depending on mode, the attack/release thresholds have
0481  * two different enum definitions; provide both
0482  */
0483 SOC_SINGLE_TLV("Limiter1 Attack Threshold (AC Mode)", STA32X_L1ATRT, STA32X_LxA_SHIFT,
0484            16, 0, sta32x_limiter_ac_attack_tlv),
0485 SOC_SINGLE_TLV("Limiter2 Attack Threshold (AC Mode)", STA32X_L2ATRT, STA32X_LxA_SHIFT,
0486            16, 0, sta32x_limiter_ac_attack_tlv),
0487 SOC_SINGLE_TLV("Limiter1 Release Threshold (AC Mode)", STA32X_L1ATRT, STA32X_LxR_SHIFT,
0488            16, 0, sta32x_limiter_ac_release_tlv),
0489 SOC_SINGLE_TLV("Limiter2 Release Threshold (AC Mode)", STA32X_L2ATRT, STA32X_LxR_SHIFT,
0490            16, 0, sta32x_limiter_ac_release_tlv),
0491 SOC_SINGLE_TLV("Limiter1 Attack Threshold (DRC Mode)", STA32X_L1ATRT, STA32X_LxA_SHIFT,
0492            16, 0, sta32x_limiter_drc_attack_tlv),
0493 SOC_SINGLE_TLV("Limiter2 Attack Threshold (DRC Mode)", STA32X_L2ATRT, STA32X_LxA_SHIFT,
0494            16, 0, sta32x_limiter_drc_attack_tlv),
0495 SOC_SINGLE_TLV("Limiter1 Release Threshold (DRC Mode)", STA32X_L1ATRT, STA32X_LxR_SHIFT,
0496            16, 0, sta32x_limiter_drc_release_tlv),
0497 SOC_SINGLE_TLV("Limiter2 Release Threshold (DRC Mode)", STA32X_L2ATRT, STA32X_LxR_SHIFT,
0498            16, 0, sta32x_limiter_drc_release_tlv),
0499 
0500 BIQUAD_COEFS("Ch1 - Biquad 1", 0),
0501 BIQUAD_COEFS("Ch1 - Biquad 2", 5),
0502 BIQUAD_COEFS("Ch1 - Biquad 3", 10),
0503 BIQUAD_COEFS("Ch1 - Biquad 4", 15),
0504 BIQUAD_COEFS("Ch2 - Biquad 1", 20),
0505 BIQUAD_COEFS("Ch2 - Biquad 2", 25),
0506 BIQUAD_COEFS("Ch2 - Biquad 3", 30),
0507 BIQUAD_COEFS("Ch2 - Biquad 4", 35),
0508 BIQUAD_COEFS("High-pass", 40),
0509 BIQUAD_COEFS("Low-pass", 45),
0510 SINGLE_COEF("Ch1 - Prescale", 50),
0511 SINGLE_COEF("Ch2 - Prescale", 51),
0512 SINGLE_COEF("Ch1 - Postscale", 52),
0513 SINGLE_COEF("Ch2 - Postscale", 53),
0514 SINGLE_COEF("Ch3 - Postscale", 54),
0515 SINGLE_COEF("Thermal warning - Postscale", 55),
0516 SINGLE_COEF("Ch1 - Mix 1", 56),
0517 SINGLE_COEF("Ch1 - Mix 2", 57),
0518 SINGLE_COEF("Ch2 - Mix 1", 58),
0519 SINGLE_COEF("Ch2 - Mix 2", 59),
0520 SINGLE_COEF("Ch3 - Mix 1", 60),
0521 SINGLE_COEF("Ch3 - Mix 2", 61),
0522 };
0523 
0524 static const struct snd_soc_dapm_widget sta32x_dapm_widgets[] = {
0525 SND_SOC_DAPM_DAC("DAC", "Playback", SND_SOC_NOPM, 0, 0),
0526 SND_SOC_DAPM_OUTPUT("LEFT"),
0527 SND_SOC_DAPM_OUTPUT("RIGHT"),
0528 SND_SOC_DAPM_OUTPUT("SUB"),
0529 };
0530 
0531 static const struct snd_soc_dapm_route sta32x_dapm_routes[] = {
0532     { "LEFT", NULL, "DAC" },
0533     { "RIGHT", NULL, "DAC" },
0534     { "SUB", NULL, "DAC" },
0535 };
0536 
0537 /* MCLK interpolation ratio per fs */
0538 static struct {
0539     int fs;
0540     int ir;
0541 } interpolation_ratios[] = {
0542     { 32000, 0 },
0543     { 44100, 0 },
0544     { 48000, 0 },
0545     { 88200, 1 },
0546     { 96000, 1 },
0547     { 176400, 2 },
0548     { 192000, 2 },
0549 };
0550 
0551 /* MCLK to fs clock ratios */
0552 static int mcs_ratio_table[3][7] = {
0553     { 768, 512, 384, 256, 128, 576, 0 },
0554     { 384, 256, 192, 128,  64,   0 },
0555     { 384, 256, 192, 128,  64,   0 },
0556 };
0557 
0558 /**
0559  * sta32x_set_dai_sysclk - configure MCLK
0560  * @codec_dai: the codec DAI
0561  * @clk_id: the clock ID (ignored)
0562  * @freq: the MCLK input frequency
0563  * @dir: the clock direction (ignored)
0564  *
0565  * The value of MCLK is used to determine which sample rates are supported
0566  * by the STA32X, based on the mclk_ratios table.
0567  *
0568  * This function must be called by the machine driver's 'startup' function,
0569  * otherwise the list of supported sample rates will not be available in
0570  * time for ALSA.
0571  *
0572  * For setups with variable MCLKs, pass 0 as 'freq' argument. This will cause
0573  * theoretically possible sample rates to be enabled. Call it again with a
0574  * proper value set one the external clock is set (most probably you would do
0575  * that from a machine's driver 'hw_param' hook.
0576  */
0577 static int sta32x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
0578         int clk_id, unsigned int freq, int dir)
0579 {
0580     struct snd_soc_component *component = codec_dai->component;
0581     struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
0582 
0583     dev_dbg(component->dev, "mclk=%u\n", freq);
0584     sta32x->mclk = freq;
0585 
0586     return 0;
0587 }
0588 
0589 /**
0590  * sta32x_set_dai_fmt - configure the codec for the selected audio format
0591  * @codec_dai: the codec DAI
0592  * @fmt: a SND_SOC_DAIFMT_x value indicating the data format
0593  *
0594  * This function takes a bitmask of SND_SOC_DAIFMT_x bits and programs the
0595  * codec accordingly.
0596  */
0597 static int sta32x_set_dai_fmt(struct snd_soc_dai *codec_dai,
0598                   unsigned int fmt)
0599 {
0600     struct snd_soc_component *component = codec_dai->component;
0601     struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
0602     u8 confb = 0;
0603 
0604     switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0605     case SND_SOC_DAIFMT_CBC_CFC:
0606         break;
0607     default:
0608         return -EINVAL;
0609     }
0610 
0611     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0612     case SND_SOC_DAIFMT_I2S:
0613     case SND_SOC_DAIFMT_RIGHT_J:
0614     case SND_SOC_DAIFMT_LEFT_J:
0615         sta32x->format = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
0616         break;
0617     default:
0618         return -EINVAL;
0619     }
0620 
0621     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0622     case SND_SOC_DAIFMT_NB_NF:
0623         confb |= STA32X_CONFB_C2IM;
0624         break;
0625     case SND_SOC_DAIFMT_NB_IF:
0626         confb |= STA32X_CONFB_C1IM;
0627         break;
0628     default:
0629         return -EINVAL;
0630     }
0631 
0632     return regmap_update_bits(sta32x->regmap, STA32X_CONFB,
0633                   STA32X_CONFB_C1IM | STA32X_CONFB_C2IM, confb);
0634 }
0635 
0636 /**
0637  * sta32x_hw_params - program the STA32X with the given hardware parameters.
0638  * @substream: the audio stream
0639  * @params: the hardware parameters to set
0640  * @dai: the SOC DAI (ignored)
0641  *
0642  * This function programs the hardware with the values provided.
0643  * Specifically, the sample rate and the data format.
0644  */
0645 static int sta32x_hw_params(struct snd_pcm_substream *substream,
0646                 struct snd_pcm_hw_params *params,
0647                 struct snd_soc_dai *dai)
0648 {
0649     struct snd_soc_component *component = dai->component;
0650     struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
0651     int i, mcs = -EINVAL, ir = -EINVAL;
0652     unsigned int confa, confb;
0653     unsigned int rate, ratio;
0654     int ret;
0655 
0656     if (!sta32x->mclk) {
0657         dev_err(component->dev,
0658             "sta32x->mclk is unset. Unable to determine ratio\n");
0659         return -EIO;
0660     }
0661 
0662     rate = params_rate(params);
0663     ratio = sta32x->mclk / rate;
0664     dev_dbg(component->dev, "rate: %u, ratio: %u\n", rate, ratio);
0665 
0666     for (i = 0; i < ARRAY_SIZE(interpolation_ratios); i++) {
0667         if (interpolation_ratios[i].fs == rate) {
0668             ir = interpolation_ratios[i].ir;
0669             break;
0670         }
0671     }
0672 
0673     if (ir < 0) {
0674         dev_err(component->dev, "Unsupported samplerate: %u\n", rate);
0675         return -EINVAL;
0676     }
0677 
0678     for (i = 0; i < 6; i++) {
0679         if (mcs_ratio_table[ir][i] == ratio) {
0680             mcs = i;
0681             break;
0682         }
0683     }
0684 
0685     if (mcs < 0) {
0686         dev_err(component->dev, "Unresolvable ratio: %u\n", ratio);
0687         return -EINVAL;
0688     }
0689 
0690     confa = (ir << STA32X_CONFA_IR_SHIFT) |
0691         (mcs << STA32X_CONFA_MCS_SHIFT);
0692     confb = 0;
0693 
0694     switch (params_width(params)) {
0695     case 24:
0696         dev_dbg(component->dev, "24bit\n");
0697         fallthrough;
0698     case 32:
0699         dev_dbg(component->dev, "24bit or 32bit\n");
0700         switch (sta32x->format) {
0701         case SND_SOC_DAIFMT_I2S:
0702             confb |= 0x0;
0703             break;
0704         case SND_SOC_DAIFMT_LEFT_J:
0705             confb |= 0x1;
0706             break;
0707         case SND_SOC_DAIFMT_RIGHT_J:
0708             confb |= 0x2;
0709             break;
0710         }
0711 
0712         break;
0713     case 20:
0714         dev_dbg(component->dev, "20bit\n");
0715         switch (sta32x->format) {
0716         case SND_SOC_DAIFMT_I2S:
0717             confb |= 0x4;
0718             break;
0719         case SND_SOC_DAIFMT_LEFT_J:
0720             confb |= 0x5;
0721             break;
0722         case SND_SOC_DAIFMT_RIGHT_J:
0723             confb |= 0x6;
0724             break;
0725         }
0726 
0727         break;
0728     case 18:
0729         dev_dbg(component->dev, "18bit\n");
0730         switch (sta32x->format) {
0731         case SND_SOC_DAIFMT_I2S:
0732             confb |= 0x8;
0733             break;
0734         case SND_SOC_DAIFMT_LEFT_J:
0735             confb |= 0x9;
0736             break;
0737         case SND_SOC_DAIFMT_RIGHT_J:
0738             confb |= 0xa;
0739             break;
0740         }
0741 
0742         break;
0743     case 16:
0744         dev_dbg(component->dev, "16bit\n");
0745         switch (sta32x->format) {
0746         case SND_SOC_DAIFMT_I2S:
0747             confb |= 0x0;
0748             break;
0749         case SND_SOC_DAIFMT_LEFT_J:
0750             confb |= 0xd;
0751             break;
0752         case SND_SOC_DAIFMT_RIGHT_J:
0753             confb |= 0xe;
0754             break;
0755         }
0756 
0757         break;
0758     default:
0759         return -EINVAL;
0760     }
0761 
0762     ret = regmap_update_bits(sta32x->regmap, STA32X_CONFA,
0763                  STA32X_CONFA_MCS_MASK | STA32X_CONFA_IR_MASK,
0764                  confa);
0765     if (ret < 0)
0766         return ret;
0767 
0768     ret = regmap_update_bits(sta32x->regmap, STA32X_CONFB,
0769                  STA32X_CONFB_SAI_MASK | STA32X_CONFB_SAIFB,
0770                  confb);
0771     if (ret < 0)
0772         return ret;
0773 
0774     return 0;
0775 }
0776 
0777 static int sta32x_startup_sequence(struct sta32x_priv *sta32x)
0778 {
0779     if (sta32x->gpiod_nreset) {
0780         gpiod_set_value(sta32x->gpiod_nreset, 0);
0781         mdelay(1);
0782         gpiod_set_value(sta32x->gpiod_nreset, 1);
0783         mdelay(1);
0784     }
0785 
0786     return 0;
0787 }
0788 
0789 /**
0790  * sta32x_set_bias_level - DAPM callback
0791  * @component: the component device
0792  * @level: DAPM power level
0793  *
0794  * This is called by ALSA to put the component into low power mode
0795  * or to wake it up.  If the component is powered off completely
0796  * all registers must be restored after power on.
0797  */
0798 static int sta32x_set_bias_level(struct snd_soc_component *component,
0799                  enum snd_soc_bias_level level)
0800 {
0801     int ret;
0802     struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
0803 
0804     dev_dbg(component->dev, "level = %d\n", level);
0805     switch (level) {
0806     case SND_SOC_BIAS_ON:
0807         break;
0808 
0809     case SND_SOC_BIAS_PREPARE:
0810         /* Full power on */
0811         regmap_update_bits(sta32x->regmap, STA32X_CONFF,
0812                     STA32X_CONFF_PWDN | STA32X_CONFF_EAPD,
0813                     STA32X_CONFF_PWDN | STA32X_CONFF_EAPD);
0814         break;
0815 
0816     case SND_SOC_BIAS_STANDBY:
0817         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
0818             ret = regulator_bulk_enable(ARRAY_SIZE(sta32x->supplies),
0819                             sta32x->supplies);
0820             if (ret != 0) {
0821                 dev_err(component->dev,
0822                     "Failed to enable supplies: %d\n", ret);
0823                 return ret;
0824             }
0825 
0826             sta32x_startup_sequence(sta32x);
0827             sta32x_cache_sync(component);
0828             sta32x_watchdog_start(sta32x);
0829         }
0830 
0831         /* Power down */
0832         regmap_update_bits(sta32x->regmap, STA32X_CONFF,
0833                    STA32X_CONFF_PWDN | STA32X_CONFF_EAPD,
0834                    0);
0835 
0836         break;
0837 
0838     case SND_SOC_BIAS_OFF:
0839         /* The chip runs through the power down sequence for us. */
0840         regmap_update_bits(sta32x->regmap, STA32X_CONFF,
0841                    STA32X_CONFF_PWDN | STA32X_CONFF_EAPD, 0);
0842         msleep(300);
0843         sta32x_watchdog_stop(sta32x);
0844 
0845         gpiod_set_value(sta32x->gpiod_nreset, 0);
0846 
0847         regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies),
0848                        sta32x->supplies);
0849         break;
0850     }
0851     return 0;
0852 }
0853 
0854 static const struct snd_soc_dai_ops sta32x_dai_ops = {
0855     .hw_params  = sta32x_hw_params,
0856     .set_sysclk = sta32x_set_dai_sysclk,
0857     .set_fmt    = sta32x_set_dai_fmt,
0858 };
0859 
0860 static struct snd_soc_dai_driver sta32x_dai = {
0861     .name = "sta32x-hifi",
0862     .playback = {
0863         .stream_name = "Playback",
0864         .channels_min = 2,
0865         .channels_max = 2,
0866         .rates = STA32X_RATES,
0867         .formats = STA32X_FORMATS,
0868     },
0869     .ops = &sta32x_dai_ops,
0870 };
0871 
0872 static int sta32x_probe(struct snd_soc_component *component)
0873 {
0874     struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
0875     struct sta32x_platform_data *pdata = sta32x->pdata;
0876     int i, ret = 0, thermal = 0;
0877 
0878     sta32x->component = component;
0879 
0880     if (sta32x->xti_clk) {
0881         ret = clk_prepare_enable(sta32x->xti_clk);
0882         if (ret != 0) {
0883             dev_err(component->dev,
0884                 "Failed to enable clock: %d\n", ret);
0885             return ret;
0886         }
0887     }
0888 
0889     ret = regulator_bulk_enable(ARRAY_SIZE(sta32x->supplies),
0890                     sta32x->supplies);
0891     if (ret != 0) {
0892         dev_err(component->dev, "Failed to enable supplies: %d\n", ret);
0893         goto err_clk_disable_unprepare;
0894     }
0895 
0896     ret = sta32x_startup_sequence(sta32x);
0897     if (ret < 0) {
0898         dev_err(component->dev, "Failed to startup device\n");
0899         goto err_regulator_bulk_disable;
0900     }
0901 
0902     /* CONFA */
0903     if (!pdata->thermal_warning_recovery)
0904         thermal |= STA32X_CONFA_TWAB;
0905     if (!pdata->thermal_warning_adjustment)
0906         thermal |= STA32X_CONFA_TWRB;
0907     if (!pdata->fault_detect_recovery)
0908         thermal |= STA32X_CONFA_FDRB;
0909     regmap_update_bits(sta32x->regmap, STA32X_CONFA,
0910                STA32X_CONFA_TWAB | STA32X_CONFA_TWRB |
0911                STA32X_CONFA_FDRB,
0912                thermal);
0913 
0914     /* CONFC */
0915     regmap_update_bits(sta32x->regmap, STA32X_CONFC,
0916                STA32X_CONFC_CSZ_MASK,
0917                pdata->drop_compensation_ns
0918                 << STA32X_CONFC_CSZ_SHIFT);
0919 
0920     /* CONFE */
0921     regmap_update_bits(sta32x->regmap, STA32X_CONFE,
0922                STA32X_CONFE_MPCV,
0923                pdata->max_power_use_mpcc ?
0924                 STA32X_CONFE_MPCV : 0);
0925     regmap_update_bits(sta32x->regmap, STA32X_CONFE,
0926                STA32X_CONFE_MPC,
0927                pdata->max_power_correction ?
0928                 STA32X_CONFE_MPC : 0);
0929     regmap_update_bits(sta32x->regmap, STA32X_CONFE,
0930                STA32X_CONFE_AME,
0931                pdata->am_reduction_mode ?
0932                 STA32X_CONFE_AME : 0);
0933     regmap_update_bits(sta32x->regmap, STA32X_CONFE,
0934                STA32X_CONFE_PWMS,
0935                pdata->odd_pwm_speed_mode ?
0936                 STA32X_CONFE_PWMS : 0);
0937 
0938     /*  CONFF */
0939     regmap_update_bits(sta32x->regmap, STA32X_CONFF,
0940                STA32X_CONFF_IDE,
0941                pdata->invalid_input_detect_mute ?
0942                 STA32X_CONFF_IDE : 0);
0943 
0944     /* select output configuration  */
0945     regmap_update_bits(sta32x->regmap, STA32X_CONFF,
0946                STA32X_CONFF_OCFG_MASK,
0947                pdata->output_conf
0948                 << STA32X_CONFF_OCFG_SHIFT);
0949 
0950     /* channel to output mapping */
0951     regmap_update_bits(sta32x->regmap, STA32X_C1CFG,
0952                STA32X_CxCFG_OM_MASK,
0953                pdata->ch1_output_mapping
0954                 << STA32X_CxCFG_OM_SHIFT);
0955     regmap_update_bits(sta32x->regmap, STA32X_C2CFG,
0956                STA32X_CxCFG_OM_MASK,
0957                pdata->ch2_output_mapping
0958                 << STA32X_CxCFG_OM_SHIFT);
0959     regmap_update_bits(sta32x->regmap, STA32X_C3CFG,
0960                STA32X_CxCFG_OM_MASK,
0961                pdata->ch3_output_mapping
0962                 << STA32X_CxCFG_OM_SHIFT);
0963 
0964     /* initialize coefficient shadow RAM with reset values */
0965     for (i = 4; i <= 49; i += 5)
0966         sta32x->coef_shadow[i] = 0x400000;
0967     for (i = 50; i <= 54; i++)
0968         sta32x->coef_shadow[i] = 0x7fffff;
0969     sta32x->coef_shadow[55] = 0x5a9df7;
0970     sta32x->coef_shadow[56] = 0x7fffff;
0971     sta32x->coef_shadow[59] = 0x7fffff;
0972     sta32x->coef_shadow[60] = 0x400000;
0973     sta32x->coef_shadow[61] = 0x400000;
0974 
0975     if (sta32x->pdata->needs_esd_watchdog)
0976         INIT_DELAYED_WORK(&sta32x->watchdog_work, sta32x_watchdog);
0977 
0978     snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
0979     /* Bias level configuration will have done an extra enable */
0980     regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies);
0981 
0982     return 0;
0983 
0984 err_regulator_bulk_disable:
0985     regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies);
0986 err_clk_disable_unprepare:
0987     if (sta32x->xti_clk)
0988         clk_disable_unprepare(sta32x->xti_clk);
0989     return ret;
0990 }
0991 
0992 static void sta32x_remove(struct snd_soc_component *component)
0993 {
0994     struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
0995 
0996     sta32x_watchdog_stop(sta32x);
0997     regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies);
0998 
0999     if (sta32x->xti_clk)
1000         clk_disable_unprepare(sta32x->xti_clk);
1001 }
1002 
1003 static const struct snd_soc_component_driver sta32x_component = {
1004     .probe          = sta32x_probe,
1005     .remove         = sta32x_remove,
1006     .set_bias_level     = sta32x_set_bias_level,
1007     .controls       = sta32x_snd_controls,
1008     .num_controls       = ARRAY_SIZE(sta32x_snd_controls),
1009     .dapm_widgets       = sta32x_dapm_widgets,
1010     .num_dapm_widgets   = ARRAY_SIZE(sta32x_dapm_widgets),
1011     .dapm_routes        = sta32x_dapm_routes,
1012     .num_dapm_routes    = ARRAY_SIZE(sta32x_dapm_routes),
1013     .suspend_bias_off   = 1,
1014     .idle_bias_on       = 1,
1015     .use_pmdown_time    = 1,
1016     .endianness     = 1,
1017 };
1018 
1019 static const struct regmap_config sta32x_regmap = {
1020     .reg_bits =     8,
1021     .val_bits =     8,
1022     .max_register =     STA32X_FDRC2,
1023     .reg_defaults =     sta32x_regs,
1024     .num_reg_defaults = ARRAY_SIZE(sta32x_regs),
1025     .cache_type =       REGCACHE_RBTREE,
1026     .wr_table =     &sta32x_write_regs,
1027     .rd_table =     &sta32x_read_regs,
1028     .volatile_table =   &sta32x_volatile_regs,
1029 };
1030 
1031 #ifdef CONFIG_OF
1032 static const struct of_device_id st32x_dt_ids[] = {
1033     { .compatible = "st,sta32x", },
1034     { }
1035 };
1036 MODULE_DEVICE_TABLE(of, st32x_dt_ids);
1037 
1038 static int sta32x_probe_dt(struct device *dev, struct sta32x_priv *sta32x)
1039 {
1040     struct device_node *np = dev->of_node;
1041     struct sta32x_platform_data *pdata;
1042     u16 tmp;
1043 
1044     pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1045     if (!pdata)
1046         return -ENOMEM;
1047 
1048     of_property_read_u8(np, "st,output-conf",
1049                 &pdata->output_conf);
1050     of_property_read_u8(np, "st,ch1-output-mapping",
1051                 &pdata->ch1_output_mapping);
1052     of_property_read_u8(np, "st,ch2-output-mapping",
1053                 &pdata->ch2_output_mapping);
1054     of_property_read_u8(np, "st,ch3-output-mapping",
1055                 &pdata->ch3_output_mapping);
1056 
1057     if (of_get_property(np, "st,fault-detect-recovery", NULL))
1058         pdata->fault_detect_recovery = 1;
1059     if (of_get_property(np, "st,thermal-warning-recovery", NULL))
1060         pdata->thermal_warning_recovery = 1;
1061     if (of_get_property(np, "st,thermal-warning-adjustment", NULL))
1062         pdata->thermal_warning_adjustment = 1;
1063     if (of_get_property(np, "st,needs_esd_watchdog", NULL))
1064         pdata->needs_esd_watchdog = 1;
1065 
1066     tmp = 140;
1067     of_property_read_u16(np, "st,drop-compensation-ns", &tmp);
1068     pdata->drop_compensation_ns = clamp_t(u16, tmp, 0, 300) / 20;
1069 
1070     /* CONFE */
1071     if (of_get_property(np, "st,max-power-use-mpcc", NULL))
1072         pdata->max_power_use_mpcc = 1;
1073 
1074     if (of_get_property(np, "st,max-power-correction", NULL))
1075         pdata->max_power_correction = 1;
1076 
1077     if (of_get_property(np, "st,am-reduction-mode", NULL))
1078         pdata->am_reduction_mode = 1;
1079 
1080     if (of_get_property(np, "st,odd-pwm-speed-mode", NULL))
1081         pdata->odd_pwm_speed_mode = 1;
1082 
1083     /* CONFF */
1084     if (of_get_property(np, "st,invalid-input-detect-mute", NULL))
1085         pdata->invalid_input_detect_mute = 1;
1086 
1087     sta32x->pdata = pdata;
1088 
1089     return 0;
1090 }
1091 #endif
1092 
1093 static int sta32x_i2c_probe(struct i2c_client *i2c)
1094 {
1095     struct device *dev = &i2c->dev;
1096     struct sta32x_priv *sta32x;
1097     int ret, i;
1098 
1099     sta32x = devm_kzalloc(&i2c->dev, sizeof(struct sta32x_priv),
1100                   GFP_KERNEL);
1101     if (!sta32x)
1102         return -ENOMEM;
1103 
1104     mutex_init(&sta32x->coeff_lock);
1105     sta32x->pdata = dev_get_platdata(dev);
1106 
1107 #ifdef CONFIG_OF
1108     if (dev->of_node) {
1109         ret = sta32x_probe_dt(dev, sta32x);
1110         if (ret < 0)
1111             return ret;
1112     }
1113 #endif
1114 
1115     /* Clock */
1116     sta32x->xti_clk = devm_clk_get(dev, "xti");
1117     if (IS_ERR(sta32x->xti_clk)) {
1118         ret = PTR_ERR(sta32x->xti_clk);
1119 
1120         if (ret == -EPROBE_DEFER)
1121             return ret;
1122 
1123         sta32x->xti_clk = NULL;
1124     }
1125 
1126     /* GPIOs */
1127     sta32x->gpiod_nreset = devm_gpiod_get_optional(dev, "reset",
1128                                GPIOD_OUT_LOW);
1129     if (IS_ERR(sta32x->gpiod_nreset))
1130         return PTR_ERR(sta32x->gpiod_nreset);
1131 
1132     /* regulators */
1133     for (i = 0; i < ARRAY_SIZE(sta32x->supplies); i++)
1134         sta32x->supplies[i].supply = sta32x_supply_names[i];
1135 
1136     ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(sta32x->supplies),
1137                       sta32x->supplies);
1138     if (ret != 0) {
1139         dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
1140         return ret;
1141     }
1142 
1143     sta32x->regmap = devm_regmap_init_i2c(i2c, &sta32x_regmap);
1144     if (IS_ERR(sta32x->regmap)) {
1145         ret = PTR_ERR(sta32x->regmap);
1146         dev_err(dev, "Failed to init regmap: %d\n", ret);
1147         return ret;
1148     }
1149 
1150     i2c_set_clientdata(i2c, sta32x);
1151 
1152     ret = devm_snd_soc_register_component(dev, &sta32x_component,
1153                           &sta32x_dai, 1);
1154     if (ret < 0)
1155         dev_err(dev, "Failed to register component (%d)\n", ret);
1156 
1157     return ret;
1158 }
1159 
1160 static const struct i2c_device_id sta32x_i2c_id[] = {
1161     { "sta326", 0 },
1162     { "sta328", 0 },
1163     { "sta329", 0 },
1164     { }
1165 };
1166 MODULE_DEVICE_TABLE(i2c, sta32x_i2c_id);
1167 
1168 static struct i2c_driver sta32x_i2c_driver = {
1169     .driver = {
1170         .name = "sta32x",
1171         .of_match_table = of_match_ptr(st32x_dt_ids),
1172     },
1173     .probe_new = sta32x_i2c_probe,
1174     .id_table = sta32x_i2c_id,
1175 };
1176 
1177 module_i2c_driver(sta32x_i2c_driver);
1178 
1179 MODULE_DESCRIPTION("ASoC STA32X driver");
1180 MODULE_AUTHOR("Johannes Stezenbach <js@sig21.net>");
1181 MODULE_LICENSE("GPL");
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