soc/codecs/ssm2602.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * File:         sound/soc/codecs/ssm2602.h
0004  * Author:       Cliff Cai <Cliff.Cai@analog.com>
0005  *
0006  * Created:      Tue June 06 2008
0007  *
0008  * Modified:
0009  *               Copyright 2008 Analog Devices Inc.
0010  *
0011  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
0012  */
0013
0014 #ifndef _SSM2602_H
0015 #define _SSM2602_H
0016
0017 #include <linux/regmap.h>
0018
0019 struct device;
0020
0021 enum ssm2602_type {
0022     SSM2602,
0023     SSM2604,
0024 };
0025
0026 extern const struct regmap_config ssm2602_regmap_config;
0027
0028 int ssm2602_probe(struct device *dev, enum ssm2602_type type,
0029     struct regmap *regmap);
0030
0031 /* SSM2602 Codec Register definitions */
0032
0033 #define SSM2602_LINVOL   0x00
0034 #define SSM2602_RINVOL   0x01
0035 #define SSM2602_LOUT1V   0x02
0036 #define SSM2602_ROUT1V   0x03
0037 #define SSM2602_APANA    0x04
0038 #define SSM2602_APDIGI   0x05
0039 #define SSM2602_PWR      0x06
0040 #define SSM2602_IFACE    0x07
0041 #define SSM2602_SRATE    0x08
0042 #define SSM2602_ACTIVE   0x09
0043 #define SSM2602_RESET    0x0f
0044
0045 /*SSM2602 Codec Register Field definitions
0046  *(Mask value to extract the corresponding Register field)
0047  */
0048
0049 /*Left ADC Volume Control (SSM2602_REG_LEFT_ADC_VOL)*/
0050 #define     LINVOL_LIN_VOL                0x01F   /* Left Channel PGA Volume control                      */
0051 #define     LINVOL_LIN_ENABLE_MUTE        0x080   /* Left Channel Input Mute                              */
0052 #define     LINVOL_LRIN_BOTH              0x100   /* Left Channel Line Input Volume update                */
0053
0054 /*Right ADC Volume Control (SSM2602_REG_RIGHT_ADC_VOL)*/
0055 #define     RINVOL_RIN_VOL                0x01F   /* Right Channel PGA Volume control                     */
0056 #define     RINVOL_RIN_ENABLE_MUTE        0x080   /* Right Channel Input Mute                             */
0057 #define     RINVOL_RLIN_BOTH              0x100   /* Right Channel Line Input Volume update               */
0058
0059 /*Left DAC Volume Control (SSM2602_REG_LEFT_DAC_VOL)*/
0060 #define     LOUT1V_LHP_VOL                0x07F   /* Left Channel Headphone volume control                */
0061 #define     LOUT1V_ENABLE_LZC             0x080   /* Left Channel Zero cross detect enable                */
0062 #define     LOUT1V_LRHP_BOTH              0x100   /* Left Channel Headphone volume update                 */
0063
0064 /*Right DAC Volume Control (SSM2602_REG_RIGHT_DAC_VOL)*/
0065 #define     ROUT1V_RHP_VOL                0x07F   /* Right Channel Headphone volume control               */
0066 #define     ROUT1V_ENABLE_RZC             0x080   /* Right Channel Zero cross detect enable               */
0067 #define     ROUT1V_RLHP_BOTH              0x100   /* Right Channel Headphone volume update                */
0068
0069 /*Analogue Audio Path Control (SSM2602_REG_ANALOGUE_PATH)*/
0070 #define     APANA_ENABLE_MIC_BOOST       0x001   /* Primary Microphone Amplifier gain booster control    */
0071 #define     APANA_ENABLE_MIC_MUTE        0x002   /* Microphone Mute Control                              */
0072 #define     APANA_ADC_IN_SELECT          0x004   /* Microphone/Line IN select to ADC (1=MIC, 0=Line In)  */
0073 #define     APANA_ENABLE_BYPASS          0x008   /* Line input bypass to line output                     */
0074 #define     APANA_SELECT_DAC             0x010   /* Select DAC (1=Select DAC, 0=Don't Select DAC)        */
0075 #define     APANA_ENABLE_SIDETONE        0x020   /* Enable/Disable Side Tone                             */
0076 #define     APANA_SIDETONE_ATTN          0x0C0   /* Side Tone Attenuation                                */
0077 #define     APANA_ENABLE_MIC_BOOST2      0x100   /* Secondary Microphone Amplifier gain booster control  */
0078
0079 /*Digital Audio Path Control (SSM2602_REG_DIGITAL_PATH)*/
0080 #define     APDIGI_ENABLE_ADC_HPF         0x001   /* Enable/Disable ADC Highpass Filter                   */
0081 #define     APDIGI_DE_EMPHASIS            0x006   /* De-Emphasis Control                                  */
0082 #define     APDIGI_ENABLE_DAC_MUTE        0x008   /* DAC Mute Control                                     */
0083 #define     APDIGI_STORE_OFFSET           0x010   /* Store/Clear DC offset when HPF is disabled           */
0084
0085 /*Power Down Control (SSM2602_REG_POWER)
0086  *(1=Enable PowerDown, 0=Disable PowerDown)
0087  */
0088 #define     PWR_LINE_IN_PDN            0x001   /* Line Input Power Down                                */
0089 #define     PWR_MIC_PDN                0x002   /* Microphone Input & Bias Power Down                   */
0090 #define     PWR_ADC_PDN                0x004   /* ADC Power Down                                       */
0091 #define     PWR_DAC_PDN                0x008   /* DAC Power Down                                       */
0092 #define     PWR_OUT_PDN                0x010   /* Outputs Power Down                                   */
0093 #define     PWR_OSC_PDN                0x020   /* Oscillator Power Down                                */
0094 #define     PWR_CLK_OUT_PDN            0x040   /* CLKOUT Power Down                                    */
0095 #define     PWR_POWER_OFF              0x080   /* POWEROFF Mode                                        */
0096
0097 /*Digital Audio Interface Format (SSM2602_REG_DIGITAL_IFACE)*/
0098 #define     IFACE_IFACE_FORMAT           0x003   /* Digital Audio input format control                   */
0099 #define     IFACE_AUDIO_DATA_LEN         0x00C   /* Audio Data word length control                       */
0100 #define     IFACE_DAC_LR_POLARITY        0x010   /* Polarity Control for clocks in RJ,LJ and I2S modes   */
0101 #define     IFACE_DAC_LR_SWAP            0x020   /* Swap DAC data control                                */
0102 #define     IFACE_ENABLE_MASTER          0x040   /* Enable/Disable Master Mode                           */
0103 #define     IFACE_BCLK_INVERT            0x080   /* Bit Clock Inversion control                          */
0104
0105 /*Sampling Control (SSM2602_REG_SAMPLING_CTRL)*/
0106 #define     SRATE_ENABLE_USB_MODE        0x001   /* Enable/Disable USB Mode                              */
0107 #define     SRATE_BOS_RATE               0x002   /* Base Over-Sampling rate                              */
0108 #define     SRATE_SAMPLE_RATE            0x03C   /* Clock setting condition (Sampling rate control)      */
0109 #define     SRATE_CORECLK_DIV2           0x040   /* Core Clock divider select                            */
0110 #define     SRATE_CLKOUT_DIV2            0x080   /* Clock Out divider select                             */
0111
0112 /*Active Control (SSM2602_REG_ACTIVE_CTRL)*/
0113 #define     ACTIVE_ACTIVATE_CODEC         0x001   /* Activate Codec Digital Audio Interface               */
0114
0115 /*********************************************************************/
0116
0117 #define SSM2602_CACHEREGNUM     10
0118
0119 enum ssm2602_clk {
0120     SSM2602_SYSCLK,
0121     SSM2602_CLK_CLKOUT,
0122     SSM2602_CLK_XTO
0123 };
0124
0125 #endif