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0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // sgtl5000.c  --  SGTL5000 ALSA SoC Audio driver
0004 //
0005 // Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
0006 
0007 #include <linux/module.h>
0008 #include <linux/moduleparam.h>
0009 #include <linux/init.h>
0010 #include <linux/delay.h>
0011 #include <linux/slab.h>
0012 #include <linux/pm.h>
0013 #include <linux/i2c.h>
0014 #include <linux/clk.h>
0015 #include <linux/log2.h>
0016 #include <linux/regmap.h>
0017 #include <linux/regulator/driver.h>
0018 #include <linux/regulator/machine.h>
0019 #include <linux/regulator/consumer.h>
0020 #include <linux/of_device.h>
0021 #include <sound/core.h>
0022 #include <sound/tlv.h>
0023 #include <sound/pcm.h>
0024 #include <sound/pcm_params.h>
0025 #include <sound/soc.h>
0026 #include <sound/soc-dapm.h>
0027 #include <sound/initval.h>
0028 
0029 #include "sgtl5000.h"
0030 
0031 #define SGTL5000_DAP_REG_OFFSET 0x0100
0032 #define SGTL5000_MAX_REG_OFFSET 0x013A
0033 
0034 /* Delay for the VAG ramp up */
0035 #define SGTL5000_VAG_POWERUP_DELAY 500 /* ms */
0036 /* Delay for the VAG ramp down */
0037 #define SGTL5000_VAG_POWERDOWN_DELAY 500 /* ms */
0038 
0039 #define SGTL5000_OUTPUTS_MUTE (SGTL5000_HP_MUTE | SGTL5000_LINE_OUT_MUTE)
0040 
0041 /* default value of sgtl5000 registers */
0042 static const struct reg_default sgtl5000_reg_defaults[] = {
0043     { SGTL5000_CHIP_DIG_POWER,      0x0000 },
0044     { SGTL5000_CHIP_I2S_CTRL,       0x0010 },
0045     { SGTL5000_CHIP_SSS_CTRL,       0x0010 },
0046     { SGTL5000_CHIP_ADCDAC_CTRL,        0x020c },
0047     { SGTL5000_CHIP_DAC_VOL,        0x3c3c },
0048     { SGTL5000_CHIP_PAD_STRENGTH,       0x015f },
0049     { SGTL5000_CHIP_ANA_ADC_CTRL,       0x0000 },
0050     { SGTL5000_CHIP_ANA_HP_CTRL,        0x1818 },
0051     { SGTL5000_CHIP_ANA_CTRL,       0x0111 },
0052     { SGTL5000_CHIP_REF_CTRL,       0x0000 },
0053     { SGTL5000_CHIP_MIC_CTRL,       0x0000 },
0054     { SGTL5000_CHIP_LINE_OUT_CTRL,      0x0000 },
0055     { SGTL5000_CHIP_LINE_OUT_VOL,       0x0404 },
0056     { SGTL5000_CHIP_PLL_CTRL,       0x5000 },
0057     { SGTL5000_CHIP_CLK_TOP_CTRL,       0x0000 },
0058     { SGTL5000_CHIP_ANA_STATUS,     0x0000 },
0059     { SGTL5000_CHIP_SHORT_CTRL,     0x0000 },
0060     { SGTL5000_CHIP_ANA_TEST2,      0x0000 },
0061     { SGTL5000_DAP_CTRL,            0x0000 },
0062     { SGTL5000_DAP_PEQ,         0x0000 },
0063     { SGTL5000_DAP_BASS_ENHANCE,        0x0040 },
0064     { SGTL5000_DAP_BASS_ENHANCE_CTRL,   0x051f },
0065     { SGTL5000_DAP_AUDIO_EQ,        0x0000 },
0066     { SGTL5000_DAP_SURROUND,        0x0040 },
0067     { SGTL5000_DAP_EQ_BASS_BAND0,       0x002f },
0068     { SGTL5000_DAP_EQ_BASS_BAND1,       0x002f },
0069     { SGTL5000_DAP_EQ_BASS_BAND2,       0x002f },
0070     { SGTL5000_DAP_EQ_BASS_BAND3,       0x002f },
0071     { SGTL5000_DAP_EQ_BASS_BAND4,       0x002f },
0072     { SGTL5000_DAP_MAIN_CHAN,       0x8000 },
0073     { SGTL5000_DAP_MIX_CHAN,        0x0000 },
0074     { SGTL5000_DAP_AVC_CTRL,        0x5100 },
0075     { SGTL5000_DAP_AVC_THRESHOLD,       0x1473 },
0076     { SGTL5000_DAP_AVC_ATTACK,      0x0028 },
0077     { SGTL5000_DAP_AVC_DECAY,       0x0050 },
0078 };
0079 
0080 /* AVC: Threshold dB -> register: pre-calculated values */
0081 static const u16 avc_thr_db2reg[97] = {
0082     0x5168, 0x488E, 0x40AA, 0x39A1, 0x335D, 0x2DC7, 0x28CC, 0x245D, 0x2068,
0083     0x1CE2, 0x19BE, 0x16F1, 0x1472, 0x1239, 0x103E, 0x0E7A, 0x0CE6, 0x0B7F,
0084     0x0A3F, 0x0922, 0x0824, 0x0741, 0x0677, 0x05C3, 0x0522, 0x0493, 0x0414,
0085     0x03A2, 0x033D, 0x02E3, 0x0293, 0x024B, 0x020B, 0x01D2, 0x019F, 0x0172,
0086     0x014A, 0x0126, 0x0106, 0x00E9, 0x00D0, 0x00B9, 0x00A5, 0x0093, 0x0083,
0087     0x0075, 0x0068, 0x005D, 0x0052, 0x0049, 0x0041, 0x003A, 0x0034, 0x002E,
0088     0x0029, 0x0025, 0x0021, 0x001D, 0x001A, 0x0017, 0x0014, 0x0012, 0x0010,
0089     0x000E, 0x000D, 0x000B, 0x000A, 0x0009, 0x0008, 0x0007, 0x0006, 0x0005,
0090     0x0005, 0x0004, 0x0004, 0x0003, 0x0003, 0x0002, 0x0002, 0x0002, 0x0002,
0091     0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0000, 0x0000, 0x0000,
0092     0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000};
0093 
0094 /* regulator supplies for sgtl5000, VDDD is an optional external supply */
0095 enum sgtl5000_regulator_supplies {
0096     VDDA,
0097     VDDIO,
0098     VDDD,
0099     SGTL5000_SUPPLY_NUM
0100 };
0101 
0102 /* vddd is optional supply */
0103 static const char *supply_names[SGTL5000_SUPPLY_NUM] = {
0104     "VDDA",
0105     "VDDIO",
0106     "VDDD"
0107 };
0108 
0109 #define LDO_VOLTAGE     1200000
0110 #define LINREG_VDDD ((1600 - LDO_VOLTAGE / 1000) / 50)
0111 
0112 enum sgtl5000_micbias_resistor {
0113     SGTL5000_MICBIAS_OFF = 0,
0114     SGTL5000_MICBIAS_2K = 2,
0115     SGTL5000_MICBIAS_4K = 4,
0116     SGTL5000_MICBIAS_8K = 8,
0117 };
0118 
0119 enum  {
0120     I2S_LRCLK_STRENGTH_DISABLE,
0121     I2S_LRCLK_STRENGTH_LOW,
0122     I2S_LRCLK_STRENGTH_MEDIUM,
0123     I2S_LRCLK_STRENGTH_HIGH,
0124 };
0125 
0126 enum  {
0127     I2S_SCLK_STRENGTH_DISABLE,
0128     I2S_SCLK_STRENGTH_LOW,
0129     I2S_SCLK_STRENGTH_MEDIUM,
0130     I2S_SCLK_STRENGTH_HIGH,
0131 };
0132 
0133 enum {
0134     HP_POWER_EVENT,
0135     DAC_POWER_EVENT,
0136     ADC_POWER_EVENT,
0137     LAST_POWER_EVENT = ADC_POWER_EVENT
0138 };
0139 
0140 /* sgtl5000 private structure in codec */
0141 struct sgtl5000_priv {
0142     int sysclk; /* sysclk rate */
0143     int master; /* i2s master or not */
0144     int fmt;    /* i2s data format */
0145     struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM];
0146     int num_supplies;
0147     struct regmap *regmap;
0148     struct clk *mclk;
0149     int revision;
0150     u8 micbias_resistor;
0151     u8 micbias_voltage;
0152     u8 lrclk_strength;
0153     u8 sclk_strength;
0154     u16 mute_state[LAST_POWER_EVENT + 1];
0155 };
0156 
0157 static inline int hp_sel_input(struct snd_soc_component *component)
0158 {
0159     return (snd_soc_component_read(component, SGTL5000_CHIP_ANA_CTRL) &
0160         SGTL5000_HP_SEL_MASK) >> SGTL5000_HP_SEL_SHIFT;
0161 }
0162 
0163 static inline u16 mute_output(struct snd_soc_component *component,
0164                   u16 mute_mask)
0165 {
0166     u16 mute_reg = snd_soc_component_read(component,
0167                           SGTL5000_CHIP_ANA_CTRL);
0168 
0169     snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_CTRL,
0170                 mute_mask, mute_mask);
0171     return mute_reg;
0172 }
0173 
0174 static inline void restore_output(struct snd_soc_component *component,
0175                   u16 mute_mask, u16 mute_reg)
0176 {
0177     snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_CTRL,
0178         mute_mask, mute_reg);
0179 }
0180 
0181 static void vag_power_on(struct snd_soc_component *component, u32 source)
0182 {
0183     if (snd_soc_component_read(component, SGTL5000_CHIP_ANA_POWER) &
0184         SGTL5000_VAG_POWERUP)
0185         return;
0186 
0187     snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
0188                 SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
0189 
0190     /* When VAG powering on to get local loop from Line-In, the sleep
0191      * is required to avoid loud pop.
0192      */
0193     if (hp_sel_input(component) == SGTL5000_HP_SEL_LINE_IN &&
0194         source == HP_POWER_EVENT)
0195         msleep(SGTL5000_VAG_POWERUP_DELAY);
0196 }
0197 
0198 static int vag_power_consumers(struct snd_soc_component *component,
0199                    u16 ana_pwr_reg, u32 source)
0200 {
0201     int consumers = 0;
0202 
0203     /* count dac/adc consumers unconditional */
0204     if (ana_pwr_reg & SGTL5000_DAC_POWERUP)
0205         consumers++;
0206     if (ana_pwr_reg & SGTL5000_ADC_POWERUP)
0207         consumers++;
0208 
0209     /*
0210      * If the event comes from HP and Line-In is selected,
0211      * current action is 'DAC to be powered down'.
0212      * As HP_POWERUP is not set when HP muxed to line-in,
0213      * we need to keep VAG power ON.
0214      */
0215     if (source == HP_POWER_EVENT) {
0216         if (hp_sel_input(component) == SGTL5000_HP_SEL_LINE_IN)
0217             consumers++;
0218     } else {
0219         if (ana_pwr_reg & SGTL5000_HP_POWERUP)
0220             consumers++;
0221     }
0222 
0223     return consumers;
0224 }
0225 
0226 static void vag_power_off(struct snd_soc_component *component, u32 source)
0227 {
0228     u16 ana_pwr = snd_soc_component_read(component,
0229                          SGTL5000_CHIP_ANA_POWER);
0230 
0231     if (!(ana_pwr & SGTL5000_VAG_POWERUP))
0232         return;
0233 
0234     /*
0235      * This function calls when any of VAG power consumers is disappearing.
0236      * Thus, if there is more than one consumer at the moment, as minimum
0237      * one consumer will definitely stay after the end of the current
0238      * event.
0239      * Don't clear VAG_POWERUP if 2 or more consumers of VAG present:
0240      * - LINE_IN (for HP events) / HP (for DAC/ADC events)
0241      * - DAC
0242      * - ADC
0243      * (the current consumer is disappearing right now)
0244      */
0245     if (vag_power_consumers(component, ana_pwr, source) >= 2)
0246         return;
0247 
0248     snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
0249         SGTL5000_VAG_POWERUP, 0);
0250     /* In power down case, we need wait 400-1000 ms
0251      * when VAG fully ramped down.
0252      * As longer we wait, as smaller pop we've got.
0253      */
0254     msleep(SGTL5000_VAG_POWERDOWN_DELAY);
0255 }
0256 
0257 /*
0258  * mic_bias power on/off share the same register bits with
0259  * output impedance of mic bias, when power on mic bias, we
0260  * need reclaim it to impedance value.
0261  * 0x0 = Powered off
0262  * 0x1 = 2Kohm
0263  * 0x2 = 4Kohm
0264  * 0x3 = 8Kohm
0265  */
0266 static int mic_bias_event(struct snd_soc_dapm_widget *w,
0267     struct snd_kcontrol *kcontrol, int event)
0268 {
0269     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0270     struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
0271 
0272     switch (event) {
0273     case SND_SOC_DAPM_POST_PMU:
0274         /* change mic bias resistor */
0275         snd_soc_component_update_bits(component, SGTL5000_CHIP_MIC_CTRL,
0276             SGTL5000_BIAS_R_MASK,
0277             sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT);
0278         break;
0279 
0280     case SND_SOC_DAPM_PRE_PMD:
0281         snd_soc_component_update_bits(component, SGTL5000_CHIP_MIC_CTRL,
0282                 SGTL5000_BIAS_R_MASK, 0);
0283         break;
0284     }
0285     return 0;
0286 }
0287 
0288 static int vag_and_mute_control(struct snd_soc_component *component,
0289                  int event, int event_source)
0290 {
0291     static const u16 mute_mask[] = {
0292         /*
0293          * Mask for HP_POWER_EVENT.
0294          * Muxing Headphones have to be wrapped with mute/unmute
0295          * headphones only.
0296          */
0297         SGTL5000_HP_MUTE,
0298         /*
0299          * Masks for DAC_POWER_EVENT/ADC_POWER_EVENT.
0300          * Muxing DAC or ADC block have to wrapped with mute/unmute
0301          * both headphones and line-out.
0302          */
0303         SGTL5000_OUTPUTS_MUTE,
0304         SGTL5000_OUTPUTS_MUTE
0305     };
0306 
0307     struct sgtl5000_priv *sgtl5000 =
0308         snd_soc_component_get_drvdata(component);
0309 
0310     switch (event) {
0311     case SND_SOC_DAPM_PRE_PMU:
0312         sgtl5000->mute_state[event_source] =
0313             mute_output(component, mute_mask[event_source]);
0314         break;
0315     case SND_SOC_DAPM_POST_PMU:
0316         vag_power_on(component, event_source);
0317         restore_output(component, mute_mask[event_source],
0318                    sgtl5000->mute_state[event_source]);
0319         break;
0320     case SND_SOC_DAPM_PRE_PMD:
0321         sgtl5000->mute_state[event_source] =
0322             mute_output(component, mute_mask[event_source]);
0323         vag_power_off(component, event_source);
0324         break;
0325     case SND_SOC_DAPM_POST_PMD:
0326         restore_output(component, mute_mask[event_source],
0327                    sgtl5000->mute_state[event_source]);
0328         break;
0329     default:
0330         break;
0331     }
0332 
0333     return 0;
0334 }
0335 
0336 /*
0337  * Mute Headphone when power it up/down.
0338  * Control VAG power on HP power path.
0339  */
0340 static int headphone_pga_event(struct snd_soc_dapm_widget *w,
0341     struct snd_kcontrol *kcontrol, int event)
0342 {
0343     struct snd_soc_component *component =
0344         snd_soc_dapm_to_component(w->dapm);
0345 
0346     return vag_and_mute_control(component, event, HP_POWER_EVENT);
0347 }
0348 
0349 /* As manual describes, ADC/DAC powering up/down requires
0350  * to mute outputs to avoid pops.
0351  * Control VAG power on ADC/DAC power path.
0352  */
0353 static int adc_updown_depop(struct snd_soc_dapm_widget *w,
0354     struct snd_kcontrol *kcontrol, int event)
0355 {
0356     struct snd_soc_component *component =
0357         snd_soc_dapm_to_component(w->dapm);
0358 
0359     return vag_and_mute_control(component, event, ADC_POWER_EVENT);
0360 }
0361 
0362 static int dac_updown_depop(struct snd_soc_dapm_widget *w,
0363     struct snd_kcontrol *kcontrol, int event)
0364 {
0365     struct snd_soc_component *component =
0366         snd_soc_dapm_to_component(w->dapm);
0367 
0368     return vag_and_mute_control(component, event, DAC_POWER_EVENT);
0369 }
0370 
0371 /* input sources for ADC */
0372 static const char *adc_mux_text[] = {
0373     "MIC_IN", "LINE_IN"
0374 };
0375 
0376 static SOC_ENUM_SINGLE_DECL(adc_enum,
0377                 SGTL5000_CHIP_ANA_CTRL, 2,
0378                 adc_mux_text);
0379 
0380 static const struct snd_kcontrol_new adc_mux =
0381 SOC_DAPM_ENUM("Capture Mux", adc_enum);
0382 
0383 /* input sources for headphone */
0384 static const char *hp_mux_text[] = {
0385     "DAC", "LINE_IN"
0386 };
0387 
0388 static SOC_ENUM_SINGLE_DECL(hp_enum,
0389                 SGTL5000_CHIP_ANA_CTRL, 6,
0390                 hp_mux_text);
0391 
0392 static const struct snd_kcontrol_new hp_mux =
0393 SOC_DAPM_ENUM("Headphone Mux", hp_enum);
0394 
0395 /* input sources for DAC */
0396 static const char *dac_mux_text[] = {
0397     "ADC", "I2S", "Rsvrd", "DAP"
0398 };
0399 
0400 static SOC_ENUM_SINGLE_DECL(dac_enum,
0401                 SGTL5000_CHIP_SSS_CTRL, SGTL5000_DAC_SEL_SHIFT,
0402                 dac_mux_text);
0403 
0404 static const struct snd_kcontrol_new dac_mux =
0405 SOC_DAPM_ENUM("Digital Input Mux", dac_enum);
0406 
0407 /* input sources for DAP */
0408 static const char *dap_mux_text[] = {
0409     "ADC", "I2S"
0410 };
0411 
0412 static SOC_ENUM_SINGLE_DECL(dap_enum,
0413                 SGTL5000_CHIP_SSS_CTRL, SGTL5000_DAP_SEL_SHIFT,
0414                 dap_mux_text);
0415 
0416 static const struct snd_kcontrol_new dap_mux =
0417 SOC_DAPM_ENUM("DAP Mux", dap_enum);
0418 
0419 /* input sources for DAP mix */
0420 static const char *dapmix_mux_text[] = {
0421     "ADC", "I2S"
0422 };
0423 
0424 static SOC_ENUM_SINGLE_DECL(dapmix_enum,
0425                 SGTL5000_CHIP_SSS_CTRL, SGTL5000_DAP_MIX_SEL_SHIFT,
0426                 dapmix_mux_text);
0427 
0428 static const struct snd_kcontrol_new dapmix_mux =
0429 SOC_DAPM_ENUM("DAP MIX Mux", dapmix_enum);
0430 
0431 
0432 static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
0433     SND_SOC_DAPM_INPUT("LINE_IN"),
0434     SND_SOC_DAPM_INPUT("MIC_IN"),
0435 
0436     SND_SOC_DAPM_OUTPUT("HP_OUT"),
0437     SND_SOC_DAPM_OUTPUT("LINE_OUT"),
0438 
0439     SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
0440                 mic_bias_event,
0441                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
0442 
0443     SND_SOC_DAPM_PGA_E("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0,
0444                headphone_pga_event,
0445                SND_SOC_DAPM_PRE_POST_PMU |
0446                SND_SOC_DAPM_PRE_POST_PMD),
0447     SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0),
0448 
0449     SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux),
0450     SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &hp_mux),
0451     SND_SOC_DAPM_MUX("Digital Input Mux", SND_SOC_NOPM, 0, 0, &dac_mux),
0452     SND_SOC_DAPM_MUX("DAP Mux", SGTL5000_DAP_CTRL, 0, 0, &dap_mux),
0453     SND_SOC_DAPM_MUX("DAP MIX Mux", SGTL5000_DAP_CTRL, 4, 0, &dapmix_mux),
0454     SND_SOC_DAPM_MIXER("DAP", SGTL5000_CHIP_DIG_POWER, 4, 0, NULL, 0),
0455 
0456 
0457     /* aif for i2s input */
0458     SND_SOC_DAPM_AIF_IN("AIFIN", "Playback",
0459                 0, SGTL5000_CHIP_DIG_POWER,
0460                 0, 0),
0461 
0462     /* aif for i2s output */
0463     SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture",
0464                 0, SGTL5000_CHIP_DIG_POWER,
0465                 1, 0),
0466 
0467     SND_SOC_DAPM_ADC_E("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0,
0468                adc_updown_depop, SND_SOC_DAPM_PRE_POST_PMU |
0469                SND_SOC_DAPM_PRE_POST_PMD),
0470     SND_SOC_DAPM_DAC_E("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0,
0471                dac_updown_depop, SND_SOC_DAPM_PRE_POST_PMU |
0472                SND_SOC_DAPM_PRE_POST_PMD),
0473 };
0474 
0475 /* routes for sgtl5000 */
0476 static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = {
0477     {"Capture Mux", "LINE_IN", "LINE_IN"},  /* line_in --> adc_mux */
0478     {"Capture Mux", "MIC_IN", "MIC_IN"},    /* mic_in --> adc_mux */
0479 
0480     {"ADC", NULL, "Capture Mux"},       /* adc_mux --> adc */
0481     {"AIFOUT", NULL, "ADC"},        /* adc --> i2s_out */
0482 
0483     {"DAP Mux", "ADC", "ADC"},      /* adc --> DAP mux */
0484     {"DAP Mux", NULL, "AIFIN"},     /* i2s --> DAP mux */
0485     {"DAP", NULL, "DAP Mux"},       /* DAP mux --> dap */
0486 
0487     {"DAP MIX Mux", "ADC", "ADC"},      /* adc --> DAP MIX mux */
0488     {"DAP MIX Mux", NULL, "AIFIN"},     /* i2s --> DAP MIX mux */
0489     {"DAP", NULL, "DAP MIX Mux"},       /* DAP MIX mux --> dap */
0490 
0491     {"Digital Input Mux", "ADC", "ADC"},    /* adc --> audio mux */
0492     {"Digital Input Mux", NULL, "AIFIN"},   /* i2s --> audio mux */
0493     {"Digital Input Mux", NULL, "DAP"}, /* dap --> audio mux */
0494     {"DAC", NULL, "Digital Input Mux"}, /* audio mux --> dac */
0495 
0496     {"Headphone Mux", "DAC", "DAC"},    /* dac --> hp_mux */
0497     {"LO", NULL, "DAC"},            /* dac --> line_out */
0498 
0499     {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */
0500     {"HP", NULL, "Headphone Mux"},      /* hp_mux --> hp */
0501 
0502     {"LINE_OUT", NULL, "LO"},
0503     {"HP_OUT", NULL, "HP"},
0504 };
0505 
0506 /* custom function to fetch info of PCM playback volume */
0507 static int dac_info_volsw(struct snd_kcontrol *kcontrol,
0508               struct snd_ctl_elem_info *uinfo)
0509 {
0510     uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
0511     uinfo->count = 2;
0512     uinfo->value.integer.min = 0;
0513     uinfo->value.integer.max = 0xfc - 0x3c;
0514     return 0;
0515 }
0516 
0517 /*
0518  * custom function to get of PCM playback volume
0519  *
0520  * dac volume register
0521  * 15-------------8-7--------------0
0522  * | R channel vol | L channel vol |
0523  *  -------------------------------
0524  *
0525  * PCM volume with 0.5017 dB steps from 0 to -90 dB
0526  *
0527  * register values map to dB
0528  * 0x3B and less = Reserved
0529  * 0x3C = 0 dB
0530  * 0x3D = -0.5 dB
0531  * 0xF0 = -90 dB
0532  * 0xFC and greater = Muted
0533  *
0534  * register value map to userspace value
0535  *
0536  * register value   0x3c(0dB)     0xf0(-90dB)0xfc
0537  *          ------------------------------
0538  * userspace value  0xc0                 0
0539  */
0540 static int dac_get_volsw(struct snd_kcontrol *kcontrol,
0541              struct snd_ctl_elem_value *ucontrol)
0542 {
0543     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0544     int reg;
0545     int l;
0546     int r;
0547 
0548     reg = snd_soc_component_read(component, SGTL5000_CHIP_DAC_VOL);
0549 
0550     /* get left channel volume */
0551     l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT;
0552 
0553     /* get right channel volume */
0554     r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT;
0555 
0556     /* make sure value fall in (0x3c,0xfc) */
0557     l = clamp(l, 0x3c, 0xfc);
0558     r = clamp(r, 0x3c, 0xfc);
0559 
0560     /* invert it and map to userspace value */
0561     l = 0xfc - l;
0562     r = 0xfc - r;
0563 
0564     ucontrol->value.integer.value[0] = l;
0565     ucontrol->value.integer.value[1] = r;
0566 
0567     return 0;
0568 }
0569 
0570 /*
0571  * custom function to put of PCM playback volume
0572  *
0573  * dac volume register
0574  * 15-------------8-7--------------0
0575  * | R channel vol | L channel vol |
0576  *  -------------------------------
0577  *
0578  * PCM volume with 0.5017 dB steps from 0 to -90 dB
0579  *
0580  * register values map to dB
0581  * 0x3B and less = Reserved
0582  * 0x3C = 0 dB
0583  * 0x3D = -0.5 dB
0584  * 0xF0 = -90 dB
0585  * 0xFC and greater = Muted
0586  *
0587  * userspace value map to register value
0588  *
0589  * userspace value  0xc0                 0
0590  *          ------------------------------
0591  * register value   0x3c(0dB)   0xf0(-90dB)0xfc
0592  */
0593 static int dac_put_volsw(struct snd_kcontrol *kcontrol,
0594              struct snd_ctl_elem_value *ucontrol)
0595 {
0596     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0597     int reg;
0598     int l;
0599     int r;
0600 
0601     l = ucontrol->value.integer.value[0];
0602     r = ucontrol->value.integer.value[1];
0603 
0604     /* make sure userspace volume fall in (0, 0xfc-0x3c) */
0605     l = clamp(l, 0, 0xfc - 0x3c);
0606     r = clamp(r, 0, 0xfc - 0x3c);
0607 
0608     /* invert it, get the value can be set to register */
0609     l = 0xfc - l;
0610     r = 0xfc - r;
0611 
0612     /* shift to get the register value */
0613     reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT |
0614         r << SGTL5000_DAC_VOL_RIGHT_SHIFT;
0615 
0616     snd_soc_component_write(component, SGTL5000_CHIP_DAC_VOL, reg);
0617 
0618     return 0;
0619 }
0620 
0621 /*
0622  * custom function to get AVC threshold
0623  *
0624  * The threshold dB is calculated by rearranging the calculation from the
0625  * avc_put_threshold function: register_value = 10^(dB/20) * 0.636 * 2^15 ==>
0626  * dB = ( fls(register_value) - 14.347 ) * 6.02
0627  *
0628  * As this calculation is expensive and the threshold dB values may not exceed
0629  * 0 to 96 we use pre-calculated values.
0630  */
0631 static int avc_get_threshold(struct snd_kcontrol *kcontrol,
0632                  struct snd_ctl_elem_value *ucontrol)
0633 {
0634     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0635     int db, i;
0636     u16 reg = snd_soc_component_read(component, SGTL5000_DAP_AVC_THRESHOLD);
0637 
0638     /* register value 0 => -96dB */
0639     if (!reg) {
0640         ucontrol->value.integer.value[0] = 96;
0641         ucontrol->value.integer.value[1] = 96;
0642         return 0;
0643     }
0644 
0645     /* get dB from register value (rounded down) */
0646     for (i = 0; avc_thr_db2reg[i] > reg; i++)
0647         ;
0648     db = i;
0649 
0650     ucontrol->value.integer.value[0] = db;
0651     ucontrol->value.integer.value[1] = db;
0652 
0653     return 0;
0654 }
0655 
0656 /*
0657  * custom function to put AVC threshold
0658  *
0659  * The register value is calculated by following formula:
0660  *                                    register_value = 10^(dB/20) * 0.636 * 2^15
0661  * As this calculation is expensive and the threshold dB values may not exceed
0662  * 0 to 96 we use pre-calculated values.
0663  */
0664 static int avc_put_threshold(struct snd_kcontrol *kcontrol,
0665                  struct snd_ctl_elem_value *ucontrol)
0666 {
0667     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0668     int db;
0669     u16 reg;
0670 
0671     db = (int)ucontrol->value.integer.value[0];
0672     if (db < 0 || db > 96)
0673         return -EINVAL;
0674     reg = avc_thr_db2reg[db];
0675     snd_soc_component_write(component, SGTL5000_DAP_AVC_THRESHOLD, reg);
0676 
0677     return 0;
0678 }
0679 
0680 static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0);
0681 
0682 /* tlv for mic gain, 0db 20db 30db 40db */
0683 static const DECLARE_TLV_DB_RANGE(mic_gain_tlv,
0684     0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
0685     1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0)
0686 );
0687 
0688 /* tlv for DAP channels, 0% - 100% - 200% */
0689 static const DECLARE_TLV_DB_SCALE(dap_volume, 0, 1, 0);
0690 
0691 /* tlv for bass bands, -11.75db to 12.0db, step .25db */
0692 static const DECLARE_TLV_DB_SCALE(bass_band, -1175, 25, 0);
0693 
0694 /* tlv for hp volume, -51.5db to 12.0db, step .5db */
0695 static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0);
0696 
0697 /* tlv for lineout volume, 31 steps of .5db each */
0698 static const DECLARE_TLV_DB_SCALE(lineout_volume, -1550, 50, 0);
0699 
0700 /* tlv for dap avc max gain, 0db, 6db, 12db */
0701 static const DECLARE_TLV_DB_SCALE(avc_max_gain, 0, 600, 0);
0702 
0703 /* tlv for dap avc threshold, */
0704 static const DECLARE_TLV_DB_MINMAX(avc_threshold, 0, 9600);
0705 
0706 static const struct snd_kcontrol_new sgtl5000_snd_controls[] = {
0707     /* SOC_DOUBLE_S8_TLV with invert */
0708     {
0709         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
0710         .name = "PCM Playback Volume",
0711         .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
0712             SNDRV_CTL_ELEM_ACCESS_READWRITE,
0713         .info = dac_info_volsw,
0714         .get = dac_get_volsw,
0715         .put = dac_put_volsw,
0716     },
0717 
0718     SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0),
0719     SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)",
0720             SGTL5000_CHIP_ANA_ADC_CTRL,
0721             8, 1, 0, capture_6db_attenuate),
0722     SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0),
0723     SOC_SINGLE("Capture Switch", SGTL5000_CHIP_ANA_CTRL, 0, 1, 1),
0724 
0725     SOC_DOUBLE_TLV("Headphone Playback Volume",
0726             SGTL5000_CHIP_ANA_HP_CTRL,
0727             0, 8,
0728             0x7f, 1,
0729             headphone_volume),
0730     SOC_SINGLE("Headphone Playback Switch", SGTL5000_CHIP_ANA_CTRL,
0731             4, 1, 1),
0732     SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL,
0733             5, 1, 0),
0734 
0735     SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL,
0736             0, 3, 0, mic_gain_tlv),
0737 
0738     SOC_DOUBLE_TLV("Lineout Playback Volume",
0739             SGTL5000_CHIP_LINE_OUT_VOL,
0740             SGTL5000_LINE_OUT_VOL_LEFT_SHIFT,
0741             SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT,
0742             0x1f, 1,
0743             lineout_volume),
0744     SOC_SINGLE("Lineout Playback Switch", SGTL5000_CHIP_ANA_CTRL, 8, 1, 1),
0745 
0746     SOC_SINGLE_TLV("DAP Main channel", SGTL5000_DAP_MAIN_CHAN,
0747     0, 0xffff, 0, dap_volume),
0748 
0749     SOC_SINGLE_TLV("DAP Mix channel", SGTL5000_DAP_MIX_CHAN,
0750     0, 0xffff, 0, dap_volume),
0751     /* Automatic Volume Control (DAP AVC) */
0752     SOC_SINGLE("AVC Switch", SGTL5000_DAP_AVC_CTRL, 0, 1, 0),
0753     SOC_SINGLE("AVC Hard Limiter Switch", SGTL5000_DAP_AVC_CTRL, 5, 1, 0),
0754     SOC_SINGLE_TLV("AVC Max Gain Volume", SGTL5000_DAP_AVC_CTRL, 12, 2, 0,
0755             avc_max_gain),
0756     SOC_SINGLE("AVC Integrator Response", SGTL5000_DAP_AVC_CTRL, 8, 3, 0),
0757     SOC_SINGLE_EXT_TLV("AVC Threshold Volume", SGTL5000_DAP_AVC_THRESHOLD,
0758             0, 96, 0, avc_get_threshold, avc_put_threshold,
0759             avc_threshold),
0760 
0761     SOC_SINGLE_TLV("BASS 0", SGTL5000_DAP_EQ_BASS_BAND0,
0762     0, 0x5F, 0, bass_band),
0763 
0764     SOC_SINGLE_TLV("BASS 1", SGTL5000_DAP_EQ_BASS_BAND1,
0765     0, 0x5F, 0, bass_band),
0766 
0767     SOC_SINGLE_TLV("BASS 2", SGTL5000_DAP_EQ_BASS_BAND2,
0768     0, 0x5F, 0, bass_band),
0769 
0770     SOC_SINGLE_TLV("BASS 3", SGTL5000_DAP_EQ_BASS_BAND3,
0771     0, 0x5F, 0, bass_band),
0772 
0773     SOC_SINGLE_TLV("BASS 4", SGTL5000_DAP_EQ_BASS_BAND4,
0774     0, 0x5F, 0, bass_band),
0775 };
0776 
0777 /* mute the codec used by alsa core */
0778 static int sgtl5000_mute_stream(struct snd_soc_dai *codec_dai, int mute, int direction)
0779 {
0780     struct snd_soc_component *component = codec_dai->component;
0781     u16 i2s_pwr = SGTL5000_I2S_IN_POWERUP;
0782 
0783     /*
0784      * During 'digital mute' do not mute DAC
0785      * because LINE_IN would be muted aswell. We want to mute
0786      * only I2S block - this can be done by powering it off
0787      */
0788     snd_soc_component_update_bits(component, SGTL5000_CHIP_DIG_POWER,
0789             i2s_pwr, mute ? 0 : i2s_pwr);
0790 
0791     return 0;
0792 }
0793 
0794 /* set codec format */
0795 static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
0796 {
0797     struct snd_soc_component *component = codec_dai->component;
0798     struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
0799     u16 i2sctl = 0;
0800 
0801     sgtl5000->master = 0;
0802     /*
0803      * i2s clock and frame master setting.
0804      * ONLY support:
0805      *  - clock and frame slave,
0806      *  - clock and frame master
0807      */
0808     switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
0809     case SND_SOC_DAIFMT_CBS_CFS:
0810         break;
0811     case SND_SOC_DAIFMT_CBM_CFM:
0812         i2sctl |= SGTL5000_I2S_MASTER;
0813         sgtl5000->master = 1;
0814         break;
0815     default:
0816         return -EINVAL;
0817     }
0818 
0819     /* setting i2s data format */
0820     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0821     case SND_SOC_DAIFMT_DSP_A:
0822         i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT;
0823         break;
0824     case SND_SOC_DAIFMT_DSP_B:
0825         i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT;
0826         i2sctl |= SGTL5000_I2S_LRALIGN;
0827         break;
0828     case SND_SOC_DAIFMT_I2S:
0829         i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT;
0830         break;
0831     case SND_SOC_DAIFMT_RIGHT_J:
0832         i2sctl |= SGTL5000_I2S_MODE_RJ << SGTL5000_I2S_MODE_SHIFT;
0833         i2sctl |= SGTL5000_I2S_LRPOL;
0834         break;
0835     case SND_SOC_DAIFMT_LEFT_J:
0836         i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT;
0837         i2sctl |= SGTL5000_I2S_LRALIGN;
0838         break;
0839     default:
0840         return -EINVAL;
0841     }
0842 
0843     sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
0844 
0845     /* Clock inversion */
0846     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0847     case SND_SOC_DAIFMT_NB_NF:
0848         break;
0849     case SND_SOC_DAIFMT_IB_NF:
0850         i2sctl |= SGTL5000_I2S_SCLK_INV;
0851         break;
0852     default:
0853         return -EINVAL;
0854     }
0855 
0856     snd_soc_component_write(component, SGTL5000_CHIP_I2S_CTRL, i2sctl);
0857 
0858     return 0;
0859 }
0860 
0861 /* set codec sysclk */
0862 static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai,
0863                    int clk_id, unsigned int freq, int dir)
0864 {
0865     struct snd_soc_component *component = codec_dai->component;
0866     struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
0867 
0868     switch (clk_id) {
0869     case SGTL5000_SYSCLK:
0870         sgtl5000->sysclk = freq;
0871         break;
0872     default:
0873         return -EINVAL;
0874     }
0875 
0876     return 0;
0877 }
0878 
0879 /*
0880  * set clock according to i2s frame clock,
0881  * sgtl5000 provides 2 clock sources:
0882  * 1. sys_mclk: sample freq can only be configured to
0883  *  1/256, 1/384, 1/512 of sys_mclk.
0884  * 2. pll: can derive any audio clocks.
0885  *
0886  * clock setting rules:
0887  * 1. in slave mode, only sys_mclk can be used
0888  * 2. as constraint by sys_mclk, sample freq should be set to 32 kHz, 44.1 kHz
0889  * and above.
0890  * 3. usage of sys_mclk is preferred over pll to save power.
0891  */
0892 static int sgtl5000_set_clock(struct snd_soc_component *component, int frame_rate)
0893 {
0894     struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
0895     int clk_ctl = 0;
0896     int sys_fs; /* sample freq */
0897 
0898     /*
0899      * sample freq should be divided by frame clock,
0900      * if frame clock is lower than 44.1 kHz, sample freq should be set to
0901      * 32 kHz or 44.1 kHz.
0902      */
0903     switch (frame_rate) {
0904     case 8000:
0905     case 16000:
0906         sys_fs = 32000;
0907         break;
0908     case 11025:
0909     case 22050:
0910         sys_fs = 44100;
0911         break;
0912     default:
0913         sys_fs = frame_rate;
0914         break;
0915     }
0916 
0917     /* set divided factor of frame clock */
0918     switch (sys_fs / frame_rate) {
0919     case 4:
0920         clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT;
0921         break;
0922     case 2:
0923         clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT;
0924         break;
0925     case 1:
0926         clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT;
0927         break;
0928     default:
0929         return -EINVAL;
0930     }
0931 
0932     /* set the sys_fs according to frame rate */
0933     switch (sys_fs) {
0934     case 32000:
0935         clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT;
0936         break;
0937     case 44100:
0938         clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT;
0939         break;
0940     case 48000:
0941         clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT;
0942         break;
0943     case 96000:
0944         clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT;
0945         break;
0946     default:
0947         dev_err(component->dev, "frame rate %d not supported\n",
0948             frame_rate);
0949         return -EINVAL;
0950     }
0951 
0952     /*
0953      * calculate the divider of mclk/sample_freq,
0954      * factor of freq = 96 kHz can only be 256, since mclk is in the range
0955      * of 8 MHz - 27 MHz
0956      */
0957     switch (sgtl5000->sysclk / frame_rate) {
0958     case 256:
0959         clk_ctl |= SGTL5000_MCLK_FREQ_256FS <<
0960             SGTL5000_MCLK_FREQ_SHIFT;
0961         break;
0962     case 384:
0963         clk_ctl |= SGTL5000_MCLK_FREQ_384FS <<
0964             SGTL5000_MCLK_FREQ_SHIFT;
0965         break;
0966     case 512:
0967         clk_ctl |= SGTL5000_MCLK_FREQ_512FS <<
0968             SGTL5000_MCLK_FREQ_SHIFT;
0969         break;
0970     default:
0971         /* if mclk does not satisfy the divider, use pll */
0972         if (sgtl5000->master) {
0973             clk_ctl |= SGTL5000_MCLK_FREQ_PLL <<
0974                 SGTL5000_MCLK_FREQ_SHIFT;
0975         } else {
0976             dev_err(component->dev,
0977                 "PLL not supported in slave mode\n");
0978             dev_err(component->dev, "%d ratio is not supported. "
0979                 "SYS_MCLK needs to be 256, 384 or 512 * fs\n",
0980                 sgtl5000->sysclk / frame_rate);
0981             return -EINVAL;
0982         }
0983     }
0984 
0985     /* if using pll, please check manual 6.4.2 for detail */
0986     if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) {
0987         u64 out, t;
0988         int div2;
0989         int pll_ctl;
0990         unsigned int in, int_div, frac_div;
0991 
0992         if (sgtl5000->sysclk > 17000000) {
0993             div2 = 1;
0994             in = sgtl5000->sysclk / 2;
0995         } else {
0996             div2 = 0;
0997             in = sgtl5000->sysclk;
0998         }
0999         if (sys_fs == 44100)
1000             out = 180633600;
1001         else
1002             out = 196608000;
1003         t = do_div(out, in);
1004         int_div = out;
1005         t *= 2048;
1006         do_div(t, in);
1007         frac_div = t;
1008         pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT |
1009             frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT;
1010 
1011         snd_soc_component_write(component, SGTL5000_CHIP_PLL_CTRL, pll_ctl);
1012         if (div2)
1013             snd_soc_component_update_bits(component,
1014                 SGTL5000_CHIP_CLK_TOP_CTRL,
1015                 SGTL5000_INPUT_FREQ_DIV2,
1016                 SGTL5000_INPUT_FREQ_DIV2);
1017         else
1018             snd_soc_component_update_bits(component,
1019                 SGTL5000_CHIP_CLK_TOP_CTRL,
1020                 SGTL5000_INPUT_FREQ_DIV2,
1021                 0);
1022 
1023         /* power up pll */
1024         snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
1025             SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
1026             SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP);
1027 
1028         /* if using pll, clk_ctrl must be set after pll power up */
1029         snd_soc_component_write(component, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
1030     } else {
1031         /* otherwise, clk_ctrl must be set before pll power down */
1032         snd_soc_component_write(component, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
1033 
1034         /* power down pll */
1035         snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
1036             SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
1037             0);
1038     }
1039 
1040     return 0;
1041 }
1042 
1043 /*
1044  * Set PCM DAI bit size and sample rate.
1045  * input: params_rate, params_fmt
1046  */
1047 static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream,
1048                   struct snd_pcm_hw_params *params,
1049                   struct snd_soc_dai *dai)
1050 {
1051     struct snd_soc_component *component = dai->component;
1052     struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
1053     int channels = params_channels(params);
1054     int i2s_ctl = 0;
1055     int stereo;
1056     int ret;
1057 
1058     /* sysclk should already set */
1059     if (!sgtl5000->sysclk) {
1060         dev_err(component->dev, "%s: set sysclk first!\n", __func__);
1061         return -EFAULT;
1062     }
1063 
1064     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1065         stereo = SGTL5000_DAC_STEREO;
1066     else
1067         stereo = SGTL5000_ADC_STEREO;
1068 
1069     /* set mono to save power */
1070     snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER, stereo,
1071             channels == 1 ? 0 : stereo);
1072 
1073     /* set codec clock base on lrclk */
1074     ret = sgtl5000_set_clock(component, params_rate(params));
1075     if (ret)
1076         return ret;
1077 
1078     /* set i2s data format */
1079     switch (params_width(params)) {
1080     case 16:
1081         if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
1082             return -EINVAL;
1083         i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT;
1084         i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS <<
1085             SGTL5000_I2S_SCLKFREQ_SHIFT;
1086         break;
1087     case 20:
1088         i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT;
1089         i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
1090             SGTL5000_I2S_SCLKFREQ_SHIFT;
1091         break;
1092     case 24:
1093         i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT;
1094         i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
1095             SGTL5000_I2S_SCLKFREQ_SHIFT;
1096         break;
1097     case 32:
1098         if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
1099             return -EINVAL;
1100         i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT;
1101         i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
1102             SGTL5000_I2S_SCLKFREQ_SHIFT;
1103         break;
1104     default:
1105         return -EINVAL;
1106     }
1107 
1108     snd_soc_component_update_bits(component, SGTL5000_CHIP_I2S_CTRL,
1109                 SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK,
1110                 i2s_ctl);
1111 
1112     return 0;
1113 }
1114 
1115 /*
1116  * set dac bias
1117  * common state changes:
1118  * startup:
1119  * off --> standby --> prepare --> on
1120  * standby --> prepare --> on
1121  *
1122  * stop:
1123  * on --> prepare --> standby
1124  */
1125 static int sgtl5000_set_bias_level(struct snd_soc_component *component,
1126                    enum snd_soc_bias_level level)
1127 {
1128     struct sgtl5000_priv *sgtl = snd_soc_component_get_drvdata(component);
1129     int ret;
1130 
1131     switch (level) {
1132     case SND_SOC_BIAS_ON:
1133     case SND_SOC_BIAS_PREPARE:
1134     case SND_SOC_BIAS_STANDBY:
1135         regcache_cache_only(sgtl->regmap, false);
1136         ret = regcache_sync(sgtl->regmap);
1137         if (ret) {
1138             regcache_cache_only(sgtl->regmap, true);
1139             return ret;
1140         }
1141 
1142         snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
1143                     SGTL5000_REFTOP_POWERUP,
1144                     SGTL5000_REFTOP_POWERUP);
1145         break;
1146     case SND_SOC_BIAS_OFF:
1147         regcache_cache_only(sgtl->regmap, true);
1148         snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
1149                     SGTL5000_REFTOP_POWERUP, 0);
1150         break;
1151     }
1152 
1153     return 0;
1154 }
1155 
1156 #define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1157             SNDRV_PCM_FMTBIT_S20_3LE |\
1158             SNDRV_PCM_FMTBIT_S24_LE |\
1159             SNDRV_PCM_FMTBIT_S32_LE)
1160 
1161 static const struct snd_soc_dai_ops sgtl5000_ops = {
1162     .hw_params = sgtl5000_pcm_hw_params,
1163     .mute_stream = sgtl5000_mute_stream,
1164     .set_fmt = sgtl5000_set_dai_fmt,
1165     .set_sysclk = sgtl5000_set_dai_sysclk,
1166     .no_capture_mute = 1,
1167 };
1168 
1169 static struct snd_soc_dai_driver sgtl5000_dai = {
1170     .name = "sgtl5000",
1171     .playback = {
1172         .stream_name = "Playback",
1173         .channels_min = 1,
1174         .channels_max = 2,
1175         /*
1176          * only support 8~48K + 96K,
1177          * TODO modify hw_param to support more
1178          */
1179         .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
1180         .formats = SGTL5000_FORMATS,
1181     },
1182     .capture = {
1183         .stream_name = "Capture",
1184         .channels_min = 1,
1185         .channels_max = 2,
1186         .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
1187         .formats = SGTL5000_FORMATS,
1188     },
1189     .ops = &sgtl5000_ops,
1190     .symmetric_rate = 1,
1191 };
1192 
1193 static bool sgtl5000_volatile(struct device *dev, unsigned int reg)
1194 {
1195     switch (reg) {
1196     case SGTL5000_CHIP_ID:
1197     case SGTL5000_CHIP_ADCDAC_CTRL:
1198     case SGTL5000_CHIP_ANA_STATUS:
1199         return true;
1200     }
1201 
1202     return false;
1203 }
1204 
1205 static bool sgtl5000_readable(struct device *dev, unsigned int reg)
1206 {
1207     switch (reg) {
1208     case SGTL5000_CHIP_ID:
1209     case SGTL5000_CHIP_DIG_POWER:
1210     case SGTL5000_CHIP_CLK_CTRL:
1211     case SGTL5000_CHIP_I2S_CTRL:
1212     case SGTL5000_CHIP_SSS_CTRL:
1213     case SGTL5000_CHIP_ADCDAC_CTRL:
1214     case SGTL5000_CHIP_DAC_VOL:
1215     case SGTL5000_CHIP_PAD_STRENGTH:
1216     case SGTL5000_CHIP_ANA_ADC_CTRL:
1217     case SGTL5000_CHIP_ANA_HP_CTRL:
1218     case SGTL5000_CHIP_ANA_CTRL:
1219     case SGTL5000_CHIP_LINREG_CTRL:
1220     case SGTL5000_CHIP_REF_CTRL:
1221     case SGTL5000_CHIP_MIC_CTRL:
1222     case SGTL5000_CHIP_LINE_OUT_CTRL:
1223     case SGTL5000_CHIP_LINE_OUT_VOL:
1224     case SGTL5000_CHIP_ANA_POWER:
1225     case SGTL5000_CHIP_PLL_CTRL:
1226     case SGTL5000_CHIP_CLK_TOP_CTRL:
1227     case SGTL5000_CHIP_ANA_STATUS:
1228     case SGTL5000_CHIP_SHORT_CTRL:
1229     case SGTL5000_CHIP_ANA_TEST2:
1230     case SGTL5000_DAP_CTRL:
1231     case SGTL5000_DAP_PEQ:
1232     case SGTL5000_DAP_BASS_ENHANCE:
1233     case SGTL5000_DAP_BASS_ENHANCE_CTRL:
1234     case SGTL5000_DAP_AUDIO_EQ:
1235     case SGTL5000_DAP_SURROUND:
1236     case SGTL5000_DAP_FLT_COEF_ACCESS:
1237     case SGTL5000_DAP_COEF_WR_B0_MSB:
1238     case SGTL5000_DAP_COEF_WR_B0_LSB:
1239     case SGTL5000_DAP_EQ_BASS_BAND0:
1240     case SGTL5000_DAP_EQ_BASS_BAND1:
1241     case SGTL5000_DAP_EQ_BASS_BAND2:
1242     case SGTL5000_DAP_EQ_BASS_BAND3:
1243     case SGTL5000_DAP_EQ_BASS_BAND4:
1244     case SGTL5000_DAP_MAIN_CHAN:
1245     case SGTL5000_DAP_MIX_CHAN:
1246     case SGTL5000_DAP_AVC_CTRL:
1247     case SGTL5000_DAP_AVC_THRESHOLD:
1248     case SGTL5000_DAP_AVC_ATTACK:
1249     case SGTL5000_DAP_AVC_DECAY:
1250     case SGTL5000_DAP_COEF_WR_B1_MSB:
1251     case SGTL5000_DAP_COEF_WR_B1_LSB:
1252     case SGTL5000_DAP_COEF_WR_B2_MSB:
1253     case SGTL5000_DAP_COEF_WR_B2_LSB:
1254     case SGTL5000_DAP_COEF_WR_A1_MSB:
1255     case SGTL5000_DAP_COEF_WR_A1_LSB:
1256     case SGTL5000_DAP_COEF_WR_A2_MSB:
1257     case SGTL5000_DAP_COEF_WR_A2_LSB:
1258         return true;
1259 
1260     default:
1261         return false;
1262     }
1263 }
1264 
1265 /*
1266  * This precalculated table contains all (vag_val * 100 / lo_calcntrl) results
1267  * to select an appropriate lo_vol_* in SGTL5000_CHIP_LINE_OUT_VOL
1268  * The calculatation was done for all possible register values which
1269  * is the array index and the following formula: 10^((idx−15)/40) * 100
1270  */
1271 static const u8 vol_quot_table[] = {
1272     42, 45, 47, 50, 53, 56, 60, 63,
1273     67, 71, 75, 79, 84, 89, 94, 100,
1274     106, 112, 119, 126, 133, 141, 150, 158,
1275     168, 178, 188, 200, 211, 224, 237, 251
1276 };
1277 
1278 /*
1279  * sgtl5000 has 3 internal power supplies:
1280  * 1. VAG, normally set to vdda/2
1281  * 2. charge pump, set to different value
1282  *  according to voltage of vdda and vddio
1283  * 3. line out VAG, normally set to vddio/2
1284  *
1285  * and should be set according to:
1286  * 1. vddd provided by external or not
1287  * 2. vdda and vddio voltage value. > 3.1v or not
1288  */
1289 static int sgtl5000_set_power_regs(struct snd_soc_component *component)
1290 {
1291     int vddd;
1292     int vdda;
1293     int vddio;
1294     u16 ana_pwr;
1295     u16 lreg_ctrl;
1296     int vag;
1297     int lo_vag;
1298     int vol_quot;
1299     int lo_vol;
1300     size_t i;
1301     struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
1302 
1303     vdda  = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer);
1304     vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer);
1305     vddd  = (sgtl5000->num_supplies > VDDD)
1306         ? regulator_get_voltage(sgtl5000->supplies[VDDD].consumer)
1307         : LDO_VOLTAGE;
1308 
1309     vdda  = vdda / 1000;
1310     vddio = vddio / 1000;
1311     vddd  = vddd / 1000;
1312 
1313     if (vdda <= 0 || vddio <= 0 || vddd < 0) {
1314         dev_err(component->dev, "regulator voltage not set correctly\n");
1315 
1316         return -EINVAL;
1317     }
1318 
1319     /* according to datasheet, maximum voltage of supplies */
1320     if (vdda > 3600 || vddio > 3600 || vddd > 1980) {
1321         dev_err(component->dev,
1322             "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n",
1323             vdda, vddio, vddd);
1324 
1325         return -EINVAL;
1326     }
1327 
1328     /* reset value */
1329     ana_pwr = snd_soc_component_read(component, SGTL5000_CHIP_ANA_POWER);
1330     ana_pwr |= SGTL5000_DAC_STEREO |
1331             SGTL5000_ADC_STEREO |
1332             SGTL5000_REFTOP_POWERUP;
1333     lreg_ctrl = snd_soc_component_read(component, SGTL5000_CHIP_LINREG_CTRL);
1334 
1335     if (vddio < 3100 && vdda < 3100) {
1336         /* enable internal oscillator used for charge pump */
1337         snd_soc_component_update_bits(component, SGTL5000_CHIP_CLK_TOP_CTRL,
1338                     SGTL5000_INT_OSC_EN,
1339                     SGTL5000_INT_OSC_EN);
1340         /* Enable VDDC charge pump */
1341         ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP;
1342     } else {
1343         ana_pwr &= ~SGTL5000_VDDC_CHRGPMP_POWERUP;
1344         /*
1345          * if vddio == vdda the source of charge pump should be
1346          * assigned manually to VDDIO
1347          */
1348         if (regulator_is_equal(sgtl5000->supplies[VDDA].consumer,
1349                        sgtl5000->supplies[VDDIO].consumer)) {
1350             lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD;
1351             lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO <<
1352                     SGTL5000_VDDC_MAN_ASSN_SHIFT;
1353         }
1354     }
1355 
1356     snd_soc_component_write(component, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl);
1357 
1358     snd_soc_component_write(component, SGTL5000_CHIP_ANA_POWER, ana_pwr);
1359 
1360     /*
1361      * set ADC/DAC VAG to vdda / 2,
1362      * should stay in range (0.8v, 1.575v)
1363      */
1364     vag = vdda / 2;
1365     if (vag <= SGTL5000_ANA_GND_BASE)
1366         vag = 0;
1367     else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP *
1368          (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT))
1369         vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT;
1370     else
1371         vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP;
1372 
1373     snd_soc_component_update_bits(component, SGTL5000_CHIP_REF_CTRL,
1374             SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT);
1375 
1376     /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */
1377     lo_vag = vddio / 2;
1378     if (lo_vag <= SGTL5000_LINE_OUT_GND_BASE)
1379         lo_vag = 0;
1380     else if (lo_vag >= SGTL5000_LINE_OUT_GND_BASE +
1381         SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX)
1382         lo_vag = SGTL5000_LINE_OUT_GND_MAX;
1383     else
1384         lo_vag = (lo_vag - SGTL5000_LINE_OUT_GND_BASE) /
1385             SGTL5000_LINE_OUT_GND_STP;
1386 
1387     snd_soc_component_update_bits(component, SGTL5000_CHIP_LINE_OUT_CTRL,
1388             SGTL5000_LINE_OUT_CURRENT_MASK |
1389             SGTL5000_LINE_OUT_GND_MASK,
1390             lo_vag << SGTL5000_LINE_OUT_GND_SHIFT |
1391             SGTL5000_LINE_OUT_CURRENT_360u <<
1392                 SGTL5000_LINE_OUT_CURRENT_SHIFT);
1393 
1394     /*
1395      * Set lineout output level in range (0..31)
1396      * the same value is used for right and left channel
1397      *
1398      * Searching for a suitable index solving this formula:
1399      * idx = 40 * log10(vag_val / lo_cagcntrl) + 15
1400      */
1401     vol_quot = lo_vag ? (vag * 100) / lo_vag : 0;
1402     lo_vol = 0;
1403     for (i = 0; i < ARRAY_SIZE(vol_quot_table); i++) {
1404         if (vol_quot >= vol_quot_table[i])
1405             lo_vol = i;
1406         else
1407             break;
1408     }
1409 
1410     snd_soc_component_update_bits(component, SGTL5000_CHIP_LINE_OUT_VOL,
1411         SGTL5000_LINE_OUT_VOL_RIGHT_MASK |
1412         SGTL5000_LINE_OUT_VOL_LEFT_MASK,
1413         lo_vol << SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT |
1414         lo_vol << SGTL5000_LINE_OUT_VOL_LEFT_SHIFT);
1415 
1416     return 0;
1417 }
1418 
1419 static int sgtl5000_enable_regulators(struct i2c_client *client)
1420 {
1421     int ret;
1422     int i;
1423     int external_vddd = 0;
1424     struct regulator *vddd;
1425     struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
1426 
1427     for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++)
1428         sgtl5000->supplies[i].supply = supply_names[i];
1429 
1430     vddd = regulator_get_optional(&client->dev, "VDDD");
1431     if (IS_ERR(vddd)) {
1432         /* See if it's just not registered yet */
1433         if (PTR_ERR(vddd) == -EPROBE_DEFER)
1434             return -EPROBE_DEFER;
1435     } else {
1436         external_vddd = 1;
1437         regulator_put(vddd);
1438     }
1439 
1440     sgtl5000->num_supplies = ARRAY_SIZE(sgtl5000->supplies)
1441                  - 1 + external_vddd;
1442     ret = regulator_bulk_get(&client->dev, sgtl5000->num_supplies,
1443                  sgtl5000->supplies);
1444     if (ret)
1445         return ret;
1446 
1447     ret = regulator_bulk_enable(sgtl5000->num_supplies,
1448                     sgtl5000->supplies);
1449     if (!ret)
1450         usleep_range(10, 20);
1451     else
1452         regulator_bulk_free(sgtl5000->num_supplies,
1453                     sgtl5000->supplies);
1454 
1455     return ret;
1456 }
1457 
1458 static int sgtl5000_probe(struct snd_soc_component *component)
1459 {
1460     int ret;
1461     u16 reg;
1462     struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
1463     unsigned int zcd_mask = SGTL5000_HP_ZCD_EN | SGTL5000_ADC_ZCD_EN;
1464 
1465     /* power up sgtl5000 */
1466     ret = sgtl5000_set_power_regs(component);
1467     if (ret)
1468         goto err;
1469 
1470     /* enable small pop, introduce 400ms delay in turning off */
1471     snd_soc_component_update_bits(component, SGTL5000_CHIP_REF_CTRL,
1472                 SGTL5000_SMALL_POP, SGTL5000_SMALL_POP);
1473 
1474     /* disable short cut detector */
1475     snd_soc_component_write(component, SGTL5000_CHIP_SHORT_CTRL, 0);
1476 
1477     snd_soc_component_write(component, SGTL5000_CHIP_DIG_POWER,
1478             SGTL5000_ADC_EN | SGTL5000_DAC_EN);
1479 
1480     /* enable dac volume ramp by default */
1481     snd_soc_component_write(component, SGTL5000_CHIP_ADCDAC_CTRL,
1482             SGTL5000_DAC_VOL_RAMP_EN |
1483             SGTL5000_DAC_MUTE_RIGHT |
1484             SGTL5000_DAC_MUTE_LEFT);
1485 
1486     reg = ((sgtl5000->lrclk_strength) << SGTL5000_PAD_I2S_LRCLK_SHIFT |
1487            (sgtl5000->sclk_strength) << SGTL5000_PAD_I2S_SCLK_SHIFT |
1488            0x1f);
1489     snd_soc_component_write(component, SGTL5000_CHIP_PAD_STRENGTH, reg);
1490 
1491     snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_CTRL,
1492         zcd_mask, zcd_mask);
1493 
1494     snd_soc_component_update_bits(component, SGTL5000_CHIP_MIC_CTRL,
1495             SGTL5000_BIAS_R_MASK,
1496             sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT);
1497 
1498     snd_soc_component_update_bits(component, SGTL5000_CHIP_MIC_CTRL,
1499             SGTL5000_BIAS_VOLT_MASK,
1500             sgtl5000->micbias_voltage << SGTL5000_BIAS_VOLT_SHIFT);
1501     /*
1502      * enable DAP Graphic EQ
1503      * TODO:
1504      * Add control for changing between PEQ/Tone Control/GEQ
1505      */
1506     snd_soc_component_write(component, SGTL5000_DAP_AUDIO_EQ, SGTL5000_DAP_SEL_GEQ);
1507 
1508     /* Unmute DAC after start */
1509     snd_soc_component_update_bits(component, SGTL5000_CHIP_ADCDAC_CTRL,
1510         SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT, 0);
1511 
1512     return 0;
1513 
1514 err:
1515     return ret;
1516 }
1517 
1518 static int sgtl5000_of_xlate_dai_id(struct snd_soc_component *component,
1519                     struct device_node *endpoint)
1520 {
1521     /* return dai id 0, whatever the endpoint index */
1522     return 0;
1523 }
1524 
1525 static const struct snd_soc_component_driver sgtl5000_driver = {
1526     .probe          = sgtl5000_probe,
1527     .set_bias_level     = sgtl5000_set_bias_level,
1528     .controls       = sgtl5000_snd_controls,
1529     .num_controls       = ARRAY_SIZE(sgtl5000_snd_controls),
1530     .dapm_widgets       = sgtl5000_dapm_widgets,
1531     .num_dapm_widgets   = ARRAY_SIZE(sgtl5000_dapm_widgets),
1532     .dapm_routes        = sgtl5000_dapm_routes,
1533     .num_dapm_routes    = ARRAY_SIZE(sgtl5000_dapm_routes),
1534     .of_xlate_dai_id    = sgtl5000_of_xlate_dai_id,
1535     .suspend_bias_off   = 1,
1536     .idle_bias_on       = 1,
1537     .use_pmdown_time    = 1,
1538     .endianness     = 1,
1539 };
1540 
1541 static const struct regmap_config sgtl5000_regmap = {
1542     .reg_bits = 16,
1543     .val_bits = 16,
1544     .reg_stride = 2,
1545 
1546     .max_register = SGTL5000_MAX_REG_OFFSET,
1547     .volatile_reg = sgtl5000_volatile,
1548     .readable_reg = sgtl5000_readable,
1549 
1550     .cache_type = REGCACHE_RBTREE,
1551     .reg_defaults = sgtl5000_reg_defaults,
1552     .num_reg_defaults = ARRAY_SIZE(sgtl5000_reg_defaults),
1553 };
1554 
1555 /*
1556  * Write all the default values from sgtl5000_reg_defaults[] array into the
1557  * sgtl5000 registers, to make sure we always start with the sane registers
1558  * values as stated in the datasheet.
1559  *
1560  * Since sgtl5000 does not have a reset line, nor a reset command in software,
1561  * we follow this approach to guarantee we always start from the default values
1562  * and avoid problems like, not being able to probe after an audio playback
1563  * followed by a system reset or a 'reboot' command in Linux
1564  */
1565 static void sgtl5000_fill_defaults(struct i2c_client *client)
1566 {
1567     struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
1568     int i, ret, val, index;
1569 
1570     for (i = 0; i < ARRAY_SIZE(sgtl5000_reg_defaults); i++) {
1571         val = sgtl5000_reg_defaults[i].def;
1572         index = sgtl5000_reg_defaults[i].reg;
1573         ret = regmap_write(sgtl5000->regmap, index, val);
1574         if (ret)
1575             dev_err(&client->dev,
1576                 "%s: error %d setting reg 0x%02x to 0x%04x\n",
1577                 __func__, ret, index, val);
1578     }
1579 }
1580 
1581 static int sgtl5000_i2c_probe(struct i2c_client *client)
1582 {
1583     struct sgtl5000_priv *sgtl5000;
1584     int ret, reg, rev;
1585     struct device_node *np = client->dev.of_node;
1586     u32 value;
1587     u16 ana_pwr;
1588 
1589     sgtl5000 = devm_kzalloc(&client->dev, sizeof(*sgtl5000), GFP_KERNEL);
1590     if (!sgtl5000)
1591         return -ENOMEM;
1592 
1593     i2c_set_clientdata(client, sgtl5000);
1594 
1595     ret = sgtl5000_enable_regulators(client);
1596     if (ret)
1597         return ret;
1598 
1599     sgtl5000->regmap = devm_regmap_init_i2c(client, &sgtl5000_regmap);
1600     if (IS_ERR(sgtl5000->regmap)) {
1601         ret = PTR_ERR(sgtl5000->regmap);
1602         dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret);
1603         goto disable_regs;
1604     }
1605 
1606     sgtl5000->mclk = devm_clk_get(&client->dev, NULL);
1607     if (IS_ERR(sgtl5000->mclk)) {
1608         ret = PTR_ERR(sgtl5000->mclk);
1609         /* Defer the probe to see if the clk will be provided later */
1610         if (ret == -ENOENT)
1611             ret = -EPROBE_DEFER;
1612 
1613         dev_err_probe(&client->dev, ret, "Failed to get mclock\n");
1614 
1615         goto disable_regs;
1616     }
1617 
1618     ret = clk_prepare_enable(sgtl5000->mclk);
1619     if (ret) {
1620         dev_err(&client->dev, "Error enabling clock %d\n", ret);
1621         goto disable_regs;
1622     }
1623 
1624     /* Need 8 clocks before I2C accesses */
1625     udelay(1);
1626 
1627     /* read chip information */
1628     ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, &reg);
1629     if (ret) {
1630         dev_err(&client->dev, "Error reading chip id %d\n", ret);
1631         goto disable_clk;
1632     }
1633 
1634     if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) !=
1635         SGTL5000_PARTID_PART_ID) {
1636         dev_err(&client->dev,
1637             "Device with ID register %x is not a sgtl5000\n", reg);
1638         ret = -ENODEV;
1639         goto disable_clk;
1640     }
1641 
1642     rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT;
1643     dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev);
1644     sgtl5000->revision = rev;
1645 
1646     /* reconfigure the clocks in case we're using the PLL */
1647     ret = regmap_write(sgtl5000->regmap,
1648                SGTL5000_CHIP_CLK_CTRL,
1649                SGTL5000_CHIP_CLK_CTRL_DEFAULT);
1650     if (ret)
1651         dev_err(&client->dev,
1652             "Error %d initializing CHIP_CLK_CTRL\n", ret);
1653 
1654     /* Mute everything to avoid pop from the following power-up */
1655     ret = regmap_write(sgtl5000->regmap, SGTL5000_CHIP_ANA_CTRL,
1656                SGTL5000_CHIP_ANA_CTRL_DEFAULT);
1657     if (ret) {
1658         dev_err(&client->dev,
1659             "Error %d muting outputs via CHIP_ANA_CTRL\n", ret);
1660         goto disable_clk;
1661     }
1662 
1663     /*
1664      * If VAG is powered-on (e.g. from previous boot), it would be disabled
1665      * by the write to ANA_POWER in later steps of the probe code. This
1666      * may create a loud pop even with all outputs muted. The proper way
1667      * to circumvent this is disabling the bit first and waiting the proper
1668      * cool-down time.
1669      */
1670     ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ANA_POWER, &value);
1671     if (ret) {
1672         dev_err(&client->dev, "Failed to read ANA_POWER: %d\n", ret);
1673         goto disable_clk;
1674     }
1675     if (value & SGTL5000_VAG_POWERUP) {
1676         ret = regmap_update_bits(sgtl5000->regmap,
1677                      SGTL5000_CHIP_ANA_POWER,
1678                      SGTL5000_VAG_POWERUP,
1679                      0);
1680         if (ret) {
1681             dev_err(&client->dev, "Error %d disabling VAG\n", ret);
1682             goto disable_clk;
1683         }
1684 
1685         msleep(SGTL5000_VAG_POWERDOWN_DELAY);
1686     }
1687 
1688     /* Follow section 2.2.1.1 of AN3663 */
1689     ana_pwr = SGTL5000_ANA_POWER_DEFAULT;
1690     if (sgtl5000->num_supplies <= VDDD) {
1691         /* internal VDDD at 1.2V */
1692         ret = regmap_update_bits(sgtl5000->regmap,
1693                      SGTL5000_CHIP_LINREG_CTRL,
1694                      SGTL5000_LINREG_VDDD_MASK,
1695                      LINREG_VDDD);
1696         if (ret)
1697             dev_err(&client->dev,
1698                 "Error %d setting LINREG_VDDD\n", ret);
1699 
1700         ana_pwr |= SGTL5000_LINEREG_D_POWERUP;
1701         dev_info(&client->dev,
1702              "Using internal LDO instead of VDDD: check ER1 erratum\n");
1703     } else {
1704         /* using external LDO for VDDD
1705          * Clear startup powerup and simple powerup
1706          * bits to save power
1707          */
1708         ana_pwr &= ~(SGTL5000_STARTUP_POWERUP
1709                  | SGTL5000_LINREG_SIMPLE_POWERUP);
1710         dev_dbg(&client->dev, "Using external VDDD\n");
1711     }
1712     ret = regmap_write(sgtl5000->regmap, SGTL5000_CHIP_ANA_POWER, ana_pwr);
1713     if (ret)
1714         dev_err(&client->dev,
1715             "Error %d setting CHIP_ANA_POWER to %04x\n",
1716             ret, ana_pwr);
1717 
1718     if (np) {
1719         if (!of_property_read_u32(np,
1720             "micbias-resistor-k-ohms", &value)) {
1721             switch (value) {
1722             case SGTL5000_MICBIAS_OFF:
1723                 sgtl5000->micbias_resistor = 0;
1724                 break;
1725             case SGTL5000_MICBIAS_2K:
1726                 sgtl5000->micbias_resistor = 1;
1727                 break;
1728             case SGTL5000_MICBIAS_4K:
1729                 sgtl5000->micbias_resistor = 2;
1730                 break;
1731             case SGTL5000_MICBIAS_8K:
1732                 sgtl5000->micbias_resistor = 3;
1733                 break;
1734             default:
1735                 sgtl5000->micbias_resistor = 2;
1736                 dev_err(&client->dev,
1737                     "Unsuitable MicBias resistor\n");
1738             }
1739         } else {
1740             /* default is 4Kohms */
1741             sgtl5000->micbias_resistor = 2;
1742         }
1743         if (!of_property_read_u32(np,
1744             "micbias-voltage-m-volts", &value)) {
1745             /* 1250mV => 0 */
1746             /* steps of 250mV */
1747             if ((value >= 1250) && (value <= 3000))
1748                 sgtl5000->micbias_voltage = (value / 250) - 5;
1749             else {
1750                 sgtl5000->micbias_voltage = 0;
1751                 dev_err(&client->dev,
1752                     "Unsuitable MicBias voltage\n");
1753             }
1754         } else {
1755             sgtl5000->micbias_voltage = 0;
1756         }
1757     }
1758 
1759     sgtl5000->lrclk_strength = I2S_LRCLK_STRENGTH_LOW;
1760     if (!of_property_read_u32(np, "lrclk-strength", &value)) {
1761         if (value > I2S_LRCLK_STRENGTH_HIGH)
1762             value = I2S_LRCLK_STRENGTH_LOW;
1763         sgtl5000->lrclk_strength = value;
1764     }
1765 
1766     sgtl5000->sclk_strength = I2S_SCLK_STRENGTH_LOW;
1767     if (!of_property_read_u32(np, "sclk-strength", &value)) {
1768         if (value > I2S_SCLK_STRENGTH_HIGH)
1769             value = I2S_SCLK_STRENGTH_LOW;
1770         sgtl5000->sclk_strength = value;
1771     }
1772 
1773     /* Ensure sgtl5000 will start with sane register values */
1774     sgtl5000_fill_defaults(client);
1775 
1776     ret = devm_snd_soc_register_component(&client->dev,
1777             &sgtl5000_driver, &sgtl5000_dai, 1);
1778     if (ret)
1779         goto disable_clk;
1780 
1781     return 0;
1782 
1783 disable_clk:
1784     clk_disable_unprepare(sgtl5000->mclk);
1785 
1786 disable_regs:
1787     regulator_bulk_disable(sgtl5000->num_supplies, sgtl5000->supplies);
1788     regulator_bulk_free(sgtl5000->num_supplies, sgtl5000->supplies);
1789 
1790     return ret;
1791 }
1792 
1793 static int sgtl5000_i2c_remove(struct i2c_client *client)
1794 {
1795     struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
1796 
1797     regmap_write(sgtl5000->regmap, SGTL5000_CHIP_DIG_POWER, SGTL5000_DIG_POWER_DEFAULT);
1798     regmap_write(sgtl5000->regmap, SGTL5000_CHIP_ANA_POWER, SGTL5000_ANA_POWER_DEFAULT);
1799 
1800     clk_disable_unprepare(sgtl5000->mclk);
1801     regulator_bulk_disable(sgtl5000->num_supplies, sgtl5000->supplies);
1802     regulator_bulk_free(sgtl5000->num_supplies, sgtl5000->supplies);
1803 
1804     return 0;
1805 }
1806 
1807 static void sgtl5000_i2c_shutdown(struct i2c_client *client)
1808 {
1809     sgtl5000_i2c_remove(client);
1810 }
1811 
1812 static const struct i2c_device_id sgtl5000_id[] = {
1813     {"sgtl5000", 0},
1814     {},
1815 };
1816 
1817 MODULE_DEVICE_TABLE(i2c, sgtl5000_id);
1818 
1819 static const struct of_device_id sgtl5000_dt_ids[] = {
1820     { .compatible = "fsl,sgtl5000", },
1821     { /* sentinel */ }
1822 };
1823 MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids);
1824 
1825 static struct i2c_driver sgtl5000_i2c_driver = {
1826     .driver = {
1827         .name = "sgtl5000",
1828         .of_match_table = sgtl5000_dt_ids,
1829     },
1830     .probe_new = sgtl5000_i2c_probe,
1831     .remove = sgtl5000_i2c_remove,
1832     .shutdown = sgtl5000_i2c_shutdown,
1833     .id_table = sgtl5000_id,
1834 };
1835 
1836 module_i2c_driver(sgtl5000_i2c_driver);
1837 
1838 MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver");
1839 MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>");
1840 MODULE_LICENSE("GPL");
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