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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 
0003 #include <linux/bits.h>
0004 #include <linux/bitfield.h>
0005 #include <linux/delay.h>
0006 #include <linux/gpio/consumer.h>
0007 #include <linux/i2c.h>
0008 #include <linux/kernel.h>
0009 #include <linux/module.h>
0010 #include <linux/pm_runtime.h>
0011 #include <linux/regmap.h>
0012 #include <linux/regulator/consumer.h>
0013 #include <sound/pcm.h>
0014 #include <sound/pcm_params.h>
0015 #include <sound/soc.h>
0016 #include <sound/tlv.h>
0017 
0018 #define RT9120_REG_DEVID    0x00
0019 #define RT9120_REG_I2SFMT   0x02
0020 #define RT9120_REG_I2SWL    0x03
0021 #define RT9120_REG_SDIOSEL  0x04
0022 #define RT9120_REG_SYSCTL   0x05
0023 #define RT9120_REG_SPKGAIN  0x07
0024 #define RT9120_REG_VOLRAMP  0x0A
0025 #define RT9120_REG_ERRRPT   0x10
0026 #define RT9120_REG_MSVOL    0x20
0027 #define RT9120_REG_SWRESET  0x40
0028 #define RT9120_REG_INTERCFG 0x63
0029 #define RT9120_REG_INTERNAL0    0x65
0030 #define RT9120_REG_INTERNAL1    0x69
0031 #define RT9120_REG_UVPOPT   0x6C
0032 #define RT9120_REG_DIGCFG   0xF8
0033 
0034 #define RT9120_VID_MASK     GENMASK(15, 8)
0035 #define RT9120_SWRST_MASK   BIT(7)
0036 #define RT9120_MUTE_MASK    GENMASK(5, 4)
0037 #define RT9120_I2SFMT_MASK  GENMASK(4, 2)
0038 #define RT9120_I2SFMT_SHIFT 2
0039 #define RT9120_CFG_FMT_I2S  0
0040 #define RT9120_CFG_FMT_LEFTJ    1
0041 #define RT9120_CFG_FMT_RIGHTJ   2
0042 #define RT9120_CFG_FMT_DSPA 3
0043 #define RT9120_CFG_FMT_DSPB 7
0044 #define RT9120_AUDBIT_MASK  GENMASK(1, 0)
0045 #define RT9120_CFG_AUDBIT_16    0
0046 #define RT9120_CFG_AUDBIT_20    1
0047 #define RT9120_CFG_AUDBIT_24    2
0048 #define RT9120_AUDWL_MASK   GENMASK(5, 0)
0049 #define RT9120_CFG_WORDLEN_16   16
0050 #define RT9120_CFG_WORDLEN_24   24
0051 #define RT9120_CFG_WORDLEN_32   32
0052 #define RT9120_DVDD_UVSEL_MASK  GENMASK(5, 4)
0053 #define RT9120_AUTOSYNC_MASK    BIT(6)
0054 
0055 #define RT9120_VENDOR_ID    0x42
0056 #define RT9120S_VENDOR_ID   0x43
0057 #define RT9120_RESET_WAITMS 20
0058 #define RT9120_CHIPON_WAITMS    20
0059 #define RT9120_AMPON_WAITMS 50
0060 #define RT9120_AMPOFF_WAITMS    100
0061 #define RT9120_LVAPP_THRESUV    2000000
0062 
0063 /* 8000 to 192000 supported , only 176400 not support */
0064 #define RT9120_RATES_MASK   (SNDRV_PCM_RATE_8000_192000 &\
0065                  ~SNDRV_PCM_RATE_176400)
0066 #define RT9120_FMTS_MASK    (SNDRV_PCM_FMTBIT_S16_LE |\
0067                  SNDRV_PCM_FMTBIT_S24_LE |\
0068                  SNDRV_PCM_FMTBIT_S32_LE)
0069 
0070 enum {
0071     CHIP_IDX_RT9120 = 0,
0072     CHIP_IDX_RT9120S,
0073     CHIP_IDX_MAX
0074 };
0075 
0076 struct rt9120_data {
0077     struct device *dev;
0078     struct regmap *regmap;
0079     struct gpio_desc *pwdnn_gpio;
0080     int chip_idx;
0081 };
0082 
0083 /* 11bit [min,max,step] = [-103.9375dB, 24dB, 0.0625dB] */
0084 static const DECLARE_TLV_DB_SCALE(digital_tlv, -1039375, 625, 1);
0085 
0086 /* {6, 8, 10, 12, 13, 14, 15, 16}dB */
0087 static const DECLARE_TLV_DB_RANGE(classd_tlv,
0088     0, 3, TLV_DB_SCALE_ITEM(600, 200, 0),
0089     4, 7, TLV_DB_SCALE_ITEM(1300, 100, 0)
0090 );
0091 
0092 static const char * const sdo_select_text[] = {
0093     "None", "INTF", "Final", "RMS Detect"
0094 };
0095 
0096 static const struct soc_enum sdo_select_enum =
0097     SOC_ENUM_SINGLE(RT9120_REG_SDIOSEL, 4, ARRAY_SIZE(sdo_select_text),
0098             sdo_select_text);
0099 
0100 static const struct snd_kcontrol_new rt9120_snd_controls[] = {
0101     SOC_SINGLE_TLV("MS Volume", RT9120_REG_MSVOL, 0, 2047, 1, digital_tlv),
0102     SOC_SINGLE_TLV("SPK Gain Volume", RT9120_REG_SPKGAIN, 0, 7, 0, classd_tlv),
0103     SOC_SINGLE("PBTL Switch", RT9120_REG_SYSCTL, 3, 1, 0),
0104     SOC_ENUM("SDO Select", sdo_select_enum),
0105 };
0106 
0107 static int internal_power_event(struct snd_soc_dapm_widget *w,
0108                 struct snd_kcontrol *kcontrol, int event)
0109 {
0110     struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
0111 
0112     switch (event) {
0113     case SND_SOC_DAPM_PRE_PMU:
0114         snd_soc_component_write(comp, RT9120_REG_ERRRPT, 0);
0115         break;
0116     case SND_SOC_DAPM_POST_PMU:
0117         msleep(RT9120_AMPON_WAITMS);
0118         break;
0119     case SND_SOC_DAPM_POST_PMD:
0120         msleep(RT9120_AMPOFF_WAITMS);
0121         break;
0122     default:
0123         break;
0124     }
0125 
0126     return 0;
0127 }
0128 
0129 static const struct snd_soc_dapm_widget rt9120_dapm_widgets[] = {
0130     SND_SOC_DAPM_MIXER("DMIX", SND_SOC_NOPM, 0, 0, NULL, 0),
0131     SND_SOC_DAPM_DAC("LDAC", NULL, SND_SOC_NOPM, 0, 0),
0132     SND_SOC_DAPM_DAC("RDAC", NULL, SND_SOC_NOPM, 0, 0),
0133     SND_SOC_DAPM_SUPPLY("PWND", RT9120_REG_SYSCTL, 6, 1,
0134                 internal_power_event, SND_SOC_DAPM_PRE_PMU |
0135                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
0136     SND_SOC_DAPM_PGA("SPKL PA", SND_SOC_NOPM, 0, 0, NULL, 0),
0137     SND_SOC_DAPM_PGA("SPKR PA", SND_SOC_NOPM, 0, 0, NULL, 0),
0138     SND_SOC_DAPM_OUTPUT("SPKL"),
0139     SND_SOC_DAPM_OUTPUT("SPKR"),
0140 };
0141 
0142 static const struct snd_soc_dapm_route rt9120_dapm_routes[] = {
0143     { "DMIX", NULL, "AIF Playback" },
0144     /* SPKL */
0145     { "LDAC", NULL, "PWND" },
0146     { "LDAC", NULL, "DMIX" },
0147     { "SPKL PA", NULL, "LDAC" },
0148     { "SPKL", NULL, "SPKL PA" },
0149     /* SPKR */
0150     { "RDAC", NULL, "PWND" },
0151     { "RDAC", NULL, "DMIX" },
0152     { "SPKR PA", NULL, "RDAC" },
0153     { "SPKR", NULL, "SPKR PA" },
0154     /* Cap */
0155     { "AIF Capture", NULL, "LDAC" },
0156     { "AIF Capture", NULL, "RDAC" },
0157 };
0158 
0159 static int rt9120_codec_probe(struct snd_soc_component *comp)
0160 {
0161     struct rt9120_data *data = snd_soc_component_get_drvdata(comp);
0162 
0163     snd_soc_component_init_regmap(comp, data->regmap);
0164 
0165     pm_runtime_get_sync(comp->dev);
0166 
0167     /* Internal setting */
0168     if (data->chip_idx == CHIP_IDX_RT9120S) {
0169         snd_soc_component_write(comp, RT9120_REG_INTERCFG, 0xde);
0170         snd_soc_component_write(comp, RT9120_REG_INTERNAL0, 0x66);
0171     } else
0172         snd_soc_component_write(comp, RT9120_REG_INTERNAL0, 0x04);
0173 
0174     pm_runtime_mark_last_busy(comp->dev);
0175     pm_runtime_put(comp->dev);
0176 
0177     return 0;
0178 }
0179 
0180 static const struct snd_soc_component_driver rt9120_component_driver = {
0181     .probe = rt9120_codec_probe,
0182     .controls = rt9120_snd_controls,
0183     .num_controls = ARRAY_SIZE(rt9120_snd_controls),
0184     .dapm_widgets = rt9120_dapm_widgets,
0185     .num_dapm_widgets = ARRAY_SIZE(rt9120_dapm_widgets),
0186     .dapm_routes = rt9120_dapm_routes,
0187     .num_dapm_routes = ARRAY_SIZE(rt9120_dapm_routes),
0188     .endianness = 1,
0189 };
0190 
0191 static int rt9120_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
0192 {
0193     struct snd_soc_component *comp = dai->component;
0194     unsigned int format;
0195 
0196     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0197     case SND_SOC_DAIFMT_I2S:
0198         format = RT9120_CFG_FMT_I2S;
0199         break;
0200     case SND_SOC_DAIFMT_LEFT_J:
0201         format = RT9120_CFG_FMT_LEFTJ;
0202         break;
0203     case SND_SOC_DAIFMT_RIGHT_J:
0204         format = RT9120_CFG_FMT_RIGHTJ;
0205         break;
0206     case SND_SOC_DAIFMT_DSP_A:
0207         format = RT9120_CFG_FMT_DSPA;
0208         break;
0209     case SND_SOC_DAIFMT_DSP_B:
0210         format = RT9120_CFG_FMT_DSPB;
0211         break;
0212     default:
0213         dev_err(dai->dev, "Unknown dai format\n");
0214         return -EINVAL;
0215     }
0216 
0217     snd_soc_component_update_bits(comp, RT9120_REG_I2SFMT,
0218                       RT9120_I2SFMT_MASK,
0219                       format << RT9120_I2SFMT_SHIFT);
0220     return 0;
0221 }
0222 
0223 static int rt9120_hw_params(struct snd_pcm_substream *substream,
0224                 struct snd_pcm_hw_params *param,
0225                 struct snd_soc_dai *dai)
0226 {
0227     struct snd_soc_component *comp = dai->component;
0228     unsigned int param_width, param_slot_width, auto_sync;
0229     int width, fs;
0230 
0231     switch (width = params_width(param)) {
0232     case 16:
0233         param_width = RT9120_CFG_AUDBIT_16;
0234         break;
0235     case 20:
0236         param_width = RT9120_CFG_AUDBIT_20;
0237         break;
0238     case 24:
0239     case 32:
0240         param_width = RT9120_CFG_AUDBIT_24;
0241         break;
0242     default:
0243         dev_err(dai->dev, "Unsupported data width [%d]\n", width);
0244         return -EINVAL;
0245     }
0246 
0247     snd_soc_component_update_bits(comp, RT9120_REG_I2SFMT,
0248                       RT9120_AUDBIT_MASK, param_width);
0249 
0250     switch (width = params_physical_width(param)) {
0251     case 16:
0252         param_slot_width = RT9120_CFG_WORDLEN_16;
0253         break;
0254     case 24:
0255         param_slot_width = RT9120_CFG_WORDLEN_24;
0256         break;
0257     case 32:
0258         param_slot_width = RT9120_CFG_WORDLEN_32;
0259         break;
0260     default:
0261         dev_err(dai->dev, "Unsupported slot width [%d]\n", width);
0262         return -EINVAL;
0263     }
0264 
0265     snd_soc_component_update_bits(comp, RT9120_REG_I2SWL,
0266                       RT9120_AUDWL_MASK, param_slot_width);
0267 
0268     fs = width * params_channels(param);
0269     /* If fs is divided by 48, disable auto sync */
0270     if (fs % 48 == 0)
0271         auto_sync = 0;
0272     else
0273         auto_sync = RT9120_AUTOSYNC_MASK;
0274 
0275     snd_soc_component_update_bits(comp, RT9120_REG_DIGCFG,
0276                       RT9120_AUTOSYNC_MASK, auto_sync);
0277     return 0;
0278 }
0279 
0280 static const struct snd_soc_dai_ops rt9120_dai_ops = {
0281     .set_fmt = rt9120_set_fmt,
0282     .hw_params = rt9120_hw_params,
0283 };
0284 
0285 static struct snd_soc_dai_driver rt9120_dai = {
0286     .name = "rt9120_aif",
0287     .playback = {
0288         .stream_name = "AIF Playback",
0289         .rates = RT9120_RATES_MASK,
0290         .formats = RT9120_FMTS_MASK,
0291         .rate_max = 192000,
0292         .rate_min = 8000,
0293         .channels_min = 1,
0294         .channels_max = 2,
0295     },
0296     .capture = {
0297         .stream_name = "AIF Capture",
0298         .rates = RT9120_RATES_MASK,
0299         .formats = RT9120_FMTS_MASK,
0300         .rate_max = 192000,
0301         .rate_min = 8000,
0302         .channels_min = 1,
0303         .channels_max = 2,
0304     },
0305     .ops = &rt9120_dai_ops,
0306     .symmetric_rate = 1,
0307     .symmetric_sample_bits = 1,
0308 };
0309 
0310 static const struct regmap_range rt9120_rd_yes_ranges[] = {
0311     regmap_reg_range(0x00, 0x0C),
0312     regmap_reg_range(0x10, 0x15),
0313     regmap_reg_range(0x20, 0x27),
0314     regmap_reg_range(0x30, 0x38),
0315     regmap_reg_range(0x3A, 0x40),
0316     regmap_reg_range(0x63, 0x63),
0317     regmap_reg_range(0x65, 0x65),
0318     regmap_reg_range(0x69, 0x69),
0319     regmap_reg_range(0x6C, 0x6C),
0320     regmap_reg_range(0xF8, 0xF8)
0321 };
0322 
0323 static const struct regmap_access_table rt9120_rd_table = {
0324     .yes_ranges = rt9120_rd_yes_ranges,
0325     .n_yes_ranges = ARRAY_SIZE(rt9120_rd_yes_ranges),
0326 };
0327 
0328 static const struct regmap_range rt9120_wr_yes_ranges[] = {
0329     regmap_reg_range(0x00, 0x00),
0330     regmap_reg_range(0x02, 0x0A),
0331     regmap_reg_range(0x10, 0x15),
0332     regmap_reg_range(0x20, 0x27),
0333     regmap_reg_range(0x30, 0x38),
0334     regmap_reg_range(0x3A, 0x3D),
0335     regmap_reg_range(0x40, 0x40),
0336     regmap_reg_range(0x63, 0x63),
0337     regmap_reg_range(0x65, 0x65),
0338     regmap_reg_range(0x69, 0x69),
0339     regmap_reg_range(0x6C, 0x6C),
0340     regmap_reg_range(0xF8, 0xF8)
0341 };
0342 
0343 static const struct regmap_access_table rt9120_wr_table = {
0344     .yes_ranges = rt9120_wr_yes_ranges,
0345     .n_yes_ranges = ARRAY_SIZE(rt9120_wr_yes_ranges),
0346 };
0347 
0348 static bool rt9120_volatile_reg(struct device *dev, unsigned int reg)
0349 {
0350     switch (reg) {
0351     case 0x00 ... 0x01:
0352     case 0x10:
0353     case 0x30 ... 0x40:
0354         return true;
0355     default:
0356         return false;
0357     }
0358 }
0359 
0360 static int rt9120_get_reg_size(unsigned int reg)
0361 {
0362     switch (reg) {
0363     case 0x00:
0364     case 0x20 ... 0x27:
0365         return 2;
0366     case 0x30 ... 0x3D:
0367         return 3;
0368     case 0x3E ... 0x3F:
0369         return 4;
0370     default:
0371         return 1;
0372     }
0373 }
0374 
0375 static int rt9120_reg_read(void *context, unsigned int reg, unsigned int *val)
0376 {
0377     struct rt9120_data *data = context;
0378     struct i2c_client *i2c = to_i2c_client(data->dev);
0379     int size = rt9120_get_reg_size(reg);
0380     u8 raw[4] = {0};
0381     int ret;
0382 
0383     ret = i2c_smbus_read_i2c_block_data(i2c, reg, size, raw);
0384     if (ret < 0)
0385         return ret;
0386     else if (ret != size)
0387         return -EIO;
0388 
0389     switch (size) {
0390     case 4:
0391         *val = be32_to_cpup((__be32 *)raw);
0392         break;
0393     case 3:
0394         *val = raw[0] << 16 | raw[1] << 8 | raw[2];
0395         break;
0396     case 2:
0397         *val = be16_to_cpup((__be16 *)raw);
0398         break;
0399     default:
0400         *val = raw[0];
0401     }
0402 
0403     return 0;
0404 }
0405 
0406 static int rt9120_reg_write(void *context, unsigned int reg, unsigned int val)
0407 {
0408     struct rt9120_data *data = context;
0409     struct i2c_client *i2c = to_i2c_client(data->dev);
0410     int size = rt9120_get_reg_size(reg);
0411     __be32 be32_val;
0412     u8 *rawp = (u8 *)&be32_val;
0413     int offs = 4 - size;
0414 
0415     be32_val = cpu_to_be32(val);
0416     return i2c_smbus_write_i2c_block_data(i2c, reg, size, rawp + offs);
0417 }
0418 
0419 static const struct reg_default rt9120_reg_defaults[] = {
0420     { .reg = 0x02, .def = 0x02 },
0421     { .reg = 0x03, .def = 0xf2 },
0422     { .reg = 0x04, .def = 0x01 },
0423     { .reg = 0x05, .def = 0xc0 },
0424     { .reg = 0x06, .def = 0x28 },
0425     { .reg = 0x07, .def = 0x04 },
0426     { .reg = 0x08, .def = 0xff },
0427     { .reg = 0x09, .def = 0x01 },
0428     { .reg = 0x0a, .def = 0x01 },
0429     { .reg = 0x0b, .def = 0x00 },
0430     { .reg = 0x0c, .def = 0x04 },
0431     { .reg = 0x11, .def = 0x30 },
0432     { .reg = 0x12, .def = 0x08 },
0433     { .reg = 0x13, .def = 0x12 },
0434     { .reg = 0x14, .def = 0x09 },
0435     { .reg = 0x15, .def = 0x00 },
0436     { .reg = 0x20, .def = 0x7ff },
0437     { .reg = 0x21, .def = 0x180 },
0438     { .reg = 0x22, .def = 0x180 },
0439     { .reg = 0x23, .def = 0x00 },
0440     { .reg = 0x24, .def = 0x80 },
0441     { .reg = 0x25, .def = 0x180 },
0442     { .reg = 0x26, .def = 0x640 },
0443     { .reg = 0x27, .def = 0x180 },
0444     { .reg = 0x63, .def = 0x5e },
0445     { .reg = 0x65, .def = 0x66 },
0446     { .reg = 0x6c, .def = 0xe0 },
0447     { .reg = 0xf8, .def = 0x44 },
0448 };
0449 
0450 static const struct regmap_config rt9120_regmap_config = {
0451     .reg_bits = 8,
0452     .val_bits = 32,
0453     .max_register = RT9120_REG_DIGCFG,
0454     .reg_defaults = rt9120_reg_defaults,
0455     .num_reg_defaults = ARRAY_SIZE(rt9120_reg_defaults),
0456     .cache_type = REGCACHE_RBTREE,
0457 
0458     .reg_read = rt9120_reg_read,
0459     .reg_write = rt9120_reg_write,
0460 
0461     .volatile_reg = rt9120_volatile_reg,
0462     .wr_table = &rt9120_wr_table,
0463     .rd_table = &rt9120_rd_table,
0464 };
0465 
0466 static int rt9120_check_vendor_info(struct rt9120_data *data)
0467 {
0468     unsigned int devid;
0469     int ret;
0470 
0471     ret = regmap_read(data->regmap, RT9120_REG_DEVID, &devid);
0472     if (ret)
0473         return ret;
0474 
0475     devid = FIELD_GET(RT9120_VID_MASK, devid);
0476     switch (devid) {
0477     case RT9120_VENDOR_ID:
0478         data->chip_idx = CHIP_IDX_RT9120;
0479         break;
0480     case RT9120S_VENDOR_ID:
0481         data->chip_idx = CHIP_IDX_RT9120S;
0482         break;
0483     default:
0484         dev_err(data->dev, "DEVID not correct [0x%0x]\n", devid);
0485         return -ENODEV;
0486     }
0487 
0488     return 0;
0489 }
0490 
0491 static int rt9120_do_register_reset(struct rt9120_data *data)
0492 {
0493     int ret;
0494 
0495     ret = regmap_write(data->regmap, RT9120_REG_SWRESET,
0496                RT9120_SWRST_MASK);
0497     if (ret)
0498         return ret;
0499 
0500     msleep(RT9120_RESET_WAITMS);
0501     return 0;
0502 }
0503 
0504 static int rt9120_probe(struct i2c_client *i2c)
0505 {
0506     struct rt9120_data *data;
0507     struct regulator *dvdd_supply;
0508     int dvdd_supply_volt, ret;
0509 
0510     data = devm_kzalloc(&i2c->dev, sizeof(*data), GFP_KERNEL);
0511     if (!data)
0512         return -ENOMEM;
0513 
0514     data->dev = &i2c->dev;
0515     i2c_set_clientdata(i2c, data);
0516 
0517     data->pwdnn_gpio = devm_gpiod_get_optional(&i2c->dev, "pwdnn",
0518                            GPIOD_OUT_HIGH);
0519     if (IS_ERR(data->pwdnn_gpio)) {
0520         dev_err(&i2c->dev, "Failed to initialize 'pwdnn' gpio\n");
0521         return PTR_ERR(data->pwdnn_gpio);
0522     } else if (data->pwdnn_gpio) {
0523         dev_dbg(&i2c->dev, "'pwdnn' from low to high, wait chip on\n");
0524         msleep(RT9120_CHIPON_WAITMS);
0525     }
0526 
0527     data->regmap = devm_regmap_init(&i2c->dev, NULL, data,
0528                     &rt9120_regmap_config);
0529     if (IS_ERR(data->regmap)) {
0530         ret = PTR_ERR(data->regmap);
0531         dev_err(&i2c->dev, "Failed to init regmap [%d]\n", ret);
0532         return ret;
0533     }
0534 
0535     ret = rt9120_check_vendor_info(data);
0536     if (ret) {
0537         dev_err(&i2c->dev, "Failed to check vendor info\n");
0538         return ret;
0539     }
0540 
0541     ret = rt9120_do_register_reset(data);
0542     if (ret) {
0543         dev_err(&i2c->dev, "Failed to do register reset\n");
0544         return ret;
0545     }
0546 
0547     dvdd_supply = devm_regulator_get(&i2c->dev, "dvdd");
0548     if (IS_ERR(dvdd_supply)) {
0549         dev_err(&i2c->dev, "No dvdd regulator found\n");
0550         return PTR_ERR(dvdd_supply);
0551     }
0552 
0553     dvdd_supply_volt = regulator_get_voltage(dvdd_supply);
0554     if (dvdd_supply_volt <= RT9120_LVAPP_THRESUV) {
0555         dev_dbg(&i2c->dev, "dvdd low voltage design\n");
0556         ret = regmap_update_bits(data->regmap, RT9120_REG_UVPOPT,
0557                      RT9120_DVDD_UVSEL_MASK, 0);
0558         if (ret) {
0559             dev_err(&i2c->dev, "Failed to config dvdd uvsel\n");
0560             return ret;
0561         }
0562     }
0563 
0564     pm_runtime_set_autosuspend_delay(&i2c->dev, 1000);
0565     pm_runtime_use_autosuspend(&i2c->dev);
0566     pm_runtime_set_active(&i2c->dev);
0567     pm_runtime_mark_last_busy(&i2c->dev);
0568     pm_runtime_enable(&i2c->dev);
0569 
0570     return devm_snd_soc_register_component(&i2c->dev,
0571                            &rt9120_component_driver,
0572                            &rt9120_dai, 1);
0573 }
0574 
0575 static int rt9120_remove(struct i2c_client *i2c)
0576 {
0577     pm_runtime_disable(&i2c->dev);
0578     pm_runtime_set_suspended(&i2c->dev);
0579     return 0;
0580 }
0581 
0582 static int __maybe_unused rt9120_runtime_suspend(struct device *dev)
0583 {
0584     struct rt9120_data *data = dev_get_drvdata(dev);
0585 
0586     if (data->pwdnn_gpio) {
0587         regcache_cache_only(data->regmap, true);
0588         regcache_mark_dirty(data->regmap);
0589         gpiod_set_value(data->pwdnn_gpio, 0);
0590     }
0591 
0592     return 0;
0593 }
0594 
0595 static int __maybe_unused rt9120_runtime_resume(struct device *dev)
0596 {
0597     struct rt9120_data *data = dev_get_drvdata(dev);
0598 
0599     if (data->pwdnn_gpio) {
0600         gpiod_set_value(data->pwdnn_gpio, 1);
0601         msleep(RT9120_CHIPON_WAITMS);
0602         regcache_cache_only(data->regmap, false);
0603         regcache_sync(data->regmap);
0604     }
0605 
0606     return 0;
0607 }
0608 
0609 static const struct dev_pm_ops rt9120_pm_ops = {
0610     SET_RUNTIME_PM_OPS(rt9120_runtime_suspend, rt9120_runtime_resume, NULL)
0611 };
0612 
0613 static const struct of_device_id __maybe_unused rt9120_device_table[] = {
0614     { .compatible = "richtek,rt9120", },
0615     { }
0616 };
0617 MODULE_DEVICE_TABLE(of, rt9120_device_table);
0618 
0619 static struct i2c_driver rt9120_driver = {
0620     .driver = {
0621         .name = "rt9120",
0622         .of_match_table = rt9120_device_table,
0623         .pm = &rt9120_pm_ops,
0624     },
0625     .probe_new = rt9120_probe,
0626     .remove = rt9120_remove,
0627 };
0628 module_i2c_driver(rt9120_driver);
0629 
0630 MODULE_AUTHOR("ChiYuan Huang <cy_huang@richtek.com>");
0631 MODULE_DESCRIPTION("RT9120 Audio Amplifier Driver");
0632 MODULE_LICENSE("GPL");
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