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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * rt715.c -- rt715 ALSA SoC audio driver
0004  *
0005  * Copyright(c) 2019 Realtek Semiconductor Corp.
0006  *
0007  * ALC715 ASoC Codec Driver based Intel Dummy SdW codec driver
0008  *
0009  */
0010 
0011 #include <linux/module.h>
0012 #include <linux/kernel.h>
0013 #include <linux/init.h>
0014 #include <linux/delay.h>
0015 #include <linux/i2c.h>
0016 #include <linux/pm_runtime.h>
0017 #include <linux/pm.h>
0018 #include <linux/soundwire/sdw.h>
0019 #include <linux/gpio.h>
0020 #include <linux/regmap.h>
0021 #include <linux/slab.h>
0022 #include <linux/platform_device.h>
0023 #include <linux/regulator/consumer.h>
0024 #include <linux/gpio/consumer.h>
0025 #include <linux/of.h>
0026 #include <linux/of_gpio.h>
0027 #include <linux/of_device.h>
0028 #include <sound/core.h>
0029 #include <sound/pcm.h>
0030 #include <sound/pcm_params.h>
0031 #include <sound/soc.h>
0032 #include <sound/soc-dapm.h>
0033 #include <sound/initval.h>
0034 #include <sound/tlv.h>
0035 #include <sound/hda_verbs.h>
0036 
0037 #include "rt715.h"
0038 
0039 static int rt715_index_write(struct regmap *regmap, unsigned int reg,
0040         unsigned int value)
0041 {
0042     int ret;
0043     unsigned int addr = ((RT715_PRIV_INDEX_W_H) << 8) | reg;
0044 
0045     ret = regmap_write(regmap, addr, value);
0046     if (ret < 0) {
0047         pr_err("Failed to set private value: %08x <= %04x %d\n", ret,
0048             addr, value);
0049     }
0050 
0051     return ret;
0052 }
0053 
0054 static void rt715_get_gain(struct rt715_priv *rt715, unsigned int addr_h,
0055                 unsigned int addr_l, unsigned int val_h,
0056                 unsigned int *r_val, unsigned int *l_val)
0057 {
0058     int ret;
0059     /* R Channel */
0060     *r_val = val_h << 8;
0061     ret = regmap_read(rt715->regmap, addr_l, r_val);
0062     if (ret < 0)
0063         pr_err("Failed to get R channel gain.\n");
0064 
0065     /* L Channel */
0066     val_h |= 0x20;
0067     *l_val = val_h << 8;
0068     ret = regmap_read(rt715->regmap, addr_h, l_val);
0069     if (ret < 0)
0070         pr_err("Failed to get L channel gain.\n");
0071 }
0072 
0073 /* For Verb-Set Amplifier Gain (Verb ID = 3h) */
0074 static int rt715_set_amp_gain_put(struct snd_kcontrol *kcontrol,
0075                     struct snd_ctl_elem_value *ucontrol)
0076 {
0077     struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
0078     struct snd_soc_dapm_context *dapm =
0079         snd_soc_component_get_dapm(component);
0080     struct soc_mixer_control *mc =
0081         (struct soc_mixer_control *)kcontrol->private_value;
0082     struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
0083     unsigned int addr_h, addr_l, val_h, val_ll, val_lr;
0084     unsigned int read_ll, read_rl, i;
0085     unsigned int k_vol_changed = 0;
0086 
0087     for (i = 0; i < 2; i++) {
0088         if (ucontrol->value.integer.value[i] != rt715->kctl_2ch_vol_ori[i]) {
0089             k_vol_changed = 1;
0090             break;
0091         }
0092     }
0093 
0094     /* Can't use update bit function, so read the original value first */
0095     addr_h = mc->reg;
0096     addr_l = mc->rreg;
0097 
0098     if (mc->shift == RT715_DIR_OUT_SFT) /* output */
0099         val_h = 0x80;
0100     else /* input */
0101         val_h = 0x0;
0102 
0103     rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll);
0104 
0105     if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)
0106         regmap_write(rt715->regmap,
0107                 RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D0);
0108 
0109     /* L Channel */
0110     rt715->kctl_2ch_vol_ori[0] = ucontrol->value.integer.value[0];
0111     /* for gain */
0112     val_ll = ((ucontrol->value.integer.value[0]) & 0x7f);
0113     if (val_ll > mc->max)
0114         val_ll = mc->max;
0115     /* keep mute status */
0116     val_ll |= read_ll & 0x80;
0117 
0118     /* R Channel */
0119     rt715->kctl_2ch_vol_ori[1] = ucontrol->value.integer.value[1];
0120     /* for gain */
0121     val_lr = ((ucontrol->value.integer.value[1]) & 0x7f);
0122     if (val_lr > mc->max)
0123         val_lr = mc->max;
0124     /* keep mute status */
0125     val_lr |= read_rl & 0x80;
0126 
0127     for (i = 0; i < 3; i++) { /* retry 3 times at most */
0128 
0129         if (val_ll == val_lr) {
0130             /* Set both L/R channels at the same time */
0131             val_h = (1 << mc->shift) | (3 << 4);
0132             regmap_write(rt715->regmap, addr_h,
0133                 (val_h << 8) | val_ll);
0134             regmap_write(rt715->regmap, addr_l,
0135                 (val_h << 8) | val_ll);
0136         } else {
0137             /* Lch*/
0138             val_h = (1 << mc->shift) | (1 << 5);
0139             regmap_write(rt715->regmap, addr_h,
0140                 (val_h << 8) | val_ll);
0141             /* Rch */
0142             val_h = (1 << mc->shift) | (1 << 4);
0143             regmap_write(rt715->regmap, addr_l,
0144                 (val_h << 8) | val_lr);
0145         }
0146         /* check result */
0147         if (mc->shift == RT715_DIR_OUT_SFT) /* output */
0148             val_h = 0x80;
0149         else /* input */
0150             val_h = 0x0;
0151 
0152         rt715_get_gain(rt715, addr_h, addr_l, val_h,
0153                 &read_rl, &read_ll);
0154         if (read_rl == val_lr && read_ll == val_ll)
0155             break;
0156     }
0157 
0158     /* D0:power on state, D3: power saving mode */
0159     if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)
0160         regmap_write(rt715->regmap,
0161                 RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D3);
0162     return k_vol_changed;
0163 }
0164 
0165 static int rt715_set_amp_gain_get(struct snd_kcontrol *kcontrol,
0166                   struct snd_ctl_elem_value *ucontrol)
0167 {
0168     struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
0169     struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
0170     struct soc_mixer_control *mc =
0171         (struct soc_mixer_control *)kcontrol->private_value;
0172     unsigned int addr_h, addr_l, val_h;
0173     unsigned int read_ll, read_rl;
0174 
0175     addr_h = mc->reg;
0176     addr_l = mc->rreg;
0177     if (mc->shift == RT715_DIR_OUT_SFT) /* output */
0178         val_h = 0x80;
0179     else /* input */
0180         val_h = 0x0;
0181 
0182     rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll);
0183 
0184     if (mc->invert) {
0185         /* for mute status */
0186         read_ll = !(read_ll & 0x80);
0187         read_rl = !(read_rl & 0x80);
0188     } else {
0189         /* for gain */
0190         read_ll = read_ll & 0x7f;
0191         read_rl = read_rl & 0x7f;
0192     }
0193     ucontrol->value.integer.value[0] = read_ll;
0194     ucontrol->value.integer.value[1] = read_rl;
0195 
0196     return 0;
0197 }
0198 
0199 static int rt715_set_main_switch_put(struct snd_kcontrol *kcontrol,
0200                     struct snd_ctl_elem_value *ucontrol)
0201 {
0202     struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
0203     struct snd_soc_dapm_context *dapm =
0204         snd_soc_component_get_dapm(component);
0205     struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
0206     unsigned int capture_reg_H[] = {RT715_SET_GAIN_MIC_ADC_H,
0207         RT715_SET_GAIN_LINE_ADC_H, RT715_SET_GAIN_MIX_ADC_H,
0208         RT715_SET_GAIN_MIX_ADC2_H};
0209     unsigned int capture_reg_L[] = {RT715_SET_GAIN_MIC_ADC_L,
0210         RT715_SET_GAIN_LINE_ADC_L, RT715_SET_GAIN_MIX_ADC_L,
0211         RT715_SET_GAIN_MIX_ADC2_L};
0212     unsigned int addr_h, addr_l, val_h = 0x0, val_ll, val_lr;
0213     unsigned int k_shift = RT715_DIR_IN_SFT, k_changed = 0;
0214     unsigned int read_ll, read_rl, i, j, loop_cnt = 4;
0215 
0216     for (i = 0; i < 8; i++) {
0217         if (ucontrol->value.integer.value[i] != rt715->kctl_8ch_switch_ori[i])
0218             k_changed = 1;
0219     }
0220 
0221     for (j = 0; j < loop_cnt; j++) {
0222         /* Can't use update bit function, so read the original value first */
0223         addr_h = capture_reg_H[j];
0224         addr_l = capture_reg_L[j];
0225         rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll);
0226 
0227         if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)
0228             regmap_write(rt715->regmap,
0229                     RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D0);
0230 
0231         /* L Channel */
0232         /* for mute */
0233         rt715->kctl_8ch_switch_ori[j * 2] =
0234             ucontrol->value.integer.value[j * 2];
0235         val_ll = (!ucontrol->value.integer.value[j * 2]) << 7;
0236         /* keep gain */
0237         val_ll |= read_ll & 0x7f;
0238 
0239         /* R Channel */
0240         /* for mute */
0241         rt715->kctl_8ch_switch_ori[j * 2 + 1] =
0242             ucontrol->value.integer.value[j * 2 + 1];
0243         val_lr = (!ucontrol->value.integer.value[j * 2 + 1]) << 7;
0244         /* keep gain */
0245         val_lr |= read_rl & 0x7f;
0246 
0247         for (i = 0; i < 3; i++) { /* retry 3 times at most */
0248 
0249             if (val_ll == val_lr) {
0250                 /* Set both L/R channels at the same time */
0251                 val_h = (1 << k_shift) | (3 << 4);
0252                 regmap_write(rt715->regmap, addr_h,
0253                     (val_h << 8) | val_ll);
0254                 regmap_write(rt715->regmap, addr_l,
0255                     (val_h << 8) | val_ll);
0256             } else {
0257                 /* Lch*/
0258                 val_h = (1 << k_shift) | (1 << 5);
0259                 regmap_write(rt715->regmap, addr_h,
0260                     (val_h << 8) | val_ll);
0261                 /* Rch */
0262                 val_h = (1 << k_shift) | (1 << 4);
0263                 regmap_write(rt715->regmap, addr_l,
0264                     (val_h << 8) | val_lr);
0265             }
0266             val_h = 0x0;
0267             rt715_get_gain(rt715, addr_h, addr_l, val_h,
0268                     &read_rl, &read_ll);
0269             if (read_rl == val_lr && read_ll == val_ll)
0270                 break;
0271         }
0272     }
0273 
0274     /* D0:power on state, D3: power saving mode */
0275     if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)
0276         regmap_write(rt715->regmap,
0277                 RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D3);
0278     return k_changed;
0279 }
0280 
0281 static int rt715_set_main_switch_get(struct snd_kcontrol *kcontrol,
0282                   struct snd_ctl_elem_value *ucontrol)
0283 {
0284     struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
0285     struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
0286     unsigned int capture_reg_H[] = {RT715_SET_GAIN_MIC_ADC_H,
0287         RT715_SET_GAIN_LINE_ADC_H, RT715_SET_GAIN_MIX_ADC_H,
0288         RT715_SET_GAIN_MIX_ADC2_H};
0289     unsigned int capture_reg_L[] = {RT715_SET_GAIN_MIC_ADC_L,
0290         RT715_SET_GAIN_LINE_ADC_L, RT715_SET_GAIN_MIX_ADC_L,
0291         RT715_SET_GAIN_MIX_ADC2_L};
0292     unsigned int addr_h, addr_l, val_h = 0x0, i, loop_cnt = 4;
0293     unsigned int read_ll, read_rl;
0294 
0295     for (i = 0; i < loop_cnt; i++) {
0296         addr_h = capture_reg_H[i];
0297         addr_l = capture_reg_L[i];
0298         rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll);
0299 
0300         ucontrol->value.integer.value[i * 2] = !(read_ll & 0x80);
0301         ucontrol->value.integer.value[i * 2 + 1] = !(read_rl & 0x80);
0302     }
0303 
0304     return 0;
0305 }
0306 
0307 static int rt715_set_main_vol_put(struct snd_kcontrol *kcontrol,
0308                     struct snd_ctl_elem_value *ucontrol)
0309 {
0310     struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
0311     struct snd_soc_dapm_context *dapm =
0312         snd_soc_component_get_dapm(component);
0313     struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
0314     unsigned int capture_reg_H[] = {RT715_SET_GAIN_MIC_ADC_H,
0315         RT715_SET_GAIN_LINE_ADC_H, RT715_SET_GAIN_MIX_ADC_H,
0316         RT715_SET_GAIN_MIX_ADC2_H};
0317     unsigned int capture_reg_L[] = {RT715_SET_GAIN_MIC_ADC_L,
0318         RT715_SET_GAIN_LINE_ADC_L, RT715_SET_GAIN_MIX_ADC_L,
0319         RT715_SET_GAIN_MIX_ADC2_L};
0320     unsigned int addr_h, addr_l, val_h = 0x0, val_ll, val_lr;
0321     unsigned int read_ll, read_rl, i, j, loop_cnt = 4, k_changed = 0;
0322     unsigned int k_shift = RT715_DIR_IN_SFT, k_max = 0x3f;
0323 
0324     for (i = 0; i < 8; i++) {
0325         if (ucontrol->value.integer.value[i] != rt715->kctl_8ch_vol_ori[i])
0326             k_changed = 1;
0327     }
0328 
0329     for (j = 0; j < loop_cnt; j++) {
0330         addr_h = capture_reg_H[j];
0331         addr_l = capture_reg_L[j];
0332         rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll);
0333 
0334         if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)
0335             regmap_write(rt715->regmap,
0336                     RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D0);
0337 
0338         /* L Channel */
0339         /* for gain */
0340         rt715->kctl_8ch_vol_ori[j * 2] = ucontrol->value.integer.value[j * 2];
0341         val_ll = ((ucontrol->value.integer.value[j * 2]) & 0x7f);
0342         if (val_ll > k_max)
0343             val_ll = k_max;
0344         /* keep mute status */
0345         val_ll |= read_ll & 0x80;
0346 
0347         /* R Channel */
0348         /* for gain */
0349         rt715->kctl_8ch_vol_ori[j * 2 + 1] =
0350             ucontrol->value.integer.value[j * 2 + 1];
0351         val_lr = ((ucontrol->value.integer.value[j * 2 + 1]) & 0x7f);
0352         if (val_lr > k_max)
0353             val_lr = k_max;
0354         /* keep mute status */
0355         val_lr |= read_rl & 0x80;
0356 
0357         for (i = 0; i < 3; i++) { /* retry 3 times at most */
0358             if (val_ll == val_lr) {
0359                 /* Set both L/R channels at the same time */
0360                 val_h = (1 << k_shift) | (3 << 4);
0361                 regmap_write(rt715->regmap, addr_h,
0362                     (val_h << 8) | val_ll);
0363                 regmap_write(rt715->regmap, addr_l,
0364                     (val_h << 8) | val_ll);
0365             } else {
0366                 /* Lch*/
0367                 val_h = (1 << k_shift) | (1 << 5);
0368                 regmap_write(rt715->regmap, addr_h,
0369                     (val_h << 8) | val_ll);
0370                 /* Rch */
0371                 val_h = (1 << k_shift) | (1 << 4);
0372                 regmap_write(rt715->regmap, addr_l,
0373                     (val_h << 8) | val_lr);
0374             }
0375             val_h = 0x0;
0376             rt715_get_gain(rt715, addr_h, addr_l, val_h,
0377                     &read_rl, &read_ll);
0378             if (read_rl == val_lr && read_ll == val_ll)
0379                 break;
0380         }
0381     }
0382 
0383     /* D0:power on state, D3: power saving mode */
0384     if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)
0385         regmap_write(rt715->regmap,
0386                 RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D3);
0387     return k_changed;
0388 }
0389 
0390 static int rt715_set_main_vol_get(struct snd_kcontrol *kcontrol,
0391                   struct snd_ctl_elem_value *ucontrol)
0392 {
0393     struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
0394     struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
0395     unsigned int capture_reg_H[] = {RT715_SET_GAIN_MIC_ADC_H,
0396         RT715_SET_GAIN_LINE_ADC_H, RT715_SET_GAIN_MIX_ADC_H,
0397         RT715_SET_GAIN_MIX_ADC2_H};
0398     unsigned int capture_reg_L[] = {RT715_SET_GAIN_MIC_ADC_L,
0399         RT715_SET_GAIN_LINE_ADC_L, RT715_SET_GAIN_MIX_ADC_L,
0400         RT715_SET_GAIN_MIX_ADC2_L};
0401     unsigned int addr_h, addr_l, val_h = 0x0, i, loop_cnt = 4;
0402     unsigned int read_ll, read_rl;
0403 
0404     for (i = 0; i < loop_cnt; i++) {
0405         addr_h = capture_reg_H[i];
0406         addr_l = capture_reg_L[i];
0407         rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll);
0408 
0409         ucontrol->value.integer.value[i * 2] = read_ll & 0x7f;
0410         ucontrol->value.integer.value[i * 2 + 1] = read_rl & 0x7f;
0411     }
0412 
0413     return 0;
0414 }
0415 
0416 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -1725, 75, 0);
0417 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
0418 
0419 static int rt715_switch_info(struct snd_kcontrol *kcontrol,
0420     struct snd_ctl_elem_info *uinfo)
0421 {
0422     uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
0423     uinfo->count = 8;
0424     uinfo->value.integer.min = 0;
0425     uinfo->value.integer.max = 1;
0426     return 0;
0427 }
0428 
0429 static int rt715_vol_info(struct snd_kcontrol *kcontrol,
0430     struct snd_ctl_elem_info *uinfo)
0431 {
0432     uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
0433     uinfo->count = 8;
0434     uinfo->value.integer.min = 0;
0435     uinfo->value.integer.max = 0x3f;
0436     return 0;
0437 }
0438 
0439 #define SOC_DOUBLE_R_EXT(xname, reg_left, reg_right, xshift, xmax, xinvert,\
0440      xhandler_get, xhandler_put) \
0441 {   .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
0442     .info = snd_soc_info_volsw, \
0443     .get = xhandler_get, .put = xhandler_put, \
0444     .private_value = SOC_DOUBLE_R_VALUE(reg_left, reg_right, xshift, \
0445                         xmax, xinvert) }
0446 
0447 #define RT715_MAIN_SWITCH_EXT(xname, xhandler_get, xhandler_put) \
0448 {   .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
0449     .info = rt715_switch_info, \
0450     .get = xhandler_get, .put = xhandler_put, \
0451 }
0452 
0453 #define RT715_MAIN_VOL_EXT_TLV(xname, xhandler_get, xhandler_put, tlv_array) \
0454 {   .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
0455     .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
0456          SNDRV_CTL_ELEM_ACCESS_READWRITE, \
0457     .tlv.p = (tlv_array), \
0458     .info = rt715_vol_info, \
0459     .get = xhandler_get, .put = xhandler_put, \
0460 }
0461 
0462 static const struct snd_kcontrol_new rt715_snd_controls[] = {
0463     /* Capture switch */
0464     RT715_MAIN_SWITCH_EXT("Capture Switch",
0465             rt715_set_main_switch_get, rt715_set_main_switch_put),
0466     /* Volume Control */
0467     RT715_MAIN_VOL_EXT_TLV("Capture Volume",
0468             rt715_set_main_vol_get, rt715_set_main_vol_put, in_vol_tlv),
0469     /* MIC Boost Control */
0470     SOC_DOUBLE_R_EXT_TLV("DMIC1 Boost", RT715_SET_GAIN_DMIC1_H,
0471             RT715_SET_GAIN_DMIC1_L, RT715_DIR_IN_SFT, 3, 0,
0472             rt715_set_amp_gain_get, rt715_set_amp_gain_put,
0473             mic_vol_tlv),
0474     SOC_DOUBLE_R_EXT_TLV("DMIC2 Boost", RT715_SET_GAIN_DMIC2_H,
0475             RT715_SET_GAIN_DMIC2_L, RT715_DIR_IN_SFT, 3, 0,
0476             rt715_set_amp_gain_get, rt715_set_amp_gain_put,
0477             mic_vol_tlv),
0478     SOC_DOUBLE_R_EXT_TLV("DMIC3 Boost", RT715_SET_GAIN_DMIC3_H,
0479             RT715_SET_GAIN_DMIC3_L, RT715_DIR_IN_SFT, 3, 0,
0480             rt715_set_amp_gain_get, rt715_set_amp_gain_put,
0481             mic_vol_tlv),
0482     SOC_DOUBLE_R_EXT_TLV("DMIC4 Boost", RT715_SET_GAIN_DMIC4_H,
0483             RT715_SET_GAIN_DMIC4_L, RT715_DIR_IN_SFT, 3, 0,
0484             rt715_set_amp_gain_get, rt715_set_amp_gain_put,
0485             mic_vol_tlv),
0486     SOC_DOUBLE_R_EXT_TLV("MIC1 Boost", RT715_SET_GAIN_MIC1_H,
0487             RT715_SET_GAIN_MIC1_L, RT715_DIR_IN_SFT, 3, 0,
0488             rt715_set_amp_gain_get, rt715_set_amp_gain_put,
0489             mic_vol_tlv),
0490     SOC_DOUBLE_R_EXT_TLV("MIC2 Boost", RT715_SET_GAIN_MIC2_H,
0491             RT715_SET_GAIN_MIC2_L, RT715_DIR_IN_SFT, 3, 0,
0492             rt715_set_amp_gain_get, rt715_set_amp_gain_put,
0493             mic_vol_tlv),
0494     SOC_DOUBLE_R_EXT_TLV("LINE1 Boost", RT715_SET_GAIN_LINE1_H,
0495             RT715_SET_GAIN_LINE1_L, RT715_DIR_IN_SFT, 3, 0,
0496             rt715_set_amp_gain_get, rt715_set_amp_gain_put,
0497             mic_vol_tlv),
0498     SOC_DOUBLE_R_EXT_TLV("LINE2 Boost", RT715_SET_GAIN_LINE2_H,
0499             RT715_SET_GAIN_LINE2_L, RT715_DIR_IN_SFT, 3, 0,
0500             rt715_set_amp_gain_get, rt715_set_amp_gain_put,
0501             mic_vol_tlv),
0502 };
0503 
0504 static int rt715_mux_get(struct snd_kcontrol *kcontrol,
0505             struct snd_ctl_elem_value *ucontrol)
0506 {
0507     struct snd_soc_component *component =
0508         snd_soc_dapm_kcontrol_component(kcontrol);
0509     struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
0510     struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
0511     unsigned int reg, val;
0512     int ret;
0513 
0514     /* nid = e->reg, vid = 0xf01 */
0515     reg = RT715_VERB_SET_CONNECT_SEL | e->reg;
0516     ret = regmap_read(rt715->regmap, reg, &val);
0517     if (ret < 0) {
0518         dev_err(component->dev, "%s: sdw read failed: %d\n",
0519             __func__, ret);
0520         return ret;
0521     }
0522 
0523     /*
0524      * The first two indices of ADC Mux 24/25 are routed to the same
0525      * hardware source. ie, ADC Mux 24 0/1 will both connect to MIC2.
0526      * To have a unique set of inputs, we skip the index1 of the muxes.
0527      */
0528     if ((e->reg == RT715_MUX_IN3 || e->reg == RT715_MUX_IN4) && (val > 0))
0529         val -= 1;
0530     ucontrol->value.enumerated.item[0] = val;
0531 
0532     return 0;
0533 }
0534 
0535 static int rt715_mux_put(struct snd_kcontrol *kcontrol,
0536             struct snd_ctl_elem_value *ucontrol)
0537 {
0538     struct snd_soc_component *component =
0539         snd_soc_dapm_kcontrol_component(kcontrol);
0540     struct snd_soc_dapm_context *dapm =
0541                 snd_soc_dapm_kcontrol_dapm(kcontrol);
0542     struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
0543     struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
0544     unsigned int *item = ucontrol->value.enumerated.item;
0545     unsigned int val, val2 = 0, change, reg;
0546     int ret;
0547 
0548     if (item[0] >= e->items)
0549         return -EINVAL;
0550 
0551     /* Verb ID = 0x701h, nid = e->reg */
0552     val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
0553 
0554     reg = RT715_VERB_SET_CONNECT_SEL | e->reg;
0555     ret = regmap_read(rt715->regmap, reg, &val2);
0556     if (ret < 0) {
0557         dev_err(component->dev, "%s: sdw read failed: %d\n",
0558             __func__, ret);
0559         return ret;
0560     }
0561 
0562     if (val == val2)
0563         change = 0;
0564     else
0565         change = 1;
0566 
0567     if (change) {
0568         reg = RT715_VERB_SET_CONNECT_SEL | e->reg;
0569         regmap_write(rt715->regmap, reg, val);
0570     }
0571 
0572     snd_soc_dapm_mux_update_power(dapm, kcontrol,
0573                         item[0], e, NULL);
0574 
0575     return change;
0576 }
0577 
0578 static const char * const adc_22_23_mux_text[] = {
0579     "MIC1",
0580     "MIC2",
0581     "LINE1",
0582     "LINE2",
0583     "DMIC1",
0584     "DMIC2",
0585     "DMIC3",
0586     "DMIC4",
0587 };
0588 
0589 /*
0590  * Due to mux design for nid 24 (MUX_IN3)/25 (MUX_IN4), connection index 0 and
0591  * 1 will be connected to the same dmic source, therefore we skip index 1 to
0592  * avoid misunderstanding on usage of dapm routing.
0593  */
0594 static const unsigned int rt715_adc_24_25_values[] = {
0595     0,
0596     2,
0597     3,
0598     4,
0599     5,
0600 };
0601 
0602 static const char * const adc_24_mux_text[] = {
0603     "MIC2",
0604     "DMIC1",
0605     "DMIC2",
0606     "DMIC3",
0607     "DMIC4",
0608 };
0609 
0610 static const char * const adc_25_mux_text[] = {
0611     "MIC1",
0612     "DMIC1",
0613     "DMIC2",
0614     "DMIC3",
0615     "DMIC4",
0616 };
0617 
0618 static SOC_ENUM_SINGLE_DECL(
0619     rt715_adc22_enum, RT715_MUX_IN1, 0, adc_22_23_mux_text);
0620 
0621 static SOC_ENUM_SINGLE_DECL(
0622     rt715_adc23_enum, RT715_MUX_IN2, 0, adc_22_23_mux_text);
0623 
0624 static SOC_VALUE_ENUM_SINGLE_DECL(rt715_adc24_enum,
0625     RT715_MUX_IN3, 0, 0xf,
0626     adc_24_mux_text, rt715_adc_24_25_values);
0627 
0628 static SOC_VALUE_ENUM_SINGLE_DECL(rt715_adc25_enum,
0629     RT715_MUX_IN4, 0, 0xf,
0630     adc_25_mux_text, rt715_adc_24_25_values);
0631 
0632 static const struct snd_kcontrol_new rt715_adc22_mux =
0633     SOC_DAPM_ENUM_EXT("ADC 22 Mux", rt715_adc22_enum,
0634             rt715_mux_get, rt715_mux_put);
0635 
0636 static const struct snd_kcontrol_new rt715_adc23_mux =
0637     SOC_DAPM_ENUM_EXT("ADC 23 Mux", rt715_adc23_enum,
0638             rt715_mux_get, rt715_mux_put);
0639 
0640 static const struct snd_kcontrol_new rt715_adc24_mux =
0641     SOC_DAPM_ENUM_EXT("ADC 24 Mux", rt715_adc24_enum,
0642             rt715_mux_get, rt715_mux_put);
0643 
0644 static const struct snd_kcontrol_new rt715_adc25_mux =
0645     SOC_DAPM_ENUM_EXT("ADC 25 Mux", rt715_adc25_enum,
0646             rt715_mux_get, rt715_mux_put);
0647 
0648 static const struct snd_soc_dapm_widget rt715_dapm_widgets[] = {
0649     SND_SOC_DAPM_INPUT("DMIC1"),
0650     SND_SOC_DAPM_INPUT("DMIC2"),
0651     SND_SOC_DAPM_INPUT("DMIC3"),
0652     SND_SOC_DAPM_INPUT("DMIC4"),
0653     SND_SOC_DAPM_INPUT("MIC1"),
0654     SND_SOC_DAPM_INPUT("MIC2"),
0655     SND_SOC_DAPM_INPUT("LINE1"),
0656     SND_SOC_DAPM_INPUT("LINE2"),
0657     SND_SOC_DAPM_ADC("ADC 07", NULL, RT715_SET_STREAMID_MIC_ADC, 4, 0),
0658     SND_SOC_DAPM_ADC("ADC 08", NULL, RT715_SET_STREAMID_LINE_ADC, 4, 0),
0659     SND_SOC_DAPM_ADC("ADC 09", NULL, RT715_SET_STREAMID_MIX_ADC, 4, 0),
0660     SND_SOC_DAPM_ADC("ADC 27", NULL, RT715_SET_STREAMID_MIX_ADC2, 4, 0),
0661     SND_SOC_DAPM_MUX("ADC 22 Mux", SND_SOC_NOPM, 0, 0,
0662         &rt715_adc22_mux),
0663     SND_SOC_DAPM_MUX("ADC 23 Mux", SND_SOC_NOPM, 0, 0,
0664         &rt715_adc23_mux),
0665     SND_SOC_DAPM_MUX("ADC 24 Mux", SND_SOC_NOPM, 0, 0,
0666         &rt715_adc24_mux),
0667     SND_SOC_DAPM_MUX("ADC 25 Mux", SND_SOC_NOPM, 0, 0,
0668         &rt715_adc25_mux),
0669     SND_SOC_DAPM_AIF_OUT("DP4TX", "DP4 Capture", 0, SND_SOC_NOPM, 0, 0),
0670     SND_SOC_DAPM_AIF_OUT("DP6TX", "DP6 Capture", 0, SND_SOC_NOPM, 0, 0),
0671 };
0672 
0673 static const struct snd_soc_dapm_route rt715_audio_map[] = {
0674     {"DP6TX", NULL, "ADC 09"},
0675     {"DP6TX", NULL, "ADC 08"},
0676     {"DP4TX", NULL, "ADC 07"},
0677     {"DP4TX", NULL, "ADC 27"},
0678     {"ADC 09", NULL, "ADC 22 Mux"},
0679     {"ADC 08", NULL, "ADC 23 Mux"},
0680     {"ADC 07", NULL, "ADC 24 Mux"},
0681     {"ADC 27", NULL, "ADC 25 Mux"},
0682     {"ADC 22 Mux", "MIC1", "MIC1"},
0683     {"ADC 22 Mux", "MIC2", "MIC2"},
0684     {"ADC 22 Mux", "LINE1", "LINE1"},
0685     {"ADC 22 Mux", "LINE2", "LINE2"},
0686     {"ADC 22 Mux", "DMIC1", "DMIC1"},
0687     {"ADC 22 Mux", "DMIC2", "DMIC2"},
0688     {"ADC 22 Mux", "DMIC3", "DMIC3"},
0689     {"ADC 22 Mux", "DMIC4", "DMIC4"},
0690     {"ADC 23 Mux", "MIC1", "MIC1"},
0691     {"ADC 23 Mux", "MIC2", "MIC2"},
0692     {"ADC 23 Mux", "LINE1", "LINE1"},
0693     {"ADC 23 Mux", "LINE2", "LINE2"},
0694     {"ADC 23 Mux", "DMIC1", "DMIC1"},
0695     {"ADC 23 Mux", "DMIC2", "DMIC2"},
0696     {"ADC 23 Mux", "DMIC3", "DMIC3"},
0697     {"ADC 23 Mux", "DMIC4", "DMIC4"},
0698     {"ADC 24 Mux", "MIC2", "MIC2"},
0699     {"ADC 24 Mux", "DMIC1", "DMIC1"},
0700     {"ADC 24 Mux", "DMIC2", "DMIC2"},
0701     {"ADC 24 Mux", "DMIC3", "DMIC3"},
0702     {"ADC 24 Mux", "DMIC4", "DMIC4"},
0703     {"ADC 25 Mux", "MIC1", "MIC1"},
0704     {"ADC 25 Mux", "DMIC1", "DMIC1"},
0705     {"ADC 25 Mux", "DMIC2", "DMIC2"},
0706     {"ADC 25 Mux", "DMIC3", "DMIC3"},
0707     {"ADC 25 Mux", "DMIC4", "DMIC4"},
0708 };
0709 
0710 static int rt715_set_bias_level(struct snd_soc_component *component,
0711                 enum snd_soc_bias_level level)
0712 {
0713     struct snd_soc_dapm_context *dapm =
0714         snd_soc_component_get_dapm(component);
0715     struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
0716 
0717     switch (level) {
0718     case SND_SOC_BIAS_PREPARE:
0719         if (dapm->bias_level == SND_SOC_BIAS_STANDBY) {
0720             regmap_write(rt715->regmap,
0721                         RT715_SET_AUDIO_POWER_STATE,
0722                         AC_PWRST_D0);
0723             msleep(RT715_POWER_UP_DELAY_MS);
0724         }
0725         break;
0726 
0727     case SND_SOC_BIAS_STANDBY:
0728         regmap_write(rt715->regmap,
0729                     RT715_SET_AUDIO_POWER_STATE,
0730                     AC_PWRST_D3);
0731         break;
0732 
0733     default:
0734         break;
0735     }
0736     dapm->bias_level = level;
0737     return 0;
0738 }
0739 
0740 static int rt715_probe(struct snd_soc_component *component)
0741 {
0742     int ret;
0743 
0744     ret = pm_runtime_resume(component->dev);
0745     if (ret < 0 && ret != -EACCES)
0746         return ret;
0747 
0748     return 0;
0749 }
0750 
0751 static const struct snd_soc_component_driver soc_codec_dev_rt715 = {
0752     .probe = rt715_probe,
0753     .set_bias_level = rt715_set_bias_level,
0754     .controls = rt715_snd_controls,
0755     .num_controls = ARRAY_SIZE(rt715_snd_controls),
0756     .dapm_widgets = rt715_dapm_widgets,
0757     .num_dapm_widgets = ARRAY_SIZE(rt715_dapm_widgets),
0758     .dapm_routes = rt715_audio_map,
0759     .num_dapm_routes = ARRAY_SIZE(rt715_audio_map),
0760     .endianness = 1,
0761 };
0762 
0763 static int rt715_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
0764                 int direction)
0765 {
0766 
0767     struct sdw_stream_data *stream;
0768 
0769     if (!sdw_stream)
0770         return 0;
0771 
0772     stream = kzalloc(sizeof(*stream), GFP_KERNEL);
0773     if (!stream)
0774         return -ENOMEM;
0775 
0776     stream->sdw_stream = sdw_stream;
0777 
0778     /* Use tx_mask or rx_mask to configure stream tag and set dma_data */
0779     if (direction == SNDRV_PCM_STREAM_PLAYBACK)
0780         dai->playback_dma_data = stream;
0781     else
0782         dai->capture_dma_data = stream;
0783 
0784     return 0;
0785 }
0786 
0787 static void rt715_shutdown(struct snd_pcm_substream *substream,
0788                 struct snd_soc_dai *dai)
0789 
0790 {
0791     struct sdw_stream_data *stream;
0792 
0793     stream = snd_soc_dai_get_dma_data(dai, substream);
0794     snd_soc_dai_set_dma_data(dai, substream, NULL);
0795     kfree(stream);
0796 }
0797 
0798 static int rt715_pcm_hw_params(struct snd_pcm_substream *substream,
0799                 struct snd_pcm_hw_params *params,
0800                 struct snd_soc_dai *dai)
0801 {
0802     struct snd_soc_component *component = dai->component;
0803     struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
0804     struct sdw_stream_config stream_config;
0805     struct sdw_port_config port_config;
0806     enum sdw_data_direction direction;
0807     struct sdw_stream_data *stream;
0808     int retval, port, num_channels;
0809     unsigned int val = 0;
0810 
0811     stream = snd_soc_dai_get_dma_data(dai, substream);
0812 
0813     if (!stream)
0814         return -EINVAL;
0815 
0816     if (!rt715->slave)
0817         return -EINVAL;
0818 
0819     switch (dai->id) {
0820     case RT715_AIF1:
0821         direction = SDW_DATA_DIR_TX;
0822         port = 6;
0823         rt715_index_write(rt715->regmap, RT715_SDW_INPUT_SEL, 0xa500);
0824         break;
0825     case RT715_AIF2:
0826         direction = SDW_DATA_DIR_TX;
0827         port = 4;
0828         rt715_index_write(rt715->regmap, RT715_SDW_INPUT_SEL, 0xa000);
0829         break;
0830     default:
0831         dev_err(component->dev, "Invalid DAI id %d\n", dai->id);
0832         return -EINVAL;
0833     }
0834 
0835     stream_config.frame_rate =  params_rate(params);
0836     stream_config.ch_count = params_channels(params);
0837     stream_config.bps = snd_pcm_format_width(params_format(params));
0838     stream_config.direction = direction;
0839 
0840     num_channels = params_channels(params);
0841     port_config.ch_mask = (1 << (num_channels)) - 1;
0842     port_config.num = port;
0843 
0844     retval = sdw_stream_add_slave(rt715->slave, &stream_config,
0845                     &port_config, 1, stream->sdw_stream);
0846     if (retval) {
0847         dev_err(dai->dev, "Unable to configure port\n");
0848         return retval;
0849     }
0850 
0851     switch (params_rate(params)) {
0852     /* bit 14 0:48K 1:44.1K */
0853     /* bit 15 Stream Type 0:PCM 1:Non-PCM, should always be PCM */
0854     case 44100:
0855         val |= 0x40 << 8;
0856         break;
0857     case 48000:
0858         val |= 0x0 << 8;
0859         break;
0860     default:
0861         dev_err(component->dev, "Unsupported sample rate %d\n",
0862             params_rate(params));
0863         return -EINVAL;
0864     }
0865 
0866     if (params_channels(params) <= 16) {
0867         /* bit 3:0 Number of Channel */
0868         val |= (params_channels(params) - 1);
0869     } else {
0870         dev_err(component->dev, "Unsupported channels %d\n",
0871             params_channels(params));
0872         return -EINVAL;
0873     }
0874 
0875     switch (params_width(params)) {
0876     /* bit 6:4 Bits per Sample */
0877     case 8:
0878         break;
0879     case 16:
0880         val |= (0x1 << 4);
0881         break;
0882     case 20:
0883         val |= (0x2 << 4);
0884         break;
0885     case 24:
0886         val |= (0x3 << 4);
0887         break;
0888     case 32:
0889         val |= (0x4 << 4);
0890         break;
0891     default:
0892         return -EINVAL;
0893     }
0894 
0895     regmap_write(rt715->regmap, RT715_MIC_ADC_FORMAT_H, val);
0896     regmap_write(rt715->regmap, RT715_MIC_LINE_FORMAT_H, val);
0897     regmap_write(rt715->regmap, RT715_MIX_ADC_FORMAT_H, val);
0898     regmap_write(rt715->regmap, RT715_MIX_ADC2_FORMAT_H, val);
0899 
0900     return retval;
0901 }
0902 
0903 static int rt715_pcm_hw_free(struct snd_pcm_substream *substream,
0904                 struct snd_soc_dai *dai)
0905 {
0906     struct snd_soc_component *component = dai->component;
0907     struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
0908     struct sdw_stream_data *stream =
0909         snd_soc_dai_get_dma_data(dai, substream);
0910 
0911     if (!rt715->slave)
0912         return -EINVAL;
0913 
0914     sdw_stream_remove_slave(rt715->slave, stream->sdw_stream);
0915     return 0;
0916 }
0917 
0918 #define RT715_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
0919 #define RT715_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
0920             SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
0921 
0922 static const struct snd_soc_dai_ops rt715_ops = {
0923     .hw_params  = rt715_pcm_hw_params,
0924     .hw_free    = rt715_pcm_hw_free,
0925     .set_stream = rt715_set_sdw_stream,
0926     .shutdown   = rt715_shutdown,
0927 };
0928 
0929 static struct snd_soc_dai_driver rt715_dai[] = {
0930     {
0931         .name = "rt715-aif1",
0932         .id = RT715_AIF1,
0933         .capture = {
0934             .stream_name = "DP6 Capture",
0935             .channels_min = 1,
0936             .channels_max = 2,
0937             .rates = RT715_STEREO_RATES,
0938             .formats = RT715_FORMATS,
0939         },
0940         .ops = &rt715_ops,
0941     },
0942     {
0943         .name = "rt715-aif2",
0944         .id = RT715_AIF2,
0945         .capture = {
0946             .stream_name = "DP4 Capture",
0947             .channels_min = 1,
0948             .channels_max = 2,
0949             .rates = RT715_STEREO_RATES,
0950             .formats = RT715_FORMATS,
0951         },
0952         .ops = &rt715_ops,
0953     },
0954 };
0955 
0956 /* Bus clock frequency */
0957 #define RT715_CLK_FREQ_9600000HZ 9600000
0958 #define RT715_CLK_FREQ_12000000HZ 12000000
0959 #define RT715_CLK_FREQ_6000000HZ 6000000
0960 #define RT715_CLK_FREQ_4800000HZ 4800000
0961 #define RT715_CLK_FREQ_2400000HZ 2400000
0962 #define RT715_CLK_FREQ_12288000HZ 12288000
0963 
0964 int rt715_clock_config(struct device *dev)
0965 {
0966     struct rt715_priv *rt715 = dev_get_drvdata(dev);
0967     unsigned int clk_freq, value;
0968 
0969     clk_freq = (rt715->params.curr_dr_freq >> 1);
0970 
0971     switch (clk_freq) {
0972     case RT715_CLK_FREQ_12000000HZ:
0973         value = 0x0;
0974         break;
0975     case RT715_CLK_FREQ_6000000HZ:
0976         value = 0x1;
0977         break;
0978     case RT715_CLK_FREQ_9600000HZ:
0979         value = 0x2;
0980         break;
0981     case RT715_CLK_FREQ_4800000HZ:
0982         value = 0x3;
0983         break;
0984     case RT715_CLK_FREQ_2400000HZ:
0985         value = 0x4;
0986         break;
0987     case RT715_CLK_FREQ_12288000HZ:
0988         value = 0x5;
0989         break;
0990     default:
0991         return -EINVAL;
0992     }
0993 
0994     regmap_write(rt715->regmap, 0xe0, value);
0995     regmap_write(rt715->regmap, 0xf0, value);
0996 
0997     return 0;
0998 }
0999 
1000 int rt715_init(struct device *dev, struct regmap *sdw_regmap,
1001     struct regmap *regmap, struct sdw_slave *slave)
1002 {
1003     struct rt715_priv *rt715;
1004     int ret;
1005 
1006     rt715 = devm_kzalloc(dev, sizeof(*rt715), GFP_KERNEL);
1007     if (!rt715)
1008         return -ENOMEM;
1009 
1010     dev_set_drvdata(dev, rt715);
1011     rt715->slave = slave;
1012     rt715->regmap = regmap;
1013     rt715->sdw_regmap = sdw_regmap;
1014 
1015     /*
1016      * Mark hw_init to false
1017      * HW init will be performed when device reports present
1018      */
1019     rt715->hw_init = false;
1020     rt715->first_hw_init = false;
1021 
1022     ret = devm_snd_soc_register_component(dev,
1023                         &soc_codec_dev_rt715,
1024                         rt715_dai,
1025                         ARRAY_SIZE(rt715_dai));
1026 
1027     return ret;
1028 }
1029 
1030 int rt715_io_init(struct device *dev, struct sdw_slave *slave)
1031 {
1032     struct rt715_priv *rt715 = dev_get_drvdata(dev);
1033 
1034     if (rt715->hw_init)
1035         return 0;
1036 
1037     /*
1038      * PM runtime is only enabled when a Slave reports as Attached
1039      */
1040     if (!rt715->first_hw_init) {
1041         /* set autosuspend parameters */
1042         pm_runtime_set_autosuspend_delay(&slave->dev, 3000);
1043         pm_runtime_use_autosuspend(&slave->dev);
1044 
1045         /* update count of parent 'active' children */
1046         pm_runtime_set_active(&slave->dev);
1047 
1048         /* make sure the device does not suspend immediately */
1049         pm_runtime_mark_last_busy(&slave->dev);
1050 
1051         pm_runtime_enable(&slave->dev);
1052     }
1053 
1054     pm_runtime_get_noresume(&slave->dev);
1055 
1056     /* Mute nid=08h/09h */
1057     regmap_write(rt715->regmap, RT715_SET_GAIN_LINE_ADC_H, 0xb080);
1058     regmap_write(rt715->regmap, RT715_SET_GAIN_MIX_ADC_H, 0xb080);
1059     /* Mute nid=07h/27h */
1060     regmap_write(rt715->regmap, RT715_SET_GAIN_MIC_ADC_H, 0xb080);
1061     regmap_write(rt715->regmap, RT715_SET_GAIN_MIX_ADC2_H, 0xb080);
1062 
1063     /* Set Pin Widget */
1064     regmap_write(rt715->regmap, RT715_SET_PIN_DMIC1, 0x20);
1065     regmap_write(rt715->regmap, RT715_SET_PIN_DMIC2, 0x20);
1066     regmap_write(rt715->regmap, RT715_SET_PIN_DMIC3, 0x20);
1067     regmap_write(rt715->regmap, RT715_SET_PIN_DMIC4, 0x20);
1068     /* Set Converter Stream */
1069     regmap_write(rt715->regmap, RT715_SET_STREAMID_LINE_ADC, 0x10);
1070     regmap_write(rt715->regmap, RT715_SET_STREAMID_MIX_ADC, 0x10);
1071     regmap_write(rt715->regmap, RT715_SET_STREAMID_MIC_ADC, 0x10);
1072     regmap_write(rt715->regmap, RT715_SET_STREAMID_MIX_ADC2, 0x10);
1073     /* Set Configuration Default */
1074     regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT1, 0xd0);
1075     regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT2, 0x11);
1076     regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT3, 0xa1);
1077     regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT4, 0x81);
1078     regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT1, 0xd1);
1079     regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT2, 0x11);
1080     regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT3, 0xa1);
1081     regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT4, 0x81);
1082     regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT1, 0xd0);
1083     regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT2, 0x11);
1084     regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT3, 0xa1);
1085     regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT4, 0x81);
1086     regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT1, 0xd1);
1087     regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT2, 0x11);
1088     regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT3, 0xa1);
1089     regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT4, 0x81);
1090 
1091     /* Finish Initial Settings, set power to D3 */
1092     regmap_write(rt715->regmap, RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D3);
1093 
1094     if (rt715->first_hw_init)
1095         regcache_mark_dirty(rt715->regmap);
1096     else
1097         rt715->first_hw_init = true;
1098 
1099     /* Mark Slave initialization complete */
1100     rt715->hw_init = true;
1101 
1102     pm_runtime_mark_last_busy(&slave->dev);
1103     pm_runtime_put_autosuspend(&slave->dev);
1104 
1105     return 0;
1106 }
1107 
1108 MODULE_DESCRIPTION("ASoC rt715 driver");
1109 MODULE_DESCRIPTION("ASoC rt715 driver SDW");
1110 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
1111 MODULE_LICENSE("GPL v2");
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