soc/codecs/rt715-sdw.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * rt715-sdw.c -- rt715 ALSA SoC audio driver
0004  *
0005  * Copyright(c) 2019 Realtek Semiconductor Corp.
0006  *
0007  * ALC715 ASoC Codec Driver based Intel Dummy SdW codec driver
0008  *
0009  */
0010 #include <linux/delay.h>
0011 #include <linux/device.h>
0012 #include <linux/mod_devicetable.h>
0013 #include <linux/soundwire/sdw.h>
0014 #include <linux/soundwire/sdw_type.h>
0015 #include <linux/soundwire/sdw_registers.h>
0016 #include <linux/module.h>
0017 #include <linux/pm_runtime.h>
0018 #include <linux/of.h>
0019 #include <linux/regmap.h>
0020 #include <sound/soc.h>
0021 #include "rt715.h"
0022 #include "rt715-sdw.h"
0023
0024 static bool rt715_readable_register(struct device *dev, unsigned int reg)
0025 {
0026     switch (reg) {
0027     case 0x00e0 ... 0x00e5:
0028     case 0x00ee ... 0x00ef:
0029     case 0x00f0 ... 0x00f5:
0030     case 0x00fe ... 0x00ff:
0031     case 0x02e0:
0032     case 0x02f0:
0033     case 0x04e0:
0034     case 0x04f0:
0035     case 0x06e0:
0036     case 0x06f0:
0037     case 0x2000 ... 0x2016:
0038     case 0x201a ... 0x2027:
0039     case 0x2029 ... 0x202a:
0040     case 0x202d ... 0x2034:
0041     case 0x2200 ... 0x2204:
0042     case 0x2206 ... 0x2212:
0043     case 0x2220 ... 0x2223:
0044     case 0x2230 ... 0x2239:
0045     case 0x22f0 ... 0x22f3:
0046     case 0x3122:
0047     case 0x3123:
0048     case 0x3124:
0049     case 0x3125:
0050     case 0x3607:
0051     case 0x3608:
0052     case 0x3609:
0053     case 0x3610:
0054     case 0x3611:
0055     case 0x3627:
0056     case 0x3712:
0057     case 0x3713:
0058     case 0x3718:
0059     case 0x3719:
0060     case 0x371a:
0061     case 0x371b:
0062     case 0x371d:
0063     case 0x3729:
0064     case 0x385e:
0065     case 0x3859:
0066     case 0x4c12:
0067     case 0x4c13:
0068     case 0x4c1d:
0069     case 0x4c29:
0070     case 0x4d12:
0071     case 0x4d13:
0072     case 0x4d1d:
0073     case 0x4d29:
0074     case 0x4e12:
0075     case 0x4e13:
0076     case 0x4e1d:
0077     case 0x4e29:
0078     case 0x4f12:
0079     case 0x4f13:
0080     case 0x4f1d:
0081     case 0x4f29:
0082     case 0x7207:
0083     case 0x7208:
0084     case 0x7209:
0085     case 0x7227:
0086     case 0x7307:
0087     case 0x7308:
0088     case 0x7309:
0089     case 0x7312:
0090     case 0x7313:
0091     case 0x7318:
0092     case 0x7319:
0093     case 0x731a:
0094     case 0x731b:
0095     case 0x731d:
0096     case 0x7327:
0097     case 0x7329:
0098     case 0x8287:
0099     case 0x8288:
0100     case 0x8289:
0101     case 0x82a7:
0102     case 0x8387:
0103     case 0x8388:
0104     case 0x8389:
0105     case 0x8392:
0106     case 0x8393:
0107     case 0x8398:
0108     case 0x8399:
0109     case 0x839a:
0110     case 0x839b:
0111     case 0x839d:
0112     case 0x83a7:
0113     case 0x83a9:
0114     case 0x752039:
0115         return true;
0116     default:
0117         return false;
0118     }
0119 }
0120
0121 static bool rt715_volatile_register(struct device *dev, unsigned int reg)
0122 {
0123     switch (reg) {
0124     case 0x00e5:
0125     case 0x00f0:
0126     case 0x00f3:
0127     case 0x00f5:
0128     case 0x2009:
0129     case 0x2016:
0130     case 0x201b:
0131     case 0x201c:
0132     case 0x201d:
0133     case 0x201f:
0134     case 0x2023:
0135     case 0x2230:
0136     case 0x200b ... 0x200e: /* i2c read */
0137     case 0x2012 ... 0x2015: /* HD-A read */
0138     case 0x202d ... 0x202f: /* BRA */
0139     case 0x2201 ... 0x2212: /* i2c debug */
0140     case 0x2220 ... 0x2223: /* decoded HD-A */
0141         return true;
0142     default:
0143         return false;
0144     }
0145 }
0146
0147 static int rt715_sdw_read(void *context, unsigned int reg, unsigned int *val)
0148 {
0149     struct device *dev = context;
0150     struct rt715_priv *rt715 = dev_get_drvdata(dev);
0151     unsigned int sdw_data_3, sdw_data_2, sdw_data_1, sdw_data_0;
0152     unsigned int reg2 = 0, reg3 = 0, reg4 = 0, mask, nid, val2;
0153     unsigned int is_hda_reg = 1, is_index_reg = 0;
0154     int ret;
0155
0156     if (reg > 0xffff)
0157         is_index_reg = 1;
0158
0159     mask = reg & 0xf000;
0160
0161     if (is_index_reg) { /* index registers */
0162         val2 = reg & 0xff;
0163         reg = reg >> 8;
0164         nid = reg & 0xff;
0165         ret = regmap_write(rt715->sdw_regmap, reg, 0);
0166         if (ret < 0)
0167             return ret;
0168         reg2 = reg + 0x1000;
0169         reg2 |= 0x80;
0170         ret = regmap_write(rt715->sdw_regmap, reg2, val2);
0171         if (ret < 0)
0172             return ret;
0173
0174         reg3 = RT715_PRIV_DATA_R_H | nid;
0175         ret = regmap_write(rt715->sdw_regmap, reg3,
0176             ((*val >> 8) & 0xff));
0177         if (ret < 0)
0178             return ret;
0179         reg4 = reg3 + 0x1000;
0180         reg4 |= 0x80;
0181         ret = regmap_write(rt715->sdw_regmap, reg4, (*val & 0xff));
0182         if (ret < 0)
0183             return ret;
0184     } else if (mask   == 0x3000) {
0185         reg += 0x8000;
0186         ret = regmap_write(rt715->sdw_regmap, reg, *val);
0187         if (ret < 0)
0188             return ret;
0189     } else if (mask == 0x7000) {
0190         reg += 0x2000;
0191         reg |= 0x800;
0192         ret = regmap_write(rt715->sdw_regmap, reg,
0193             ((*val >> 8) & 0xff));
0194         if (ret < 0)
0195             return ret;
0196         reg2 = reg + 0x1000;
0197         reg2 |= 0x80;
0198         ret = regmap_write(rt715->sdw_regmap, reg2, (*val & 0xff));
0199         if (ret < 0)
0200             return ret;
0201     } else if ((reg & 0xff00) == 0x8300) { /* for R channel */
0202         reg2 = reg - 0x1000;
0203         reg2 &= ~0x80;
0204         ret = regmap_write(rt715->sdw_regmap, reg2,
0205             ((*val >> 8) & 0xff));
0206         if (ret < 0)
0207             return ret;
0208         ret = regmap_write(rt715->sdw_regmap, reg, (*val & 0xff));
0209         if (ret < 0)
0210             return ret;
0211     } else if (mask == 0x9000) {
0212         ret = regmap_write(rt715->sdw_regmap, reg,
0213             ((*val >> 8) & 0xff));
0214         if (ret < 0)
0215             return ret;
0216         reg2 = reg + 0x1000;
0217         reg2 |= 0x80;
0218         ret = regmap_write(rt715->sdw_regmap, reg2, (*val & 0xff));
0219         if (ret < 0)
0220             return ret;
0221     } else if (mask == 0xb000) {
0222         ret = regmap_write(rt715->sdw_regmap, reg, *val);
0223         if (ret < 0)
0224             return ret;
0225     } else {
0226         ret = regmap_read(rt715->sdw_regmap, reg, val);
0227         if (ret < 0)
0228             return ret;
0229         is_hda_reg = 0;
0230     }
0231
0232     if (is_hda_reg || is_index_reg) {
0233         sdw_data_3 = 0;
0234         sdw_data_2 = 0;
0235         sdw_data_1 = 0;
0236         sdw_data_0 = 0;
0237         ret = regmap_read(rt715->sdw_regmap, RT715_READ_HDA_3,
0238             &sdw_data_3);
0239         if (ret < 0)
0240             return ret;
0241         ret = regmap_read(rt715->sdw_regmap, RT715_READ_HDA_2,
0242             &sdw_data_2);
0243         if (ret < 0)
0244             return ret;
0245         ret = regmap_read(rt715->sdw_regmap, RT715_READ_HDA_1,
0246             &sdw_data_1);
0247         if (ret < 0)
0248             return ret;
0249         ret = regmap_read(rt715->sdw_regmap, RT715_READ_HDA_0,
0250             &sdw_data_0);
0251         if (ret < 0)
0252             return ret;
0253         *val = ((sdw_data_3 & 0xff) << 24) |
0254             ((sdw_data_2 & 0xff) << 16) |
0255             ((sdw_data_1 & 0xff) << 8) | (sdw_data_0 & 0xff);
0256     }
0257
0258     if (is_hda_reg == 0)
0259         dev_dbg(dev, "[%s] %04x => %08x\n", __func__, reg, *val);
0260     else if (is_index_reg)
0261         dev_dbg(dev, "[%s] %04x %04x %04x %04x => %08x\n", __func__,
0262             reg, reg2, reg3, reg4, *val);
0263     else
0264         dev_dbg(dev, "[%s] %04x %04x => %08x\n",
0265         __func__, reg, reg2, *val);
0266
0267     return 0;
0268 }
0269
0270 static int rt715_sdw_write(void *context, unsigned int reg, unsigned int val)
0271 {
0272     struct device *dev = context;
0273     struct rt715_priv *rt715 = dev_get_drvdata(dev);
0274     unsigned int reg2 = 0, reg3, reg4, nid, mask, val2;
0275     unsigned int is_index_reg = 0;
0276     int ret;
0277
0278     if (reg > 0xffff)
0279         is_index_reg = 1;
0280
0281     mask = reg & 0xf000;
0282
0283     if (is_index_reg) { /* index registers */
0284         val2 = reg & 0xff;
0285         reg = reg >> 8;
0286         nid = reg & 0xff;
0287         ret = regmap_write(rt715->sdw_regmap, reg, 0);
0288         if (ret < 0)
0289             return ret;
0290         reg2 = reg + 0x1000;
0291         reg2 |= 0x80;
0292         ret = regmap_write(rt715->sdw_regmap, reg2, val2);
0293         if (ret < 0)
0294             return ret;
0295
0296         reg3 = RT715_PRIV_DATA_W_H | nid;
0297         ret = regmap_write(rt715->sdw_regmap, reg3,
0298             ((val >> 8) & 0xff));
0299         if (ret < 0)
0300             return ret;
0301         reg4 = reg3 + 0x1000;
0302         reg4 |= 0x80;
0303         ret = regmap_write(rt715->sdw_regmap, reg4, (val & 0xff));
0304         if (ret < 0)
0305             return ret;
0306         is_index_reg = 1;
0307     } else if (reg < 0x4fff) {
0308         ret = regmap_write(rt715->sdw_regmap, reg, val);
0309         if (ret < 0)
0310             return ret;
0311     } else if (reg == RT715_FUNC_RESET) {
0312         ret = regmap_write(rt715->sdw_regmap, reg, val);
0313         if (ret < 0)
0314             return ret;
0315     } else if (mask == 0x7000) {
0316         ret = regmap_write(rt715->sdw_regmap, reg,
0317             ((val >> 8) & 0xff));
0318         if (ret < 0)
0319             return ret;
0320         reg2 = reg + 0x1000;
0321         reg2 |= 0x80;
0322         ret = regmap_write(rt715->sdw_regmap, reg2, (val & 0xff));
0323         if (ret < 0)
0324             return ret;
0325     } else if ((reg & 0xff00) == 0x8300) {  /* for R channel */
0326         reg2 = reg - 0x1000;
0327         reg2 &= ~0x80;
0328         ret = regmap_write(rt715->sdw_regmap, reg2,
0329             ((val >> 8) & 0xff));
0330         if (ret < 0)
0331             return ret;
0332         ret = regmap_write(rt715->sdw_regmap, reg, (val & 0xff));
0333         if (ret < 0)
0334             return ret;
0335     }
0336
0337     if (reg2 == 0)
0338         dev_dbg(dev, "[%s] %04x <= %04x\n", __func__, reg, val);
0339     else if (is_index_reg)
0340         dev_dbg(dev, "[%s] %04x %04x %04x %04x <= %04x %04x\n",
0341             __func__, reg, reg2, reg3, reg4, val2, val);
0342     else
0343         dev_dbg(dev, "[%s] %04x %04x <= %04x\n",
0344         __func__, reg, reg2, val);
0345
0346     return 0;
0347 }
0348
0349 static const struct regmap_config rt715_regmap = {
0350     .reg_bits = 24,
0351     .val_bits = 32,
0352     .readable_reg = rt715_readable_register, /* Readable registers */
0353     .volatile_reg = rt715_volatile_register, /* volatile register */
0354     .max_register = 0x752039, /* Maximum number of register */
0355     .reg_defaults = rt715_reg_defaults, /* Defaults */
0356     .num_reg_defaults = ARRAY_SIZE(rt715_reg_defaults),
0357     .cache_type = REGCACHE_RBTREE,
0358     .use_single_read = true,
0359     .use_single_write = true,
0360     .reg_read = rt715_sdw_read,
0361     .reg_write = rt715_sdw_write,
0362 };
0363
0364 static const struct regmap_config rt715_sdw_regmap = {
0365     .name = "sdw",
0366     .reg_bits = 32, /* Total register space for SDW */
0367     .val_bits = 8, /* Total number of bits in register */
0368     .max_register = 0xff01, /* Maximum number of register */
0369     .cache_type = REGCACHE_NONE,
0370     .use_single_read = true,
0371     .use_single_write = true,
0372 };
0373
0374 int hda_to_sdw(unsigned int nid, unsigned int verb, unsigned int payload,
0375            unsigned int *sdw_addr_h, unsigned int *sdw_data_h,
0376            unsigned int *sdw_addr_l, unsigned int *sdw_data_l)
0377 {
0378     unsigned int offset_h, offset_l, e_verb;
0379
0380     if (((verb & 0xff) != 0) || verb == 0xf00) { /* 12 bits command */
0381         if (verb == 0x7ff) /* special case */
0382             offset_h = 0;
0383         else
0384             offset_h = 0x3000;
0385
0386         if (verb & 0x800) /* get command */
0387             e_verb = (verb - 0xf00) | 0x80;
0388         else /* set command */
0389             e_verb = (verb - 0x700);
0390
0391         *sdw_data_h = payload; /* 7 bits payload */
0392         *sdw_addr_l = *sdw_data_l = 0;
0393     } else { /* 4 bits command */
0394         if ((verb & 0x800) == 0x800) { /* read */
0395             offset_h = 0x9000;
0396             offset_l = 0xa000;
0397         } else { /* write */
0398             offset_h = 0x7000;
0399             offset_l = 0x8000;
0400         }
0401         e_verb = verb >> 8;
0402         *sdw_data_h = (payload >> 8); /* 16 bits payload [15:8] */
0403         *sdw_addr_l = (e_verb << 8) | nid | 0x80; /* 0x80: valid bit */
0404         *sdw_addr_l += offset_l;
0405         *sdw_data_l = payload & 0xff;
0406     }
0407
0408     *sdw_addr_h = (e_verb << 8) | nid;
0409     *sdw_addr_h += offset_h;
0410
0411     return 0;
0412 }
0413 EXPORT_SYMBOL(hda_to_sdw);
0414
0415 static int rt715_update_status(struct sdw_slave *slave,
0416                 enum sdw_slave_status status)
0417 {
0418     struct rt715_priv *rt715 = dev_get_drvdata(&slave->dev);
0419
0420     /* Update the status */
0421     rt715->status = status;
0422     /*
0423      * Perform initialization only if slave status is present and
0424      * hw_init flag is false
0425      */
0426     if (rt715->hw_init || rt715->status != SDW_SLAVE_ATTACHED)
0427         return 0;
0428
0429     /* perform I/O transfers required for Slave initialization */
0430     return rt715_io_init(&slave->dev, slave);
0431 }
0432
0433 static int rt715_read_prop(struct sdw_slave *slave)
0434 {
0435     struct sdw_slave_prop *prop = &slave->prop;
0436     int nval, i;
0437     u32 bit;
0438     unsigned long addr;
0439     struct sdw_dpn_prop *dpn;
0440
0441     prop->scp_int1_mask = SDW_SCP_INT1_IMPL_DEF | SDW_SCP_INT1_BUS_CLASH |
0442         SDW_SCP_INT1_PARITY;
0443     prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
0444
0445     prop->paging_support = false;
0446
0447     /* first we need to allocate memory for set bits in port lists */
0448     prop->source_ports = 0x50;/* BITMAP: 01010000 */
0449     prop->sink_ports = 0x0; /* BITMAP:  00000000 */
0450
0451     nval = hweight32(prop->source_ports);
0452     prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
0453                     sizeof(*prop->src_dpn_prop),
0454                     GFP_KERNEL);
0455     if (!prop->src_dpn_prop)
0456         return -ENOMEM;
0457
0458     dpn = prop->src_dpn_prop;
0459     i = 0;
0460     addr = prop->source_ports;
0461     for_each_set_bit(bit, &addr, 32) {
0462         dpn[i].num = bit;
0463         dpn[i].simple_ch_prep_sm = true;
0464         dpn[i].ch_prep_timeout = 10;
0465         i++;
0466     }
0467
0468     /* set the timeout values */
0469     prop->clk_stop_timeout = 20;
0470
0471     /* wake-up event */
0472     prop->wake_capable = 1;
0473
0474     return 0;
0475 }
0476
0477 static int rt715_bus_config(struct sdw_slave *slave,
0478                 struct sdw_bus_params *params)
0479 {
0480     struct rt715_priv *rt715 = dev_get_drvdata(&slave->dev);
0481     int ret;
0482
0483     memcpy(&rt715->params, params, sizeof(*params));
0484
0485     ret = rt715_clock_config(&slave->dev);
0486     if (ret < 0)
0487         dev_err(&slave->dev, "Invalid clk config");
0488
0489     return 0;
0490 }
0491
0492 static const struct sdw_slave_ops rt715_slave_ops = {
0493     .read_prop = rt715_read_prop,
0494     .update_status = rt715_update_status,
0495     .bus_config = rt715_bus_config,
0496 };
0497
0498 static int rt715_sdw_probe(struct sdw_slave *slave,
0499                const struct sdw_device_id *id)
0500 {
0501     struct regmap *sdw_regmap, *regmap;
0502
0503     /* Regmap Initialization */
0504     sdw_regmap = devm_regmap_init_sdw(slave, &rt715_sdw_regmap);
0505     if (IS_ERR(sdw_regmap))
0506         return PTR_ERR(sdw_regmap);
0507
0508     regmap = devm_regmap_init(&slave->dev, NULL, &slave->dev,
0509         &rt715_regmap);
0510     if (IS_ERR(regmap))
0511         return PTR_ERR(regmap);
0512
0513     rt715_init(&slave->dev, sdw_regmap, regmap, slave);
0514
0515     return 0;
0516 }
0517
0518 static int rt715_sdw_remove(struct sdw_slave *slave)
0519 {
0520     struct rt715_priv *rt715 = dev_get_drvdata(&slave->dev);
0521
0522     if (rt715->first_hw_init)
0523         pm_runtime_disable(&slave->dev);
0524
0525     return 0;
0526 }
0527
0528 static const struct sdw_device_id rt715_id[] = {
0529     SDW_SLAVE_ENTRY_EXT(0x025d, 0x714, 0x2, 0, 0),
0530     SDW_SLAVE_ENTRY_EXT(0x025d, 0x715, 0x2, 0, 0),
0531     {},
0532 };
0533 MODULE_DEVICE_TABLE(sdw, rt715_id);
0534
0535 static int __maybe_unused rt715_dev_suspend(struct device *dev)
0536 {
0537     struct rt715_priv *rt715 = dev_get_drvdata(dev);
0538
0539     if (!rt715->hw_init)
0540         return 0;
0541
0542     regcache_cache_only(rt715->regmap, true);
0543
0544     return 0;
0545 }
0546
0547 #define RT715_PROBE_TIMEOUT 5000
0548
0549 static int __maybe_unused rt715_dev_resume(struct device *dev)
0550 {
0551     struct sdw_slave *slave = dev_to_sdw_dev(dev);
0552     struct rt715_priv *rt715 = dev_get_drvdata(dev);
0553     unsigned long time;
0554
0555     if (!rt715->first_hw_init)
0556         return 0;
0557
0558     if (!slave->unattach_request)
0559         goto regmap_sync;
0560
0561     time = wait_for_completion_timeout(&slave->initialization_complete,
0562                        msecs_to_jiffies(RT715_PROBE_TIMEOUT));
0563     if (!time) {
0564         dev_err(&slave->dev, "Initialization not complete, timed out\n");
0565         return -ETIMEDOUT;
0566     }
0567
0568 regmap_sync:
0569     slave->unattach_request = 0;
0570     regcache_cache_only(rt715->regmap, false);
0571     regcache_sync_region(rt715->regmap, 0x3000, 0x8fff);
0572     regcache_sync_region(rt715->regmap, 0x752039, 0x752039);
0573
0574     return 0;
0575 }
0576
0577 static const struct dev_pm_ops rt715_pm = {
0578     SET_SYSTEM_SLEEP_PM_OPS(rt715_dev_suspend, rt715_dev_resume)
0579     SET_RUNTIME_PM_OPS(rt715_dev_suspend, rt715_dev_resume, NULL)
0580 };
0581
0582 static struct sdw_driver rt715_sdw_driver = {
0583     .driver = {
0584            .name = "rt715",
0585            .owner = THIS_MODULE,
0586            .pm = &rt715_pm,
0587            },
0588     .probe = rt715_sdw_probe,
0589     .remove = rt715_sdw_remove,
0590     .ops = &rt715_slave_ops,
0591     .id_table = rt715_id,
0592 };
0593 module_sdw_driver(rt715_sdw_driver);
0594
0595 MODULE_DESCRIPTION("ASoC RT715 driver SDW");
0596 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
0597 MODULE_LICENSE("GPL v2");