soc/codecs/rt715-sdca.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * rt715-sdca.h -- RT715 ALSA SoC audio driver header
0004  *
0005  * Copyright(c) 2020 Realtek Semiconductor Corp.
0006  */
0007
0008 #ifndef __RT715_SDCA_H__
0009 #define __RT715_SDCA_H__
0010
0011 #include <linux/regmap.h>
0012 #include <linux/soundwire/sdw.h>
0013 #include <linux/soundwire/sdw_type.h>
0014 #include <sound/soc.h>
0015 #include <linux/workqueue.h>
0016 #include <linux/device.h>
0017
0018 struct rt715_sdca_priv {
0019     struct regmap *regmap;
0020     struct regmap *mbq_regmap;
0021     struct snd_soc_codec *codec;
0022     struct sdw_slave *slave;
0023     struct delayed_work adc_mute_work;
0024     int dbg_nid;
0025     int dbg_vid;
0026     int dbg_payload;
0027     enum sdw_slave_status status;
0028     struct sdw_bus_params params;
0029     bool hw_init;
0030     bool first_hw_init;
0031     int l_is_unmute;
0032     int r_is_unmute;
0033     int hw_sdw_ver;
0034     int kctl_switch_orig[4];
0035     int kctl_2ch_orig[2];
0036     int kctl_4ch_orig[4];
0037     int kctl_8ch_orig[8];
0038 };
0039
0040 struct rt715_sdw_stream_data {
0041     struct sdw_stream_runtime *sdw_stream;
0042 };
0043
0044 struct rt715_sdca_kcontrol_private {
0045     unsigned int reg_base;
0046     unsigned int count;
0047     unsigned int max;
0048     unsigned int shift;
0049     unsigned int invert;
0050 };
0051
0052 /* MIPI Register */
0053 #define RT715_INT_CTRL                  0x005a
0054 #define RT715_INT_MASK                  0x005e
0055
0056 /* NID */
0057 #define RT715_AUDIO_FUNCTION_GROUP          0x01
0058 #define RT715_MIC_ADC                   0x07
0059 #define RT715_LINE_ADC                  0x08
0060 #define RT715_MIX_ADC                   0x09
0061 #define RT715_DMIC1                 0x12
0062 #define RT715_DMIC2                 0x13
0063 #define RT715_MIC1                  0x18
0064 #define RT715_MIC2                  0x19
0065 #define RT715_LINE1                 0x1a
0066 #define RT715_LINE2                 0x1b
0067 #define RT715_DMIC3                 0x1d
0068 #define RT715_DMIC4                 0x29
0069 #define RT715_VENDOR_REG                0x20
0070 #define RT715_MUX_IN1                   0x22
0071 #define RT715_MUX_IN2                   0x23
0072 #define RT715_MUX_IN3                   0x24
0073 #define RT715_MUX_IN4                   0x25
0074 #define RT715_MIX_ADC2                  0x27
0075 #define RT715_INLINE_CMD                0x55
0076 #define RT715_VENDOR_HDA_CTL                0x61
0077
0078 /* Index (NID:20h) */
0079 #define RT715_PRODUCT_NUM               0x0
0080 #define RT715_IRQ_CTRL                  0x2b
0081 #define RT715_AD_FUNC_EN                0x36
0082 #define RT715_REV_1                 0x37
0083 #define RT715_SDW_INPUT_SEL             0x39
0084 #define RT715_DFLL_VAD                  0x44
0085 #define RT715_EXT_DMIC_CLK_CTRL2            0x54
0086
0087 /* Index (NID:61h) */
0088 #define RT715_HDA_LEGACY_MUX_CTL1           0x00
0089
0090 /* SDCA (Function) */
0091 #define FUN_JACK_CODEC              0x01
0092 #define FUN_MIC_ARRAY               0x02
0093 #define FUN_HID                     0x03
0094 /* SDCA (Entity) */
0095 #define RT715_SDCA_ST_EN                            0x00
0096 #define RT715_SDCA_CS_FREQ_IND_EN                   0x01
0097 #define RT715_SDCA_FU_ADC8_9_VOL                    0x02
0098 #define RT715_SDCA_SMPU_TRIG_ST_EN                  0x05
0099 #define RT715_SDCA_FU_ADC10_11_VOL                  0x06
0100 #define RT715_SDCA_FU_ADC7_27_VOL                   0x0a
0101 #define RT715_SDCA_FU_AMIC_GAIN_EN                  0x0c
0102 #define RT715_SDCA_FU_DMIC_GAIN_EN                  0x0e
0103 #define RT715_SDCA_CX_CLK_SEL_EN                    0x10
0104 #define RT715_SDCA_CREQ_POW_EN                      0x18
0105 /* SDCA (Control) */
0106 #define RT715_SDCA_ST_CTRL                          0x00
0107 #define RT715_SDCA_CX_CLK_SEL_CTRL                  0x01
0108 #define RT715_SDCA_REQ_POW_CTRL                 0x01
0109 #define RT715_SDCA_FU_MUTE_CTRL                 0x01
0110 #define RT715_SDCA_FU_VOL_CTRL                      0x02
0111 #define RT715_SDCA_FU_DMIC_GAIN_CTRL                0x0b
0112 #define RT715_SDCA_FREQ_IND_CTRL                    0x10
0113 #define RT715_SDCA_SMPU_TRIG_EN_CTRL                0x10
0114 #define RT715_SDCA_SMPU_TRIG_ST_CTRL                0x11
0115 /* SDCA (Channel) */
0116 #define CH_00                       0x00
0117 #define CH_01                       0x01
0118 #define CH_02                       0x02
0119 #define CH_03                       0x03
0120 #define CH_04                       0x04
0121 #define CH_05                       0x05
0122 #define CH_06                       0x06
0123 #define CH_07                       0x07
0124 #define CH_08                       0x08
0125
0126 #define RT715_SDCA_DB_STEP          375
0127
0128 enum {
0129     RT715_AIF1,
0130     RT715_AIF2,
0131 };
0132
0133 int rt715_sdca_io_init(struct device *dev, struct sdw_slave *slave);
0134 int rt715_sdca_init(struct device *dev, struct regmap *mbq_regmap,
0135     struct regmap *regmap, struct sdw_slave *slave);
0136
0137 #endif /* __RT715_SDCA_H__ */