soc/codecs/rt5682s.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 //
0003 // rt5682s.c  --  RT5682I-VS ALSA SoC audio component driver
0004 //
0005 // Copyright 2021 Realtek Semiconductor Corp.
0006 // Author: Derek Fang <derek.fang@realtek.com>
0007 //
0008
0009 #include <linux/module.h>
0010 #include <linux/moduleparam.h>
0011 #include <linux/init.h>
0012 #include <linux/delay.h>
0013 #include <linux/pm.h>
0014 #include <linux/pm_runtime.h>
0015 #include <linux/i2c.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/spi/spi.h>
0018 #include <linux/acpi.h>
0019 #include <linux/gpio.h>
0020 #include <linux/of_gpio.h>
0021 #include <linux/mutex.h>
0022 #include <sound/core.h>
0023 #include <sound/pcm.h>
0024 #include <sound/pcm_params.h>
0025 #include <sound/jack.h>
0026 #include <sound/soc.h>
0027 #include <sound/soc-dapm.h>
0028 #include <sound/initval.h>
0029 #include <sound/tlv.h>
0030 #include <sound/rt5682s.h>
0031
0032 #include "rt5682s.h"
0033
0034 #define DEVICE_ID 0x6749
0035
0036 static const struct rt5682s_platform_data i2s_default_platform_data = {
0037     .dmic1_data_pin = RT5682S_DMIC1_DATA_GPIO2,
0038     .dmic1_clk_pin = RT5682S_DMIC1_CLK_GPIO3,
0039     .jd_src = RT5682S_JD1,
0040     .dai_clk_names[RT5682S_DAI_WCLK_IDX] = "rt5682-dai-wclk",
0041     .dai_clk_names[RT5682S_DAI_BCLK_IDX] = "rt5682-dai-bclk",
0042 };
0043
0044 static const char *rt5682s_supply_names[RT5682S_NUM_SUPPLIES] = {
0045     [RT5682S_SUPPLY_AVDD] = "AVDD",
0046     [RT5682S_SUPPLY_MICVDD] = "MICVDD",
0047 };
0048
0049 static const struct reg_sequence patch_list[] = {
0050     {RT5682S_I2C_CTRL,          0x0007},
0051     {RT5682S_DIG_IN_CTRL_1,         0x0000},
0052     {RT5682S_CHOP_DAC_2,            0x2020},
0053     {RT5682S_VREF_REC_OP_FB_CAP_CTRL_2, 0x0101},
0054     {RT5682S_VREF_REC_OP_FB_CAP_CTRL_1, 0x80c0},
0055     {RT5682S_HP_CALIB_CTRL_9,       0x0002},
0056     {RT5682S_DEPOP_1,           0x0000},
0057     {RT5682S_HP_CHARGE_PUMP_2,      0x3c15},
0058     {RT5682S_DAC1_DIG_VOL,          0xfefe},
0059     {RT5682S_SAR_IL_CMD_2,          0xac00},
0060     {RT5682S_SAR_IL_CMD_3,          0x024c},
0061     {RT5682S_CBJ_CTRL_6,            0x0804},
0062 };
0063
0064 static void rt5682s_apply_patch_list(struct rt5682s_priv *rt5682s,
0065         struct device *dev)
0066 {
0067     int ret;
0068
0069     ret = regmap_multi_reg_write(rt5682s->regmap, patch_list, ARRAY_SIZE(patch_list));
0070     if (ret)
0071         dev_warn(dev, "Failed to apply regmap patch: %d\n", ret);
0072 }
0073
0074 static const struct reg_default rt5682s_reg[] = {
0075     {0x0002, 0x8080},
0076     {0x0003, 0x0001},
0077     {0x0005, 0x0000},
0078     {0x0006, 0x0000},
0079     {0x0008, 0x8007},
0080     {0x000b, 0x0000},
0081     {0x000f, 0x4000},
0082     {0x0010, 0x4040},
0083     {0x0011, 0x0000},
0084     {0x0012, 0x0000},
0085     {0x0013, 0x1200},
0086     {0x0014, 0x200a},
0087     {0x0015, 0x0404},
0088     {0x0016, 0x0404},
0089     {0x0017, 0x05a4},
0090     {0x0019, 0xffff},
0091     {0x001c, 0x2f2f},
0092     {0x001f, 0x0000},
0093     {0x0022, 0x5757},
0094     {0x0023, 0x0039},
0095     {0x0024, 0x000b},
0096     {0x0026, 0xc0c4},
0097     {0x0029, 0x8080},
0098     {0x002a, 0xa0a0},
0099     {0x002b, 0x0300},
0100     {0x0030, 0x0000},
0101     {0x003c, 0x08c0},
0102     {0x0044, 0x1818},
0103     {0x004b, 0x00c0},
0104     {0x004c, 0x0000},
0105     {0x004d, 0x0000},
0106     {0x0061, 0x00c0},
0107     {0x0062, 0x008a},
0108     {0x0063, 0x0800},
0109     {0x0064, 0x0000},
0110     {0x0065, 0x0000},
0111     {0x0066, 0x0030},
0112     {0x0067, 0x000c},
0113     {0x0068, 0x0000},
0114     {0x0069, 0x0000},
0115     {0x006a, 0x0000},
0116     {0x006b, 0x0000},
0117     {0x006c, 0x0000},
0118     {0x006d, 0x2200},
0119     {0x006e, 0x0810},
0120     {0x006f, 0xe4de},
0121     {0x0070, 0x3320},
0122     {0x0071, 0x0000},
0123     {0x0073, 0x0000},
0124     {0x0074, 0x0000},
0125     {0x0075, 0x0002},
0126     {0x0076, 0x0001},
0127     {0x0079, 0x0000},
0128     {0x007a, 0x0000},
0129     {0x007b, 0x0000},
0130     {0x007c, 0x0100},
0131     {0x007e, 0x0000},
0132     {0x007f, 0x0000},
0133     {0x0080, 0x0000},
0134     {0x0083, 0x0000},
0135     {0x0084, 0x0000},
0136     {0x0085, 0x0000},
0137     {0x0086, 0x0005},
0138     {0x0087, 0x0000},
0139     {0x0088, 0x0000},
0140     {0x008c, 0x0003},
0141     {0x008e, 0x0060},
0142     {0x008f, 0x4da1},
0143     {0x0091, 0x1c15},
0144     {0x0092, 0x0425},
0145     {0x0093, 0x0000},
0146     {0x0094, 0x0080},
0147     {0x0095, 0x008f},
0148     {0x0096, 0x0000},
0149     {0x0097, 0x0000},
0150     {0x0098, 0x0000},
0151     {0x0099, 0x0000},
0152     {0x009a, 0x0000},
0153     {0x009b, 0x0000},
0154     {0x009c, 0x0000},
0155     {0x009d, 0x0000},
0156     {0x009e, 0x0000},
0157     {0x009f, 0x0009},
0158     {0x00a0, 0x0000},
0159     {0x00a3, 0x0002},
0160     {0x00a4, 0x0001},
0161     {0x00b6, 0x0000},
0162     {0x00b7, 0x0000},
0163     {0x00b8, 0x0000},
0164     {0x00b9, 0x0002},
0165     {0x00be, 0x0000},
0166     {0x00c0, 0x0160},
0167     {0x00c1, 0x82a0},
0168     {0x00c2, 0x0000},
0169     {0x00d0, 0x0000},
0170     {0x00d2, 0x3300},
0171     {0x00d3, 0x2200},
0172     {0x00d4, 0x0000},
0173     {0x00d9, 0x0000},
0174     {0x00da, 0x0000},
0175     {0x00db, 0x0000},
0176     {0x00dc, 0x00c0},
0177     {0x00dd, 0x2220},
0178     {0x00de, 0x3131},
0179     {0x00df, 0x3131},
0180     {0x00e0, 0x3131},
0181     {0x00e2, 0x0000},
0182     {0x00e3, 0x4000},
0183     {0x00e4, 0x0aa0},
0184     {0x00e5, 0x3131},
0185     {0x00e6, 0x3131},
0186     {0x00e7, 0x3131},
0187     {0x00e8, 0x3131},
0188     {0x00ea, 0xb320},
0189     {0x00eb, 0x0000},
0190     {0x00f0, 0x0000},
0191     {0x00f6, 0x0000},
0192     {0x00fa, 0x0000},
0193     {0x00fb, 0x0000},
0194     {0x00fc, 0x0000},
0195     {0x00fd, 0x0000},
0196     {0x00fe, 0x10ec},
0197     {0x00ff, 0x6749},
0198     {0x0100, 0xa000},
0199     {0x010b, 0x0066},
0200     {0x010c, 0x6666},
0201     {0x010d, 0x2202},
0202     {0x010e, 0x6666},
0203     {0x010f, 0xa800},
0204     {0x0110, 0x0006},
0205     {0x0111, 0x0460},
0206     {0x0112, 0x2000},
0207     {0x0113, 0x0200},
0208     {0x0117, 0x8000},
0209     {0x0118, 0x0303},
0210     {0x0125, 0x0020},
0211     {0x0132, 0x5026},
0212     {0x0136, 0x8000},
0213     {0x0139, 0x0005},
0214     {0x013a, 0x3030},
0215     {0x013b, 0xa000},
0216     {0x013c, 0x4110},
0217     {0x013f, 0x0000},
0218     {0x0145, 0x0022},
0219     {0x0146, 0x0000},
0220     {0x0147, 0x0000},
0221     {0x0148, 0x0000},
0222     {0x0156, 0x0022},
0223     {0x0157, 0x0303},
0224     {0x0158, 0x2222},
0225     {0x0159, 0x0000},
0226     {0x0160, 0x4ec0},
0227     {0x0161, 0x0080},
0228     {0x0162, 0x0200},
0229     {0x0163, 0x0800},
0230     {0x0164, 0x0000},
0231     {0x0165, 0x0000},
0232     {0x0166, 0x0000},
0233     {0x0167, 0x000f},
0234     {0x0168, 0x000f},
0235     {0x0169, 0x0001},
0236     {0x0190, 0x4131},
0237     {0x0194, 0x0000},
0238     {0x0195, 0x0000},
0239     {0x0197, 0x0022},
0240     {0x0198, 0x0000},
0241     {0x0199, 0x0000},
0242     {0x01ac, 0x0000},
0243     {0x01ad, 0x0000},
0244     {0x01ae, 0x0000},
0245     {0x01af, 0x2000},
0246     {0x01b0, 0x0000},
0247     {0x01b1, 0x0000},
0248     {0x01b2, 0x0000},
0249     {0x01b3, 0x0017},
0250     {0x01b4, 0x004b},
0251     {0x01b5, 0x0000},
0252     {0x01b6, 0x03e8},
0253     {0x01b7, 0x0000},
0254     {0x01b8, 0x0000},
0255     {0x01b9, 0x0400},
0256     {0x01ba, 0xb5b6},
0257     {0x01bb, 0x9124},
0258     {0x01bc, 0x4924},
0259     {0x01bd, 0x0009},
0260     {0x01be, 0x0018},
0261     {0x01bf, 0x002a},
0262     {0x01c0, 0x004c},
0263     {0x01c1, 0x0097},
0264     {0x01c2, 0x01c3},
0265     {0x01c3, 0x03e9},
0266     {0x01c4, 0x1389},
0267     {0x01c5, 0xc351},
0268     {0x01c6, 0x02a0},
0269     {0x01c7, 0x0b0f},
0270     {0x01c8, 0x402f},
0271     {0x01c9, 0x0702},
0272     {0x01ca, 0x0000},
0273     {0x01cb, 0x0000},
0274     {0x01cc, 0x5757},
0275     {0x01cd, 0x5757},
0276     {0x01ce, 0x5757},
0277     {0x01cf, 0x5757},
0278     {0x01d0, 0x5757},
0279     {0x01d1, 0x5757},
0280     {0x01d2, 0x5757},
0281     {0x01d3, 0x5757},
0282     {0x01d4, 0x5757},
0283     {0x01d5, 0x5757},
0284     {0x01d6, 0x0000},
0285     {0x01d7, 0x0000},
0286     {0x01d8, 0x0162},
0287     {0x01d9, 0x0007},
0288     {0x01da, 0x0000},
0289     {0x01db, 0x0004},
0290     {0x01dc, 0x0000},
0291     {0x01de, 0x7c00},
0292     {0x01df, 0x0020},
0293     {0x01e0, 0x04c1},
0294     {0x01e1, 0x0000},
0295     {0x01e2, 0x0000},
0296     {0x01e3, 0x0000},
0297     {0x01e4, 0x0000},
0298     {0x01e5, 0x0000},
0299     {0x01e6, 0x0001},
0300     {0x01e7, 0x0000},
0301     {0x01e8, 0x0000},
0302     {0x01eb, 0x0000},
0303     {0x01ec, 0x0000},
0304     {0x01ed, 0x0000},
0305     {0x01ee, 0x0000},
0306     {0x01ef, 0x0000},
0307     {0x01f0, 0x0000},
0308     {0x01f1, 0x0000},
0309     {0x01f2, 0x0000},
0310     {0x01f3, 0x0000},
0311     {0x01f4, 0x0000},
0312     {0x0210, 0x6297},
0313     {0x0211, 0xa004},
0314     {0x0212, 0x0365},
0315     {0x0213, 0xf7ff},
0316     {0x0214, 0xf24c},
0317     {0x0215, 0x0102},
0318     {0x0216, 0x00a3},
0319     {0x0217, 0x0048},
0320     {0x0218, 0xa2c0},
0321     {0x0219, 0x0400},
0322     {0x021a, 0x00c8},
0323     {0x021b, 0x00c0},
0324     {0x021c, 0x0000},
0325     {0x021d, 0x024c},
0326     {0x02fa, 0x0000},
0327     {0x02fb, 0x0000},
0328     {0x02fc, 0x0000},
0329     {0x03fe, 0x0000},
0330     {0x03ff, 0x0000},
0331     {0x0500, 0x0000},
0332     {0x0600, 0x0000},
0333     {0x0610, 0x6666},
0334     {0x0611, 0xa9aa},
0335     {0x0620, 0x6666},
0336     {0x0621, 0xa9aa},
0337     {0x0630, 0x6666},
0338     {0x0631, 0xa9aa},
0339     {0x0640, 0x6666},
0340     {0x0641, 0xa9aa},
0341     {0x07fa, 0x0000},
0342     {0x08fa, 0x0000},
0343     {0x08fb, 0x0000},
0344     {0x0d00, 0x0000},
0345     {0x1100, 0x0000},
0346     {0x1101, 0x0000},
0347     {0x1102, 0x0000},
0348     {0x1103, 0x0000},
0349     {0x1104, 0x0000},
0350     {0x1105, 0x0000},
0351     {0x1106, 0x0000},
0352     {0x1107, 0x0000},
0353     {0x1108, 0x0000},
0354     {0x1109, 0x0000},
0355     {0x110a, 0x0000},
0356     {0x110b, 0x0000},
0357     {0x110c, 0x0000},
0358     {0x1111, 0x0000},
0359     {0x1112, 0x0000},
0360     {0x1113, 0x0000},
0361     {0x1114, 0x0000},
0362     {0x1115, 0x0000},
0363     {0x1116, 0x0000},
0364     {0x1117, 0x0000},
0365     {0x1118, 0x0000},
0366     {0x1119, 0x0000},
0367     {0x111a, 0x0000},
0368     {0x111b, 0x0000},
0369     {0x111c, 0x0000},
0370     {0x1401, 0x0404},
0371     {0x1402, 0x0007},
0372     {0x1403, 0x0365},
0373     {0x1404, 0x0210},
0374     {0x1405, 0x0365},
0375     {0x1406, 0x0210},
0376     {0x1407, 0x0000},
0377     {0x1408, 0x0000},
0378     {0x1409, 0x0000},
0379     {0x140a, 0x0000},
0380     {0x140b, 0x0000},
0381     {0x140c, 0x0000},
0382     {0x140d, 0x0000},
0383     {0x140e, 0x0000},
0384     {0x140f, 0x0000},
0385     {0x1410, 0x0000},
0386     {0x1411, 0x0000},
0387     {0x1801, 0x0004},
0388     {0x1802, 0x0000},
0389     {0x1803, 0x0000},
0390     {0x1804, 0x0000},
0391     {0x1805, 0x00ff},
0392     {0x2c00, 0x0000},
0393     {0x3400, 0x0200},
0394     {0x3404, 0x0000},
0395     {0x3405, 0x0000},
0396     {0x3406, 0x0000},
0397     {0x3407, 0x0000},
0398     {0x3408, 0x0000},
0399     {0x3409, 0x0000},
0400     {0x340a, 0x0000},
0401     {0x340b, 0x0000},
0402     {0x340c, 0x0000},
0403     {0x340d, 0x0000},
0404     {0x340e, 0x0000},
0405     {0x340f, 0x0000},
0406     {0x3410, 0x0000},
0407     {0x3411, 0x0000},
0408     {0x3412, 0x0000},
0409     {0x3413, 0x0000},
0410     {0x3414, 0x0000},
0411     {0x3415, 0x0000},
0412     {0x3424, 0x0000},
0413     {0x3425, 0x0000},
0414     {0x3426, 0x0000},
0415     {0x3427, 0x0000},
0416     {0x3428, 0x0000},
0417     {0x3429, 0x0000},
0418     {0x342a, 0x0000},
0419     {0x342b, 0x0000},
0420     {0x342c, 0x0000},
0421     {0x342d, 0x0000},
0422     {0x342e, 0x0000},
0423     {0x342f, 0x0000},
0424     {0x3430, 0x0000},
0425     {0x3431, 0x0000},
0426     {0x3432, 0x0000},
0427     {0x3433, 0x0000},
0428     {0x3434, 0x0000},
0429     {0x3435, 0x0000},
0430     {0x3440, 0x6319},
0431     {0x3441, 0x3771},
0432     {0x3500, 0x0002},
0433     {0x3501, 0x5728},
0434     {0x3b00, 0x3010},
0435     {0x3b01, 0x3300},
0436     {0x3b02, 0x2200},
0437     {0x3b03, 0x0100},
0438 };
0439
0440 static bool rt5682s_volatile_register(struct device *dev, unsigned int reg)
0441 {
0442     switch (reg) {
0443     case RT5682S_RESET:
0444     case RT5682S_CBJ_CTRL_2:
0445     case RT5682S_I2S1_F_DIV_CTRL_2:
0446     case RT5682S_I2S2_F_DIV_CTRL_2:
0447     case RT5682S_INT_ST_1:
0448     case RT5682S_GPIO_ST:
0449     case RT5682S_IL_CMD_1:
0450     case RT5682S_4BTN_IL_CMD_1:
0451     case RT5682S_AJD1_CTRL:
0452     case RT5682S_VERSION_ID...RT5682S_DEVICE_ID:
0453     case RT5682S_STO_NG2_CTRL_1:
0454     case RT5682S_STO_NG2_CTRL_5...RT5682S_STO_NG2_CTRL_7:
0455     case RT5682S_STO1_DAC_SIL_DET:
0456     case RT5682S_HP_IMP_SENS_CTRL_1...RT5682S_HP_IMP_SENS_CTRL_4:
0457     case RT5682S_HP_IMP_SENS_CTRL_13:
0458     case RT5682S_HP_IMP_SENS_CTRL_14:
0459     case RT5682S_HP_IMP_SENS_CTRL_43...RT5682S_HP_IMP_SENS_CTRL_46:
0460     case RT5682S_HP_CALIB_CTRL_1:
0461     case RT5682S_HP_CALIB_CTRL_10:
0462     case RT5682S_HP_CALIB_ST_1...RT5682S_HP_CALIB_ST_11:
0463     case RT5682S_SAR_IL_CMD_2...RT5682S_SAR_IL_CMD_5:
0464     case RT5682S_SAR_IL_CMD_10:
0465     case RT5682S_SAR_IL_CMD_11:
0466     case RT5682S_VERSION_ID_HIDE:
0467     case RT5682S_VERSION_ID_CUS:
0468     case RT5682S_I2C_TRANS_CTRL:
0469     case RT5682S_DMIC_FLOAT_DET:
0470     case RT5682S_HA_CMP_OP_1:
0471     case RT5682S_NEW_CBJ_DET_CTL_10...RT5682S_NEW_CBJ_DET_CTL_16:
0472     case RT5682S_CLK_SW_TEST_1:
0473     case RT5682S_CLK_SW_TEST_2:
0474     case RT5682S_EFUSE_READ_1...RT5682S_EFUSE_READ_18:
0475     case RT5682S_PILOT_DIG_CTL_1:
0476         return true;
0477     default:
0478         return false;
0479     }
0480 }
0481
0482 static bool rt5682s_readable_register(struct device *dev, unsigned int reg)
0483 {
0484     switch (reg) {
0485     case RT5682S_RESET:
0486     case RT5682S_VERSION_ID:
0487     case RT5682S_VENDOR_ID:
0488     case RT5682S_DEVICE_ID:
0489     case RT5682S_HP_CTRL_1:
0490     case RT5682S_HP_CTRL_2:
0491     case RT5682S_HPL_GAIN:
0492     case RT5682S_HPR_GAIN:
0493     case RT5682S_I2C_CTRL:
0494     case RT5682S_CBJ_BST_CTRL:
0495     case RT5682S_CBJ_DET_CTRL:
0496     case RT5682S_CBJ_CTRL_1...RT5682S_CBJ_CTRL_8:
0497     case RT5682S_DAC1_DIG_VOL:
0498     case RT5682S_STO1_ADC_DIG_VOL:
0499     case RT5682S_STO1_ADC_BOOST:
0500     case RT5682S_HP_IMP_GAIN_1:
0501     case RT5682S_HP_IMP_GAIN_2:
0502     case RT5682S_SIDETONE_CTRL:
0503     case RT5682S_STO1_ADC_MIXER:
0504     case RT5682S_AD_DA_MIXER:
0505     case RT5682S_STO1_DAC_MIXER:
0506     case RT5682S_A_DAC1_MUX:
0507     case RT5682S_DIG_INF2_DATA:
0508     case RT5682S_REC_MIXER:
0509     case RT5682S_CAL_REC:
0510     case RT5682S_HP_ANA_OST_CTRL_1...RT5682S_HP_ANA_OST_CTRL_3:
0511     case RT5682S_PWR_DIG_1...RT5682S_PWR_MIXER:
0512     case RT5682S_MB_CTRL:
0513     case RT5682S_CLK_GATE_TCON_1...RT5682S_CLK_GATE_TCON_3:
0514     case RT5682S_CLK_DET...RT5682S_LPF_AD_DMIC:
0515     case RT5682S_I2S1_SDP:
0516     case RT5682S_I2S2_SDP:
0517     case RT5682S_ADDA_CLK_1:
0518     case RT5682S_ADDA_CLK_2:
0519     case RT5682S_I2S1_F_DIV_CTRL_1:
0520     case RT5682S_I2S1_F_DIV_CTRL_2:
0521     case RT5682S_TDM_CTRL:
0522     case RT5682S_TDM_ADDA_CTRL_1:
0523     case RT5682S_TDM_ADDA_CTRL_2:
0524     case RT5682S_DATA_SEL_CTRL_1:
0525     case RT5682S_TDM_TCON_CTRL_1:
0526     case RT5682S_TDM_TCON_CTRL_2:
0527     case RT5682S_GLB_CLK:
0528     case RT5682S_PLL_TRACK_1...RT5682S_PLL_TRACK_6:
0529     case RT5682S_PLL_TRACK_11:
0530     case RT5682S_DEPOP_1:
0531     case RT5682S_HP_CHARGE_PUMP_1:
0532     case RT5682S_HP_CHARGE_PUMP_2:
0533     case RT5682S_HP_CHARGE_PUMP_3:
0534     case RT5682S_MICBIAS_1...RT5682S_MICBIAS_3:
0535     case RT5682S_PLL_TRACK_12...RT5682S_PLL_CTRL_7:
0536     case RT5682S_RC_CLK_CTRL:
0537     case RT5682S_I2S2_M_CLK_CTRL_1:
0538     case RT5682S_I2S2_F_DIV_CTRL_1:
0539     case RT5682S_I2S2_F_DIV_CTRL_2:
0540     case RT5682S_IRQ_CTRL_1...RT5682S_IRQ_CTRL_4:
0541     case RT5682S_INT_ST_1:
0542     case RT5682S_GPIO_CTRL_1:
0543     case RT5682S_GPIO_CTRL_2:
0544     case RT5682S_GPIO_ST:
0545     case RT5682S_HP_AMP_DET_CTRL_1:
0546     case RT5682S_MID_HP_AMP_DET:
0547     case RT5682S_LOW_HP_AMP_DET:
0548     case RT5682S_DELAY_BUF_CTRL:
0549     case RT5682S_SV_ZCD_1:
0550     case RT5682S_SV_ZCD_2:
0551     case RT5682S_IL_CMD_1...RT5682S_IL_CMD_6:
0552     case RT5682S_4BTN_IL_CMD_1...RT5682S_4BTN_IL_CMD_7:
0553     case RT5682S_ADC_STO1_HP_CTRL_1:
0554     case RT5682S_ADC_STO1_HP_CTRL_2:
0555     case RT5682S_AJD1_CTRL:
0556     case RT5682S_JD_CTRL_1:
0557     case RT5682S_DUMMY_1...RT5682S_DUMMY_3:
0558     case RT5682S_DAC_ADC_DIG_VOL1:
0559     case RT5682S_BIAS_CUR_CTRL_2...RT5682S_BIAS_CUR_CTRL_10:
0560     case RT5682S_VREF_REC_OP_FB_CAP_CTRL_1:
0561     case RT5682S_VREF_REC_OP_FB_CAP_CTRL_2:
0562     case RT5682S_CHARGE_PUMP_1:
0563     case RT5682S_DIG_IN_CTRL_1:
0564     case RT5682S_PAD_DRIVING_CTRL:
0565     case RT5682S_CHOP_DAC_1:
0566     case RT5682S_CHOP_DAC_2:
0567     case RT5682S_CHOP_ADC:
0568     case RT5682S_CALIB_ADC_CTRL:
0569     case RT5682S_VOL_TEST:
0570     case RT5682S_SPKVDD_DET_ST:
0571     case RT5682S_TEST_MODE_CTRL_1...RT5682S_TEST_MODE_CTRL_4:
0572     case RT5682S_PLL_INTERNAL_1...RT5682S_PLL_INTERNAL_4:
0573     case RT5682S_STO_NG2_CTRL_1...RT5682S_STO_NG2_CTRL_10:
0574     case RT5682S_STO1_DAC_SIL_DET:
0575     case RT5682S_SIL_PSV_CTRL1:
0576     case RT5682S_SIL_PSV_CTRL2:
0577     case RT5682S_SIL_PSV_CTRL3:
0578     case RT5682S_SIL_PSV_CTRL4:
0579     case RT5682S_SIL_PSV_CTRL5:
0580     case RT5682S_HP_IMP_SENS_CTRL_1...RT5682S_HP_IMP_SENS_CTRL_46:
0581     case RT5682S_HP_LOGIC_CTRL_1...RT5682S_HP_LOGIC_CTRL_3:
0582     case RT5682S_HP_CALIB_CTRL_1...RT5682S_HP_CALIB_CTRL_11:
0583     case RT5682S_HP_CALIB_ST_1...RT5682S_HP_CALIB_ST_11:
0584     case RT5682S_SAR_IL_CMD_1...RT5682S_SAR_IL_CMD_14:
0585     case RT5682S_DUMMY_4...RT5682S_DUMMY_6:
0586     case RT5682S_VERSION_ID_HIDE:
0587     case RT5682S_VERSION_ID_CUS:
0588     case RT5682S_SCAN_CTL:
0589     case RT5682S_HP_AMP_DET:
0590     case RT5682S_BIAS_CUR_CTRL_11:
0591     case RT5682S_BIAS_CUR_CTRL_12:
0592     case RT5682S_BIAS_CUR_CTRL_13:
0593     case RT5682S_BIAS_CUR_CTRL_14:
0594     case RT5682S_BIAS_CUR_CTRL_15:
0595     case RT5682S_BIAS_CUR_CTRL_16:
0596     case RT5682S_BIAS_CUR_CTRL_17:
0597     case RT5682S_BIAS_CUR_CTRL_18:
0598     case RT5682S_I2C_TRANS_CTRL:
0599     case RT5682S_DUMMY_7:
0600     case RT5682S_DUMMY_8:
0601     case RT5682S_DMIC_FLOAT_DET:
0602     case RT5682S_HA_CMP_OP_1...RT5682S_HA_CMP_OP_13:
0603     case RT5682S_HA_CMP_OP_14...RT5682S_HA_CMP_OP_25:
0604     case RT5682S_NEW_CBJ_DET_CTL_1...RT5682S_NEW_CBJ_DET_CTL_16:
0605     case RT5682S_DA_FILTER_1...RT5682S_DA_FILTER_5:
0606     case RT5682S_CLK_SW_TEST_1:
0607     case RT5682S_CLK_SW_TEST_2:
0608     case RT5682S_CLK_SW_TEST_3...RT5682S_CLK_SW_TEST_14:
0609     case RT5682S_EFUSE_MANU_WRITE_1...RT5682S_EFUSE_MANU_WRITE_6:
0610     case RT5682S_EFUSE_READ_1...RT5682S_EFUSE_READ_18:
0611     case RT5682S_EFUSE_TIMING_CTL_1:
0612     case RT5682S_EFUSE_TIMING_CTL_2:
0613     case RT5682S_PILOT_DIG_CTL_1:
0614     case RT5682S_PILOT_DIG_CTL_2:
0615     case RT5682S_HP_AMP_DET_CTL_1...RT5682S_HP_AMP_DET_CTL_4:
0616         return true;
0617     default:
0618         return false;
0619     }
0620 }
0621
0622 static void rt5682s_reset(struct rt5682s_priv *rt5682s)
0623 {
0624     regmap_write(rt5682s->regmap, RT5682S_RESET, 0);
0625 }
0626
0627 static int rt5682s_button_detect(struct snd_soc_component *component)
0628 {
0629     int btn_type, val;
0630
0631     val = snd_soc_component_read(component, RT5682S_4BTN_IL_CMD_1);
0632     btn_type = val & 0xfff0;
0633     snd_soc_component_write(component, RT5682S_4BTN_IL_CMD_1, val);
0634     dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type);
0635     snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_2,
0636         RT5682S_SAR_ADC_PSV_MASK, RT5682S_SAR_ADC_PSV_ENTRY);
0637
0638     return btn_type;
0639 }
0640
0641 enum {
0642     SAR_PWR_OFF,
0643     SAR_PWR_NORMAL,
0644     SAR_PWR_SAVING,
0645 };
0646
0647 static void rt5682s_sar_power_mode(struct snd_soc_component *component, int mode)
0648 {
0649     struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
0650
0651     mutex_lock(&rt5682s->sar_mutex);
0652
0653     switch (mode) {
0654     case SAR_PWR_SAVING:
0655         snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_3,
0656             RT5682S_CBJ_IN_BUF_MASK, RT5682S_CBJ_IN_BUF_DIS);
0657         snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
0658             RT5682S_MB1_PATH_MASK | RT5682S_MB2_PATH_MASK,
0659             RT5682S_CTRL_MB1_REG | RT5682S_CTRL_MB2_REG);
0660         snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
0661             RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK |
0662             RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_BUTDET_DIS |
0663             RT5682S_SAR_BUTDET_POW_SAV | RT5682S_SAR_SEL_MB1_2_MANU);
0664         usleep_range(5000, 5500);
0665         snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
0666             RT5682S_SAR_BUTDET_MASK, RT5682S_SAR_BUTDET_EN);
0667         usleep_range(5000, 5500);
0668         snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_2,
0669             RT5682S_SAR_ADC_PSV_MASK, RT5682S_SAR_ADC_PSV_ENTRY);
0670         break;
0671     case SAR_PWR_NORMAL:
0672         snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_3,
0673             RT5682S_CBJ_IN_BUF_MASK, RT5682S_CBJ_IN_BUF_EN);
0674         snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
0675             RT5682S_MB1_PATH_MASK | RT5682S_MB2_PATH_MASK,
0676             RT5682S_CTRL_MB1_FSM | RT5682S_CTRL_MB2_FSM);
0677         snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
0678             RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_SEL_MB1_2_AUTO);
0679         usleep_range(5000, 5500);
0680         snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
0681             RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK,
0682             RT5682S_SAR_BUTDET_EN | RT5682S_SAR_BUTDET_POW_NORM);
0683         break;
0684     case SAR_PWR_OFF:
0685         snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
0686             RT5682S_MB1_PATH_MASK | RT5682S_MB2_PATH_MASK,
0687             RT5682S_CTRL_MB1_FSM | RT5682S_CTRL_MB2_FSM);
0688         snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
0689             RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK |
0690             RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_BUTDET_DIS |
0691             RT5682S_SAR_BUTDET_POW_SAV | RT5682S_SAR_SEL_MB1_2_MANU);
0692         break;
0693     default:
0694         dev_err(component->dev, "Invalid SAR Power mode: %d\n", mode);
0695         break;
0696     }
0697
0698     mutex_unlock(&rt5682s->sar_mutex);
0699 }
0700
0701 static void rt5682s_enable_push_button_irq(struct snd_soc_component *component)
0702 {
0703     snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_13,
0704         RT5682S_SAR_SOUR_MASK, RT5682S_SAR_SOUR_BTN);
0705     snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
0706         RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK |
0707         RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_BUTDET_EN |
0708         RT5682S_SAR_BUTDET_POW_NORM | RT5682S_SAR_SEL_MB1_2_AUTO);
0709     snd_soc_component_write(component, RT5682S_IL_CMD_1, 0x0040);
0710     snd_soc_component_update_bits(component, RT5682S_4BTN_IL_CMD_2,
0711         RT5682S_4BTN_IL_MASK | RT5682S_4BTN_IL_RST_MASK,
0712         RT5682S_4BTN_IL_EN | RT5682S_4BTN_IL_NOR);
0713     snd_soc_component_update_bits(component, RT5682S_IRQ_CTRL_3,
0714         RT5682S_IL_IRQ_MASK, RT5682S_IL_IRQ_EN);
0715 }
0716
0717 static void rt5682s_disable_push_button_irq(struct snd_soc_component *component)
0718 {
0719     snd_soc_component_update_bits(component, RT5682S_IRQ_CTRL_3,
0720         RT5682S_IL_IRQ_MASK, RT5682S_IL_IRQ_DIS);
0721     snd_soc_component_update_bits(component, RT5682S_4BTN_IL_CMD_2,
0722         RT5682S_4BTN_IL_MASK, RT5682S_4BTN_IL_DIS);
0723     snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_13,
0724         RT5682S_SAR_SOUR_MASK, RT5682S_SAR_SOUR_TYPE);
0725     snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
0726         RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK |
0727         RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_BUTDET_DIS |
0728         RT5682S_SAR_BUTDET_POW_SAV | RT5682S_SAR_SEL_MB1_2_MANU);
0729 }
0730
0731 /**
0732  * rt5682s_headset_detect - Detect headset.
0733  * @component: SoC audio component device.
0734  * @jack_insert: Jack insert or not.
0735  *
0736  * Detect whether is headset or not when jack inserted.
0737  *
0738  * Returns detect status.
0739  */
0740 static int rt5682s_headset_detect(struct snd_soc_component *component, int jack_insert)
0741 {
0742     unsigned int val, count;
0743     int jack_type = 0;
0744
0745     if (jack_insert) {
0746         rt5682s_disable_push_button_irq(component);
0747         snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
0748             RT5682S_PWR_VREF1 | RT5682S_PWR_VREF2 | RT5682S_PWR_MB,
0749             RT5682S_PWR_VREF1 | RT5682S_PWR_VREF2 | RT5682S_PWR_MB);
0750         snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
0751             RT5682S_PWR_FV1 | RT5682S_PWR_FV2, 0);
0752         usleep_range(15000, 20000);
0753         snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
0754             RT5682S_PWR_FV1 | RT5682S_PWR_FV2,
0755             RT5682S_PWR_FV1 | RT5682S_PWR_FV2);
0756         snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_3,
0757             RT5682S_PWR_CBJ, RT5682S_PWR_CBJ);
0758         snd_soc_component_write(component, RT5682S_SAR_IL_CMD_3, 0x0365);
0759         snd_soc_component_update_bits(component, RT5682S_HP_CHARGE_PUMP_2,
0760             RT5682S_OSW_L_MASK | RT5682S_OSW_R_MASK,
0761             RT5682S_OSW_L_DIS | RT5682S_OSW_R_DIS);
0762         snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_13,
0763             RT5682S_SAR_SOUR_MASK, RT5682S_SAR_SOUR_TYPE);
0764         snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_3,
0765             RT5682S_CBJ_IN_BUF_MASK, RT5682S_CBJ_IN_BUF_EN);
0766         snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
0767             RT5682S_TRIG_JD_MASK, RT5682S_TRIG_JD_LOW);
0768         usleep_range(45000, 50000);
0769         snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
0770             RT5682S_TRIG_JD_MASK, RT5682S_TRIG_JD_HIGH);
0771
0772         count = 0;
0773         do {
0774             usleep_range(10000, 15000);
0775             val = snd_soc_component_read(component, RT5682S_CBJ_CTRL_2)
0776                 & RT5682S_JACK_TYPE_MASK;
0777             count++;
0778         } while (val == 0 && count < 50);
0779
0780         dev_dbg(component->dev, "%s, val=%d, count=%d\n", __func__, val, count);
0781
0782         switch (val) {
0783         case 0x1:
0784         case 0x2:
0785             jack_type = SND_JACK_HEADSET;
0786             snd_soc_component_write(component, RT5682S_SAR_IL_CMD_3, 0x024c);
0787             snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
0788                 RT5682S_FAST_OFF_MASK, RT5682S_FAST_OFF_EN);
0789             snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
0790                 RT5682S_SAR_SEL_MB1_2_MASK, val << RT5682S_SAR_SEL_MB1_2_SFT);
0791             rt5682s_enable_push_button_irq(component);
0792             rt5682s_sar_power_mode(component, SAR_PWR_SAVING);
0793             break;
0794         default:
0795             jack_type = SND_JACK_HEADPHONE;
0796             break;
0797         }
0798         snd_soc_component_update_bits(component, RT5682S_HP_CHARGE_PUMP_2,
0799             RT5682S_OSW_L_MASK | RT5682S_OSW_R_MASK,
0800             RT5682S_OSW_L_EN | RT5682S_OSW_R_EN);
0801         usleep_range(35000, 40000);
0802     } else {
0803         rt5682s_sar_power_mode(component, SAR_PWR_OFF);
0804         rt5682s_disable_push_button_irq(component);
0805         snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
0806             RT5682S_TRIG_JD_MASK, RT5682S_TRIG_JD_LOW);
0807
0808         if (!snd_soc_dapm_get_pin_status(&component->dapm, "MICBIAS"))
0809             snd_soc_component_update_bits(component,
0810                 RT5682S_PWR_ANLG_1, RT5682S_PWR_MB, 0);
0811         if (!snd_soc_dapm_get_pin_status(&component->dapm, "Vref2"))
0812             snd_soc_component_update_bits(component,
0813                 RT5682S_PWR_ANLG_1, RT5682S_PWR_VREF2, 0);
0814
0815         snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_3,
0816             RT5682S_PWR_CBJ, 0);
0817         snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
0818             RT5682S_FAST_OFF_MASK, RT5682S_FAST_OFF_DIS);
0819         snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_3,
0820             RT5682S_CBJ_IN_BUF_MASK, RT5682S_CBJ_IN_BUF_DIS);
0821         jack_type = 0;
0822     }
0823
0824     dev_dbg(component->dev, "jack_type = %d\n", jack_type);
0825
0826     return jack_type;
0827 }
0828
0829 static void rt5682s_jack_detect_handler(struct work_struct *work)
0830 {
0831     struct rt5682s_priv *rt5682s =
0832         container_of(work, struct rt5682s_priv, jack_detect_work.work);
0833     struct snd_soc_dapm_context *dapm;
0834     int val, btn_type;
0835
0836     if (!rt5682s->component || !rt5682s->component->card ||
0837         !rt5682s->component->card->instantiated) {
0838         /* card not yet ready, try later */
0839         mod_delayed_work(system_power_efficient_wq,
0840                  &rt5682s->jack_detect_work, msecs_to_jiffies(15));
0841         return;
0842     }
0843
0844     dapm = snd_soc_component_get_dapm(rt5682s->component);
0845
0846     snd_soc_dapm_mutex_lock(dapm);
0847     mutex_lock(&rt5682s->calibrate_mutex);
0848
0849     val = snd_soc_component_read(rt5682s->component, RT5682S_AJD1_CTRL)
0850         & RT5682S_JDH_RS_MASK;
0851     if (!val) {
0852         /* jack in */
0853         if (rt5682s->jack_type == 0) {
0854             /* jack was out, report jack type */
0855             rt5682s->jack_type = rt5682s_headset_detect(rt5682s->component, 1);
0856             rt5682s->irq_work_delay_time = 0;
0857         } else if ((rt5682s->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) {
0858             /* jack is already in, report button event */
0859             rt5682s->jack_type = SND_JACK_HEADSET;
0860             btn_type = rt5682s_button_detect(rt5682s->component);
0861             /**
0862              * rt5682s can report three kinds of button behavior,
0863              * one click, double click and hold. However,
0864              * currently we will report button pressed/released
0865              * event. So all the three button behaviors are
0866              * treated as button pressed.
0867              */
0868             switch (btn_type) {
0869             case 0x8000:
0870             case 0x4000:
0871             case 0x2000:
0872                 rt5682s->jack_type |= SND_JACK_BTN_0;
0873                 break;
0874             case 0x1000:
0875             case 0x0800:
0876             case 0x0400:
0877                 rt5682s->jack_type |= SND_JACK_BTN_1;
0878                 break;
0879             case 0x0200:
0880             case 0x0100:
0881             case 0x0080:
0882                 rt5682s->jack_type |= SND_JACK_BTN_2;
0883                 break;
0884             case 0x0040:
0885             case 0x0020:
0886             case 0x0010:
0887                 rt5682s->jack_type |= SND_JACK_BTN_3;
0888                 break;
0889             case 0x0000: /* unpressed */
0890                 break;
0891             default:
0892                 dev_err(rt5682s->component->dev,
0893                     "Unexpected button code 0x%04x\n", btn_type);
0894                 break;
0895             }
0896         }
0897     } else {
0898         /* jack out */
0899         rt5682s->jack_type = rt5682s_headset_detect(rt5682s->component, 0);
0900         rt5682s->irq_work_delay_time = 50;
0901     }
0902
0903     mutex_unlock(&rt5682s->calibrate_mutex);
0904     snd_soc_dapm_mutex_unlock(dapm);
0905
0906     snd_soc_jack_report(rt5682s->hs_jack, rt5682s->jack_type,
0907         SND_JACK_HEADSET | SND_JACK_BTN_0 | SND_JACK_BTN_1 |
0908         SND_JACK_BTN_2 | SND_JACK_BTN_3);
0909
0910     if (rt5682s->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
0911         SND_JACK_BTN_2 | SND_JACK_BTN_3))
0912         schedule_delayed_work(&rt5682s->jd_check_work, 0);
0913     else
0914         cancel_delayed_work_sync(&rt5682s->jd_check_work);
0915 }
0916
0917 static void rt5682s_jd_check_handler(struct work_struct *work)
0918 {
0919     struct rt5682s_priv *rt5682s =
0920         container_of(work, struct rt5682s_priv, jd_check_work.work);
0921
0922     if (snd_soc_component_read(rt5682s->component, RT5682S_AJD1_CTRL) & RT5682S_JDH_RS_MASK) {
0923         /* jack out */
0924         schedule_delayed_work(&rt5682s->jack_detect_work, 0);
0925     } else {
0926         schedule_delayed_work(&rt5682s->jd_check_work, 500);
0927     }
0928 }
0929
0930 static irqreturn_t rt5682s_irq(int irq, void *data)
0931 {
0932     struct rt5682s_priv *rt5682s = data;
0933
0934     mod_delayed_work(system_power_efficient_wq, &rt5682s->jack_detect_work,
0935         msecs_to_jiffies(rt5682s->irq_work_delay_time));
0936
0937     return IRQ_HANDLED;
0938 }
0939
0940 static int rt5682s_set_jack_detect(struct snd_soc_component *component,
0941         struct snd_soc_jack *hs_jack, void *data)
0942 {
0943     struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
0944     int btndet_delay = 16;
0945
0946     rt5682s->hs_jack = hs_jack;
0947
0948     if (!hs_jack) {
0949         regmap_update_bits(rt5682s->regmap, RT5682S_IRQ_CTRL_2,
0950             RT5682S_JD1_EN_MASK, RT5682S_JD1_DIS);
0951         regmap_update_bits(rt5682s->regmap, RT5682S_RC_CLK_CTRL,
0952             RT5682S_POW_JDH, 0);
0953         cancel_delayed_work_sync(&rt5682s->jack_detect_work);
0954
0955         return 0;
0956     }
0957
0958     switch (rt5682s->pdata.jd_src) {
0959     case RT5682S_JD1:
0960         regmap_update_bits(rt5682s->regmap, RT5682S_CBJ_CTRL_5,
0961             RT5682S_JD_FAST_OFF_SRC_MASK, RT5682S_JD_FAST_OFF_SRC_JDH);
0962         regmap_update_bits(rt5682s->regmap, RT5682S_CBJ_CTRL_2,
0963             RT5682S_EXT_JD_SRC, RT5682S_EXT_JD_SRC_MANUAL);
0964         regmap_update_bits(rt5682s->regmap, RT5682S_CBJ_CTRL_1,
0965             RT5682S_EMB_JD_MASK | RT5682S_DET_TYPE |
0966             RT5682S_POL_FAST_OFF_MASK | RT5682S_MIC_CAP_MASK,
0967             RT5682S_EMB_JD_EN | RT5682S_DET_TYPE |
0968             RT5682S_POL_FAST_OFF_HIGH | RT5682S_MIC_CAP_HS);
0969         regmap_update_bits(rt5682s->regmap, RT5682S_SAR_IL_CMD_1,
0970             RT5682S_SAR_POW_MASK, RT5682S_SAR_POW_EN);
0971         regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1,
0972             RT5682S_GP1_PIN_MASK, RT5682S_GP1_PIN_IRQ);
0973         regmap_update_bits(rt5682s->regmap, RT5682S_PWR_ANLG_3,
0974             RT5682S_PWR_BGLDO, RT5682S_PWR_BGLDO);
0975         regmap_update_bits(rt5682s->regmap, RT5682S_PWR_ANLG_2,
0976             RT5682S_PWR_JD_MASK, RT5682S_PWR_JD_ENABLE);
0977         regmap_update_bits(rt5682s->regmap, RT5682S_RC_CLK_CTRL,
0978             RT5682S_POW_IRQ | RT5682S_POW_JDH, RT5682S_POW_IRQ | RT5682S_POW_JDH);
0979         regmap_update_bits(rt5682s->regmap, RT5682S_IRQ_CTRL_2,
0980             RT5682S_JD1_EN_MASK | RT5682S_JD1_POL_MASK,
0981             RT5682S_JD1_EN | RT5682S_JD1_POL_NOR);
0982         regmap_update_bits(rt5682s->regmap, RT5682S_4BTN_IL_CMD_4,
0983             RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK,
0984             (btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay));
0985         regmap_update_bits(rt5682s->regmap, RT5682S_4BTN_IL_CMD_5,
0986             RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK,
0987             (btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay));
0988         regmap_update_bits(rt5682s->regmap, RT5682S_4BTN_IL_CMD_6,
0989             RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK,
0990             (btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay));
0991         regmap_update_bits(rt5682s->regmap, RT5682S_4BTN_IL_CMD_7,
0992             RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK,
0993             (btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay));
0994
0995         mod_delayed_work(system_power_efficient_wq,
0996             &rt5682s->jack_detect_work, msecs_to_jiffies(250));
0997         break;
0998
0999     case RT5682S_JD_NULL:
1000         regmap_update_bits(rt5682s->regmap, RT5682S_IRQ_CTRL_2,
1001             RT5682S_JD1_EN_MASK, RT5682S_JD1_DIS);
1002         regmap_update_bits(rt5682s->regmap, RT5682S_RC_CLK_CTRL,
1003             RT5682S_POW_JDH, 0);
1004         break;
1005
1006     default:
1007         dev_warn(component->dev, "Wrong JD source\n");
1008         break;
1009     }
1010
1011     return 0;
1012 }
1013
1014 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9562, 75, 0);
1015 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
1016 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
1017 static const DECLARE_TLV_DB_SCALE(cbj_bst_tlv, -1200, 150, 0);
1018
1019 static const struct snd_kcontrol_new rt5682s_snd_controls[] = {
1020     /* DAC Digital Volume */
1021     SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682S_DAC1_DIG_VOL,
1022         RT5682S_L_VOL_SFT + 1, RT5682S_R_VOL_SFT + 1, 127, 0, dac_vol_tlv),
1023
1024     /* CBJ Boost Volume */
1025     SOC_SINGLE_TLV("CBJ Boost Volume", RT5682S_REC_MIXER,
1026         RT5682S_BST_CBJ_SFT, 35, 0,  cbj_bst_tlv),
1027
1028     /* ADC Digital Volume Control */
1029     SOC_DOUBLE("STO1 ADC Capture Switch", RT5682S_STO1_ADC_DIG_VOL,
1030         RT5682S_L_MUTE_SFT, RT5682S_R_MUTE_SFT, 1, 1),
1031     SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682S_STO1_ADC_DIG_VOL,
1032         RT5682S_L_VOL_SFT + 1, RT5682S_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
1033
1034     /* ADC Boost Volume Control */
1035     SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682S_STO1_ADC_BOOST,
1036         RT5682S_STO1_ADC_L_BST_SFT, RT5682S_STO1_ADC_R_BST_SFT, 3, 0, adc_bst_tlv),
1037 };
1038
1039 /**
1040  * rt5682s_sel_asrc_clk_src - select ASRC clock source for a set of filters
1041  * @component: SoC audio component device.
1042  * @filter_mask: mask of filters.
1043  * @clk_src: clock source
1044  *
1045  * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682S can
1046  * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1047  * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1048  * ASRC function will track i2s clock and generate a corresponding system clock
1049  * for codec. This function provides an API to select the clock source for a
1050  * set of filters specified by the mask. And the component driver will turn on
1051  * ASRC for these filters if ASRC is selected as their clock source.
1052  */
1053 int rt5682s_sel_asrc_clk_src(struct snd_soc_component *component,
1054         unsigned int filter_mask, unsigned int clk_src)
1055 {
1056     switch (clk_src) {
1057     case RT5682S_CLK_SEL_SYS:
1058     case RT5682S_CLK_SEL_I2S1_ASRC:
1059     case RT5682S_CLK_SEL_I2S2_ASRC:
1060         break;
1061
1062     default:
1063         return -EINVAL;
1064     }
1065
1066     if (filter_mask & RT5682S_DA_STEREO1_FILTER) {
1067         snd_soc_component_update_bits(component, RT5682S_PLL_TRACK_2,
1068             RT5682S_FILTER_CLK_SEL_MASK, clk_src << RT5682S_FILTER_CLK_SEL_SFT);
1069     }
1070
1071     if (filter_mask & RT5682S_AD_STEREO1_FILTER) {
1072         snd_soc_component_update_bits(component, RT5682S_PLL_TRACK_3,
1073             RT5682S_FILTER_CLK_SEL_MASK, clk_src << RT5682S_FILTER_CLK_SEL_SFT);
1074     }
1075
1076     snd_soc_component_update_bits(component, RT5682S_PLL_TRACK_11,
1077         RT5682S_ASRCIN_AUTO_CLKOUT_MASK, RT5682S_ASRCIN_AUTO_CLKOUT_EN);
1078
1079     return 0;
1080 }
1081 EXPORT_SYMBOL_GPL(rt5682s_sel_asrc_clk_src);
1082
1083 static int rt5682s_div_sel(struct rt5682s_priv *rt5682s,
1084         int target, const int div[], int size)
1085 {
1086     int i;
1087
1088     if (rt5682s->sysclk < target) {
1089         dev_err(rt5682s->component->dev,
1090             "sysclk rate %d is too low\n", rt5682s->sysclk);
1091         return 0;
1092     }
1093
1094     for (i = 0; i < size - 1; i++) {
1095         dev_dbg(rt5682s->component->dev, "div[%d]=%d\n", i, div[i]);
1096         if (target * div[i] == rt5682s->sysclk)
1097             return i;
1098         if (target * div[i + 1] > rt5682s->sysclk) {
1099             dev_dbg(rt5682s->component->dev,
1100                 "can't find div for sysclk %d\n", rt5682s->sysclk);
1101             return i;
1102         }
1103     }
1104
1105     if (target * div[i] < rt5682s->sysclk)
1106         dev_err(rt5682s->component->dev,
1107             "sysclk rate %d is too high\n", rt5682s->sysclk);
1108
1109     return size - 1;
1110 }
1111
1112 static int get_clk_info(int sclk, int rate)
1113 {
1114     int i;
1115     static const int pd[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
1116
1117     if (sclk <= 0 || rate <= 0)
1118         return -EINVAL;
1119
1120     rate = rate << 8;
1121     for (i = 0; i < ARRAY_SIZE(pd); i++)
1122         if (sclk == rate * pd[i])
1123             return i;
1124
1125     return -EINVAL;
1126 }
1127
1128 /**
1129  * set_dmic_clk - Set parameter of dmic.
1130  *
1131  * @w: DAPM widget.
1132  * @kcontrol: The kcontrol of this widget.
1133  * @event: Event id.
1134  *
1135  * Choose dmic clock between 1MHz and 3MHz.
1136  * It is better for clock to approximate 3MHz.
1137  */
1138 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1139         struct snd_kcontrol *kcontrol, int event)
1140 {
1141     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1142     struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1143     int idx, dmic_clk_rate = 3072000;
1144     static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
1145
1146     if (rt5682s->pdata.dmic_clk_rate)
1147         dmic_clk_rate = rt5682s->pdata.dmic_clk_rate;
1148
1149     idx = rt5682s_div_sel(rt5682s, dmic_clk_rate, div, ARRAY_SIZE(div));
1150
1151     snd_soc_component_update_bits(component, RT5682S_DMIC_CTRL_1,
1152         RT5682S_DMIC_CLK_MASK, idx << RT5682S_DMIC_CLK_SFT);
1153
1154     return 0;
1155 }
1156
1157 static int set_filter_clk(struct snd_soc_dapm_widget *w,
1158         struct snd_kcontrol *kcontrol, int event)
1159 {
1160     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1161     struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1162     int ref, val, reg, idx;
1163     static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
1164     static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48};
1165
1166     val = snd_soc_component_read(component, RT5682S_GPIO_CTRL_1)
1167             & RT5682S_GP4_PIN_MASK;
1168
1169     if (w->shift == RT5682S_PWR_ADC_S1F_BIT && val == RT5682S_GP4_PIN_ADCDAT2)
1170         ref = 256 * rt5682s->lrck[RT5682S_AIF2];
1171     else
1172         ref = 256 * rt5682s->lrck[RT5682S_AIF1];
1173
1174     idx = rt5682s_div_sel(rt5682s, ref, div_f, ARRAY_SIZE(div_f));
1175
1176     if (w->shift == RT5682S_PWR_ADC_S1F_BIT)
1177         reg = RT5682S_PLL_TRACK_3;
1178     else
1179         reg = RT5682S_PLL_TRACK_2;
1180
1181     snd_soc_component_update_bits(component, reg,
1182         RT5682S_FILTER_CLK_DIV_MASK, idx << RT5682S_FILTER_CLK_DIV_SFT);
1183
1184     /* select over sample rate */
1185     for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) {
1186         if (rt5682s->sysclk <= 12288000 * div_o[idx])
1187             break;
1188     }
1189
1190     snd_soc_component_update_bits(component, RT5682S_ADDA_CLK_1,
1191         RT5682S_ADC_OSR_MASK | RT5682S_DAC_OSR_MASK,
1192         (idx << RT5682S_ADC_OSR_SFT) | (idx << RT5682S_DAC_OSR_SFT));
1193
1194     return 0;
1195 }
1196
1197 static int set_dmic_power(struct snd_soc_dapm_widget *w,
1198         struct snd_kcontrol *kcontrol, int event)
1199 {
1200     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1201     struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1202     unsigned int delay = 50, val;
1203
1204     if (rt5682s->pdata.dmic_delay)
1205         delay = rt5682s->pdata.dmic_delay;
1206
1207     switch (event) {
1208     case SND_SOC_DAPM_POST_PMU:
1209         val = (snd_soc_component_read(component, RT5682S_GLB_CLK)
1210             & RT5682S_SCLK_SRC_MASK) >> RT5682S_SCLK_SRC_SFT;
1211         if (val == RT5682S_CLK_SRC_PLL1 || val == RT5682S_CLK_SRC_PLL2)
1212             snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
1213                 RT5682S_PWR_VREF2 | RT5682S_PWR_MB,
1214                 RT5682S_PWR_VREF2 | RT5682S_PWR_MB);
1215
1216         /*Add delay to avoid pop noise*/
1217         msleep(delay);
1218         break;
1219
1220     case SND_SOC_DAPM_POST_PMD:
1221         if (!rt5682s->jack_type) {
1222             if (!snd_soc_dapm_get_pin_status(w->dapm, "MICBIAS"))
1223                 snd_soc_component_update_bits(component,
1224                     RT5682S_PWR_ANLG_1, RT5682S_PWR_MB, 0);
1225             if (!snd_soc_dapm_get_pin_status(w->dapm, "Vref2"))
1226                 snd_soc_component_update_bits(component,
1227                     RT5682S_PWR_ANLG_1, RT5682S_PWR_VREF2, 0);
1228         }
1229         break;
1230     }
1231
1232     return 0;
1233 }
1234
1235 static int set_i2s_clk(struct snd_soc_dapm_widget *w,
1236         struct snd_kcontrol *kcontrol, int event)
1237 {
1238     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1239     struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1240     int pre_div, id;
1241     unsigned int reg, mask, sft;
1242
1243     if (event != SND_SOC_DAPM_PRE_PMU)
1244         return 0;
1245
1246     if (w->shift == RT5682S_PWR_I2S2_BIT) {
1247         id = RT5682S_AIF2;
1248         reg = RT5682S_I2S2_M_CLK_CTRL_1;
1249         mask = RT5682S_I2S2_M_D_MASK;
1250         sft = RT5682S_I2S2_M_D_SFT;
1251     } else {
1252         id = RT5682S_AIF1;
1253         reg = RT5682S_ADDA_CLK_1;
1254         mask = RT5682S_I2S_M_D_MASK;
1255         sft = RT5682S_I2S_M_D_SFT;
1256     }
1257
1258     if (!rt5682s->master[id])
1259         return 0;
1260
1261     pre_div = get_clk_info(rt5682s->sysclk, rt5682s->lrck[id]);
1262     if (pre_div < 0) {
1263         dev_err(component->dev, "get pre_div failed\n");
1264         return -EINVAL;
1265     }
1266
1267     dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d master\n",
1268         rt5682s->lrck[id], pre_div, id);
1269     snd_soc_component_update_bits(component, reg, mask, pre_div << sft);
1270
1271     return 0;
1272 }
1273
1274 static int is_sys_clk_from_plla(struct snd_soc_dapm_widget *w,
1275         struct snd_soc_dapm_widget *sink)
1276 {
1277     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1278     struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1279
1280     if ((rt5682s->sysclk_src == RT5682S_CLK_SRC_PLL1) ||
1281         (rt5682s->sysclk_src == RT5682S_CLK_SRC_PLL2 && rt5682s->pll_comb == USE_PLLAB))
1282         return 1;
1283
1284     return 0;
1285 }
1286
1287 static int is_sys_clk_from_pllb(struct snd_soc_dapm_widget *w,
1288         struct snd_soc_dapm_widget *sink)
1289 {
1290     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1291     struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1292
1293     if (rt5682s->sysclk_src == RT5682S_CLK_SRC_PLL2)
1294         return 1;
1295
1296     return 0;
1297 }
1298
1299 static int is_using_asrc(struct snd_soc_dapm_widget *w,
1300         struct snd_soc_dapm_widget *sink)
1301 {
1302     unsigned int reg, sft, val;
1303     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1304
1305     switch (w->shift) {
1306     case RT5682S_ADC_STO1_ASRC_SFT:
1307         reg = RT5682S_PLL_TRACK_3;
1308         sft = RT5682S_FILTER_CLK_SEL_SFT;
1309         break;
1310     case RT5682S_DAC_STO1_ASRC_SFT:
1311         reg = RT5682S_PLL_TRACK_2;
1312         sft = RT5682S_FILTER_CLK_SEL_SFT;
1313         break;
1314     default:
1315         return 0;
1316     }
1317
1318     val = (snd_soc_component_read(component, reg) >> sft) & 0xf;
1319     switch (val) {
1320     case RT5682S_CLK_SEL_I2S1_ASRC:
1321     case RT5682S_CLK_SEL_I2S2_ASRC:
1322         return 1;
1323     default:
1324         return 0;
1325     }
1326 }
1327
1328 static int rt5682s_hp_amp_event(struct snd_soc_dapm_widget *w,
1329         struct snd_kcontrol *kcontrol, int event)
1330 {
1331     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1332
1333     switch (event) {
1334     case SND_SOC_DAPM_POST_PMU:
1335         snd_soc_component_update_bits(component, RT5682S_DEPOP_1,
1336             RT5682S_OUT_HP_L_EN | RT5682S_OUT_HP_R_EN,
1337             RT5682S_OUT_HP_L_EN | RT5682S_OUT_HP_R_EN);
1338         usleep_range(15000, 20000);
1339         snd_soc_component_update_bits(component, RT5682S_DEPOP_1,
1340             RT5682S_LDO_PUMP_EN | RT5682S_PUMP_EN |
1341             RT5682S_CAPLESS_L_EN | RT5682S_CAPLESS_R_EN,
1342             RT5682S_LDO_PUMP_EN | RT5682S_PUMP_EN |
1343             RT5682S_CAPLESS_L_EN | RT5682S_CAPLESS_R_EN);
1344         snd_soc_component_write(component, RT5682S_BIAS_CUR_CTRL_11, 0x6666);
1345         snd_soc_component_write(component, RT5682S_BIAS_CUR_CTRL_12, 0xa82a);
1346
1347         snd_soc_component_update_bits(component, RT5682S_HP_CTRL_2,
1348             RT5682S_HPO_L_PATH_MASK | RT5682S_HPO_R_PATH_MASK |
1349             RT5682S_HPO_SEL_IP_EN_SW, RT5682S_HPO_L_PATH_EN |
1350             RT5682S_HPO_R_PATH_EN | RT5682S_HPO_IP_EN_GATING);
1351         usleep_range(5000, 10000);
1352         snd_soc_component_update_bits(component, RT5682S_HP_AMP_DET_CTL_1,
1353             RT5682S_CP_SW_SIZE_MASK, RT5682S_CP_SW_SIZE_L | RT5682S_CP_SW_SIZE_S);
1354         break;
1355
1356     case SND_SOC_DAPM_POST_PMD:
1357         snd_soc_component_update_bits(component, RT5682S_HP_CTRL_2,
1358             RT5682S_HPO_L_PATH_MASK | RT5682S_HPO_R_PATH_MASK |
1359             RT5682S_HPO_SEL_IP_EN_SW, 0);
1360         snd_soc_component_update_bits(component, RT5682S_HP_AMP_DET_CTL_1,
1361             RT5682S_CP_SW_SIZE_MASK, RT5682S_CP_SW_SIZE_M);
1362         snd_soc_component_update_bits(component, RT5682S_DEPOP_1,
1363             RT5682S_LDO_PUMP_EN | RT5682S_PUMP_EN |
1364             RT5682S_CAPLESS_L_EN | RT5682S_CAPLESS_R_EN, 0);
1365         snd_soc_component_update_bits(component, RT5682S_DEPOP_1,
1366             RT5682S_OUT_HP_L_EN | RT5682S_OUT_HP_R_EN, 0);
1367         break;
1368     }
1369
1370     return 0;
1371 }
1372
1373 static int rt5682s_stereo1_adc_mixl_event(struct snd_soc_dapm_widget *w,
1374         struct snd_kcontrol *kcontrol, int event)
1375 {
1376     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1377     struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1378     unsigned int delay = 0;
1379
1380     if (rt5682s->pdata.amic_delay)
1381         delay = rt5682s->pdata.amic_delay;
1382
1383     switch (event) {
1384     case SND_SOC_DAPM_POST_PMU:
1385         msleep(delay);
1386         snd_soc_component_update_bits(component, RT5682S_STO1_ADC_DIG_VOL,
1387             RT5682S_L_MUTE, 0);
1388         break;
1389     case SND_SOC_DAPM_PRE_PMD:
1390         snd_soc_component_update_bits(component, RT5682S_STO1_ADC_DIG_VOL,
1391             RT5682S_L_MUTE, RT5682S_L_MUTE);
1392         break;
1393     }
1394
1395     return 0;
1396 }
1397
1398 static int sar_power_event(struct snd_soc_dapm_widget *w,
1399         struct snd_kcontrol *kcontrol, int event)
1400 {
1401     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1402     struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1403
1404     if ((rt5682s->jack_type & SND_JACK_HEADSET) != SND_JACK_HEADSET)
1405         return 0;
1406
1407     switch (event) {
1408     case SND_SOC_DAPM_PRE_PMU:
1409         rt5682s_sar_power_mode(component, SAR_PWR_NORMAL);
1410         break;
1411     case SND_SOC_DAPM_POST_PMD:
1412         rt5682s_sar_power_mode(component, SAR_PWR_SAVING);
1413         break;
1414     }
1415
1416     return 0;
1417 }
1418
1419 /* Interface data select */
1420 static const char * const rt5682s_data_select[] = {
1421     "L/R", "R/L", "L/L", "R/R"
1422 };
1423
1424 static SOC_ENUM_SINGLE_DECL(rt5682s_if2_adc_enum, RT5682S_DIG_INF2_DATA,
1425     RT5682S_IF2_ADC_SEL_SFT, rt5682s_data_select);
1426
1427 static SOC_ENUM_SINGLE_DECL(rt5682s_if1_01_adc_enum, RT5682S_TDM_ADDA_CTRL_1,
1428     RT5682S_IF1_ADC1_SEL_SFT, rt5682s_data_select);
1429
1430 static SOC_ENUM_SINGLE_DECL(rt5682s_if1_23_adc_enum, RT5682S_TDM_ADDA_CTRL_1,
1431     RT5682S_IF1_ADC2_SEL_SFT, rt5682s_data_select);
1432
1433 static SOC_ENUM_SINGLE_DECL(rt5682s_if1_45_adc_enum, RT5682S_TDM_ADDA_CTRL_1,
1434     RT5682S_IF1_ADC3_SEL_SFT, rt5682s_data_select);
1435
1436 static SOC_ENUM_SINGLE_DECL(rt5682s_if1_67_adc_enum, RT5682S_TDM_ADDA_CTRL_1,
1437     RT5682S_IF1_ADC4_SEL_SFT, rt5682s_data_select);
1438
1439 static const struct snd_kcontrol_new rt5682s_if2_adc_swap_mux =
1440     SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682s_if2_adc_enum);
1441
1442 static const struct snd_kcontrol_new rt5682s_if1_01_adc_swap_mux =
1443     SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682s_if1_01_adc_enum);
1444
1445 static const struct snd_kcontrol_new rt5682s_if1_23_adc_swap_mux =
1446     SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682s_if1_23_adc_enum);
1447
1448 static const struct snd_kcontrol_new rt5682s_if1_45_adc_swap_mux =
1449     SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682s_if1_45_adc_enum);
1450
1451 static const struct snd_kcontrol_new rt5682s_if1_67_adc_swap_mux =
1452     SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682s_if1_67_adc_enum);
1453
1454 /* Digital Mixer */
1455 static const struct snd_kcontrol_new rt5682s_sto1_adc_l_mix[] = {
1456     SOC_DAPM_SINGLE("ADC1 Switch", RT5682S_STO1_ADC_MIXER,
1457             RT5682S_M_STO1_ADC_L1_SFT, 1, 1),
1458     SOC_DAPM_SINGLE("ADC2 Switch", RT5682S_STO1_ADC_MIXER,
1459             RT5682S_M_STO1_ADC_L2_SFT, 1, 1),
1460 };
1461
1462 static const struct snd_kcontrol_new rt5682s_sto1_adc_r_mix[] = {
1463     SOC_DAPM_SINGLE("ADC1 Switch", RT5682S_STO1_ADC_MIXER,
1464             RT5682S_M_STO1_ADC_R1_SFT, 1, 1),
1465     SOC_DAPM_SINGLE("ADC2 Switch", RT5682S_STO1_ADC_MIXER,
1466             RT5682S_M_STO1_ADC_R2_SFT, 1, 1),
1467 };
1468
1469 static const struct snd_kcontrol_new rt5682s_dac_l_mix[] = {
1470     SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682S_AD_DA_MIXER,
1471             RT5682S_M_ADCMIX_L_SFT, 1, 1),
1472     SOC_DAPM_SINGLE("DAC1 Switch", RT5682S_AD_DA_MIXER,
1473             RT5682S_M_DAC1_L_SFT, 1, 1),
1474 };
1475
1476 static const struct snd_kcontrol_new rt5682s_dac_r_mix[] = {
1477     SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682S_AD_DA_MIXER,
1478             RT5682S_M_ADCMIX_R_SFT, 1, 1),
1479     SOC_DAPM_SINGLE("DAC1 Switch", RT5682S_AD_DA_MIXER,
1480             RT5682S_M_DAC1_R_SFT, 1, 1),
1481 };
1482
1483 static const struct snd_kcontrol_new rt5682s_sto1_dac_l_mix[] = {
1484     SOC_DAPM_SINGLE("DAC L1 Switch", RT5682S_STO1_DAC_MIXER,
1485             RT5682S_M_DAC_L1_STO_L_SFT, 1, 1),
1486     SOC_DAPM_SINGLE("DAC R1 Switch", RT5682S_STO1_DAC_MIXER,
1487             RT5682S_M_DAC_R1_STO_L_SFT, 1, 1),
1488 };
1489
1490 static const struct snd_kcontrol_new rt5682s_sto1_dac_r_mix[] = {
1491     SOC_DAPM_SINGLE("DAC L1 Switch", RT5682S_STO1_DAC_MIXER,
1492             RT5682S_M_DAC_L1_STO_R_SFT, 1, 1),
1493     SOC_DAPM_SINGLE("DAC R1 Switch", RT5682S_STO1_DAC_MIXER,
1494             RT5682S_M_DAC_R1_STO_R_SFT, 1, 1),
1495 };
1496
1497 /* Analog Input Mixer */
1498 static const struct snd_kcontrol_new rt5682s_rec1_l_mix[] = {
1499     SOC_DAPM_SINGLE("CBJ Switch", RT5682S_REC_MIXER,
1500             RT5682S_M_CBJ_RM1_L_SFT, 1, 1),
1501 };
1502
1503 static const struct snd_kcontrol_new rt5682s_rec1_r_mix[] = {
1504     SOC_DAPM_SINGLE("CBJ Switch", RT5682S_REC_MIXER,
1505             RT5682S_M_CBJ_RM1_R_SFT, 1, 1),
1506 };
1507
1508 /* STO1 ADC1 Source */
1509 /* MX-26 [13] [5] */
1510 static const char * const rt5682s_sto1_adc1_src[] = {
1511     "DAC MIX", "ADC"
1512 };
1513
1514 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adc1l_enum, RT5682S_STO1_ADC_MIXER,
1515     RT5682S_STO1_ADC1L_SRC_SFT, rt5682s_sto1_adc1_src);
1516
1517 static const struct snd_kcontrol_new rt5682s_sto1_adc1l_mux =
1518     SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682s_sto1_adc1l_enum);
1519
1520 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adc1r_enum, RT5682S_STO1_ADC_MIXER,
1521     RT5682S_STO1_ADC1R_SRC_SFT, rt5682s_sto1_adc1_src);
1522
1523 static const struct snd_kcontrol_new rt5682s_sto1_adc1r_mux =
1524     SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682s_sto1_adc1r_enum);
1525
1526 /* STO1 ADC Source */
1527 /* MX-26 [11:10] [3:2] */
1528 static const char * const rt5682s_sto1_adc_src[] = {
1529     "ADC1 L", "ADC1 R"
1530 };
1531
1532 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adcl_enum, RT5682S_STO1_ADC_MIXER,
1533     RT5682S_STO1_ADCL_SRC_SFT, rt5682s_sto1_adc_src);
1534
1535 static const struct snd_kcontrol_new rt5682s_sto1_adcl_mux =
1536     SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682s_sto1_adcl_enum);
1537
1538 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adcr_enum, RT5682S_STO1_ADC_MIXER,
1539     RT5682S_STO1_ADCR_SRC_SFT, rt5682s_sto1_adc_src);
1540
1541 static const struct snd_kcontrol_new rt5682s_sto1_adcr_mux =
1542     SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682s_sto1_adcr_enum);
1543
1544 /* STO1 ADC2 Source */
1545 /* MX-26 [12] [4] */
1546 static const char * const rt5682s_sto1_adc2_src[] = {
1547     "DAC MIX", "DMIC"
1548 };
1549
1550 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adc2l_enum, RT5682S_STO1_ADC_MIXER,
1551     RT5682S_STO1_ADC2L_SRC_SFT, rt5682s_sto1_adc2_src);
1552
1553 static const struct snd_kcontrol_new rt5682s_sto1_adc2l_mux =
1554     SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682s_sto1_adc2l_enum);
1555
1556 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adc2r_enum, RT5682S_STO1_ADC_MIXER,
1557     RT5682S_STO1_ADC2R_SRC_SFT, rt5682s_sto1_adc2_src);
1558
1559 static const struct snd_kcontrol_new rt5682s_sto1_adc2r_mux =
1560     SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682s_sto1_adc2r_enum);
1561
1562 /* MX-79 [6:4] I2S1 ADC data location */
1563 static const unsigned int rt5682s_if1_adc_slot_values[] = {
1564     0, 2, 4, 6,
1565 };
1566
1567 static const char * const rt5682s_if1_adc_slot_src[] = {
1568     "Slot 0", "Slot 2", "Slot 4", "Slot 6"
1569 };
1570
1571 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682s_if1_adc_slot_enum,
1572     RT5682S_TDM_CTRL, RT5682S_TDM_ADC_LCA_SFT, RT5682S_TDM_ADC_LCA_MASK,
1573     rt5682s_if1_adc_slot_src, rt5682s_if1_adc_slot_values);
1574
1575 static const struct snd_kcontrol_new rt5682s_if1_adc_slot_mux =
1576     SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682s_if1_adc_slot_enum);
1577
1578 /* Analog DAC L1 Source, Analog DAC R1 Source*/
1579 /* MX-2B [4], MX-2B [0]*/
1580 static const char * const rt5682s_alg_dac1_src[] = {
1581     "Stereo1 DAC Mixer", "DAC1"
1582 };
1583
1584 static SOC_ENUM_SINGLE_DECL(rt5682s_alg_dac_l1_enum, RT5682S_A_DAC1_MUX,
1585     RT5682S_A_DACL1_SFT, rt5682s_alg_dac1_src);
1586
1587 static const struct snd_kcontrol_new rt5682s_alg_dac_l1_mux =
1588     SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682s_alg_dac_l1_enum);
1589
1590 static SOC_ENUM_SINGLE_DECL(rt5682s_alg_dac_r1_enum, RT5682S_A_DAC1_MUX,
1591     RT5682S_A_DACR1_SFT, rt5682s_alg_dac1_src);
1592
1593 static const struct snd_kcontrol_new rt5682s_alg_dac_r1_mux =
1594     SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682s_alg_dac_r1_enum);
1595
1596 static const unsigned int rt5682s_adcdat_pin_values[] = {
1597     1, 3,
1598 };
1599
1600 static const char * const rt5682s_adcdat_pin_select[] = {
1601     "ADCDAT1", "ADCDAT2",
1602 };
1603
1604 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682s_adcdat_pin_enum,
1605     RT5682S_GPIO_CTRL_1, RT5682S_GP4_PIN_SFT, RT5682S_GP4_PIN_MASK,
1606     rt5682s_adcdat_pin_select, rt5682s_adcdat_pin_values);
1607
1608 static const struct snd_kcontrol_new rt5682s_adcdat_pin_ctrl =
1609     SOC_DAPM_ENUM("ADCDAT", rt5682s_adcdat_pin_enum);
1610
1611 static const struct snd_soc_dapm_widget rt5682s_dapm_widgets[] = {
1612     SND_SOC_DAPM_SUPPLY("LDO MB1", RT5682S_PWR_ANLG_3,
1613         RT5682S_PWR_LDO_MB1_BIT, 0, NULL, 0),
1614     SND_SOC_DAPM_SUPPLY("LDO MB2", RT5682S_PWR_ANLG_3,
1615         RT5682S_PWR_LDO_MB2_BIT, 0, NULL, 0),
1616     SND_SOC_DAPM_SUPPLY("LDO", RT5682S_PWR_ANLG_3,
1617         RT5682S_PWR_LDO_BIT, 0, NULL, 0),
1618     SND_SOC_DAPM_SUPPLY("Vref2", SND_SOC_NOPM, 0, 0, NULL, 0),
1619     SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, NULL, 0),
1620
1621     /* PLL Powers */
1622     SND_SOC_DAPM_SUPPLY_S("PLLA_LDO", 0, RT5682S_PWR_ANLG_3,
1623         RT5682S_PWR_LDO_PLLA_BIT, 0, NULL, 0),
1624     SND_SOC_DAPM_SUPPLY_S("PLLB_LDO", 0, RT5682S_PWR_ANLG_3,
1625         RT5682S_PWR_LDO_PLLB_BIT, 0, NULL, 0),
1626     SND_SOC_DAPM_SUPPLY_S("PLLA_BIAS", 0, RT5682S_PWR_ANLG_3,
1627         RT5682S_PWR_BIAS_PLLA_BIT, 0, NULL, 0),
1628     SND_SOC_DAPM_SUPPLY_S("PLLB_BIAS", 0, RT5682S_PWR_ANLG_3,
1629         RT5682S_PWR_BIAS_PLLB_BIT, 0, NULL, 0),
1630     SND_SOC_DAPM_SUPPLY_S("PLLA", 0, RT5682S_PWR_ANLG_3,
1631         RT5682S_PWR_PLLA_BIT, 0, NULL, 0),
1632     SND_SOC_DAPM_SUPPLY_S("PLLB", 0, RT5682S_PWR_ANLG_3,
1633         RT5682S_PWR_PLLB_BIT, 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU),
1634     SND_SOC_DAPM_SUPPLY_S("PLLA_RST", 1, RT5682S_PWR_ANLG_3,
1635         RT5682S_RSTB_PLLA_BIT, 0, NULL, 0),
1636     SND_SOC_DAPM_SUPPLY_S("PLLB_RST", 1, RT5682S_PWR_ANLG_3,
1637         RT5682S_RSTB_PLLB_BIT, 0, NULL, 0),
1638
1639     /* ASRC */
1640     SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682S_PLL_TRACK_1,
1641         RT5682S_DAC_STO1_ASRC_SFT, 0, NULL, 0),
1642     SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682S_PLL_TRACK_1,
1643         RT5682S_ADC_STO1_ASRC_SFT, 0, NULL, 0),
1644     SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682S_PLL_TRACK_1,
1645         RT5682S_AD_ASRC_SFT, 0, NULL, 0),
1646     SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682S_PLL_TRACK_1,
1647         RT5682S_DA_ASRC_SFT, 0, NULL, 0),
1648     SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682S_PLL_TRACK_1,
1649         RT5682S_DMIC_ASRC_SFT, 0, NULL, 0),
1650
1651     /* Input Side */
1652     SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682S_PWR_ANLG_2,
1653         RT5682S_PWR_MB1_BIT, 0, NULL, 0),
1654     SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682S_PWR_ANLG_2,
1655         RT5682S_PWR_MB2_BIT, 0, NULL, 0),
1656
1657     /* Input Lines */
1658     SND_SOC_DAPM_INPUT("DMIC L1"),
1659     SND_SOC_DAPM_INPUT("DMIC R1"),
1660
1661     SND_SOC_DAPM_INPUT("IN1P"),
1662
1663     SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1664         set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1665     SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682S_DMIC_CTRL_1, RT5682S_DMIC_1_EN_SFT, 0,
1666         set_dmic_power, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1667
1668     /* Boost */
1669     SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 0, 0, NULL, 0),
1670
1671     /* REC Mixer */
1672     SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682s_rec1_l_mix,
1673         ARRAY_SIZE(rt5682s_rec1_l_mix)),
1674     SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5682s_rec1_r_mix,
1675         ARRAY_SIZE(rt5682s_rec1_r_mix)),
1676     SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682S_CAL_REC,
1677         RT5682S_PWR_RM1_L_BIT, 0, NULL, 0),
1678     SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5682S_CAL_REC,
1679         RT5682S_PWR_RM1_R_BIT, 0, NULL, 0),
1680
1681     /* ADCs */
1682     SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
1683     SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
1684
1685     SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682S_PWR_DIG_1,
1686         RT5682S_PWR_ADC_L1_BIT, 0, NULL, 0),
1687     SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682S_PWR_DIG_1,
1688         RT5682S_PWR_ADC_R1_BIT, 0, NULL, 0),
1689     SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682S_CHOP_ADC,
1690         RT5682S_CKGEN_ADC1_SFT, 0, NULL, 0),
1691
1692     /* ADC Mux */
1693     SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1694         &rt5682s_sto1_adc1l_mux),
1695     SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1696         &rt5682s_sto1_adc1r_mux),
1697     SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1698         &rt5682s_sto1_adc2l_mux),
1699     SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1700         &rt5682s_sto1_adc2r_mux),
1701     SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
1702         &rt5682s_sto1_adcl_mux),
1703     SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
1704         &rt5682s_sto1_adcr_mux),
1705     SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
1706         &rt5682s_if1_adc_slot_mux),
1707
1708     /* ADC Mixer */
1709     SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682S_PWR_DIG_2,
1710         RT5682S_PWR_ADC_S1F_BIT, 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU),
1711     SND_SOC_DAPM_MIXER_E("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0,
1712         rt5682s_sto1_adc_l_mix, ARRAY_SIZE(rt5682s_sto1_adc_l_mix),
1713         rt5682s_stereo1_adc_mixl_event,
1714         SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1715     SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682S_STO1_ADC_DIG_VOL,
1716         RT5682S_R_MUTE_SFT, 1, rt5682s_sto1_adc_r_mix,
1717         ARRAY_SIZE(rt5682s_sto1_adc_r_mix)),
1718
1719     /* ADC PGA */
1720     SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1721
1722     /* Digital Interface */
1723     SND_SOC_DAPM_SUPPLY("I2S1", RT5682S_PWR_DIG_1, RT5682S_PWR_I2S1_BIT,
1724         0, set_i2s_clk, SND_SOC_DAPM_PRE_PMU),
1725     SND_SOC_DAPM_SUPPLY("I2S2", RT5682S_PWR_DIG_1, RT5682S_PWR_I2S2_BIT,
1726         0, set_i2s_clk, SND_SOC_DAPM_PRE_PMU),
1727     SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1728     SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1729
1730     /* Digital Interface Select */
1731     SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1732         &rt5682s_if1_01_adc_swap_mux),
1733     SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1734         &rt5682s_if1_23_adc_swap_mux),
1735     SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1736         &rt5682s_if1_45_adc_swap_mux),
1737     SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1738         &rt5682s_if1_67_adc_swap_mux),
1739     SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1740         &rt5682s_if2_adc_swap_mux),
1741
1742     SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0, &rt5682s_adcdat_pin_ctrl),
1743
1744     /* Audio Interface */
1745     SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, RT5682S_I2S1_SDP,
1746         RT5682S_SEL_ADCDAT_SFT, 1),
1747     SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, RT5682S_I2S2_SDP,
1748         RT5682S_I2S2_PIN_CFG_SFT, 1),
1749     SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1750
1751     /* Output Side */
1752     /* DAC mixer before sound effect  */
1753     SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1754         rt5682s_dac_l_mix, ARRAY_SIZE(rt5682s_dac_l_mix)),
1755     SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1756         rt5682s_dac_r_mix, ARRAY_SIZE(rt5682s_dac_r_mix)),
1757
1758     /* DAC channel Mux */
1759     SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0, &rt5682s_alg_dac_l1_mux),
1760     SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0, &rt5682s_alg_dac_r1_mux),
1761
1762     /* DAC Mixer */
1763     SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682S_PWR_DIG_2,
1764         RT5682S_PWR_DAC_S1F_BIT, 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU),
1765     SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
1766         rt5682s_sto1_dac_l_mix, ARRAY_SIZE(rt5682s_sto1_dac_l_mix)),
1767     SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
1768         rt5682s_sto1_dac_r_mix, ARRAY_SIZE(rt5682s_sto1_dac_r_mix)),
1769
1770     /* DACs */
1771     SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682S_PWR_DIG_1, RT5682S_PWR_DAC_L1_BIT, 0),
1772     SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682S_PWR_DIG_1, RT5682S_PWR_DAC_R1_BIT, 0),
1773
1774     /* HPO */
1775     SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682s_hp_amp_event,
1776         SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
1777
1778     /* CLK DET */
1779     SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682S_CLK_DET,
1780         RT5682S_SYS_CLK_DET_SFT, 0, NULL, 0),
1781     SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682S_CLK_DET,
1782         RT5682S_PLL1_CLK_DET_SFT, 0, NULL, 0),
1783     SND_SOC_DAPM_SUPPLY("MCLK0 DET PWR", RT5682S_PWR_ANLG_2,
1784         RT5682S_PWR_MCLK0_WD_BIT, 0, NULL, 0),
1785
1786     /* SAR */
1787     SND_SOC_DAPM_SUPPLY("SAR", SND_SOC_NOPM, 0, 0, sar_power_event,
1788         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1789
1790     /* Output Lines */
1791     SND_SOC_DAPM_OUTPUT("HPOL"),
1792     SND_SOC_DAPM_OUTPUT("HPOR"),
1793 };
1794
1795 static const struct snd_soc_dapm_route rt5682s_dapm_routes[] = {
1796     /*PLL*/
1797     {"ADC Stereo1 Filter", NULL, "PLLA", is_sys_clk_from_plla},
1798     {"ADC Stereo1 Filter", NULL, "PLLB", is_sys_clk_from_pllb},
1799     {"DAC Stereo1 Filter", NULL, "PLLA", is_sys_clk_from_plla},
1800     {"DAC Stereo1 Filter", NULL, "PLLB", is_sys_clk_from_pllb},
1801     {"PLLA", NULL, "PLLA_LDO"},
1802     {"PLLA", NULL, "PLLA_BIAS"},
1803     {"PLLA", NULL, "PLLA_RST"},
1804     {"PLLB", NULL, "PLLB_LDO"},
1805     {"PLLB", NULL, "PLLB_BIAS"},
1806     {"PLLB", NULL, "PLLB_RST"},
1807
1808     /*ASRC*/
1809     {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
1810     {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
1811     {"ADC STO1 ASRC", NULL, "AD ASRC"},
1812     {"ADC STO1 ASRC", NULL, "DA ASRC"},
1813     {"DAC STO1 ASRC", NULL, "AD ASRC"},
1814     {"DAC STO1 ASRC", NULL, "DA ASRC"},
1815
1816     {"CLKDET SYS", NULL, "MCLK0 DET PWR"},
1817
1818     {"BST1 CBJ", NULL, "IN1P"},
1819     {"BST1 CBJ", NULL, "SAR"},
1820
1821     {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
1822     {"RECMIX1L", NULL, "RECMIX1L Power"},
1823     {"RECMIX1R", "CBJ Switch", "BST1 CBJ"},
1824     {"RECMIX1R", NULL, "RECMIX1R Power"},
1825
1826     {"ADC1 L", NULL, "RECMIX1L"},
1827     {"ADC1 L", NULL, "ADC1 L Power"},
1828     {"ADC1 L", NULL, "ADC1 clock"},
1829     {"ADC1 R", NULL, "RECMIX1R"},
1830     {"ADC1 R", NULL, "ADC1 R Power"},
1831     {"ADC1 R", NULL, "ADC1 clock"},
1832
1833     {"DMIC L1", NULL, "DMIC CLK"},
1834     {"DMIC L1", NULL, "DMIC1 Power"},
1835     {"DMIC R1", NULL, "DMIC CLK"},
1836     {"DMIC R1", NULL, "DMIC1 Power"},
1837     {"DMIC CLK", NULL, "DMIC ASRC"},
1838
1839     {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
1840     {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
1841     {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
1842     {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
1843
1844     {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
1845     {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1846     {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1847     {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1848
1849     {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
1850     {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1851     {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1852     {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1853
1854     {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1855     {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1856     {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
1857
1858     {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1859     {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1860     {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
1861
1862     {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
1863     {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
1864
1865     {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1866     {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1867     {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1868     {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1869     {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1870     {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1871     {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1872     {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1873     {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1874     {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1875     {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1876     {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1877     {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1878     {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1879     {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1880     {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1881
1882     {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
1883     {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
1884     {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
1885     {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
1886     {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
1887     {"AIF1TX", NULL, "I2S1"},
1888     {"AIF1TX", NULL, "ADCDAT Mux"},
1889     {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1890     {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1891     {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1892     {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1893     {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
1894     {"AIF2TX", NULL, "ADCDAT Mux"},
1895
1896     {"IF1 DAC1 L", NULL, "AIF1RX"},
1897     {"IF1 DAC1 L", NULL, "I2S1"},
1898     {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},
1899     {"IF1 DAC1 R", NULL, "AIF1RX"},
1900     {"IF1 DAC1 R", NULL, "I2S1"},
1901     {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},
1902
1903     {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
1904     {"DAC1 MIXL", "DAC1 Switch", "IF1 DAC1 L"},
1905     {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
1906     {"DAC1 MIXR", "DAC1 Switch", "IF1 DAC1 R"},
1907
1908     {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
1909     {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
1910
1911     {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
1912     {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
1913
1914     {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
1915     {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
1916     {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
1917     {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
1918
1919     {"DAC L1", NULL, "DAC L1 Source"},
1920     {"DAC R1", NULL, "DAC R1 Source"},
1921
1922     {"HP Amp", NULL, "DAC L1"},
1923     {"HP Amp", NULL, "DAC R1"},
1924     {"HP Amp", NULL, "CLKDET SYS"},
1925     {"HP Amp", NULL, "SAR"},
1926
1927     {"HPOL", NULL, "HP Amp"},
1928     {"HPOR", NULL, "HP Amp"},
1929 };
1930
1931 static int rt5682s_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1932         unsigned int rx_mask, int slots, int slot_width)
1933 {
1934     struct snd_soc_component *component = dai->component;
1935     unsigned int cl, val = 0;
1936
1937     if (tx_mask || rx_mask)
1938         snd_soc_component_update_bits(component,
1939             RT5682S_TDM_ADDA_CTRL_2, RT5682S_TDM_EN, RT5682S_TDM_EN);
1940     else
1941         snd_soc_component_update_bits(component,
1942             RT5682S_TDM_ADDA_CTRL_2, RT5682S_TDM_EN, 0);
1943
1944     switch (slots) {
1945     case 4:
1946         val |= RT5682S_TDM_TX_CH_4;
1947         val |= RT5682S_TDM_RX_CH_4;
1948         break;
1949     case 6:
1950         val |= RT5682S_TDM_TX_CH_6;
1951         val |= RT5682S_TDM_RX_CH_6;
1952         break;
1953     case 8:
1954         val |= RT5682S_TDM_TX_CH_8;
1955         val |= RT5682S_TDM_RX_CH_8;
1956         break;
1957     case 2:
1958         break;
1959     default:
1960         return -EINVAL;
1961     }
1962
1963     snd_soc_component_update_bits(component, RT5682S_TDM_CTRL,
1964         RT5682S_TDM_TX_CH_MASK | RT5682S_TDM_RX_CH_MASK, val);
1965
1966     switch (slot_width) {
1967     case 8:
1968         if (tx_mask || rx_mask)
1969             return -EINVAL;
1970         cl = RT5682S_I2S1_TX_CHL_8 | RT5682S_I2S1_RX_CHL_8;
1971         break;
1972     case 16:
1973         val = RT5682S_TDM_CL_16;
1974         cl = RT5682S_I2S1_TX_CHL_16 | RT5682S_I2S1_RX_CHL_16;
1975         break;
1976     case 20:
1977         val = RT5682S_TDM_CL_20;
1978         cl = RT5682S_I2S1_TX_CHL_20 | RT5682S_I2S1_RX_CHL_20;
1979         break;
1980     case 24:
1981         val = RT5682S_TDM_CL_24;
1982         cl = RT5682S_I2S1_TX_CHL_24 | RT5682S_I2S1_RX_CHL_24;
1983         break;
1984     case 32:
1985         val = RT5682S_TDM_CL_32;
1986         cl = RT5682S_I2S1_TX_CHL_32 | RT5682S_I2S1_RX_CHL_32;
1987         break;
1988     default:
1989         return -EINVAL;
1990     }
1991
1992     snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
1993         RT5682S_TDM_CL_MASK, val);
1994     snd_soc_component_update_bits(component, RT5682S_I2S1_SDP,
1995         RT5682S_I2S1_TX_CHL_MASK | RT5682S_I2S1_RX_CHL_MASK, cl);
1996
1997     return 0;
1998 }
1999
2000 static int rt5682s_hw_params(struct snd_pcm_substream *substream,
2001         struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2002 {
2003     struct snd_soc_component *component = dai->component;
2004     struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2005     unsigned int len_1 = 0, len_2 = 0;
2006     int frame_size;
2007
2008     rt5682s->lrck[dai->id] = params_rate(params);
2009
2010     frame_size = snd_soc_params_to_frame_size(params);
2011     if (frame_size < 0) {
2012         dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
2013         return -EINVAL;
2014     }
2015
2016     switch (params_width(params)) {
2017     case 16:
2018         break;
2019     case 20:
2020         len_1 |= RT5682S_I2S1_DL_20;
2021         len_2 |= RT5682S_I2S2_DL_20;
2022         break;
2023     case 24:
2024         len_1 |= RT5682S_I2S1_DL_24;
2025         len_2 |= RT5682S_I2S2_DL_24;
2026         break;
2027     case 32:
2028         len_1 |= RT5682S_I2S1_DL_32;
2029         len_2 |= RT5682S_I2S2_DL_24;
2030         break;
2031     case 8:
2032         len_1 |= RT5682S_I2S2_DL_8;
2033         len_2 |= RT5682S_I2S2_DL_8;
2034         break;
2035     default:
2036         return -EINVAL;
2037     }
2038
2039     switch (dai->id) {
2040     case RT5682S_AIF1:
2041         snd_soc_component_update_bits(component, RT5682S_I2S1_SDP,
2042             RT5682S_I2S1_DL_MASK, len_1);
2043         if (params_channels(params) == 1) /* mono mode */
2044             snd_soc_component_update_bits(component, RT5682S_I2S1_SDP,
2045                 RT5682S_I2S1_MONO_MASK, RT5682S_I2S1_MONO_EN);
2046         else
2047             snd_soc_component_update_bits(component, RT5682S_I2S1_SDP,
2048                 RT5682S_I2S1_MONO_MASK, RT5682S_I2S1_MONO_DIS);
2049         break;
2050     case RT5682S_AIF2:
2051         snd_soc_component_update_bits(component, RT5682S_I2S2_SDP,
2052             RT5682S_I2S2_DL_MASK, len_2);
2053         if (params_channels(params) == 1) /* mono mode */
2054             snd_soc_component_update_bits(component, RT5682S_I2S2_SDP,
2055                 RT5682S_I2S2_MONO_MASK, RT5682S_I2S2_MONO_EN);
2056         else
2057             snd_soc_component_update_bits(component, RT5682S_I2S2_SDP,
2058                 RT5682S_I2S2_MONO_MASK, RT5682S_I2S2_MONO_DIS);
2059         break;
2060     default:
2061         dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2062         return -EINVAL;
2063     }
2064
2065     return 0;
2066 }
2067
2068 static int rt5682s_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2069 {
2070     struct snd_soc_component *component = dai->component;
2071     struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2072     unsigned int reg_val = 0, tdm_ctrl = 0;
2073
2074     switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2075     case SND_SOC_DAIFMT_CBM_CFM:
2076         rt5682s->master[dai->id] = 1;
2077         break;
2078     case SND_SOC_DAIFMT_CBS_CFS:
2079         rt5682s->master[dai->id] = 0;
2080         break;
2081     default:
2082         return -EINVAL;
2083     }
2084
2085     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2086     case SND_SOC_DAIFMT_NB_NF:
2087         break;
2088     case SND_SOC_DAIFMT_IB_NF:
2089         reg_val |= RT5682S_I2S_BP_INV;
2090         tdm_ctrl |= RT5682S_TDM_S_BP_INV;
2091         break;
2092     case SND_SOC_DAIFMT_NB_IF:
2093         if (dai->id == RT5682S_AIF1)
2094             tdm_ctrl |= RT5682S_TDM_S_LP_INV | RT5682S_TDM_M_BP_INV;
2095         else
2096             return -EINVAL;
2097         break;
2098     case SND_SOC_DAIFMT_IB_IF:
2099         if (dai->id == RT5682S_AIF1)
2100             tdm_ctrl |= RT5682S_TDM_S_BP_INV | RT5682S_TDM_S_LP_INV |
2101                 RT5682S_TDM_M_BP_INV | RT5682S_TDM_M_LP_INV;
2102         else
2103             return -EINVAL;
2104         break;
2105     default:
2106         return -EINVAL;
2107     }
2108
2109     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2110     case SND_SOC_DAIFMT_I2S:
2111         break;
2112     case SND_SOC_DAIFMT_LEFT_J:
2113         reg_val |= RT5682S_I2S_DF_LEFT;
2114         tdm_ctrl |= RT5682S_TDM_DF_LEFT;
2115         break;
2116     case SND_SOC_DAIFMT_DSP_A:
2117         reg_val |= RT5682S_I2S_DF_PCM_A;
2118         tdm_ctrl |= RT5682S_TDM_DF_PCM_A;
2119         break;
2120     case SND_SOC_DAIFMT_DSP_B:
2121         reg_val |= RT5682S_I2S_DF_PCM_B;
2122         tdm_ctrl |= RT5682S_TDM_DF_PCM_B;
2123         break;
2124     default:
2125         return -EINVAL;
2126     }
2127
2128     switch (dai->id) {
2129     case RT5682S_AIF1:
2130         snd_soc_component_update_bits(component, RT5682S_I2S1_SDP,
2131             RT5682S_I2S_DF_MASK, reg_val);
2132         snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
2133             RT5682S_TDM_MS_MASK | RT5682S_TDM_S_BP_MASK |
2134             RT5682S_TDM_DF_MASK | RT5682S_TDM_M_BP_MASK |
2135             RT5682S_TDM_M_LP_MASK | RT5682S_TDM_S_LP_MASK,
2136             tdm_ctrl | rt5682s->master[dai->id]);
2137         break;
2138     case RT5682S_AIF2:
2139         if (rt5682s->master[dai->id] == 0)
2140             reg_val |= RT5682S_I2S2_MS_S;
2141         snd_soc_component_update_bits(component, RT5682S_I2S2_SDP,
2142             RT5682S_I2S2_MS_MASK | RT5682S_I2S_BP_MASK |
2143             RT5682S_I2S_DF_MASK, reg_val);
2144         break;
2145     default:
2146         dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2147         return -EINVAL;
2148     }
2149     return 0;
2150 }
2151
2152 static int rt5682s_set_component_sysclk(struct snd_soc_component *component,
2153         int clk_id, int source, unsigned int freq, int dir)
2154 {
2155     struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2156     unsigned int src = 0;
2157
2158     if (freq == rt5682s->sysclk && clk_id == rt5682s->sysclk_src)
2159         return 0;
2160
2161     switch (clk_id) {
2162     case RT5682S_SCLK_S_MCLK:
2163         src = RT5682S_CLK_SRC_MCLK;
2164         break;
2165     case RT5682S_SCLK_S_PLL1:
2166         src = RT5682S_CLK_SRC_PLL1;
2167         break;
2168     case RT5682S_SCLK_S_PLL2:
2169         src = RT5682S_CLK_SRC_PLL2;
2170         break;
2171     case RT5682S_SCLK_S_RCCLK:
2172         src = RT5682S_CLK_SRC_RCCLK;
2173         break;
2174     default:
2175         dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2176         return -EINVAL;
2177     }
2178
2179     snd_soc_component_update_bits(component, RT5682S_GLB_CLK,
2180         RT5682S_SCLK_SRC_MASK, src << RT5682S_SCLK_SRC_SFT);
2181     snd_soc_component_update_bits(component, RT5682S_ADDA_CLK_1,
2182         RT5682S_I2S_M_CLK_SRC_MASK, src << RT5682S_I2S_M_CLK_SRC_SFT);
2183     snd_soc_component_update_bits(component, RT5682S_I2S2_M_CLK_CTRL_1,
2184         RT5682S_I2S2_M_CLK_SRC_MASK, src << RT5682S_I2S2_M_CLK_SRC_SFT);
2185
2186     rt5682s->sysclk = freq;
2187     rt5682s->sysclk_src = clk_id;
2188
2189     dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2190         freq, clk_id);
2191
2192     return 0;
2193 }
2194
2195 static const struct pll_calc_map plla_table[] = {
2196     {2048000, 24576000, 0, 46, 2, true, false, false, false},
2197     {256000, 24576000, 0, 382, 2, true, false, false, false},
2198     {512000, 24576000, 0, 190, 2, true, false, false, false},
2199     {4096000, 24576000, 0, 22, 2, true, false, false, false},
2200     {1024000, 24576000, 0, 94, 2, true, false, false, false},
2201     {11289600, 22579200, 1, 22, 2, false, false, false, false},
2202     {1411200, 22579200, 0, 62, 2, true, false, false, false},
2203     {2822400, 22579200, 0, 30, 2, true, false, false, false},
2204     {12288000, 24576000, 1, 22, 2, false, false, false, false},
2205     {1536000, 24576000, 0, 62, 2, true, false, false, false},
2206     {3072000, 24576000, 0, 30, 2, true, false, false, false},
2207     {24576000, 49152000, 4, 22, 0, false, false, false, false},
2208     {3072000, 49152000, 0, 30, 0, true, false, false, false},
2209     {6144000, 49152000, 0, 30, 0, false, false, false, false},
2210     {49152000, 98304000, 10, 22, 0, false, true, false, false},
2211     {6144000, 98304000, 0, 30, 0, false, true, false, false},
2212     {12288000, 98304000, 1, 22, 0, false, true, false, false},
2213     {48000000, 3840000, 10, 22, 23, false, false, false, false},
2214     {24000000, 3840000, 4, 22, 23, false, false, false, false},
2215     {19200000, 3840000, 3, 23, 23, false, false, false, false},
2216     {38400000, 3840000, 8, 23, 23, false, false, false, false},
2217 };
2218
2219 static const struct pll_calc_map pllb_table[] = {
2220     {48000000, 24576000, 8, 6, 3, false, false, false, false},
2221     {48000000, 22579200, 23, 12, 3, false, false, false, true},
2222     {24000000, 24576000, 3, 6, 3, false, false, false, false},
2223     {24000000, 22579200, 23, 26, 3, false, false, false, true},
2224     {19200000, 24576000, 2, 6, 3, false, false, false, false},
2225     {19200000, 22579200, 3, 5, 3, false, false, false, true},
2226     {38400000, 24576000, 6, 6, 3, false, false, false, false},
2227     {38400000, 22579200, 8, 5, 3, false, false, false, true},
2228     {3840000, 49152000, 0, 6, 0, true, false, false, false},
2229 };
2230
2231 static int find_pll_inter_combination(unsigned int f_in, unsigned int f_out,
2232         struct pll_calc_map *a, struct pll_calc_map *b)
2233 {
2234     int i, j;
2235
2236     /* Look at PLLA table */
2237     for (i = 0; i < ARRAY_SIZE(plla_table); i++) {
2238         if (plla_table[i].freq_in == f_in && plla_table[i].freq_out == f_out) {
2239             memcpy(a, plla_table + i, sizeof(*a));
2240             return USE_PLLA;
2241         }
2242     }
2243
2244     /* Look at PLLB table */
2245     for (i = 0; i < ARRAY_SIZE(pllb_table); i++) {
2246         if (pllb_table[i].freq_in == f_in && pllb_table[i].freq_out == f_out) {
2247             memcpy(b, pllb_table + i, sizeof(*b));
2248             return USE_PLLB;
2249         }
2250     }
2251
2252     /* Find a combination of PLLA & PLLB */
2253     for (i = ARRAY_SIZE(plla_table) - 1; i >= 0; i--) {
2254         if (plla_table[i].freq_in == f_in && plla_table[i].freq_out == 3840000) {
2255             for (j = ARRAY_SIZE(pllb_table) - 1; j >= 0; j--) {
2256                 if (pllb_table[j].freq_in == 3840000 &&
2257                     pllb_table[j].freq_out == f_out) {
2258                     memcpy(a, plla_table + i, sizeof(*a));
2259                     memcpy(b, pllb_table + j, sizeof(*b));
2260                     return USE_PLLAB;
2261                 }
2262             }
2263         }
2264     }
2265
2266     return -EINVAL;
2267 }
2268
2269 static int rt5682s_set_component_pll(struct snd_soc_component *component,
2270         int pll_id, int source, unsigned int freq_in,
2271         unsigned int freq_out)
2272 {
2273     struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2274     struct pll_calc_map a_map, b_map;
2275
2276     if (source == rt5682s->pll_src[pll_id] && freq_in == rt5682s->pll_in[pll_id] &&
2277         freq_out == rt5682s->pll_out[pll_id])
2278         return 0;
2279
2280     if (!freq_in || !freq_out) {
2281         dev_dbg(component->dev, "PLL disabled\n");
2282         rt5682s->pll_in[pll_id] = 0;
2283         rt5682s->pll_out[pll_id] = 0;
2284         snd_soc_component_update_bits(component, RT5682S_GLB_CLK,
2285             RT5682S_SCLK_SRC_MASK, RT5682S_CLK_SRC_MCLK << RT5682S_SCLK_SRC_SFT);
2286         return 0;
2287     }
2288
2289     switch (source) {
2290     case RT5682S_PLL_S_MCLK:
2291         snd_soc_component_update_bits(component, RT5682S_GLB_CLK,
2292             RT5682S_PLL_SRC_MASK, RT5682S_PLL_SRC_MCLK);
2293         break;
2294     case RT5682S_PLL_S_BCLK1:
2295         snd_soc_component_update_bits(component, RT5682S_GLB_CLK,
2296             RT5682S_PLL_SRC_MASK, RT5682S_PLL_SRC_BCLK1);
2297         break;
2298     default:
2299         dev_err(component->dev, "Unknown PLL Source %d\n", source);
2300         return -EINVAL;
2301     }
2302
2303     rt5682s->pll_comb = find_pll_inter_combination(freq_in, freq_out,
2304                             &a_map, &b_map);
2305
2306     if ((pll_id == RT5682S_PLL1 && rt5682s->pll_comb == USE_PLLA) ||
2307         (pll_id == RT5682S_PLL2 && (rt5682s->pll_comb == USE_PLLB ||
2308                     rt5682s->pll_comb == USE_PLLAB))) {
2309         dev_dbg(component->dev,
2310             "Supported freq conversion for PLL%d:(%d->%d): %d\n",
2311             pll_id + 1, freq_in, freq_out, rt5682s->pll_comb);
2312     } else {
2313         dev_err(component->dev,
2314             "Unsupported freq conversion for PLL%d:(%d->%d): %d\n",
2315             pll_id + 1, freq_in, freq_out, rt5682s->pll_comb);
2316         return -EINVAL;
2317     }
2318
2319     if (rt5682s->pll_comb == USE_PLLA || rt5682s->pll_comb == USE_PLLAB) {
2320         dev_dbg(component->dev,
2321             "PLLA: fin=%d fout=%d m_bp=%d k_bp=%d m=%d n=%d k=%d\n",
2322             a_map.freq_in, a_map.freq_out, a_map.m_bp, a_map.k_bp,
2323             (a_map.m_bp ? 0 : a_map.m), a_map.n, (a_map.k_bp ? 0 : a_map.k));
2324         snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_1,
2325             RT5682S_PLLA_N_MASK, a_map.n);
2326         snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_2,
2327             RT5682S_PLLA_M_MASK | RT5682S_PLLA_K_MASK,
2328             a_map.m << RT5682S_PLLA_M_SFT | a_map.k);
2329         snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_6,
2330             RT5682S_PLLA_M_BP_MASK | RT5682S_PLLA_K_BP_MASK,
2331             a_map.m_bp << RT5682S_PLLA_M_BP_SFT |
2332             a_map.k_bp << RT5682S_PLLA_K_BP_SFT);
2333     }
2334
2335     if (rt5682s->pll_comb == USE_PLLB || rt5682s->pll_comb == USE_PLLAB) {
2336         dev_dbg(component->dev,
2337             "PLLB: fin=%d fout=%d m_bp=%d k_bp=%d m=%d n=%d k=%d byp_ps=%d sel_ps=%d\n",
2338             b_map.freq_in, b_map.freq_out, b_map.m_bp, b_map.k_bp,
2339             (b_map.m_bp ? 0 : b_map.m), b_map.n, (b_map.k_bp ? 0 : b_map.k),
2340             b_map.byp_ps, b_map.sel_ps);
2341         snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_3,
2342             RT5682S_PLLB_N_MASK, b_map.n);
2343         snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_4,
2344             RT5682S_PLLB_M_MASK | RT5682S_PLLB_K_MASK,
2345             b_map.m << RT5682S_PLLB_M_SFT | b_map.k);
2346         snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_6,
2347             RT5682S_PLLB_SEL_PS_MASK | RT5682S_PLLB_BYP_PS_MASK |
2348             RT5682S_PLLB_M_BP_MASK | RT5682S_PLLB_K_BP_MASK,
2349             b_map.sel_ps << RT5682S_PLLB_SEL_PS_SFT |
2350             b_map.byp_ps << RT5682S_PLLB_BYP_PS_SFT |
2351             b_map.m_bp << RT5682S_PLLB_M_BP_SFT |
2352             b_map.k_bp << RT5682S_PLLB_K_BP_SFT);
2353     }
2354
2355     if (rt5682s->pll_comb == USE_PLLB)
2356         snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_7,
2357             RT5682S_PLLB_SRC_MASK, RT5682S_PLLB_SRC_DFIN);
2358
2359     rt5682s->pll_in[pll_id] = freq_in;
2360     rt5682s->pll_out[pll_id] = freq_out;
2361     rt5682s->pll_src[pll_id] = source;
2362
2363     return 0;
2364 }
2365
2366 static int rt5682s_set_bclk1_ratio(struct snd_soc_dai *dai,
2367         unsigned int ratio)
2368 {
2369     struct snd_soc_component *component = dai->component;
2370     struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2371
2372     rt5682s->bclk[dai->id] = ratio;
2373
2374     switch (ratio) {
2375     case 256:
2376         snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
2377             RT5682S_TDM_BCLK_MS1_MASK, RT5682S_TDM_BCLK_MS1_256);
2378         break;
2379     case 128:
2380         snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
2381             RT5682S_TDM_BCLK_MS1_MASK, RT5682S_TDM_BCLK_MS1_128);
2382         break;
2383     case 64:
2384         snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
2385             RT5682S_TDM_BCLK_MS1_MASK, RT5682S_TDM_BCLK_MS1_64);
2386         break;
2387     case 32:
2388         snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
2389             RT5682S_TDM_BCLK_MS1_MASK, RT5682S_TDM_BCLK_MS1_32);
2390         break;
2391     default:
2392         dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio);
2393         return -EINVAL;
2394     }
2395
2396     return 0;
2397 }
2398
2399 static int rt5682s_set_bclk2_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2400 {
2401     struct snd_soc_component *component = dai->component;
2402     struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2403
2404     rt5682s->bclk[dai->id] = ratio;
2405
2406     switch (ratio) {
2407     case 64:
2408         snd_soc_component_update_bits(component, RT5682S_ADDA_CLK_2,
2409             RT5682S_I2S2_BCLK_MS2_MASK, RT5682S_I2S2_BCLK_MS2_64);
2410         break;
2411     case 32:
2412         snd_soc_component_update_bits(component, RT5682S_ADDA_CLK_2,
2413             RT5682S_I2S2_BCLK_MS2_MASK, RT5682S_I2S2_BCLK_MS2_32);
2414         break;
2415     default:
2416         dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio);
2417         return -EINVAL;
2418     }
2419
2420     return 0;
2421 }
2422
2423 static int rt5682s_set_bias_level(struct snd_soc_component *component,
2424         enum snd_soc_bias_level level)
2425 {
2426     struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2427
2428     switch (level) {
2429     case SND_SOC_BIAS_PREPARE:
2430         regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_1,
2431             RT5682S_PWR_LDO, RT5682S_PWR_LDO);
2432         break;
2433     case SND_SOC_BIAS_STANDBY:
2434         regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_1,
2435             RT5682S_DIG_GATE_CTRL, RT5682S_DIG_GATE_CTRL);
2436         break;
2437     case SND_SOC_BIAS_OFF:
2438         regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_1,
2439             RT5682S_DIG_GATE_CTRL | RT5682S_PWR_LDO, 0);
2440         break;
2441     case SND_SOC_BIAS_ON:
2442         break;
2443     }
2444
2445     return 0;
2446 }
2447
2448 #ifdef CONFIG_COMMON_CLK
2449 #define CLK_PLL2_FIN 48000000
2450 #define CLK_48 48000
2451 #define CLK_44 44100
2452
2453 static bool rt5682s_clk_check(struct rt5682s_priv *rt5682s)
2454 {
2455     if (!rt5682s->master[RT5682S_AIF1]) {
2456         dev_dbg(rt5682s->component->dev, "dai clk fmt not set correctly\n");
2457         return false;
2458     }
2459     return true;
2460 }
2461
2462 static int rt5682s_wclk_prepare(struct clk_hw *hw)
2463 {
2464     struct rt5682s_priv *rt5682s =
2465         container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]);
2466     struct snd_soc_component *component = rt5682s->component;
2467     struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
2468
2469     if (!rt5682s_clk_check(rt5682s))
2470         return -EINVAL;
2471
2472     snd_soc_dapm_mutex_lock(dapm);
2473
2474     snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS");
2475     snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
2476         RT5682S_PWR_MB, RT5682S_PWR_MB);
2477
2478     snd_soc_dapm_force_enable_pin_unlocked(dapm, "Vref2");
2479     snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
2480         RT5682S_PWR_VREF2 | RT5682S_PWR_FV2, RT5682S_PWR_VREF2);
2481     usleep_range(15000, 20000);
2482     snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
2483         RT5682S_PWR_FV2, RT5682S_PWR_FV2);
2484
2485     snd_soc_dapm_force_enable_pin_unlocked(dapm, "I2S1");
2486     /* Only need to power PLLB due to the rate set restriction */
2487     snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLLB");
2488     snd_soc_dapm_sync_unlocked(dapm);
2489
2490     snd_soc_dapm_mutex_unlock(dapm);
2491
2492     return 0;
2493 }
2494
2495 static void rt5682s_wclk_unprepare(struct clk_hw *hw)
2496 {
2497     struct rt5682s_priv *rt5682s =
2498         container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]);
2499     struct snd_soc_component *component = rt5682s->component;
2500     struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
2501
2502     if (!rt5682s_clk_check(rt5682s))
2503         return;
2504
2505     snd_soc_dapm_mutex_lock(dapm);
2506
2507     snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS");
2508     snd_soc_dapm_disable_pin_unlocked(dapm, "Vref2");
2509     if (!rt5682s->jack_type)
2510         snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
2511             RT5682S_PWR_VREF2 | RT5682S_PWR_FV2 | RT5682S_PWR_MB, 0);
2512
2513     snd_soc_dapm_disable_pin_unlocked(dapm, "I2S1");
2514     snd_soc_dapm_disable_pin_unlocked(dapm, "PLLB");
2515     snd_soc_dapm_sync_unlocked(dapm);
2516
2517     snd_soc_dapm_mutex_unlock(dapm);
2518 }
2519
2520 static unsigned long rt5682s_wclk_recalc_rate(struct clk_hw *hw,
2521                          unsigned long parent_rate)
2522 {
2523     struct rt5682s_priv *rt5682s =
2524         container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]);
2525     struct snd_soc_component *component = rt5682s->component;
2526     const char * const clk_name = clk_hw_get_name(hw);
2527
2528     if (!rt5682s_clk_check(rt5682s))
2529         return 0;
2530     /*
2531      * Only accept to set wclk rate to 44.1k or 48kHz.
2532      */
2533     if (rt5682s->lrck[RT5682S_AIF1] != CLK_48 &&
2534         rt5682s->lrck[RT5682S_AIF1] != CLK_44) {
2535         dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n",
2536             __func__, clk_name, CLK_44, CLK_48);
2537         return 0;
2538     }
2539
2540     return rt5682s->lrck[RT5682S_AIF1];
2541 }
2542
2543 static long rt5682s_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
2544                    unsigned long *parent_rate)
2545 {
2546     struct rt5682s_priv *rt5682s =
2547         container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]);
2548     struct snd_soc_component *component = rt5682s->component;
2549     const char * const clk_name = clk_hw_get_name(hw);
2550
2551     if (!rt5682s_clk_check(rt5682s))
2552         return -EINVAL;
2553     /*
2554      * Only accept to set wclk rate to 44.1k or 48kHz.
2555      * It will force to 48kHz if not both.
2556      */
2557     if (rate != CLK_48 && rate != CLK_44) {
2558         dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n",
2559             __func__, clk_name, CLK_44, CLK_48);
2560         rate = CLK_48;
2561     }
2562
2563     return rate;
2564 }
2565
2566 static int rt5682s_wclk_set_rate(struct clk_hw *hw, unsigned long rate,
2567                 unsigned long parent_rate)
2568 {
2569     struct rt5682s_priv *rt5682s =
2570         container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]);
2571     struct snd_soc_component *component = rt5682s->component;
2572     struct clk *parent_clk;
2573     const char * const clk_name = clk_hw_get_name(hw);
2574     unsigned int clk_pll2_fout;
2575
2576     if (!rt5682s_clk_check(rt5682s))
2577         return -EINVAL;
2578
2579     /*
2580      * Whether the wclk's parent clk (mclk) exists or not, please ensure
2581      * it is fixed or set to 48MHz before setting wclk rate. It's a
2582      * temporary limitation. Only accept 48MHz clk as the clk provider.
2583      *
2584      * It will set the codec anyway by assuming mclk is 48MHz.
2585      */
2586     parent_clk = clk_get_parent(hw->clk);
2587     if (!parent_clk)
2588         dev_warn(component->dev,
2589             "Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n",
2590             CLK_PLL2_FIN);
2591
2592     if (parent_rate != CLK_PLL2_FIN)
2593         dev_warn(component->dev, "clk %s only support %d Hz input\n",
2594             clk_name, CLK_PLL2_FIN);
2595
2596     /*
2597      * To achieve the rate conversion from 48MHz to 44.1k or 48kHz,
2598      * PLL2 is needed.
2599      */
2600     clk_pll2_fout = rate * 512;
2601     rt5682s_set_component_pll(component, RT5682S_PLL2, RT5682S_PLL_S_MCLK,
2602         CLK_PLL2_FIN, clk_pll2_fout);
2603
2604     rt5682s_set_component_sysclk(component, RT5682S_SCLK_S_PLL2, 0,
2605         clk_pll2_fout, SND_SOC_CLOCK_IN);
2606
2607     rt5682s->lrck[RT5682S_AIF1] = rate;
2608
2609     return 0;
2610 }
2611
2612 static unsigned long rt5682s_bclk_recalc_rate(struct clk_hw *hw,
2613                          unsigned long parent_rate)
2614 {
2615     struct rt5682s_priv *rt5682s =
2616         container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_BCLK_IDX]);
2617     struct snd_soc_component *component = rt5682s->component;
2618     unsigned int bclks_per_wclk;
2619
2620     bclks_per_wclk = snd_soc_component_read(component, RT5682S_TDM_TCON_CTRL_1);
2621
2622     switch (bclks_per_wclk & RT5682S_TDM_BCLK_MS1_MASK) {
2623     case RT5682S_TDM_BCLK_MS1_256:
2624         return parent_rate * 256;
2625     case RT5682S_TDM_BCLK_MS1_128:
2626         return parent_rate * 128;
2627     case RT5682S_TDM_BCLK_MS1_64:
2628         return parent_rate * 64;
2629     case RT5682S_TDM_BCLK_MS1_32:
2630         return parent_rate * 32;
2631     default:
2632         return 0;
2633     }
2634 }
2635
2636 static unsigned long rt5682s_bclk_get_factor(unsigned long rate,
2637                         unsigned long parent_rate)
2638 {
2639     unsigned long factor;
2640
2641     factor = rate / parent_rate;
2642     if (factor < 64)
2643         return 32;
2644     else if (factor < 128)
2645         return 64;
2646     else if (factor < 256)
2647         return 128;
2648     else
2649         return 256;
2650 }
2651
2652 static long rt5682s_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
2653                    unsigned long *parent_rate)
2654 {
2655     struct rt5682s_priv *rt5682s =
2656         container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_BCLK_IDX]);
2657     unsigned long factor;
2658
2659     if (!*parent_rate || !rt5682s_clk_check(rt5682s))
2660         return -EINVAL;
2661
2662     /*
2663      * BCLK rates are set as a multiplier of WCLK in HW.
2664      * We don't allow changing the parent WCLK. We just do
2665      * some rounding down based on the parent WCLK rate
2666      * and find the appropriate multiplier of BCLK to
2667      * get the rounded down BCLK value.
2668      */
2669     factor = rt5682s_bclk_get_factor(rate, *parent_rate);
2670
2671     return *parent_rate * factor;
2672 }
2673
2674 static int rt5682s_bclk_set_rate(struct clk_hw *hw, unsigned long rate,
2675                 unsigned long parent_rate)
2676 {
2677     struct rt5682s_priv *rt5682s =
2678         container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_BCLK_IDX]);
2679     struct snd_soc_component *component = rt5682s->component;
2680     struct snd_soc_dai *dai;
2681     unsigned long factor;
2682
2683     if (!rt5682s_clk_check(rt5682s))
2684         return -EINVAL;
2685
2686     factor = rt5682s_bclk_get_factor(rate, parent_rate);
2687
2688     for_each_component_dais(component, dai)
2689         if (dai->id == RT5682S_AIF1)
2690             return rt5682s_set_bclk1_ratio(dai, factor);
2691
2692     dev_err(component->dev, "dai %d not found in component\n",
2693         RT5682S_AIF1);
2694     return -ENODEV;
2695 }
2696
2697 static const struct clk_ops rt5682s_dai_clk_ops[RT5682S_DAI_NUM_CLKS] = {
2698     [RT5682S_DAI_WCLK_IDX] = {
2699         .prepare = rt5682s_wclk_prepare,
2700         .unprepare = rt5682s_wclk_unprepare,
2701         .recalc_rate = rt5682s_wclk_recalc_rate,
2702         .round_rate = rt5682s_wclk_round_rate,
2703         .set_rate = rt5682s_wclk_set_rate,
2704     },
2705     [RT5682S_DAI_BCLK_IDX] = {
2706         .recalc_rate = rt5682s_bclk_recalc_rate,
2707         .round_rate = rt5682s_bclk_round_rate,
2708         .set_rate = rt5682s_bclk_set_rate,
2709     },
2710 };
2711
2712 static int rt5682s_register_dai_clks(struct snd_soc_component *component)
2713 {
2714     struct device *dev = component->dev;
2715     struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2716     struct rt5682s_platform_data *pdata = &rt5682s->pdata;
2717     struct clk_hw *dai_clk_hw;
2718     int i, ret;
2719
2720     for (i = 0; i < RT5682S_DAI_NUM_CLKS; ++i) {
2721         struct clk_init_data init = { };
2722         struct clk_parent_data parent_data;
2723         const struct clk_hw *parent;
2724
2725         dai_clk_hw = &rt5682s->dai_clks_hw[i];
2726
2727         switch (i) {
2728         case RT5682S_DAI_WCLK_IDX:
2729             /* Make MCLK the parent of WCLK */
2730             if (rt5682s->mclk) {
2731                 parent_data = (struct clk_parent_data){
2732                     .fw_name = "mclk",
2733                 };
2734                 init.parent_data = &parent_data;
2735                 init.num_parents = 1;
2736             }
2737             break;
2738         case RT5682S_DAI_BCLK_IDX:
2739             /* Make WCLK the parent of BCLK */
2740             parent = &rt5682s->dai_clks_hw[RT5682S_DAI_WCLK_IDX];
2741             init.parent_hws = &parent;
2742             init.num_parents = 1;
2743             break;
2744         default:
2745             dev_err(dev, "Invalid clock index\n");
2746             return -EINVAL;
2747         }
2748
2749         init.name = pdata->dai_clk_names[i];
2750         init.ops = &rt5682s_dai_clk_ops[i];
2751         init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE;
2752         dai_clk_hw->init = &init;
2753
2754         ret = devm_clk_hw_register(dev, dai_clk_hw);
2755         if (ret) {
2756             dev_warn(dev, "Failed to register %s: %d\n", init.name, ret);
2757             return ret;
2758         }
2759
2760         if (dev->of_node) {
2761             devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, dai_clk_hw);
2762         } else {
2763             ret = devm_clk_hw_register_clkdev(dev, dai_clk_hw,
2764                               init.name, dev_name(dev));
2765             if (ret)
2766                 return ret;
2767         }
2768     }
2769
2770     return 0;
2771 }
2772
2773 static int rt5682s_dai_probe_clks(struct snd_soc_component *component)
2774 {
2775     struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2776     int ret;
2777
2778     /* Check if MCLK provided */
2779     rt5682s->mclk = devm_clk_get(component->dev, "mclk");
2780     if (IS_ERR(rt5682s->mclk)) {
2781         if (PTR_ERR(rt5682s->mclk) != -ENOENT) {
2782             ret = PTR_ERR(rt5682s->mclk);
2783             return ret;
2784         }
2785         rt5682s->mclk = NULL;
2786     }
2787
2788     /* Register CCF DAI clock control */
2789     ret = rt5682s_register_dai_clks(component);
2790     if (ret)
2791         return ret;
2792
2793     /* Initial setup for CCF */
2794     rt5682s->lrck[RT5682S_AIF1] = CLK_48;
2795
2796     return 0;
2797 }
2798 #else
2799 static inline int rt5682s_dai_probe_clks(struct snd_soc_component *component)
2800 {
2801     return 0;
2802 }
2803 #endif /* CONFIG_COMMON_CLK */
2804
2805 static int rt5682s_probe(struct snd_soc_component *component)
2806 {
2807     struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2808     struct snd_soc_dapm_context *dapm = &component->dapm;
2809     int ret;
2810
2811     rt5682s->component = component;
2812
2813     ret = rt5682s_dai_probe_clks(component);
2814     if (ret)
2815         return ret;
2816
2817     snd_soc_dapm_disable_pin(dapm, "MICBIAS");
2818     snd_soc_dapm_disable_pin(dapm, "Vref2");
2819     snd_soc_dapm_sync(dapm);
2820     return 0;
2821 }
2822
2823 static void rt5682s_remove(struct snd_soc_component *component)
2824 {
2825     struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2826
2827     rt5682s_reset(rt5682s);
2828 }
2829
2830 #ifdef CONFIG_PM
2831 static int rt5682s_suspend(struct snd_soc_component *component)
2832 {
2833     struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2834
2835     cancel_delayed_work_sync(&rt5682s->jack_detect_work);
2836     cancel_delayed_work_sync(&rt5682s->jd_check_work);
2837
2838     if (rt5682s->hs_jack)
2839         rt5682s->jack_type = rt5682s_headset_detect(component, 0);
2840
2841     regcache_cache_only(rt5682s->regmap, true);
2842     regcache_mark_dirty(rt5682s->regmap);
2843
2844     return 0;
2845 }
2846
2847 static int rt5682s_resume(struct snd_soc_component *component)
2848 {
2849     struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2850
2851     regcache_cache_only(rt5682s->regmap, false);
2852     regcache_sync(rt5682s->regmap);
2853
2854     if (rt5682s->hs_jack) {
2855         mod_delayed_work(system_power_efficient_wq,
2856             &rt5682s->jack_detect_work, msecs_to_jiffies(0));
2857     }
2858
2859     return 0;
2860 }
2861 #else
2862 #define rt5682s_suspend NULL
2863 #define rt5682s_resume NULL
2864 #endif
2865
2866 static const struct snd_soc_dai_ops rt5682s_aif1_dai_ops = {
2867     .hw_params = rt5682s_hw_params,
2868     .set_fmt = rt5682s_set_dai_fmt,
2869     .set_tdm_slot = rt5682s_set_tdm_slot,
2870     .set_bclk_ratio = rt5682s_set_bclk1_ratio,
2871 };
2872
2873 static const struct snd_soc_dai_ops rt5682s_aif2_dai_ops = {
2874     .hw_params = rt5682s_hw_params,
2875     .set_fmt = rt5682s_set_dai_fmt,
2876     .set_bclk_ratio = rt5682s_set_bclk2_ratio,
2877 };
2878
2879 static const struct snd_soc_component_driver rt5682s_soc_component_dev = {
2880     .probe = rt5682s_probe,
2881     .remove = rt5682s_remove,
2882     .suspend = rt5682s_suspend,
2883     .resume = rt5682s_resume,
2884     .set_bias_level = rt5682s_set_bias_level,
2885     .controls = rt5682s_snd_controls,
2886     .num_controls = ARRAY_SIZE(rt5682s_snd_controls),
2887     .dapm_widgets = rt5682s_dapm_widgets,
2888     .num_dapm_widgets = ARRAY_SIZE(rt5682s_dapm_widgets),
2889     .dapm_routes = rt5682s_dapm_routes,
2890     .num_dapm_routes = ARRAY_SIZE(rt5682s_dapm_routes),
2891     .set_sysclk = rt5682s_set_component_sysclk,
2892     .set_pll = rt5682s_set_component_pll,
2893     .set_jack = rt5682s_set_jack_detect,
2894     .use_pmdown_time    = 1,
2895     .endianness     = 1,
2896 };
2897
2898 static int rt5682s_parse_dt(struct rt5682s_priv *rt5682s, struct device *dev)
2899 {
2900     device_property_read_u32(dev, "realtek,dmic1-data-pin",
2901         &rt5682s->pdata.dmic1_data_pin);
2902     device_property_read_u32(dev, "realtek,dmic1-clk-pin",
2903         &rt5682s->pdata.dmic1_clk_pin);
2904     device_property_read_u32(dev, "realtek,jd-src",
2905         &rt5682s->pdata.jd_src);
2906     device_property_read_u32(dev, "realtek,dmic-clk-rate-hz",
2907         &rt5682s->pdata.dmic_clk_rate);
2908     device_property_read_u32(dev, "realtek,dmic-delay-ms",
2909         &rt5682s->pdata.dmic_delay);
2910     device_property_read_u32(dev, "realtek,amic-delay-ms",
2911         &rt5682s->pdata.amic_delay);
2912
2913     rt5682s->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
2914         "realtek,ldo1-en-gpios", 0);
2915
2916     if (device_property_read_string_array(dev, "clock-output-names",
2917                           rt5682s->pdata.dai_clk_names,
2918                           RT5682S_DAI_NUM_CLKS) < 0)
2919         dev_warn(dev, "Using default DAI clk names: %s, %s\n",
2920              rt5682s->pdata.dai_clk_names[RT5682S_DAI_WCLK_IDX],
2921              rt5682s->pdata.dai_clk_names[RT5682S_DAI_BCLK_IDX]);
2922
2923     rt5682s->pdata.dmic_clk_driving_high = device_property_read_bool(dev,
2924         "realtek,dmic-clk-driving-high");
2925
2926     return 0;
2927 }
2928
2929 static void rt5682s_calibrate(struct rt5682s_priv *rt5682s)
2930 {
2931     unsigned int count, value;
2932
2933     mutex_lock(&rt5682s->calibrate_mutex);
2934
2935     regmap_write(rt5682s->regmap, RT5682S_PWR_ANLG_1, 0xaa80);
2936     usleep_range(15000, 20000);
2937     regmap_write(rt5682s->regmap, RT5682S_PWR_ANLG_1, 0xfa80);
2938     regmap_write(rt5682s->regmap, RT5682S_PWR_DIG_1, 0x01c0);
2939     regmap_write(rt5682s->regmap, RT5682S_MICBIAS_2, 0x0380);
2940     regmap_write(rt5682s->regmap, RT5682S_GLB_CLK, 0x8000);
2941     regmap_write(rt5682s->regmap, RT5682S_ADDA_CLK_1, 0x1001);
2942     regmap_write(rt5682s->regmap, RT5682S_CHOP_DAC_2, 0x3030);
2943     regmap_write(rt5682s->regmap, RT5682S_CHOP_ADC, 0xb000);
2944     regmap_write(rt5682s->regmap, RT5682S_STO1_ADC_MIXER, 0x686c);
2945     regmap_write(rt5682s->regmap, RT5682S_CAL_REC, 0x5151);
2946     regmap_write(rt5682s->regmap, RT5682S_HP_CALIB_CTRL_2, 0x0321);
2947     regmap_write(rt5682s->regmap, RT5682S_HP_LOGIC_CTRL_2, 0x0004);
2948     regmap_write(rt5682s->regmap, RT5682S_HP_CALIB_CTRL_1, 0x7c00);
2949     regmap_write(rt5682s->regmap, RT5682S_HP_CALIB_CTRL_1, 0xfc00);
2950
2951     for (count = 0; count < 60; count++) {
2952         regmap_read(rt5682s->regmap, RT5682S_HP_CALIB_ST_1, &value);
2953         if (!(value & 0x8000))
2954             break;
2955
2956         usleep_range(10000, 10005);
2957     }
2958
2959     if (count >= 60)
2960         dev_err(rt5682s->component->dev, "HP Calibration Failure\n");
2961
2962     /* restore settings */
2963     regmap_write(rt5682s->regmap, RT5682S_MICBIAS_2, 0x0180);
2964     regmap_write(rt5682s->regmap, RT5682S_CAL_REC, 0x5858);
2965     regmap_write(rt5682s->regmap, RT5682S_STO1_ADC_MIXER, 0xc0c4);
2966     regmap_write(rt5682s->regmap, RT5682S_HP_CALIB_CTRL_2, 0x0320);
2967     regmap_write(rt5682s->regmap, RT5682S_PWR_DIG_1, 0x00c0);
2968     regmap_write(rt5682s->regmap, RT5682S_PWR_ANLG_1, 0x0800);
2969     regmap_write(rt5682s->regmap, RT5682S_GLB_CLK, 0x0000);
2970
2971     mutex_unlock(&rt5682s->calibrate_mutex);
2972 }
2973
2974 static const struct regmap_config rt5682s_regmap = {
2975     .reg_bits = 16,
2976     .val_bits = 16,
2977     .max_register = RT5682S_MAX_REG,
2978     .volatile_reg = rt5682s_volatile_register,
2979     .readable_reg = rt5682s_readable_register,
2980     .cache_type = REGCACHE_RBTREE,
2981     .reg_defaults = rt5682s_reg,
2982     .num_reg_defaults = ARRAY_SIZE(rt5682s_reg),
2983     .use_single_read = true,
2984     .use_single_write = true,
2985 };
2986
2987 static struct snd_soc_dai_driver rt5682s_dai[] = {
2988     {
2989         .name = "rt5682s-aif1",
2990         .id = RT5682S_AIF1,
2991         .playback = {
2992             .stream_name = "AIF1 Playback",
2993             .channels_min = 1,
2994             .channels_max = 2,
2995             .rates = RT5682S_STEREO_RATES,
2996             .formats = RT5682S_FORMATS,
2997         },
2998         .capture = {
2999             .stream_name = "AIF1 Capture",
3000             .channels_min = 1,
3001             .channels_max = 2,
3002             .rates = RT5682S_STEREO_RATES,
3003             .formats = RT5682S_FORMATS,
3004         },
3005         .ops = &rt5682s_aif1_dai_ops,
3006     },
3007     {
3008         .name = "rt5682s-aif2",
3009         .id = RT5682S_AIF2,
3010         .capture = {
3011             .stream_name = "AIF2 Capture",
3012             .channels_min = 1,
3013             .channels_max = 2,
3014             .rates = RT5682S_STEREO_RATES,
3015             .formats = RT5682S_FORMATS,
3016         },
3017         .ops = &rt5682s_aif2_dai_ops,
3018     },
3019 };
3020
3021 static void rt5682s_i2c_disable_regulators(void *data)
3022 {
3023     struct rt5682s_priv *rt5682s = data;
3024     struct device *dev = regmap_get_device(rt5682s->regmap);
3025     int ret;
3026
3027     ret = regulator_disable(rt5682s->supplies[RT5682S_SUPPLY_AVDD].consumer);
3028     if (ret)
3029         dev_err(dev, "Failed to disable supply AVDD: %d\n", ret);
3030
3031     usleep_range(1000, 1500);
3032
3033     ret = regulator_disable(rt5682s->supplies[RT5682S_SUPPLY_MICVDD].consumer);
3034     if (ret)
3035         dev_err(dev, "Failed to disable supply MICVDD: %d\n", ret);
3036 }
3037
3038 static int rt5682s_i2c_probe(struct i2c_client *i2c)
3039 {
3040     struct rt5682s_platform_data *pdata = dev_get_platdata(&i2c->dev);
3041     struct rt5682s_priv *rt5682s;
3042     int i, ret;
3043     unsigned int val;
3044
3045     rt5682s = devm_kzalloc(&i2c->dev, sizeof(struct rt5682s_priv), GFP_KERNEL);
3046     if (!rt5682s)
3047         return -ENOMEM;
3048
3049     i2c_set_clientdata(i2c, rt5682s);
3050
3051     rt5682s->pdata = i2s_default_platform_data;
3052
3053     if (pdata)
3054         rt5682s->pdata = *pdata;
3055     else
3056         rt5682s_parse_dt(rt5682s, &i2c->dev);
3057
3058     rt5682s->regmap = devm_regmap_init_i2c(i2c, &rt5682s_regmap);
3059     if (IS_ERR(rt5682s->regmap)) {
3060         ret = PTR_ERR(rt5682s->regmap);
3061         dev_err(&i2c->dev, "Failed to allocate register map: %d\n", ret);
3062         return ret;
3063     }
3064
3065     for (i = 0; i < ARRAY_SIZE(rt5682s->supplies); i++)
3066         rt5682s->supplies[i].supply = rt5682s_supply_names[i];
3067
3068     ret = devm_regulator_bulk_get(&i2c->dev,
3069             ARRAY_SIZE(rt5682s->supplies), rt5682s->supplies);
3070     if (ret) {
3071         dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
3072         return ret;
3073     }
3074
3075     ret = devm_add_action_or_reset(&i2c->dev, rt5682s_i2c_disable_regulators, rt5682s);
3076     if (ret)
3077         return ret;
3078
3079     ret = regulator_enable(rt5682s->supplies[RT5682S_SUPPLY_MICVDD].consumer);
3080     if (ret) {
3081         dev_err(&i2c->dev, "Failed to enable supply MICVDD: %d\n", ret);
3082         return ret;
3083     }
3084     usleep_range(1000, 1500);
3085
3086     ret = regulator_enable(rt5682s->supplies[RT5682S_SUPPLY_AVDD].consumer);
3087     if (ret) {
3088         dev_err(&i2c->dev, "Failed to enable supply AVDD: %d\n", ret);
3089         return ret;
3090     }
3091
3092     if (gpio_is_valid(rt5682s->pdata.ldo1_en)) {
3093         if (devm_gpio_request_one(&i2c->dev, rt5682s->pdata.ldo1_en,
3094                       GPIOF_OUT_INIT_HIGH, "rt5682s"))
3095             dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n");
3096     }
3097
3098     /* Sleep for 50 ms minimum */
3099     usleep_range(50000, 55000);
3100
3101     regmap_read(rt5682s->regmap, RT5682S_DEVICE_ID, &val);
3102     if (val != DEVICE_ID) {
3103         dev_err(&i2c->dev, "Device with ID register %x is not rt5682s\n", val);
3104         return -ENODEV;
3105     }
3106
3107     rt5682s_reset(rt5682s);
3108     rt5682s_apply_patch_list(rt5682s, &i2c->dev);
3109
3110     regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_2,
3111         RT5682S_DLDO_I_LIMIT_MASK, RT5682S_DLDO_I_LIMIT_DIS);
3112     usleep_range(20000, 25000);
3113
3114     mutex_init(&rt5682s->calibrate_mutex);
3115     mutex_init(&rt5682s->sar_mutex);
3116     rt5682s_calibrate(rt5682s);
3117
3118     regmap_update_bits(rt5682s->regmap, RT5682S_MICBIAS_2,
3119         RT5682S_PWR_CLK25M_MASK | RT5682S_PWR_CLK1M_MASK,
3120         RT5682S_PWR_CLK25M_PD | RT5682S_PWR_CLK1M_PU);
3121     regmap_update_bits(rt5682s->regmap, RT5682S_PWR_ANLG_1,
3122         RT5682S_PWR_BG, RT5682S_PWR_BG);
3123     regmap_update_bits(rt5682s->regmap, RT5682S_HP_LOGIC_CTRL_2,
3124         RT5682S_HP_SIG_SRC_MASK, RT5682S_HP_SIG_SRC_1BIT_CTL);
3125     regmap_update_bits(rt5682s->regmap, RT5682S_HP_CHARGE_PUMP_2,
3126         RT5682S_PM_HP_MASK, RT5682S_PM_HP_HV);
3127     regmap_update_bits(rt5682s->regmap, RT5682S_HP_AMP_DET_CTL_1,
3128         RT5682S_CP_SW_SIZE_MASK, RT5682S_CP_SW_SIZE_M);
3129
3130     /* DMIC data pin */
3131     switch (rt5682s->pdata.dmic1_data_pin) {
3132     case RT5682S_DMIC1_DATA_NULL:
3133         break;
3134     case RT5682S_DMIC1_DATA_GPIO2: /* share with LRCK2 */
3135         regmap_update_bits(rt5682s->regmap, RT5682S_DMIC_CTRL_1,
3136             RT5682S_DMIC_1_DP_MASK, RT5682S_DMIC_1_DP_GPIO2);
3137         regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1,
3138             RT5682S_GP2_PIN_MASK, RT5682S_GP2_PIN_DMIC_SDA);
3139         break;
3140     case RT5682S_DMIC1_DATA_GPIO5: /* share with DACDAT1 */
3141         regmap_update_bits(rt5682s->regmap, RT5682S_DMIC_CTRL_1,
3142             RT5682S_DMIC_1_DP_MASK, RT5682S_DMIC_1_DP_GPIO5);
3143         regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1,
3144             RT5682S_GP5_PIN_MASK, RT5682S_GP5_PIN_DMIC_SDA);
3145         break;
3146     default:
3147         dev_warn(&i2c->dev, "invalid DMIC_DAT pin\n");
3148         break;
3149     }
3150
3151     /* DMIC clk pin */
3152     switch (rt5682s->pdata.dmic1_clk_pin) {
3153     case RT5682S_DMIC1_CLK_NULL:
3154         break;
3155     case RT5682S_DMIC1_CLK_GPIO1: /* share with IRQ */
3156         regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1,
3157             RT5682S_GP1_PIN_MASK, RT5682S_GP1_PIN_DMIC_CLK);
3158         break;
3159     case RT5682S_DMIC1_CLK_GPIO3: /* share with BCLK2 */
3160         regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1,
3161             RT5682S_GP3_PIN_MASK, RT5682S_GP3_PIN_DMIC_CLK);
3162         if (rt5682s->pdata.dmic_clk_driving_high)
3163             regmap_update_bits(rt5682s->regmap, RT5682S_PAD_DRIVING_CTRL,
3164                 RT5682S_PAD_DRV_GP3_MASK, RT5682S_PAD_DRV_GP3_HIGH);
3165         break;
3166     default:
3167         dev_warn(&i2c->dev, "invalid DMIC_CLK pin\n");
3168         break;
3169     }
3170
3171     INIT_DELAYED_WORK(&rt5682s->jack_detect_work, rt5682s_jack_detect_handler);
3172     INIT_DELAYED_WORK(&rt5682s->jd_check_work, rt5682s_jd_check_handler);
3173
3174     if (i2c->irq) {
3175         ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, rt5682s_irq,
3176             IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
3177             "rt5682s", rt5682s);
3178         if (ret)
3179             dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
3180     }
3181
3182     return devm_snd_soc_register_component(&i2c->dev, &rt5682s_soc_component_dev,
3183             rt5682s_dai, ARRAY_SIZE(rt5682s_dai));
3184 }
3185
3186 static void rt5682s_i2c_shutdown(struct i2c_client *client)
3187 {
3188     struct rt5682s_priv *rt5682s = i2c_get_clientdata(client);
3189
3190     disable_irq(client->irq);
3191     cancel_delayed_work_sync(&rt5682s->jack_detect_work);
3192     cancel_delayed_work_sync(&rt5682s->jd_check_work);
3193
3194     rt5682s_reset(rt5682s);
3195 }
3196
3197 static int rt5682s_i2c_remove(struct i2c_client *client)
3198 {
3199     rt5682s_i2c_shutdown(client);
3200
3201     return 0;
3202 }
3203
3204 static const struct of_device_id rt5682s_of_match[] = {
3205     {.compatible = "realtek,rt5682s"},
3206     {},
3207 };
3208 MODULE_DEVICE_TABLE(of, rt5682s_of_match);
3209
3210 static const struct acpi_device_id rt5682s_acpi_match[] = {
3211     {"RTL5682", 0,},
3212     {},
3213 };
3214 MODULE_DEVICE_TABLE(acpi, rt5682s_acpi_match);
3215
3216 static const struct i2c_device_id rt5682s_i2c_id[] = {
3217     {"rt5682s", 0},
3218     {}
3219 };
3220 MODULE_DEVICE_TABLE(i2c, rt5682s_i2c_id);
3221
3222 static struct i2c_driver rt5682s_i2c_driver = {
3223     .driver = {
3224         .name = "rt5682s",
3225         .of_match_table = rt5682s_of_match,
3226         .acpi_match_table = rt5682s_acpi_match,
3227         .probe_type = PROBE_PREFER_ASYNCHRONOUS,
3228     },
3229     .probe_new = rt5682s_i2c_probe,
3230     .remove = rt5682s_i2c_remove,
3231     .shutdown = rt5682s_i2c_shutdown,
3232     .id_table = rt5682s_i2c_id,
3233 };
3234 module_i2c_driver(rt5682s_i2c_driver);
3235
3236 MODULE_DESCRIPTION("ASoC RT5682I-VS driver");
3237 MODULE_AUTHOR("Derek Fang <derek.fang@realtek.com>");
3238 MODULE_LICENSE("GPL v2");