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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 //
0003 // rt5682.c  --  RT5682 ALSA SoC audio component driver
0004 //
0005 // Copyright 2018 Realtek Semiconductor Corp.
0006 // Author: Bard Liao <bardliao@realtek.com>
0007 //
0008 
0009 #include <linux/module.h>
0010 #include <linux/moduleparam.h>
0011 #include <linux/init.h>
0012 #include <linux/delay.h>
0013 #include <linux/pm.h>
0014 #include <linux/pm_runtime.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/spi/spi.h>
0017 #include <linux/acpi.h>
0018 #include <linux/gpio.h>
0019 #include <linux/of_gpio.h>
0020 #include <linux/mutex.h>
0021 #include <sound/core.h>
0022 #include <sound/pcm.h>
0023 #include <sound/pcm_params.h>
0024 #include <sound/jack.h>
0025 #include <sound/soc.h>
0026 #include <sound/soc-dapm.h>
0027 #include <sound/initval.h>
0028 #include <sound/tlv.h>
0029 #include <sound/rt5682.h>
0030 
0031 #include "rl6231.h"
0032 #include "rt5682.h"
0033 
0034 const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = {
0035     "AVDD",
0036     "MICVDD",
0037     "VBAT",
0038 };
0039 EXPORT_SYMBOL_GPL(rt5682_supply_names);
0040 
0041 static const struct reg_sequence patch_list[] = {
0042     {RT5682_HP_IMP_SENS_CTRL_19, 0x1000},
0043     {RT5682_DAC_ADC_DIG_VOL1, 0xa020},
0044     {RT5682_I2C_CTRL, 0x000f},
0045     {RT5682_PLL2_INTERNAL, 0x8266},
0046     {RT5682_SAR_IL_CMD_1, 0x22b7},
0047     {RT5682_SAR_IL_CMD_3, 0x0365},
0048     {RT5682_SAR_IL_CMD_6, 0x0110},
0049     {RT5682_CHARGE_PUMP_1, 0x0210},
0050     {RT5682_HP_LOGIC_CTRL_2, 0x0007},
0051     {RT5682_SAR_IL_CMD_2, 0xac00},
0052     {RT5682_CBJ_CTRL_7, 0x0104},
0053 };
0054 
0055 void rt5682_apply_patch_list(struct rt5682_priv *rt5682, struct device *dev)
0056 {
0057     int ret;
0058 
0059     ret = regmap_multi_reg_write(rt5682->regmap, patch_list,
0060                      ARRAY_SIZE(patch_list));
0061     if (ret)
0062         dev_warn(dev, "Failed to apply regmap patch: %d\n", ret);
0063 }
0064 EXPORT_SYMBOL_GPL(rt5682_apply_patch_list);
0065 
0066 const struct reg_default rt5682_reg[RT5682_REG_NUM] = {
0067     {0x0002, 0x8080},
0068     {0x0003, 0x8000},
0069     {0x0005, 0x0000},
0070     {0x0006, 0x0000},
0071     {0x0008, 0x800f},
0072     {0x000b, 0x0000},
0073     {0x0010, 0x4040},
0074     {0x0011, 0x0000},
0075     {0x0012, 0x1404},
0076     {0x0013, 0x1000},
0077     {0x0014, 0xa00a},
0078     {0x0015, 0x0404},
0079     {0x0016, 0x0404},
0080     {0x0019, 0xafaf},
0081     {0x001c, 0x2f2f},
0082     {0x001f, 0x0000},
0083     {0x0022, 0x5757},
0084     {0x0023, 0x0039},
0085     {0x0024, 0x000b},
0086     {0x0026, 0xc0c4},
0087     {0x0029, 0x8080},
0088     {0x002a, 0xa0a0},
0089     {0x002b, 0x0300},
0090     {0x0030, 0x0000},
0091     {0x003c, 0x0080},
0092     {0x0044, 0x0c0c},
0093     {0x0049, 0x0000},
0094     {0x0061, 0x0000},
0095     {0x0062, 0x0000},
0096     {0x0063, 0x003f},
0097     {0x0064, 0x0000},
0098     {0x0065, 0x0000},
0099     {0x0066, 0x0030},
0100     {0x0067, 0x0000},
0101     {0x006b, 0x0000},
0102     {0x006c, 0x0000},
0103     {0x006d, 0x2200},
0104     {0x006e, 0x0a10},
0105     {0x0070, 0x8000},
0106     {0x0071, 0x8000},
0107     {0x0073, 0x0000},
0108     {0x0074, 0x0000},
0109     {0x0075, 0x0002},
0110     {0x0076, 0x0001},
0111     {0x0079, 0x0000},
0112     {0x007a, 0x0000},
0113     {0x007b, 0x0000},
0114     {0x007c, 0x0100},
0115     {0x007e, 0x0000},
0116     {0x0080, 0x0000},
0117     {0x0081, 0x0000},
0118     {0x0082, 0x0000},
0119     {0x0083, 0x0000},
0120     {0x0084, 0x0000},
0121     {0x0085, 0x0000},
0122     {0x0086, 0x0005},
0123     {0x0087, 0x0000},
0124     {0x0088, 0x0000},
0125     {0x008c, 0x0003},
0126     {0x008d, 0x0000},
0127     {0x008e, 0x0060},
0128     {0x008f, 0x1000},
0129     {0x0091, 0x0c26},
0130     {0x0092, 0x0073},
0131     {0x0093, 0x0000},
0132     {0x0094, 0x0080},
0133     {0x0098, 0x0000},
0134     {0x009a, 0x0000},
0135     {0x009b, 0x0000},
0136     {0x009c, 0x0000},
0137     {0x009d, 0x0000},
0138     {0x009e, 0x100c},
0139     {0x009f, 0x0000},
0140     {0x00a0, 0x0000},
0141     {0x00a3, 0x0002},
0142     {0x00a4, 0x0001},
0143     {0x00ae, 0x2040},
0144     {0x00af, 0x0000},
0145     {0x00b6, 0x0000},
0146     {0x00b7, 0x0000},
0147     {0x00b8, 0x0000},
0148     {0x00b9, 0x0002},
0149     {0x00be, 0x0000},
0150     {0x00c0, 0x0160},
0151     {0x00c1, 0x82a0},
0152     {0x00c2, 0x0000},
0153     {0x00d0, 0x0000},
0154     {0x00d1, 0x2244},
0155     {0x00d2, 0x3300},
0156     {0x00d3, 0x2200},
0157     {0x00d4, 0x0000},
0158     {0x00d9, 0x0009},
0159     {0x00da, 0x0000},
0160     {0x00db, 0x0000},
0161     {0x00dc, 0x00c0},
0162     {0x00dd, 0x2220},
0163     {0x00de, 0x3131},
0164     {0x00df, 0x3131},
0165     {0x00e0, 0x3131},
0166     {0x00e2, 0x0000},
0167     {0x00e3, 0x4000},
0168     {0x00e4, 0x0aa0},
0169     {0x00e5, 0x3131},
0170     {0x00e6, 0x3131},
0171     {0x00e7, 0x3131},
0172     {0x00e8, 0x3131},
0173     {0x00ea, 0xb320},
0174     {0x00eb, 0x0000},
0175     {0x00f0, 0x0000},
0176     {0x00f1, 0x00d0},
0177     {0x00f2, 0x00d0},
0178     {0x00f6, 0x0000},
0179     {0x00fa, 0x0000},
0180     {0x00fb, 0x0000},
0181     {0x00fc, 0x0000},
0182     {0x00fd, 0x0000},
0183     {0x00fe, 0x10ec},
0184     {0x00ff, 0x6530},
0185     {0x0100, 0xa0a0},
0186     {0x010b, 0x0000},
0187     {0x010c, 0xae00},
0188     {0x010d, 0xaaa0},
0189     {0x010e, 0x8aa2},
0190     {0x010f, 0x02a2},
0191     {0x0110, 0xc000},
0192     {0x0111, 0x04a2},
0193     {0x0112, 0x2800},
0194     {0x0113, 0x0000},
0195     {0x0117, 0x0100},
0196     {0x0125, 0x0410},
0197     {0x0132, 0x6026},
0198     {0x0136, 0x5555},
0199     {0x0138, 0x3700},
0200     {0x013a, 0x2000},
0201     {0x013b, 0x2000},
0202     {0x013c, 0x2005},
0203     {0x013f, 0x0000},
0204     {0x0142, 0x0000},
0205     {0x0145, 0x0002},
0206     {0x0146, 0x0000},
0207     {0x0147, 0x0000},
0208     {0x0148, 0x0000},
0209     {0x0149, 0x0000},
0210     {0x0150, 0x79a1},
0211     {0x0156, 0xaaaa},
0212     {0x0160, 0x4ec0},
0213     {0x0161, 0x0080},
0214     {0x0162, 0x0200},
0215     {0x0163, 0x0800},
0216     {0x0164, 0x0000},
0217     {0x0165, 0x0000},
0218     {0x0166, 0x0000},
0219     {0x0167, 0x000f},
0220     {0x0168, 0x000f},
0221     {0x0169, 0x0021},
0222     {0x0190, 0x413d},
0223     {0x0194, 0x0000},
0224     {0x0195, 0x0000},
0225     {0x0197, 0x0022},
0226     {0x0198, 0x0000},
0227     {0x0199, 0x0000},
0228     {0x01af, 0x0000},
0229     {0x01b0, 0x0400},
0230     {0x01b1, 0x0000},
0231     {0x01b2, 0x0000},
0232     {0x01b3, 0x0000},
0233     {0x01b4, 0x0000},
0234     {0x01b5, 0x0000},
0235     {0x01b6, 0x01c3},
0236     {0x01b7, 0x02a0},
0237     {0x01b8, 0x03e9},
0238     {0x01b9, 0x1389},
0239     {0x01ba, 0xc351},
0240     {0x01bb, 0x0009},
0241     {0x01bc, 0x0018},
0242     {0x01bd, 0x002a},
0243     {0x01be, 0x004c},
0244     {0x01bf, 0x0097},
0245     {0x01c0, 0x433d},
0246     {0x01c2, 0x0000},
0247     {0x01c3, 0x0000},
0248     {0x01c4, 0x0000},
0249     {0x01c5, 0x0000},
0250     {0x01c6, 0x0000},
0251     {0x01c7, 0x0000},
0252     {0x01c8, 0x40af},
0253     {0x01c9, 0x0702},
0254     {0x01ca, 0x0000},
0255     {0x01cb, 0x0000},
0256     {0x01cc, 0x5757},
0257     {0x01cd, 0x5757},
0258     {0x01ce, 0x5757},
0259     {0x01cf, 0x5757},
0260     {0x01d0, 0x5757},
0261     {0x01d1, 0x5757},
0262     {0x01d2, 0x5757},
0263     {0x01d3, 0x5757},
0264     {0x01d4, 0x5757},
0265     {0x01d5, 0x5757},
0266     {0x01d6, 0x0000},
0267     {0x01d7, 0x0008},
0268     {0x01d8, 0x0029},
0269     {0x01d9, 0x3333},
0270     {0x01da, 0x0000},
0271     {0x01db, 0x0004},
0272     {0x01dc, 0x0000},
0273     {0x01de, 0x7c00},
0274     {0x01df, 0x0320},
0275     {0x01e0, 0x06a1},
0276     {0x01e1, 0x0000},
0277     {0x01e2, 0x0000},
0278     {0x01e3, 0x0000},
0279     {0x01e4, 0x0000},
0280     {0x01e6, 0x0001},
0281     {0x01e7, 0x0000},
0282     {0x01e8, 0x0000},
0283     {0x01ea, 0x0000},
0284     {0x01eb, 0x0000},
0285     {0x01ec, 0x0000},
0286     {0x01ed, 0x0000},
0287     {0x01ee, 0x0000},
0288     {0x01ef, 0x0000},
0289     {0x01f0, 0x0000},
0290     {0x01f1, 0x0000},
0291     {0x01f2, 0x0000},
0292     {0x01f3, 0x0000},
0293     {0x01f4, 0x0000},
0294     {0x0210, 0x6297},
0295     {0x0211, 0xa005},
0296     {0x0212, 0x824c},
0297     {0x0213, 0xf7ff},
0298     {0x0214, 0xf24c},
0299     {0x0215, 0x0102},
0300     {0x0216, 0x00a3},
0301     {0x0217, 0x0048},
0302     {0x0218, 0xa2c0},
0303     {0x0219, 0x0400},
0304     {0x021a, 0x00c8},
0305     {0x021b, 0x00c0},
0306     {0x021c, 0x0000},
0307     {0x0250, 0x4500},
0308     {0x0251, 0x40b3},
0309     {0x0252, 0x0000},
0310     {0x0253, 0x0000},
0311     {0x0254, 0x0000},
0312     {0x0255, 0x0000},
0313     {0x0256, 0x0000},
0314     {0x0257, 0x0000},
0315     {0x0258, 0x0000},
0316     {0x0259, 0x0000},
0317     {0x025a, 0x0005},
0318     {0x0270, 0x0000},
0319     {0x02ff, 0x0110},
0320     {0x0300, 0x001f},
0321     {0x0301, 0x032c},
0322     {0x0302, 0x5f21},
0323     {0x0303, 0x4000},
0324     {0x0304, 0x4000},
0325     {0x0305, 0x06d5},
0326     {0x0306, 0x8000},
0327     {0x0307, 0x0700},
0328     {0x0310, 0x4560},
0329     {0x0311, 0xa4a8},
0330     {0x0312, 0x7418},
0331     {0x0313, 0x0000},
0332     {0x0314, 0x0006},
0333     {0x0315, 0xffff},
0334     {0x0316, 0xc400},
0335     {0x0317, 0x0000},
0336     {0x03c0, 0x7e00},
0337     {0x03c1, 0x8000},
0338     {0x03c2, 0x8000},
0339     {0x03c3, 0x8000},
0340     {0x03c4, 0x8000},
0341     {0x03c5, 0x8000},
0342     {0x03c6, 0x8000},
0343     {0x03c7, 0x8000},
0344     {0x03c8, 0x8000},
0345     {0x03c9, 0x8000},
0346     {0x03ca, 0x8000},
0347     {0x03cb, 0x8000},
0348     {0x03cc, 0x8000},
0349     {0x03d0, 0x0000},
0350     {0x03d1, 0x0000},
0351     {0x03d2, 0x0000},
0352     {0x03d3, 0x0000},
0353     {0x03d4, 0x2000},
0354     {0x03d5, 0x2000},
0355     {0x03d6, 0x0000},
0356     {0x03d7, 0x0000},
0357     {0x03d8, 0x2000},
0358     {0x03d9, 0x2000},
0359     {0x03da, 0x2000},
0360     {0x03db, 0x2000},
0361     {0x03dc, 0x0000},
0362     {0x03dd, 0x0000},
0363     {0x03de, 0x0000},
0364     {0x03df, 0x2000},
0365     {0x03e0, 0x0000},
0366     {0x03e1, 0x0000},
0367     {0x03e2, 0x0000},
0368     {0x03e3, 0x0000},
0369     {0x03e4, 0x0000},
0370     {0x03e5, 0x0000},
0371     {0x03e6, 0x0000},
0372     {0x03e7, 0x0000},
0373     {0x03e8, 0x0000},
0374     {0x03e9, 0x0000},
0375     {0x03ea, 0x0000},
0376     {0x03eb, 0x0000},
0377     {0x03ec, 0x0000},
0378     {0x03ed, 0x0000},
0379     {0x03ee, 0x0000},
0380     {0x03ef, 0x0000},
0381     {0x03f0, 0x0800},
0382     {0x03f1, 0x0800},
0383     {0x03f2, 0x0800},
0384     {0x03f3, 0x0800},
0385 };
0386 EXPORT_SYMBOL_GPL(rt5682_reg);
0387 
0388 bool rt5682_volatile_register(struct device *dev, unsigned int reg)
0389 {
0390     switch (reg) {
0391     case RT5682_RESET:
0392     case RT5682_CBJ_CTRL_2:
0393     case RT5682_INT_ST_1:
0394     case RT5682_4BTN_IL_CMD_1:
0395     case RT5682_AJD1_CTRL:
0396     case RT5682_HP_CALIB_CTRL_1:
0397     case RT5682_DEVICE_ID:
0398     case RT5682_I2C_MODE:
0399     case RT5682_HP_CALIB_CTRL_10:
0400     case RT5682_EFUSE_CTRL_2:
0401     case RT5682_JD_TOP_VC_VTRL:
0402     case RT5682_HP_IMP_SENS_CTRL_19:
0403     case RT5682_IL_CMD_1:
0404     case RT5682_SAR_IL_CMD_2:
0405     case RT5682_SAR_IL_CMD_4:
0406     case RT5682_SAR_IL_CMD_10:
0407     case RT5682_SAR_IL_CMD_11:
0408     case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11:
0409     case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11:
0410         return true;
0411     default:
0412         return false;
0413     }
0414 }
0415 EXPORT_SYMBOL_GPL(rt5682_volatile_register);
0416 
0417 bool rt5682_readable_register(struct device *dev, unsigned int reg)
0418 {
0419     switch (reg) {
0420     case RT5682_RESET:
0421     case RT5682_VERSION_ID:
0422     case RT5682_VENDOR_ID:
0423     case RT5682_DEVICE_ID:
0424     case RT5682_HP_CTRL_1:
0425     case RT5682_HP_CTRL_2:
0426     case RT5682_HPL_GAIN:
0427     case RT5682_HPR_GAIN:
0428     case RT5682_I2C_CTRL:
0429     case RT5682_CBJ_BST_CTRL:
0430     case RT5682_CBJ_CTRL_1:
0431     case RT5682_CBJ_CTRL_2:
0432     case RT5682_CBJ_CTRL_3:
0433     case RT5682_CBJ_CTRL_4:
0434     case RT5682_CBJ_CTRL_5:
0435     case RT5682_CBJ_CTRL_6:
0436     case RT5682_CBJ_CTRL_7:
0437     case RT5682_DAC1_DIG_VOL:
0438     case RT5682_STO1_ADC_DIG_VOL:
0439     case RT5682_STO1_ADC_BOOST:
0440     case RT5682_HP_IMP_GAIN_1:
0441     case RT5682_HP_IMP_GAIN_2:
0442     case RT5682_SIDETONE_CTRL:
0443     case RT5682_STO1_ADC_MIXER:
0444     case RT5682_AD_DA_MIXER:
0445     case RT5682_STO1_DAC_MIXER:
0446     case RT5682_A_DAC1_MUX:
0447     case RT5682_DIG_INF2_DATA:
0448     case RT5682_REC_MIXER:
0449     case RT5682_CAL_REC:
0450     case RT5682_ALC_BACK_GAIN:
0451     case RT5682_PWR_DIG_1:
0452     case RT5682_PWR_DIG_2:
0453     case RT5682_PWR_ANLG_1:
0454     case RT5682_PWR_ANLG_2:
0455     case RT5682_PWR_ANLG_3:
0456     case RT5682_PWR_MIXER:
0457     case RT5682_PWR_VOL:
0458     case RT5682_CLK_DET:
0459     case RT5682_RESET_LPF_CTRL:
0460     case RT5682_RESET_HPF_CTRL:
0461     case RT5682_DMIC_CTRL_1:
0462     case RT5682_I2S1_SDP:
0463     case RT5682_I2S2_SDP:
0464     case RT5682_ADDA_CLK_1:
0465     case RT5682_ADDA_CLK_2:
0466     case RT5682_I2S1_F_DIV_CTRL_1:
0467     case RT5682_I2S1_F_DIV_CTRL_2:
0468     case RT5682_TDM_CTRL:
0469     case RT5682_TDM_ADDA_CTRL_1:
0470     case RT5682_TDM_ADDA_CTRL_2:
0471     case RT5682_DATA_SEL_CTRL_1:
0472     case RT5682_TDM_TCON_CTRL:
0473     case RT5682_GLB_CLK:
0474     case RT5682_PLL_CTRL_1:
0475     case RT5682_PLL_CTRL_2:
0476     case RT5682_PLL_TRACK_1:
0477     case RT5682_PLL_TRACK_2:
0478     case RT5682_PLL_TRACK_3:
0479     case RT5682_PLL_TRACK_4:
0480     case RT5682_PLL_TRACK_5:
0481     case RT5682_PLL_TRACK_6:
0482     case RT5682_PLL_TRACK_11:
0483     case RT5682_SDW_REF_CLK:
0484     case RT5682_DEPOP_1:
0485     case RT5682_DEPOP_2:
0486     case RT5682_HP_CHARGE_PUMP_1:
0487     case RT5682_HP_CHARGE_PUMP_2:
0488     case RT5682_MICBIAS_1:
0489     case RT5682_MICBIAS_2:
0490     case RT5682_PLL_TRACK_12:
0491     case RT5682_PLL_TRACK_14:
0492     case RT5682_PLL2_CTRL_1:
0493     case RT5682_PLL2_CTRL_2:
0494     case RT5682_PLL2_CTRL_3:
0495     case RT5682_PLL2_CTRL_4:
0496     case RT5682_RC_CLK_CTRL:
0497     case RT5682_I2S_M_CLK_CTRL_1:
0498     case RT5682_I2S2_F_DIV_CTRL_1:
0499     case RT5682_I2S2_F_DIV_CTRL_2:
0500     case RT5682_EQ_CTRL_1:
0501     case RT5682_EQ_CTRL_2:
0502     case RT5682_IRQ_CTRL_1:
0503     case RT5682_IRQ_CTRL_2:
0504     case RT5682_IRQ_CTRL_3:
0505     case RT5682_IRQ_CTRL_4:
0506     case RT5682_INT_ST_1:
0507     case RT5682_GPIO_CTRL_1:
0508     case RT5682_GPIO_CTRL_2:
0509     case RT5682_GPIO_CTRL_3:
0510     case RT5682_HP_AMP_DET_CTRL_1:
0511     case RT5682_HP_AMP_DET_CTRL_2:
0512     case RT5682_MID_HP_AMP_DET:
0513     case RT5682_LOW_HP_AMP_DET:
0514     case RT5682_DELAY_BUF_CTRL:
0515     case RT5682_SV_ZCD_1:
0516     case RT5682_SV_ZCD_2:
0517     case RT5682_IL_CMD_1:
0518     case RT5682_IL_CMD_2:
0519     case RT5682_IL_CMD_3:
0520     case RT5682_IL_CMD_4:
0521     case RT5682_IL_CMD_5:
0522     case RT5682_IL_CMD_6:
0523     case RT5682_4BTN_IL_CMD_1:
0524     case RT5682_4BTN_IL_CMD_2:
0525     case RT5682_4BTN_IL_CMD_3:
0526     case RT5682_4BTN_IL_CMD_4:
0527     case RT5682_4BTN_IL_CMD_5:
0528     case RT5682_4BTN_IL_CMD_6:
0529     case RT5682_4BTN_IL_CMD_7:
0530     case RT5682_ADC_STO1_HP_CTRL_1:
0531     case RT5682_ADC_STO1_HP_CTRL_2:
0532     case RT5682_AJD1_CTRL:
0533     case RT5682_JD1_THD:
0534     case RT5682_JD2_THD:
0535     case RT5682_JD_CTRL_1:
0536     case RT5682_DUMMY_1:
0537     case RT5682_DUMMY_2:
0538     case RT5682_DUMMY_3:
0539     case RT5682_DAC_ADC_DIG_VOL1:
0540     case RT5682_BIAS_CUR_CTRL_2:
0541     case RT5682_BIAS_CUR_CTRL_3:
0542     case RT5682_BIAS_CUR_CTRL_4:
0543     case RT5682_BIAS_CUR_CTRL_5:
0544     case RT5682_BIAS_CUR_CTRL_6:
0545     case RT5682_BIAS_CUR_CTRL_7:
0546     case RT5682_BIAS_CUR_CTRL_8:
0547     case RT5682_BIAS_CUR_CTRL_9:
0548     case RT5682_BIAS_CUR_CTRL_10:
0549     case RT5682_VREF_REC_OP_FB_CAP_CTRL:
0550     case RT5682_CHARGE_PUMP_1:
0551     case RT5682_DIG_IN_CTRL_1:
0552     case RT5682_PAD_DRIVING_CTRL:
0553     case RT5682_SOFT_RAMP_DEPOP:
0554     case RT5682_CHOP_DAC:
0555     case RT5682_CHOP_ADC:
0556     case RT5682_CALIB_ADC_CTRL:
0557     case RT5682_VOL_TEST:
0558     case RT5682_SPKVDD_DET_STA:
0559     case RT5682_TEST_MODE_CTRL_1:
0560     case RT5682_TEST_MODE_CTRL_2:
0561     case RT5682_TEST_MODE_CTRL_3:
0562     case RT5682_TEST_MODE_CTRL_4:
0563     case RT5682_TEST_MODE_CTRL_5:
0564     case RT5682_PLL1_INTERNAL:
0565     case RT5682_PLL2_INTERNAL:
0566     case RT5682_STO_NG2_CTRL_1:
0567     case RT5682_STO_NG2_CTRL_2:
0568     case RT5682_STO_NG2_CTRL_3:
0569     case RT5682_STO_NG2_CTRL_4:
0570     case RT5682_STO_NG2_CTRL_5:
0571     case RT5682_STO_NG2_CTRL_6:
0572     case RT5682_STO_NG2_CTRL_7:
0573     case RT5682_STO_NG2_CTRL_8:
0574     case RT5682_STO_NG2_CTRL_9:
0575     case RT5682_STO_NG2_CTRL_10:
0576     case RT5682_STO1_DAC_SIL_DET:
0577     case RT5682_SIL_PSV_CTRL1:
0578     case RT5682_SIL_PSV_CTRL2:
0579     case RT5682_SIL_PSV_CTRL3:
0580     case RT5682_SIL_PSV_CTRL4:
0581     case RT5682_SIL_PSV_CTRL5:
0582     case RT5682_HP_IMP_SENS_CTRL_01:
0583     case RT5682_HP_IMP_SENS_CTRL_02:
0584     case RT5682_HP_IMP_SENS_CTRL_03:
0585     case RT5682_HP_IMP_SENS_CTRL_04:
0586     case RT5682_HP_IMP_SENS_CTRL_05:
0587     case RT5682_HP_IMP_SENS_CTRL_06:
0588     case RT5682_HP_IMP_SENS_CTRL_07:
0589     case RT5682_HP_IMP_SENS_CTRL_08:
0590     case RT5682_HP_IMP_SENS_CTRL_09:
0591     case RT5682_HP_IMP_SENS_CTRL_10:
0592     case RT5682_HP_IMP_SENS_CTRL_11:
0593     case RT5682_HP_IMP_SENS_CTRL_12:
0594     case RT5682_HP_IMP_SENS_CTRL_13:
0595     case RT5682_HP_IMP_SENS_CTRL_14:
0596     case RT5682_HP_IMP_SENS_CTRL_15:
0597     case RT5682_HP_IMP_SENS_CTRL_16:
0598     case RT5682_HP_IMP_SENS_CTRL_17:
0599     case RT5682_HP_IMP_SENS_CTRL_18:
0600     case RT5682_HP_IMP_SENS_CTRL_19:
0601     case RT5682_HP_IMP_SENS_CTRL_20:
0602     case RT5682_HP_IMP_SENS_CTRL_21:
0603     case RT5682_HP_IMP_SENS_CTRL_22:
0604     case RT5682_HP_IMP_SENS_CTRL_23:
0605     case RT5682_HP_IMP_SENS_CTRL_24:
0606     case RT5682_HP_IMP_SENS_CTRL_25:
0607     case RT5682_HP_IMP_SENS_CTRL_26:
0608     case RT5682_HP_IMP_SENS_CTRL_27:
0609     case RT5682_HP_IMP_SENS_CTRL_28:
0610     case RT5682_HP_IMP_SENS_CTRL_29:
0611     case RT5682_HP_IMP_SENS_CTRL_30:
0612     case RT5682_HP_IMP_SENS_CTRL_31:
0613     case RT5682_HP_IMP_SENS_CTRL_32:
0614     case RT5682_HP_IMP_SENS_CTRL_33:
0615     case RT5682_HP_IMP_SENS_CTRL_34:
0616     case RT5682_HP_IMP_SENS_CTRL_35:
0617     case RT5682_HP_IMP_SENS_CTRL_36:
0618     case RT5682_HP_IMP_SENS_CTRL_37:
0619     case RT5682_HP_IMP_SENS_CTRL_38:
0620     case RT5682_HP_IMP_SENS_CTRL_39:
0621     case RT5682_HP_IMP_SENS_CTRL_40:
0622     case RT5682_HP_IMP_SENS_CTRL_41:
0623     case RT5682_HP_IMP_SENS_CTRL_42:
0624     case RT5682_HP_IMP_SENS_CTRL_43:
0625     case RT5682_HP_LOGIC_CTRL_1:
0626     case RT5682_HP_LOGIC_CTRL_2:
0627     case RT5682_HP_LOGIC_CTRL_3:
0628     case RT5682_HP_CALIB_CTRL_1:
0629     case RT5682_HP_CALIB_CTRL_2:
0630     case RT5682_HP_CALIB_CTRL_3:
0631     case RT5682_HP_CALIB_CTRL_4:
0632     case RT5682_HP_CALIB_CTRL_5:
0633     case RT5682_HP_CALIB_CTRL_6:
0634     case RT5682_HP_CALIB_CTRL_7:
0635     case RT5682_HP_CALIB_CTRL_9:
0636     case RT5682_HP_CALIB_CTRL_10:
0637     case RT5682_HP_CALIB_CTRL_11:
0638     case RT5682_HP_CALIB_STA_1:
0639     case RT5682_HP_CALIB_STA_2:
0640     case RT5682_HP_CALIB_STA_3:
0641     case RT5682_HP_CALIB_STA_4:
0642     case RT5682_HP_CALIB_STA_5:
0643     case RT5682_HP_CALIB_STA_6:
0644     case RT5682_HP_CALIB_STA_7:
0645     case RT5682_HP_CALIB_STA_8:
0646     case RT5682_HP_CALIB_STA_9:
0647     case RT5682_HP_CALIB_STA_10:
0648     case RT5682_HP_CALIB_STA_11:
0649     case RT5682_SAR_IL_CMD_1:
0650     case RT5682_SAR_IL_CMD_2:
0651     case RT5682_SAR_IL_CMD_3:
0652     case RT5682_SAR_IL_CMD_4:
0653     case RT5682_SAR_IL_CMD_5:
0654     case RT5682_SAR_IL_CMD_6:
0655     case RT5682_SAR_IL_CMD_7:
0656     case RT5682_SAR_IL_CMD_8:
0657     case RT5682_SAR_IL_CMD_9:
0658     case RT5682_SAR_IL_CMD_10:
0659     case RT5682_SAR_IL_CMD_11:
0660     case RT5682_SAR_IL_CMD_12:
0661     case RT5682_SAR_IL_CMD_13:
0662     case RT5682_EFUSE_CTRL_1:
0663     case RT5682_EFUSE_CTRL_2:
0664     case RT5682_EFUSE_CTRL_3:
0665     case RT5682_EFUSE_CTRL_4:
0666     case RT5682_EFUSE_CTRL_5:
0667     case RT5682_EFUSE_CTRL_6:
0668     case RT5682_EFUSE_CTRL_7:
0669     case RT5682_EFUSE_CTRL_8:
0670     case RT5682_EFUSE_CTRL_9:
0671     case RT5682_EFUSE_CTRL_10:
0672     case RT5682_EFUSE_CTRL_11:
0673     case RT5682_JD_TOP_VC_VTRL:
0674     case RT5682_DRC1_CTRL_0:
0675     case RT5682_DRC1_CTRL_1:
0676     case RT5682_DRC1_CTRL_2:
0677     case RT5682_DRC1_CTRL_3:
0678     case RT5682_DRC1_CTRL_4:
0679     case RT5682_DRC1_CTRL_5:
0680     case RT5682_DRC1_CTRL_6:
0681     case RT5682_DRC1_HARD_LMT_CTRL_1:
0682     case RT5682_DRC1_HARD_LMT_CTRL_2:
0683     case RT5682_DRC1_PRIV_1:
0684     case RT5682_DRC1_PRIV_2:
0685     case RT5682_DRC1_PRIV_3:
0686     case RT5682_DRC1_PRIV_4:
0687     case RT5682_DRC1_PRIV_5:
0688     case RT5682_DRC1_PRIV_6:
0689     case RT5682_DRC1_PRIV_7:
0690     case RT5682_DRC1_PRIV_8:
0691     case RT5682_EQ_AUTO_RCV_CTRL1:
0692     case RT5682_EQ_AUTO_RCV_CTRL2:
0693     case RT5682_EQ_AUTO_RCV_CTRL3:
0694     case RT5682_EQ_AUTO_RCV_CTRL4:
0695     case RT5682_EQ_AUTO_RCV_CTRL5:
0696     case RT5682_EQ_AUTO_RCV_CTRL6:
0697     case RT5682_EQ_AUTO_RCV_CTRL7:
0698     case RT5682_EQ_AUTO_RCV_CTRL8:
0699     case RT5682_EQ_AUTO_RCV_CTRL9:
0700     case RT5682_EQ_AUTO_RCV_CTRL10:
0701     case RT5682_EQ_AUTO_RCV_CTRL11:
0702     case RT5682_EQ_AUTO_RCV_CTRL12:
0703     case RT5682_EQ_AUTO_RCV_CTRL13:
0704     case RT5682_ADC_L_EQ_LPF1_A1:
0705     case RT5682_R_EQ_LPF1_A1:
0706     case RT5682_L_EQ_LPF1_H0:
0707     case RT5682_R_EQ_LPF1_H0:
0708     case RT5682_L_EQ_BPF1_A1:
0709     case RT5682_R_EQ_BPF1_A1:
0710     case RT5682_L_EQ_BPF1_A2:
0711     case RT5682_R_EQ_BPF1_A2:
0712     case RT5682_L_EQ_BPF1_H0:
0713     case RT5682_R_EQ_BPF1_H0:
0714     case RT5682_L_EQ_BPF2_A1:
0715     case RT5682_R_EQ_BPF2_A1:
0716     case RT5682_L_EQ_BPF2_A2:
0717     case RT5682_R_EQ_BPF2_A2:
0718     case RT5682_L_EQ_BPF2_H0:
0719     case RT5682_R_EQ_BPF2_H0:
0720     case RT5682_L_EQ_BPF3_A1:
0721     case RT5682_R_EQ_BPF3_A1:
0722     case RT5682_L_EQ_BPF3_A2:
0723     case RT5682_R_EQ_BPF3_A2:
0724     case RT5682_L_EQ_BPF3_H0:
0725     case RT5682_R_EQ_BPF3_H0:
0726     case RT5682_L_EQ_BPF4_A1:
0727     case RT5682_R_EQ_BPF4_A1:
0728     case RT5682_L_EQ_BPF4_A2:
0729     case RT5682_R_EQ_BPF4_A2:
0730     case RT5682_L_EQ_BPF4_H0:
0731     case RT5682_R_EQ_BPF4_H0:
0732     case RT5682_L_EQ_HPF1_A1:
0733     case RT5682_R_EQ_HPF1_A1:
0734     case RT5682_L_EQ_HPF1_H0:
0735     case RT5682_R_EQ_HPF1_H0:
0736     case RT5682_L_EQ_PRE_VOL:
0737     case RT5682_R_EQ_PRE_VOL:
0738     case RT5682_L_EQ_POST_VOL:
0739     case RT5682_R_EQ_POST_VOL:
0740     case RT5682_I2C_MODE:
0741         return true;
0742     default:
0743         return false;
0744     }
0745 }
0746 EXPORT_SYMBOL_GPL(rt5682_readable_register);
0747 
0748 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
0749 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
0750 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
0751 
0752 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
0753 static const DECLARE_TLV_DB_RANGE(bst_tlv,
0754     0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
0755     1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
0756     2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
0757     3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
0758     6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
0759     7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
0760     8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
0761 );
0762 
0763 /* Interface data select */
0764 static const char * const rt5682_data_select[] = {
0765     "L/R", "R/L", "L/L", "R/R"
0766 };
0767 
0768 static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum,
0769     RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select);
0770 
0771 static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum,
0772     RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select);
0773 
0774 static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum,
0775     RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select);
0776 
0777 static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum,
0778     RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select);
0779 
0780 static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum,
0781     RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select);
0782 
0783 static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux =
0784     SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum);
0785 
0786 static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux =
0787     SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum);
0788 
0789 static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux =
0790     SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum);
0791 
0792 static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux =
0793     SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum);
0794 
0795 static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux =
0796     SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum);
0797 
0798 static const char * const rt5682_dac_select[] = {
0799     "IF1", "SOUND"
0800 };
0801 
0802 static SOC_ENUM_SINGLE_DECL(rt5682_dacl_enum,
0803     RT5682_AD_DA_MIXER, RT5682_DAC1_L_SEL_SFT, rt5682_dac_select);
0804 
0805 static const struct snd_kcontrol_new rt5682_dac_l_mux =
0806     SOC_DAPM_ENUM("DAC L Mux", rt5682_dacl_enum);
0807 
0808 static SOC_ENUM_SINGLE_DECL(rt5682_dacr_enum,
0809     RT5682_AD_DA_MIXER, RT5682_DAC1_R_SEL_SFT, rt5682_dac_select);
0810 
0811 static const struct snd_kcontrol_new rt5682_dac_r_mux =
0812     SOC_DAPM_ENUM("DAC R Mux", rt5682_dacr_enum);
0813 
0814 void rt5682_reset(struct rt5682_priv *rt5682)
0815 {
0816     regmap_write(rt5682->regmap, RT5682_RESET, 0);
0817     if (!rt5682->is_sdw)
0818         regmap_write(rt5682->regmap, RT5682_I2C_MODE, 1);
0819 }
0820 EXPORT_SYMBOL_GPL(rt5682_reset);
0821 
0822 /**
0823  * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters
0824  * @component: SoC audio component device.
0825  * @filter_mask: mask of filters.
0826  * @clk_src: clock source
0827  *
0828  * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can
0829  * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
0830  * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
0831  * ASRC function will track i2s clock and generate a corresponding system clock
0832  * for codec. This function provides an API to select the clock source for a
0833  * set of filters specified by the mask. And the component driver will turn on
0834  * ASRC for these filters if ASRC is selected as their clock source.
0835  */
0836 int rt5682_sel_asrc_clk_src(struct snd_soc_component *component,
0837         unsigned int filter_mask, unsigned int clk_src)
0838 {
0839     switch (clk_src) {
0840     case RT5682_CLK_SEL_SYS:
0841     case RT5682_CLK_SEL_I2S1_ASRC:
0842     case RT5682_CLK_SEL_I2S2_ASRC:
0843         break;
0844 
0845     default:
0846         return -EINVAL;
0847     }
0848 
0849     if (filter_mask & RT5682_DA_STEREO1_FILTER) {
0850         snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2,
0851             RT5682_FILTER_CLK_SEL_MASK,
0852             clk_src << RT5682_FILTER_CLK_SEL_SFT);
0853     }
0854 
0855     if (filter_mask & RT5682_AD_STEREO1_FILTER) {
0856         snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3,
0857             RT5682_FILTER_CLK_SEL_MASK,
0858             clk_src << RT5682_FILTER_CLK_SEL_SFT);
0859     }
0860 
0861     return 0;
0862 }
0863 EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src);
0864 
0865 static int rt5682_button_detect(struct snd_soc_component *component)
0866 {
0867     int btn_type, val;
0868 
0869     val = snd_soc_component_read(component, RT5682_4BTN_IL_CMD_1);
0870     btn_type = val & 0xfff0;
0871     snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val);
0872     dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type);
0873     snd_soc_component_update_bits(component,
0874         RT5682_SAR_IL_CMD_2, 0x10, 0x10);
0875 
0876     return btn_type;
0877 }
0878 
0879 static void rt5682_enable_push_button_irq(struct snd_soc_component *component,
0880         bool enable)
0881 {
0882     struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
0883 
0884     if (enable) {
0885         snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
0886             RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN);
0887         snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
0888             RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN);
0889         snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040);
0890         snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
0891             RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK,
0892             RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR);
0893         if (rt5682->is_sdw)
0894             snd_soc_component_update_bits(component,
0895                 RT5682_IRQ_CTRL_3,
0896                 RT5682_IL_IRQ_MASK | RT5682_IL_IRQ_TYPE_MASK,
0897                 RT5682_IL_IRQ_EN | RT5682_IL_IRQ_PUL);
0898         else
0899             snd_soc_component_update_bits(component,
0900                 RT5682_IRQ_CTRL_3, RT5682_IL_IRQ_MASK,
0901                 RT5682_IL_IRQ_EN);
0902     } else {
0903         snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3,
0904             RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS);
0905         snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
0906             RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS);
0907         snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
0908             RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS);
0909         snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
0910             RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST);
0911         snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
0912             RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE);
0913     }
0914 }
0915 
0916 /**
0917  * rt5682_headset_detect - Detect headset.
0918  * @component: SoC audio component device.
0919  * @jack_insert: Jack insert or not.
0920  *
0921  * Detect whether is headset or not when jack inserted.
0922  *
0923  * Returns detect status.
0924  */
0925 static int rt5682_headset_detect(struct snd_soc_component *component, int jack_insert)
0926 {
0927     struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
0928     struct snd_soc_dapm_context *dapm = &component->dapm;
0929     unsigned int val, count;
0930 
0931     if (jack_insert) {
0932         snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
0933             RT5682_PWR_VREF2 | RT5682_PWR_MB,
0934             RT5682_PWR_VREF2 | RT5682_PWR_MB);
0935         snd_soc_component_update_bits(component,
0936             RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
0937         usleep_range(15000, 20000);
0938         snd_soc_component_update_bits(component,
0939             RT5682_PWR_ANLG_1, RT5682_PWR_FV2, RT5682_PWR_FV2);
0940         snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
0941             RT5682_PWR_CBJ, RT5682_PWR_CBJ);
0942         snd_soc_component_update_bits(component,
0943             RT5682_HP_CHARGE_PUMP_1,
0944             RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 0);
0945         rt5682_enable_push_button_irq(component, false);
0946         snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
0947             RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW);
0948         usleep_range(55000, 60000);
0949         snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
0950             RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH);
0951 
0952         count = 0;
0953         val = snd_soc_component_read(component, RT5682_CBJ_CTRL_2)
0954             & RT5682_JACK_TYPE_MASK;
0955         while (val == 0 && count < 50) {
0956             usleep_range(10000, 15000);
0957             val = snd_soc_component_read(component,
0958                 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK;
0959             count++;
0960         }
0961 
0962         switch (val) {
0963         case 0x1:
0964         case 0x2:
0965             rt5682->jack_type = SND_JACK_HEADSET;
0966             snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
0967                 RT5682_FAST_OFF_MASK, RT5682_FAST_OFF_EN);
0968             rt5682_enable_push_button_irq(component, true);
0969             break;
0970         default:
0971             rt5682->jack_type = SND_JACK_HEADPHONE;
0972             break;
0973         }
0974 
0975         snd_soc_component_update_bits(component,
0976             RT5682_HP_CHARGE_PUMP_1,
0977             RT5682_OSW_L_MASK | RT5682_OSW_R_MASK,
0978             RT5682_OSW_L_EN | RT5682_OSW_R_EN);
0979         snd_soc_component_update_bits(component, RT5682_MICBIAS_2,
0980             RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK,
0981             RT5682_PWR_CLK25M_PU | RT5682_PWR_CLK1M_PU);
0982     } else {
0983         rt5682_enable_push_button_irq(component, false);
0984         snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
0985             RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW);
0986         if (!snd_soc_dapm_get_pin_status(dapm, "MICBIAS") &&
0987             !snd_soc_dapm_get_pin_status(dapm, "PLL1") &&
0988             !snd_soc_dapm_get_pin_status(dapm, "PLL2B"))
0989             snd_soc_component_update_bits(component,
0990                 RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0);
0991         if (!snd_soc_dapm_get_pin_status(dapm, "Vref2") &&
0992             !snd_soc_dapm_get_pin_status(dapm, "PLL1") &&
0993             !snd_soc_dapm_get_pin_status(dapm, "PLL2B"))
0994             snd_soc_component_update_bits(component,
0995                 RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0);
0996         snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
0997             RT5682_PWR_CBJ, 0);
0998         snd_soc_component_update_bits(component, RT5682_MICBIAS_2,
0999             RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK,
1000             RT5682_PWR_CLK25M_PD | RT5682_PWR_CLK1M_PD);
1001         snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
1002             RT5682_FAST_OFF_MASK, RT5682_FAST_OFF_DIS);
1003 
1004         rt5682->jack_type = 0;
1005     }
1006 
1007     dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type);
1008     return rt5682->jack_type;
1009 }
1010 
1011 static int rt5682_set_jack_detect(struct snd_soc_component *component,
1012         struct snd_soc_jack *hs_jack, void *data)
1013 {
1014     struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1015 
1016     rt5682->hs_jack = hs_jack;
1017 
1018     if (!hs_jack) {
1019         regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1020             RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1021         regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1022             RT5682_POW_JDH | RT5682_POW_JDL, 0);
1023         cancel_delayed_work_sync(&rt5682->jack_detect_work);
1024 
1025         return 0;
1026     }
1027 
1028     if (!rt5682->is_sdw) {
1029         switch (rt5682->pdata.jd_src) {
1030         case RT5682_JD1:
1031             snd_soc_component_update_bits(component,
1032                 RT5682_CBJ_CTRL_5, 0x0700, 0x0600);
1033             snd_soc_component_update_bits(component,
1034                 RT5682_CBJ_CTRL_2, RT5682_EXT_JD_SRC,
1035                 RT5682_EXT_JD_SRC_MANUAL);
1036             snd_soc_component_write(component, RT5682_CBJ_CTRL_1,
1037                 0xd142);
1038             snd_soc_component_update_bits(component,
1039                 RT5682_CBJ_CTRL_3, RT5682_CBJ_IN_BUF_EN,
1040                 RT5682_CBJ_IN_BUF_EN);
1041             snd_soc_component_update_bits(component,
1042                 RT5682_SAR_IL_CMD_1, RT5682_SAR_POW_MASK,
1043                 RT5682_SAR_POW_EN);
1044             regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
1045                 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ);
1046             regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1047                 RT5682_POW_IRQ | RT5682_POW_JDH |
1048                 RT5682_POW_ANA, RT5682_POW_IRQ |
1049                 RT5682_POW_JDH | RT5682_POW_ANA);
1050             regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2,
1051                 RT5682_PWR_JDH, RT5682_PWR_JDH);
1052             regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1053                 RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK,
1054                 RT5682_JD1_EN | RT5682_JD1_POL_NOR);
1055             regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_4,
1056                 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1057                 rt5682->pdata.btndet_delay));
1058             regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_5,
1059                 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1060                 rt5682->pdata.btndet_delay));
1061             regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_6,
1062                 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1063                 rt5682->pdata.btndet_delay));
1064             regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_7,
1065                 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1066                 rt5682->pdata.btndet_delay));
1067             mod_delayed_work(system_power_efficient_wq,
1068                 &rt5682->jack_detect_work,
1069                 msecs_to_jiffies(250));
1070             break;
1071 
1072         case RT5682_JD_NULL:
1073             regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1074                 RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1075             regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1076                 RT5682_POW_JDH | RT5682_POW_JDL, 0);
1077             break;
1078 
1079         default:
1080             dev_warn(component->dev, "Wrong JD source\n");
1081             break;
1082         }
1083     }
1084 
1085     return 0;
1086 }
1087 
1088 void rt5682_jack_detect_handler(struct work_struct *work)
1089 {
1090     struct rt5682_priv *rt5682 =
1091         container_of(work, struct rt5682_priv, jack_detect_work.work);
1092     struct snd_soc_dapm_context *dapm;
1093     int val, btn_type;
1094 
1095     if (!rt5682->component || !rt5682->component->card ||
1096         !rt5682->component->card->instantiated) {
1097         /* card not yet ready, try later */
1098         mod_delayed_work(system_power_efficient_wq,
1099                  &rt5682->jack_detect_work, msecs_to_jiffies(15));
1100         return;
1101     }
1102 
1103     if (rt5682->is_sdw) {
1104         if (pm_runtime_status_suspended(rt5682->slave->dev.parent)) {
1105             dev_dbg(&rt5682->slave->dev,
1106                 "%s: parent device is pm_runtime_status_suspended, skipping jack detection\n",
1107                 __func__);
1108             return;
1109         }
1110     }
1111 
1112     dapm = snd_soc_component_get_dapm(rt5682->component);
1113 
1114     snd_soc_dapm_mutex_lock(dapm);
1115     mutex_lock(&rt5682->calibrate_mutex);
1116 
1117     val = snd_soc_component_read(rt5682->component, RT5682_AJD1_CTRL)
1118         & RT5682_JDH_RS_MASK;
1119     if (!val) {
1120         /* jack in */
1121         if (rt5682->jack_type == 0) {
1122             /* jack was out, report jack type */
1123             rt5682->jack_type =
1124                 rt5682_headset_detect(rt5682->component, 1);
1125             rt5682->irq_work_delay_time = 0;
1126         } else if ((rt5682->jack_type & SND_JACK_HEADSET) ==
1127             SND_JACK_HEADSET) {
1128             /* jack is already in, report button event */
1129             rt5682->jack_type = SND_JACK_HEADSET;
1130             btn_type = rt5682_button_detect(rt5682->component);
1131             /**
1132              * rt5682 can report three kinds of button behavior,
1133              * one click, double click and hold. However,
1134              * currently we will report button pressed/released
1135              * event. So all the three button behaviors are
1136              * treated as button pressed.
1137              */
1138             switch (btn_type) {
1139             case 0x8000:
1140             case 0x4000:
1141             case 0x2000:
1142                 rt5682->jack_type |= SND_JACK_BTN_0;
1143                 break;
1144             case 0x1000:
1145             case 0x0800:
1146             case 0x0400:
1147                 rt5682->jack_type |= SND_JACK_BTN_1;
1148                 break;
1149             case 0x0200:
1150             case 0x0100:
1151             case 0x0080:
1152                 rt5682->jack_type |= SND_JACK_BTN_2;
1153                 break;
1154             case 0x0040:
1155             case 0x0020:
1156             case 0x0010:
1157                 rt5682->jack_type |= SND_JACK_BTN_3;
1158                 break;
1159             case 0x0000: /* unpressed */
1160                 break;
1161             default:
1162                 dev_err(rt5682->component->dev,
1163                     "Unexpected button code 0x%04x\n",
1164                     btn_type);
1165                 break;
1166             }
1167         }
1168     } else {
1169         /* jack out */
1170         rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0);
1171         rt5682->irq_work_delay_time = 50;
1172     }
1173 
1174     mutex_unlock(&rt5682->calibrate_mutex);
1175     snd_soc_dapm_mutex_unlock(dapm);
1176 
1177     snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type,
1178         SND_JACK_HEADSET |
1179         SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1180         SND_JACK_BTN_2 | SND_JACK_BTN_3);
1181 
1182     if (!rt5682->is_sdw) {
1183         if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1184             SND_JACK_BTN_2 | SND_JACK_BTN_3))
1185             schedule_delayed_work(&rt5682->jd_check_work, 0);
1186         else
1187             cancel_delayed_work_sync(&rt5682->jd_check_work);
1188     }
1189 }
1190 EXPORT_SYMBOL_GPL(rt5682_jack_detect_handler);
1191 
1192 static const struct snd_kcontrol_new rt5682_snd_controls[] = {
1193     /* DAC Digital Volume */
1194     SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL,
1195         RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
1196 
1197     /* IN Boost Volume */
1198     SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL,
1199         RT5682_BST_CBJ_SFT, 8, 0, bst_tlv),
1200 
1201     /* ADC Digital Volume Control */
1202     SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL,
1203         RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1),
1204     SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL,
1205         RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
1206 
1207     /* ADC Boost Volume Control */
1208     SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST,
1209         RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT,
1210         3, 0, adc_bst_tlv),
1211 };
1212 
1213 static int rt5682_div_sel(struct rt5682_priv *rt5682,
1214         int target, const int div[], int size)
1215 {
1216     int i;
1217 
1218     if (rt5682->sysclk < target) {
1219         dev_err(rt5682->component->dev,
1220             "sysclk rate %d is too low\n", rt5682->sysclk);
1221         return 0;
1222     }
1223 
1224     for (i = 0; i < size - 1; i++) {
1225         dev_dbg(rt5682->component->dev, "div[%d]=%d\n", i, div[i]);
1226         if (target * div[i] == rt5682->sysclk)
1227             return i;
1228         if (target * div[i + 1] > rt5682->sysclk) {
1229             dev_dbg(rt5682->component->dev,
1230                 "can't find div for sysclk %d\n",
1231                 rt5682->sysclk);
1232             return i;
1233         }
1234     }
1235 
1236     if (target * div[i] < rt5682->sysclk)
1237         dev_err(rt5682->component->dev,
1238             "sysclk rate %d is too high\n", rt5682->sysclk);
1239 
1240     return size - 1;
1241 }
1242 
1243 /**
1244  * set_dmic_clk - Set parameter of dmic.
1245  *
1246  * @w: DAPM widget.
1247  * @kcontrol: The kcontrol of this widget.
1248  * @event: Event id.
1249  *
1250  * Choose dmic clock between 1MHz and 3MHz.
1251  * It is better for clock to approximate 3MHz.
1252  */
1253 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1254         struct snd_kcontrol *kcontrol, int event)
1255 {
1256     struct snd_soc_component *component =
1257         snd_soc_dapm_to_component(w->dapm);
1258     struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1259     int idx, dmic_clk_rate = 3072000;
1260     static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
1261 
1262     if (rt5682->pdata.dmic_clk_rate)
1263         dmic_clk_rate = rt5682->pdata.dmic_clk_rate;
1264 
1265     idx = rt5682_div_sel(rt5682, dmic_clk_rate, div, ARRAY_SIZE(div));
1266 
1267     snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1,
1268         RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT);
1269 
1270     return 0;
1271 }
1272 
1273 static int set_filter_clk(struct snd_soc_dapm_widget *w,
1274         struct snd_kcontrol *kcontrol, int event)
1275 {
1276     struct snd_soc_component *component =
1277         snd_soc_dapm_to_component(w->dapm);
1278     struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1279     int ref, val, reg, idx;
1280     static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
1281     static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48};
1282 
1283     if (rt5682->is_sdw)
1284         return 0;
1285 
1286     val = snd_soc_component_read(component, RT5682_GPIO_CTRL_1) &
1287         RT5682_GP4_PIN_MASK;
1288     if (w->shift == RT5682_PWR_ADC_S1F_BIT &&
1289         val == RT5682_GP4_PIN_ADCDAT2)
1290         ref = 256 * rt5682->lrck[RT5682_AIF2];
1291     else
1292         ref = 256 * rt5682->lrck[RT5682_AIF1];
1293 
1294     idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f));
1295 
1296     if (w->shift == RT5682_PWR_ADC_S1F_BIT)
1297         reg = RT5682_PLL_TRACK_3;
1298     else
1299         reg = RT5682_PLL_TRACK_2;
1300 
1301     snd_soc_component_update_bits(component, reg,
1302         RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT);
1303 
1304     /* select over sample rate */
1305     for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) {
1306         if (rt5682->sysclk <= 12288000 * div_o[idx])
1307             break;
1308     }
1309 
1310     snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
1311         RT5682_ADC_OSR_MASK | RT5682_DAC_OSR_MASK,
1312         (idx << RT5682_ADC_OSR_SFT) | (idx << RT5682_DAC_OSR_SFT));
1313 
1314     return 0;
1315 }
1316 
1317 static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w,
1318         struct snd_soc_dapm_widget *sink)
1319 {
1320     unsigned int val;
1321     struct snd_soc_component *component =
1322         snd_soc_dapm_to_component(w->dapm);
1323 
1324     val = snd_soc_component_read(component, RT5682_GLB_CLK);
1325     val &= RT5682_SCLK_SRC_MASK;
1326     if (val == RT5682_SCLK_SRC_PLL1)
1327         return 1;
1328     else
1329         return 0;
1330 }
1331 
1332 static int is_sys_clk_from_pll2(struct snd_soc_dapm_widget *w,
1333         struct snd_soc_dapm_widget *sink)
1334 {
1335     unsigned int val;
1336     struct snd_soc_component *component =
1337         snd_soc_dapm_to_component(w->dapm);
1338 
1339     val = snd_soc_component_read(component, RT5682_GLB_CLK);
1340     val &= RT5682_SCLK_SRC_MASK;
1341     if (val == RT5682_SCLK_SRC_PLL2)
1342         return 1;
1343     else
1344         return 0;
1345 }
1346 
1347 static int is_using_asrc(struct snd_soc_dapm_widget *w,
1348         struct snd_soc_dapm_widget *sink)
1349 {
1350     unsigned int reg, shift, val;
1351     struct snd_soc_component *component =
1352         snd_soc_dapm_to_component(w->dapm);
1353 
1354     switch (w->shift) {
1355     case RT5682_ADC_STO1_ASRC_SFT:
1356         reg = RT5682_PLL_TRACK_3;
1357         shift = RT5682_FILTER_CLK_SEL_SFT;
1358         break;
1359     case RT5682_DAC_STO1_ASRC_SFT:
1360         reg = RT5682_PLL_TRACK_2;
1361         shift = RT5682_FILTER_CLK_SEL_SFT;
1362         break;
1363     default:
1364         return 0;
1365     }
1366 
1367     val = (snd_soc_component_read(component, reg) >> shift) & 0xf;
1368     switch (val) {
1369     case RT5682_CLK_SEL_I2S1_ASRC:
1370     case RT5682_CLK_SEL_I2S2_ASRC:
1371         return 1;
1372     default:
1373         return 0;
1374     }
1375 }
1376 
1377 /* Digital Mixer */
1378 static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = {
1379     SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1380             RT5682_M_STO1_ADC_L1_SFT, 1, 1),
1381     SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1382             RT5682_M_STO1_ADC_L2_SFT, 1, 1),
1383 };
1384 
1385 static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = {
1386     SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1387             RT5682_M_STO1_ADC_R1_SFT, 1, 1),
1388     SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1389             RT5682_M_STO1_ADC_R2_SFT, 1, 1),
1390 };
1391 
1392 static const struct snd_kcontrol_new rt5682_dac_l_mix[] = {
1393     SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1394             RT5682_M_ADCMIX_L_SFT, 1, 1),
1395     SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1396             RT5682_M_DAC1_L_SFT, 1, 1),
1397 };
1398 
1399 static const struct snd_kcontrol_new rt5682_dac_r_mix[] = {
1400     SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1401             RT5682_M_ADCMIX_R_SFT, 1, 1),
1402     SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1403             RT5682_M_DAC1_R_SFT, 1, 1),
1404 };
1405 
1406 static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = {
1407     SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1408             RT5682_M_DAC_L1_STO_L_SFT, 1, 1),
1409     SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1410             RT5682_M_DAC_R1_STO_L_SFT, 1, 1),
1411 };
1412 
1413 static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = {
1414     SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1415             RT5682_M_DAC_L1_STO_R_SFT, 1, 1),
1416     SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1417             RT5682_M_DAC_R1_STO_R_SFT, 1, 1),
1418 };
1419 
1420 /* Analog Input Mixer */
1421 static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = {
1422     SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER,
1423             RT5682_M_CBJ_RM1_L_SFT, 1, 1),
1424 };
1425 
1426 /* STO1 ADC1 Source */
1427 /* MX-26 [13] [5] */
1428 static const char * const rt5682_sto1_adc1_src[] = {
1429     "DAC MIX", "ADC"
1430 };
1431 
1432 static SOC_ENUM_SINGLE_DECL(
1433     rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER,
1434     RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src);
1435 
1436 static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux =
1437     SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum);
1438 
1439 static SOC_ENUM_SINGLE_DECL(
1440     rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER,
1441     RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src);
1442 
1443 static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux =
1444     SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum);
1445 
1446 /* STO1 ADC Source */
1447 /* MX-26 [11:10] [3:2] */
1448 static const char * const rt5682_sto1_adc_src[] = {
1449     "ADC1 L", "ADC1 R"
1450 };
1451 
1452 static SOC_ENUM_SINGLE_DECL(
1453     rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER,
1454     RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src);
1455 
1456 static const struct snd_kcontrol_new rt5682_sto1_adcl_mux =
1457     SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum);
1458 
1459 static SOC_ENUM_SINGLE_DECL(
1460     rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER,
1461     RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src);
1462 
1463 static const struct snd_kcontrol_new rt5682_sto1_adcr_mux =
1464     SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum);
1465 
1466 /* STO1 ADC2 Source */
1467 /* MX-26 [12] [4] */
1468 static const char * const rt5682_sto1_adc2_src[] = {
1469     "DAC MIX", "DMIC"
1470 };
1471 
1472 static SOC_ENUM_SINGLE_DECL(
1473     rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER,
1474     RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src);
1475 
1476 static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux =
1477     SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum);
1478 
1479 static SOC_ENUM_SINGLE_DECL(
1480     rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER,
1481     RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src);
1482 
1483 static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux =
1484     SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum);
1485 
1486 /* MX-79 [6:4] I2S1 ADC data location */
1487 static const unsigned int rt5682_if1_adc_slot_values[] = {
1488     0,
1489     2,
1490     4,
1491     6,
1492 };
1493 
1494 static const char * const rt5682_if1_adc_slot_src[] = {
1495     "Slot 0", "Slot 2", "Slot 4", "Slot 6"
1496 };
1497 
1498 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum,
1499     RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK,
1500     rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values);
1501 
1502 static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux =
1503     SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum);
1504 
1505 /* Analog DAC L1 Source, Analog DAC R1 Source*/
1506 /* MX-2B [4], MX-2B [0]*/
1507 static const char * const rt5682_alg_dac1_src[] = {
1508     "Stereo1 DAC Mixer", "DAC1"
1509 };
1510 
1511 static SOC_ENUM_SINGLE_DECL(
1512     rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX,
1513     RT5682_A_DACL1_SFT, rt5682_alg_dac1_src);
1514 
1515 static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux =
1516     SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum);
1517 
1518 static SOC_ENUM_SINGLE_DECL(
1519     rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX,
1520     RT5682_A_DACR1_SFT, rt5682_alg_dac1_src);
1521 
1522 static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux =
1523     SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum);
1524 
1525 /* Out Switch */
1526 static const struct snd_kcontrol_new hpol_switch =
1527     SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1528         RT5682_L_MUTE_SFT, 1, 1);
1529 static const struct snd_kcontrol_new hpor_switch =
1530     SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1531         RT5682_R_MUTE_SFT, 1, 1);
1532 
1533 static int rt5682_hp_event(struct snd_soc_dapm_widget *w,
1534         struct snd_kcontrol *kcontrol, int event)
1535 {
1536     struct snd_soc_component *component =
1537         snd_soc_dapm_to_component(w->dapm);
1538 
1539     switch (event) {
1540     case SND_SOC_DAPM_PRE_PMU:
1541         snd_soc_component_update_bits(component, RT5682_HP_CTRL_2,
1542             RT5682_HP_C2_DAC_AMP_MUTE, 0);
1543         snd_soc_component_update_bits(component, RT5682_HP_LOGIC_CTRL_2,
1544             RT5682_HP_LC2_SIG_SOUR2_MASK, RT5682_HP_LC2_SIG_SOUR2_REG);
1545         snd_soc_component_update_bits(component,
1546             RT5682_DEPOP_1, 0x60, 0x60);
1547         snd_soc_component_update_bits(component,
1548             RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0080);
1549         snd_soc_component_update_bits(component, RT5682_HP_CTRL_2,
1550             RT5682_HP_C2_DAC_L_EN | RT5682_HP_C2_DAC_R_EN,
1551             RT5682_HP_C2_DAC_L_EN | RT5682_HP_C2_DAC_R_EN);
1552         usleep_range(5000, 10000);
1553         snd_soc_component_update_bits(component, RT5682_CHARGE_PUMP_1,
1554             RT5682_CP_SW_SIZE_MASK, RT5682_CP_SW_SIZE_L);
1555         break;
1556 
1557     case SND_SOC_DAPM_POST_PMD:
1558         snd_soc_component_update_bits(component, RT5682_HP_CTRL_2,
1559             RT5682_HP_C2_DAC_L_EN | RT5682_HP_C2_DAC_R_EN, 0);
1560         snd_soc_component_update_bits(component, RT5682_CHARGE_PUMP_1,
1561             RT5682_CP_SW_SIZE_MASK, RT5682_CP_SW_SIZE_M);
1562         snd_soc_component_update_bits(component,
1563             RT5682_DEPOP_1, 0x60, 0x0);
1564         snd_soc_component_update_bits(component,
1565             RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0000);
1566         break;
1567     }
1568 
1569     return 0;
1570 }
1571 
1572 static int set_dmic_power(struct snd_soc_dapm_widget *w,
1573         struct snd_kcontrol *kcontrol, int event)
1574 {
1575     struct snd_soc_component *component =
1576         snd_soc_dapm_to_component(w->dapm);
1577     struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1578     unsigned int delay = 50, val;
1579 
1580     if (rt5682->pdata.dmic_delay)
1581         delay = rt5682->pdata.dmic_delay;
1582 
1583     switch (event) {
1584     case SND_SOC_DAPM_POST_PMU:
1585         val = snd_soc_component_read(component, RT5682_GLB_CLK);
1586         val &= RT5682_SCLK_SRC_MASK;
1587         if (val == RT5682_SCLK_SRC_PLL1 || val == RT5682_SCLK_SRC_PLL2)
1588             snd_soc_component_update_bits(component,
1589                 RT5682_PWR_ANLG_1,
1590                 RT5682_PWR_VREF2 | RT5682_PWR_MB,
1591                 RT5682_PWR_VREF2 | RT5682_PWR_MB);
1592 
1593         /*Add delay to avoid pop noise*/
1594         msleep(delay);
1595         break;
1596 
1597     case SND_SOC_DAPM_POST_PMD:
1598         if (!rt5682->jack_type) {
1599             if (!snd_soc_dapm_get_pin_status(w->dapm, "MICBIAS"))
1600                 snd_soc_component_update_bits(component,
1601                     RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0);
1602             if (!snd_soc_dapm_get_pin_status(w->dapm, "Vref2"))
1603                 snd_soc_component_update_bits(component,
1604                     RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0);
1605         }
1606         break;
1607     }
1608 
1609     return 0;
1610 }
1611 
1612 static int rt5682_set_verf(struct snd_soc_dapm_widget *w,
1613         struct snd_kcontrol *kcontrol, int event)
1614 {
1615     struct snd_soc_component *component =
1616         snd_soc_dapm_to_component(w->dapm);
1617 
1618     switch (event) {
1619     case SND_SOC_DAPM_PRE_PMU:
1620         switch (w->shift) {
1621         case RT5682_PWR_VREF1_BIT:
1622             snd_soc_component_update_bits(component,
1623                 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0);
1624             break;
1625 
1626         case RT5682_PWR_VREF2_BIT:
1627             snd_soc_component_update_bits(component,
1628                 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
1629             break;
1630         }
1631         break;
1632 
1633     case SND_SOC_DAPM_POST_PMU:
1634         usleep_range(15000, 20000);
1635         switch (w->shift) {
1636         case RT5682_PWR_VREF1_BIT:
1637             snd_soc_component_update_bits(component,
1638                 RT5682_PWR_ANLG_1, RT5682_PWR_FV1,
1639                 RT5682_PWR_FV1);
1640             break;
1641 
1642         case RT5682_PWR_VREF2_BIT:
1643             snd_soc_component_update_bits(component,
1644                 RT5682_PWR_ANLG_1, RT5682_PWR_FV2,
1645                 RT5682_PWR_FV2);
1646             break;
1647         }
1648         break;
1649     }
1650 
1651     return 0;
1652 }
1653 
1654 static const unsigned int rt5682_adcdat_pin_values[] = {
1655     1,
1656     3,
1657 };
1658 
1659 static const char * const rt5682_adcdat_pin_select[] = {
1660     "ADCDAT1",
1661     "ADCDAT2",
1662 };
1663 
1664 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum,
1665     RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK,
1666     rt5682_adcdat_pin_select, rt5682_adcdat_pin_values);
1667 
1668 static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl =
1669     SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum);
1670 
1671 static const unsigned int rt5682_hpo_sig_out_values[] = {
1672     2,
1673     7,
1674 };
1675 
1676 static const char * const rt5682_hpo_sig_out_mode[] = {
1677     "Legacy",
1678     "OneBit",
1679 };
1680 
1681 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_hpo_sig_out_enum,
1682     RT5682_HP_LOGIC_CTRL_2, 0, RT5682_HP_LC2_SIG_SOUR1_MASK,
1683     rt5682_hpo_sig_out_mode, rt5682_hpo_sig_out_values);
1684 
1685 static const struct snd_kcontrol_new rt5682_hpo_sig_demux =
1686     SOC_DAPM_ENUM("HPO Signal Demux", rt5682_hpo_sig_out_enum);
1687 
1688 static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = {
1689     SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT,
1690         0, NULL, 0),
1691     SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT,
1692         0, NULL, 0),
1693     SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT,
1694         0, NULL, 0),
1695     SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT,
1696         0, set_filter_clk, SND_SOC_DAPM_PRE_PMU),
1697     SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0,
1698         rt5682_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1699     SND_SOC_DAPM_SUPPLY("Vref2", SND_SOC_NOPM, 0, 0, NULL, 0),
1700     SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, NULL, 0),
1701 
1702     /* ASRC */
1703     SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1704         RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0),
1705     SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1706         RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0),
1707     SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1,
1708         RT5682_AD_ASRC_SFT, 0, NULL, 0),
1709     SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1,
1710         RT5682_DA_ASRC_SFT, 0, NULL, 0),
1711     SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1,
1712         RT5682_DMIC_ASRC_SFT, 0, NULL, 0),
1713 
1714     /* Input Side */
1715     SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT,
1716         0, NULL, 0),
1717     SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT,
1718         0, NULL, 0),
1719 
1720     /* Input Lines */
1721     SND_SOC_DAPM_INPUT("DMIC L1"),
1722     SND_SOC_DAPM_INPUT("DMIC R1"),
1723 
1724     SND_SOC_DAPM_INPUT("IN1P"),
1725 
1726     SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1727         set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1728     SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1,
1729         RT5682_DMIC_1_EN_SFT, 0, set_dmic_power,
1730         SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1731 
1732     /* Boost */
1733     SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
1734         0, 0, NULL, 0),
1735 
1736     /* REC Mixer */
1737     SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix,
1738         ARRAY_SIZE(rt5682_rec1_l_mix)),
1739     SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2,
1740         RT5682_PWR_RM1_L_BIT, 0, NULL, 0),
1741 
1742     /* ADCs */
1743     SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
1744     SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
1745 
1746     SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1,
1747         RT5682_PWR_ADC_L1_BIT, 0, NULL, 0),
1748     SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1,
1749         RT5682_PWR_ADC_R1_BIT, 0, NULL, 0),
1750     SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC,
1751         RT5682_CKGEN_ADC1_SFT, 0, NULL, 0),
1752 
1753     /* ADC Mux */
1754     SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1755         &rt5682_sto1_adc1l_mux),
1756     SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1757         &rt5682_sto1_adc1r_mux),
1758     SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1759         &rt5682_sto1_adc2l_mux),
1760     SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1761         &rt5682_sto1_adc2r_mux),
1762     SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
1763         &rt5682_sto1_adcl_mux),
1764     SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
1765         &rt5682_sto1_adcr_mux),
1766     SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
1767         &rt5682_if1_adc_slot_mux),
1768 
1769     /* ADC Mixer */
1770     SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2,
1771         RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk,
1772         SND_SOC_DAPM_PRE_PMU),
1773     SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL,
1774         RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix,
1775         ARRAY_SIZE(rt5682_sto1_adc_l_mix)),
1776     SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL,
1777         RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix,
1778         ARRAY_SIZE(rt5682_sto1_adc_r_mix)),
1779 
1780     /* ADC PGA */
1781     SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1782 
1783     /* Digital Interface */
1784     SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT,
1785         0, NULL, 0),
1786     SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT,
1787         0, NULL, 0),
1788     SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1789     SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1790     SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1791     SND_SOC_DAPM_PGA("SOUND DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1792     SND_SOC_DAPM_PGA("SOUND DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1793 
1794     /* Digital Interface Select */
1795     SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1796         &rt5682_if1_01_adc_swap_mux),
1797     SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1798         &rt5682_if1_23_adc_swap_mux),
1799     SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1800         &rt5682_if1_45_adc_swap_mux),
1801     SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1802         &rt5682_if1_67_adc_swap_mux),
1803     SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1804         &rt5682_if2_adc_swap_mux),
1805 
1806     SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0,
1807         &rt5682_adcdat_pin_ctrl),
1808 
1809     SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0,
1810         &rt5682_dac_l_mux),
1811     SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0,
1812         &rt5682_dac_r_mux),
1813 
1814     /* Audio Interface */
1815     SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0,
1816         RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1),
1817     SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
1818         RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1),
1819     SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1820     SND_SOC_DAPM_AIF_IN("SDWRX", "SDW Playback", 0, SND_SOC_NOPM, 0, 0),
1821     SND_SOC_DAPM_AIF_OUT("SDWTX", "SDW Capture", 0, SND_SOC_NOPM, 0, 0),
1822 
1823     /* Output Side */
1824     /* DAC mixer before sound effect  */
1825     SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1826         rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)),
1827     SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1828         rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)),
1829 
1830     /* DAC channel Mux */
1831     SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
1832         &rt5682_alg_dac_l1_mux),
1833     SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
1834         &rt5682_alg_dac_r1_mux),
1835 
1836     /* DAC Mixer */
1837     SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2,
1838         RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk,
1839         SND_SOC_DAPM_PRE_PMU),
1840     SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
1841         rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)),
1842     SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
1843         rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)),
1844 
1845     /* DACs */
1846     SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1,
1847         RT5682_PWR_DAC_L1_BIT, 0),
1848     SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1,
1849         RT5682_PWR_DAC_R1_BIT, 0),
1850     SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC,
1851         RT5682_CKGEN_DAC1_SFT, 0, NULL, 0),
1852 
1853     /* HPO */
1854     SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event,
1855         SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
1856 
1857     SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1,
1858         RT5682_PWR_HA_L_BIT, 0, NULL, 0),
1859     SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1,
1860         RT5682_PWR_HA_R_BIT, 0, NULL, 0),
1861     SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1,
1862         RT5682_PUMP_EN_SFT, 0, NULL, 0),
1863     SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1,
1864         RT5682_CAPLESS_EN_SFT, 0, NULL, 0),
1865 
1866     SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0,
1867         &hpol_switch),
1868     SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0,
1869         &hpor_switch),
1870 
1871     SND_SOC_DAPM_OUT_DRV("HPO Legacy", SND_SOC_NOPM, 0, 0, NULL, 0),
1872     SND_SOC_DAPM_OUT_DRV("HPO OneBit", SND_SOC_NOPM, 0, 0, NULL, 0),
1873     SND_SOC_DAPM_DEMUX("HPO Signal Demux", SND_SOC_NOPM, 0, 0, &rt5682_hpo_sig_demux),
1874 
1875     /* CLK DET */
1876     SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET,
1877         RT5682_SYS_CLK_DET_SFT, 0, NULL, 0),
1878     SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET,
1879         RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0),
1880     SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET,
1881         RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0),
1882     SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET,
1883         RT5682_POW_CLK_DET_SFT, 0, NULL, 0),
1884 
1885     /* Output Lines */
1886     SND_SOC_DAPM_OUTPUT("HPOL"),
1887     SND_SOC_DAPM_OUTPUT("HPOR"),
1888 };
1889 
1890 static const struct snd_soc_dapm_route rt5682_dapm_routes[] = {
1891     /*PLL*/
1892     {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1893     {"ADC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
1894     {"ADC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
1895     {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1896     {"DAC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
1897     {"DAC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
1898 
1899     /*ASRC*/
1900     {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
1901     {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
1902     {"ADC STO1 ASRC", NULL, "AD ASRC"},
1903     {"ADC STO1 ASRC", NULL, "DA ASRC"},
1904     {"ADC STO1 ASRC", NULL, "CLKDET"},
1905     {"DAC STO1 ASRC", NULL, "AD ASRC"},
1906     {"DAC STO1 ASRC", NULL, "DA ASRC"},
1907     {"DAC STO1 ASRC", NULL, "CLKDET"},
1908 
1909     /*Vref*/
1910     {"MICBIAS1", NULL, "Vref1"},
1911     {"MICBIAS2", NULL, "Vref1"},
1912 
1913     {"CLKDET SYS", NULL, "CLKDET"},
1914 
1915     {"BST1 CBJ", NULL, "IN1P"},
1916 
1917     {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
1918     {"RECMIX1L", NULL, "RECMIX1L Power"},
1919 
1920     {"ADC1 L", NULL, "RECMIX1L"},
1921     {"ADC1 L", NULL, "ADC1 L Power"},
1922     {"ADC1 L", NULL, "ADC1 clock"},
1923 
1924     {"DMIC L1", NULL, "DMIC CLK"},
1925     {"DMIC L1", NULL, "DMIC1 Power"},
1926     {"DMIC R1", NULL, "DMIC CLK"},
1927     {"DMIC R1", NULL, "DMIC1 Power"},
1928     {"DMIC CLK", NULL, "DMIC ASRC"},
1929 
1930     {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
1931     {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
1932     {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
1933     {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
1934 
1935     {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
1936     {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1937     {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1938     {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1939 
1940     {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
1941     {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1942     {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1943     {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1944 
1945     {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1946     {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1947     {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
1948 
1949     {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1950     {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1951     {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
1952 
1953     {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
1954     {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
1955 
1956     {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1957     {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1958     {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1959     {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1960     {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1961     {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1962     {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1963     {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1964     {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1965     {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1966     {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1967     {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1968     {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1969     {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1970     {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1971     {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1972 
1973     {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
1974     {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
1975     {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
1976     {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
1977     {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
1978     {"AIF1TX", NULL, "I2S1"},
1979     {"AIF1TX", NULL, "ADCDAT Mux"},
1980     {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1981     {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1982     {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1983     {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1984     {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
1985     {"AIF2TX", NULL, "ADCDAT Mux"},
1986 
1987     {"SDWTX", NULL, "PLL2B"},
1988     {"SDWTX", NULL, "PLL2F"},
1989     {"SDWTX", NULL, "ADCDAT Mux"},
1990 
1991     {"IF1 DAC1 L", NULL, "AIF1RX"},
1992     {"IF1 DAC1 L", NULL, "I2S1"},
1993     {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},
1994     {"IF1 DAC1 R", NULL, "AIF1RX"},
1995     {"IF1 DAC1 R", NULL, "I2S1"},
1996     {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},
1997 
1998     {"SOUND DAC L", NULL, "SDWRX"},
1999     {"SOUND DAC L", NULL, "DAC Stereo1 Filter"},
2000     {"SOUND DAC L", NULL, "PLL2B"},
2001     {"SOUND DAC L", NULL, "PLL2F"},
2002     {"SOUND DAC R", NULL, "SDWRX"},
2003     {"SOUND DAC R", NULL, "DAC Stereo1 Filter"},
2004     {"SOUND DAC R", NULL, "PLL2B"},
2005     {"SOUND DAC R", NULL, "PLL2F"},
2006 
2007     {"DAC L Mux", "IF1", "IF1 DAC1 L"},
2008     {"DAC L Mux", "SOUND", "SOUND DAC L"},
2009     {"DAC R Mux", "IF1", "IF1 DAC1 R"},
2010     {"DAC R Mux", "SOUND", "SOUND DAC R"},
2011 
2012     {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
2013     {"DAC1 MIXL", "DAC1 Switch", "DAC L Mux"},
2014     {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
2015     {"DAC1 MIXR", "DAC1 Switch", "DAC R Mux"},
2016 
2017     {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
2018     {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
2019 
2020     {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
2021     {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
2022 
2023     {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
2024     {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
2025     {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
2026     {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
2027 
2028     {"DAC L1", NULL, "DAC L1 Source"},
2029     {"DAC R1", NULL, "DAC R1 Source"},
2030 
2031     {"DAC L1", NULL, "DAC 1 Clock"},
2032     {"DAC R1", NULL, "DAC 1 Clock"},
2033 
2034     {"HP Amp", NULL, "DAC L1"},
2035     {"HP Amp", NULL, "DAC R1"},
2036     {"HP Amp", NULL, "HP Amp L"},
2037     {"HP Amp", NULL, "HP Amp R"},
2038     {"HP Amp", NULL, "Capless"},
2039     {"HP Amp", NULL, "Charge Pump"},
2040     {"HP Amp", NULL, "CLKDET SYS"},
2041     {"HP Amp", NULL, "Vref1"},
2042 
2043     {"HPO Signal Demux", NULL, "HP Amp"},
2044 
2045     {"HPO Legacy", "Legacy", "HPO Signal Demux"},
2046     {"HPO OneBit", "OneBit", "HPO Signal Demux"},
2047 
2048     {"HPOL Playback", "Switch", "HPO Legacy"},
2049     {"HPOR Playback", "Switch", "HPO Legacy"},
2050 
2051     {"HPOL", NULL, "HPOL Playback"},
2052     {"HPOR", NULL, "HPOR Playback"},
2053     {"HPOL", NULL, "HPO OneBit"},
2054     {"HPOR", NULL, "HPO OneBit"},
2055 };
2056 
2057 static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2058         unsigned int rx_mask, int slots, int slot_width)
2059 {
2060     struct snd_soc_component *component = dai->component;
2061     unsigned int cl, val = 0;
2062 
2063     if (tx_mask || rx_mask)
2064         snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
2065             RT5682_TDM_EN, RT5682_TDM_EN);
2066     else
2067         snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
2068             RT5682_TDM_EN, 0);
2069 
2070     switch (slots) {
2071     case 4:
2072         val |= RT5682_TDM_TX_CH_4;
2073         val |= RT5682_TDM_RX_CH_4;
2074         break;
2075     case 6:
2076         val |= RT5682_TDM_TX_CH_6;
2077         val |= RT5682_TDM_RX_CH_6;
2078         break;
2079     case 8:
2080         val |= RT5682_TDM_TX_CH_8;
2081         val |= RT5682_TDM_RX_CH_8;
2082         break;
2083     case 2:
2084         break;
2085     default:
2086         return -EINVAL;
2087     }
2088 
2089     snd_soc_component_update_bits(component, RT5682_TDM_CTRL,
2090         RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val);
2091 
2092     switch (slot_width) {
2093     case 8:
2094         if (tx_mask || rx_mask)
2095             return -EINVAL;
2096         cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8;
2097         break;
2098     case 16:
2099         val = RT5682_TDM_CL_16;
2100         cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16;
2101         break;
2102     case 20:
2103         val = RT5682_TDM_CL_20;
2104         cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20;
2105         break;
2106     case 24:
2107         val = RT5682_TDM_CL_24;
2108         cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24;
2109         break;
2110     case 32:
2111         val = RT5682_TDM_CL_32;
2112         cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32;
2113         break;
2114     default:
2115         return -EINVAL;
2116     }
2117 
2118     snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2119         RT5682_TDM_CL_MASK, val);
2120     snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2121         RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl);
2122 
2123     return 0;
2124 }
2125 
2126 static int rt5682_hw_params(struct snd_pcm_substream *substream,
2127         struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2128 {
2129     struct snd_soc_component *component = dai->component;
2130     struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2131     unsigned int len_1 = 0, len_2 = 0;
2132     int pre_div, frame_size;
2133 
2134     rt5682->lrck[dai->id] = params_rate(params);
2135     pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]);
2136 
2137     frame_size = snd_soc_params_to_frame_size(params);
2138     if (frame_size < 0) {
2139         dev_err(component->dev, "Unsupported frame size: %d\n",
2140             frame_size);
2141         return -EINVAL;
2142     }
2143 
2144     dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
2145         rt5682->lrck[dai->id], pre_div, dai->id);
2146 
2147     switch (params_width(params)) {
2148     case 16:
2149         break;
2150     case 20:
2151         len_1 |= RT5682_I2S1_DL_20;
2152         len_2 |= RT5682_I2S2_DL_20;
2153         break;
2154     case 24:
2155         len_1 |= RT5682_I2S1_DL_24;
2156         len_2 |= RT5682_I2S2_DL_24;
2157         break;
2158     case 32:
2159         len_1 |= RT5682_I2S1_DL_32;
2160         len_2 |= RT5682_I2S2_DL_24;
2161         break;
2162     case 8:
2163         len_1 |= RT5682_I2S2_DL_8;
2164         len_2 |= RT5682_I2S2_DL_8;
2165         break;
2166     default:
2167         return -EINVAL;
2168     }
2169 
2170     switch (dai->id) {
2171     case RT5682_AIF1:
2172         snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2173             RT5682_I2S1_DL_MASK, len_1);
2174         if (rt5682->master[RT5682_AIF1]) {
2175             snd_soc_component_update_bits(component,
2176                 RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK |
2177                 RT5682_I2S_CLK_SRC_MASK,
2178                 pre_div << RT5682_I2S_M_DIV_SFT |
2179                 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);
2180         }
2181         if (params_channels(params) == 1) /* mono mode */
2182             snd_soc_component_update_bits(component,
2183                 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2184                 RT5682_I2S1_MONO_EN);
2185         else
2186             snd_soc_component_update_bits(component,
2187                 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2188                 RT5682_I2S1_MONO_DIS);
2189         break;
2190     case RT5682_AIF2:
2191         snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2192             RT5682_I2S2_DL_MASK, len_2);
2193         if (rt5682->master[RT5682_AIF2]) {
2194             snd_soc_component_update_bits(component,
2195                 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK,
2196                 pre_div << RT5682_I2S2_M_PD_SFT);
2197         }
2198         if (params_channels(params) == 1) /* mono mode */
2199             snd_soc_component_update_bits(component,
2200                 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2201                 RT5682_I2S2_MONO_EN);
2202         else
2203             snd_soc_component_update_bits(component,
2204                 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2205                 RT5682_I2S2_MONO_DIS);
2206         break;
2207     default:
2208         dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2209         return -EINVAL;
2210     }
2211 
2212     return 0;
2213 }
2214 
2215 static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2216 {
2217     struct snd_soc_component *component = dai->component;
2218     struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2219     unsigned int reg_val = 0, tdm_ctrl = 0;
2220 
2221     switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2222     case SND_SOC_DAIFMT_CBM_CFM:
2223         rt5682->master[dai->id] = 1;
2224         break;
2225     case SND_SOC_DAIFMT_CBS_CFS:
2226         rt5682->master[dai->id] = 0;
2227         break;
2228     default:
2229         return -EINVAL;
2230     }
2231 
2232     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2233     case SND_SOC_DAIFMT_NB_NF:
2234         break;
2235     case SND_SOC_DAIFMT_IB_NF:
2236         reg_val |= RT5682_I2S_BP_INV;
2237         tdm_ctrl |= RT5682_TDM_S_BP_INV;
2238         break;
2239     case SND_SOC_DAIFMT_NB_IF:
2240         if (dai->id == RT5682_AIF1)
2241             tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV;
2242         else
2243             return -EINVAL;
2244         break;
2245     case SND_SOC_DAIFMT_IB_IF:
2246         if (dai->id == RT5682_AIF1)
2247             tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV |
2248                     RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV;
2249         else
2250             return -EINVAL;
2251         break;
2252     default:
2253         return -EINVAL;
2254     }
2255 
2256     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2257     case SND_SOC_DAIFMT_I2S:
2258         break;
2259     case SND_SOC_DAIFMT_LEFT_J:
2260         reg_val |= RT5682_I2S_DF_LEFT;
2261         tdm_ctrl |= RT5682_TDM_DF_LEFT;
2262         break;
2263     case SND_SOC_DAIFMT_DSP_A:
2264         reg_val |= RT5682_I2S_DF_PCM_A;
2265         tdm_ctrl |= RT5682_TDM_DF_PCM_A;
2266         break;
2267     case SND_SOC_DAIFMT_DSP_B:
2268         reg_val |= RT5682_I2S_DF_PCM_B;
2269         tdm_ctrl |= RT5682_TDM_DF_PCM_B;
2270         break;
2271     default:
2272         return -EINVAL;
2273     }
2274 
2275     switch (dai->id) {
2276     case RT5682_AIF1:
2277         snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2278             RT5682_I2S_DF_MASK, reg_val);
2279         snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2280             RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK |
2281             RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK |
2282             RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK,
2283             tdm_ctrl | rt5682->master[dai->id]);
2284         break;
2285     case RT5682_AIF2:
2286         if (rt5682->master[dai->id] == 0)
2287             reg_val |= RT5682_I2S2_MS_S;
2288         snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2289             RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK |
2290             RT5682_I2S_DF_MASK, reg_val);
2291         break;
2292     default:
2293         dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2294         return -EINVAL;
2295     }
2296     return 0;
2297 }
2298 
2299 static int rt5682_set_component_sysclk(struct snd_soc_component *component,
2300         int clk_id, int source, unsigned int freq, int dir)
2301 {
2302     struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2303     unsigned int reg_val = 0, src = 0;
2304 
2305     if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src)
2306         return 0;
2307 
2308     switch (clk_id) {
2309     case RT5682_SCLK_S_MCLK:
2310         reg_val |= RT5682_SCLK_SRC_MCLK;
2311         src = RT5682_CLK_SRC_MCLK;
2312         break;
2313     case RT5682_SCLK_S_PLL1:
2314         reg_val |= RT5682_SCLK_SRC_PLL1;
2315         src = RT5682_CLK_SRC_PLL1;
2316         break;
2317     case RT5682_SCLK_S_PLL2:
2318         reg_val |= RT5682_SCLK_SRC_PLL2;
2319         src = RT5682_CLK_SRC_PLL2;
2320         break;
2321     case RT5682_SCLK_S_RCCLK:
2322         reg_val |= RT5682_SCLK_SRC_RCCLK;
2323         src = RT5682_CLK_SRC_RCCLK;
2324         break;
2325     default:
2326         dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2327         return -EINVAL;
2328     }
2329     snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2330         RT5682_SCLK_SRC_MASK, reg_val);
2331 
2332     if (rt5682->master[RT5682_AIF2]) {
2333         snd_soc_component_update_bits(component,
2334             RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK,
2335             src << RT5682_I2S2_SRC_SFT);
2336     }
2337 
2338     rt5682->sysclk = freq;
2339     rt5682->sysclk_src = clk_id;
2340 
2341     dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2342         freq, clk_id);
2343 
2344     return 0;
2345 }
2346 
2347 static int rt5682_set_component_pll(struct snd_soc_component *component,
2348         int pll_id, int source, unsigned int freq_in,
2349         unsigned int freq_out)
2350 {
2351     struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2352     struct rl6231_pll_code pll_code, pll2f_code, pll2b_code;
2353     unsigned int pll2_fout1, pll2_ps_val;
2354     int ret;
2355 
2356     if (source == rt5682->pll_src[pll_id] &&
2357         freq_in == rt5682->pll_in[pll_id] &&
2358         freq_out == rt5682->pll_out[pll_id])
2359         return 0;
2360 
2361     if (!freq_in || !freq_out) {
2362         dev_dbg(component->dev, "PLL disabled\n");
2363 
2364         rt5682->pll_in[pll_id] = 0;
2365         rt5682->pll_out[pll_id] = 0;
2366         snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2367             RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK);
2368         return 0;
2369     }
2370 
2371     if (pll_id == RT5682_PLL2) {
2372         switch (source) {
2373         case RT5682_PLL2_S_MCLK:
2374             snd_soc_component_update_bits(component,
2375                 RT5682_GLB_CLK, RT5682_PLL2_SRC_MASK,
2376                 RT5682_PLL2_SRC_MCLK);
2377             break;
2378         default:
2379             dev_err(component->dev, "Unknown PLL2 Source %d\n",
2380                 source);
2381             return -EINVAL;
2382         }
2383 
2384         /**
2385          * PLL2 concatenates 2 PLL units.
2386          * We suggest the Fout of the front PLL is 3.84MHz.
2387          */
2388         pll2_fout1 = 3840000;
2389         ret = rl6231_pll_calc(freq_in, pll2_fout1, &pll2f_code);
2390         if (ret < 0) {
2391             dev_err(component->dev, "Unsupported input clock %d\n",
2392                 freq_in);
2393             return ret;
2394         }
2395         dev_dbg(component->dev, "PLL2F: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",
2396             freq_in, pll2_fout1,
2397             pll2f_code.m_bp,
2398             (pll2f_code.m_bp ? 0 : pll2f_code.m_code),
2399             pll2f_code.n_code, pll2f_code.k_code);
2400 
2401         ret = rl6231_pll_calc(pll2_fout1, freq_out, &pll2b_code);
2402         if (ret < 0) {
2403             dev_err(component->dev, "Unsupported input clock %d\n",
2404                 pll2_fout1);
2405             return ret;
2406         }
2407         dev_dbg(component->dev, "PLL2B: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",
2408             pll2_fout1, freq_out,
2409             pll2b_code.m_bp,
2410             (pll2b_code.m_bp ? 0 : pll2b_code.m_code),
2411             pll2b_code.n_code, pll2b_code.k_code);
2412 
2413         snd_soc_component_write(component, RT5682_PLL2_CTRL_1,
2414             pll2f_code.k_code << RT5682_PLL2F_K_SFT |
2415             pll2b_code.k_code << RT5682_PLL2B_K_SFT |
2416             pll2b_code.m_code);
2417         snd_soc_component_write(component, RT5682_PLL2_CTRL_2,
2418             pll2f_code.m_code << RT5682_PLL2F_M_SFT |
2419             pll2b_code.n_code);
2420         snd_soc_component_write(component, RT5682_PLL2_CTRL_3,
2421             pll2f_code.n_code << RT5682_PLL2F_N_SFT);
2422 
2423         if (freq_out == 22579200)
2424             pll2_ps_val = 1 << RT5682_PLL2B_SEL_PS_SFT;
2425         else
2426             pll2_ps_val = 1 << RT5682_PLL2B_PS_BYP_SFT;
2427         snd_soc_component_update_bits(component, RT5682_PLL2_CTRL_4,
2428             RT5682_PLL2B_SEL_PS_MASK | RT5682_PLL2B_PS_BYP_MASK |
2429             RT5682_PLL2B_M_BP_MASK | RT5682_PLL2F_M_BP_MASK | 0xf,
2430             pll2_ps_val |
2431             (pll2b_code.m_bp ? 1 : 0) << RT5682_PLL2B_M_BP_SFT |
2432             (pll2f_code.m_bp ? 1 : 0) << RT5682_PLL2F_M_BP_SFT |
2433             0xf);
2434     } else {
2435         switch (source) {
2436         case RT5682_PLL1_S_MCLK:
2437             snd_soc_component_update_bits(component,
2438                 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,
2439                 RT5682_PLL1_SRC_MCLK);
2440             break;
2441         case RT5682_PLL1_S_BCLK1:
2442             snd_soc_component_update_bits(component,
2443                 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,
2444                 RT5682_PLL1_SRC_BCLK1);
2445             break;
2446         default:
2447             dev_err(component->dev, "Unknown PLL1 Source %d\n",
2448                 source);
2449             return -EINVAL;
2450         }
2451 
2452         ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2453         if (ret < 0) {
2454             dev_err(component->dev, "Unsupported input clock %d\n",
2455                 freq_in);
2456             return ret;
2457         }
2458 
2459         dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
2460             pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2461             pll_code.n_code, pll_code.k_code);
2462 
2463         snd_soc_component_write(component, RT5682_PLL_CTRL_1,
2464             (pll_code.n_code << RT5682_PLL_N_SFT) | pll_code.k_code);
2465         snd_soc_component_write(component, RT5682_PLL_CTRL_2,
2466             ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT) |
2467             ((pll_code.m_bp << RT5682_PLL_M_BP_SFT) | RT5682_PLL_RST));
2468     }
2469 
2470     rt5682->pll_in[pll_id] = freq_in;
2471     rt5682->pll_out[pll_id] = freq_out;
2472     rt5682->pll_src[pll_id] = source;
2473 
2474     return 0;
2475 }
2476 
2477 static int rt5682_set_bclk1_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2478 {
2479     struct snd_soc_component *component = dai->component;
2480     struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2481 
2482     rt5682->bclk[dai->id] = ratio;
2483 
2484     switch (ratio) {
2485     case 256:
2486         snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2487             RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_256);
2488         break;
2489     case 128:
2490         snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2491             RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_128);
2492         break;
2493     case 64:
2494         snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2495             RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_64);
2496         break;
2497     case 32:
2498         snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2499             RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_32);
2500         break;
2501     default:
2502         dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio);
2503         return -EINVAL;
2504     }
2505 
2506     return 0;
2507 }
2508 
2509 static int rt5682_set_bclk2_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2510 {
2511     struct snd_soc_component *component = dai->component;
2512     struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2513 
2514     rt5682->bclk[dai->id] = ratio;
2515 
2516     switch (ratio) {
2517     case 64:
2518         snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2519             RT5682_I2S2_BCLK_MS2_MASK,
2520             RT5682_I2S2_BCLK_MS2_64);
2521         break;
2522     case 32:
2523         snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2524             RT5682_I2S2_BCLK_MS2_MASK,
2525             RT5682_I2S2_BCLK_MS2_32);
2526         break;
2527     default:
2528         dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio);
2529         return -EINVAL;
2530     }
2531 
2532     return 0;
2533 }
2534 
2535 static int rt5682_set_bias_level(struct snd_soc_component *component,
2536         enum snd_soc_bias_level level)
2537 {
2538     struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2539 
2540     switch (level) {
2541     case SND_SOC_BIAS_PREPARE:
2542         regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2543             RT5682_PWR_BG, RT5682_PWR_BG);
2544         regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2545             RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO,
2546             RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO);
2547         break;
2548 
2549     case SND_SOC_BIAS_STANDBY:
2550         regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2551             RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL);
2552         break;
2553     case SND_SOC_BIAS_OFF:
2554         regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2555             RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0);
2556         regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2557             RT5682_PWR_BG, 0);
2558         break;
2559     case SND_SOC_BIAS_ON:
2560         break;
2561     }
2562 
2563     return 0;
2564 }
2565 
2566 #ifdef CONFIG_COMMON_CLK
2567 #define CLK_PLL2_FIN 48000000
2568 #define CLK_48 48000
2569 #define CLK_44 44100
2570 
2571 static bool rt5682_clk_check(struct rt5682_priv *rt5682)
2572 {
2573     if (!rt5682->master[RT5682_AIF1]) {
2574         dev_dbg(rt5682->i2c_dev, "sysclk/dai not set correctly\n");
2575         return false;
2576     }
2577     return true;
2578 }
2579 
2580 static int rt5682_wclk_prepare(struct clk_hw *hw)
2581 {
2582     struct rt5682_priv *rt5682 =
2583         container_of(hw, struct rt5682_priv,
2584                  dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2585     struct snd_soc_component *component;
2586     struct snd_soc_dapm_context *dapm;
2587 
2588     if (!rt5682_clk_check(rt5682))
2589         return -EINVAL;
2590 
2591     component = rt5682->component;
2592     dapm = snd_soc_component_get_dapm(component);
2593 
2594     snd_soc_dapm_mutex_lock(dapm);
2595 
2596     snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS");
2597     snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2598                 RT5682_PWR_MB, RT5682_PWR_MB);
2599 
2600     snd_soc_dapm_force_enable_pin_unlocked(dapm, "Vref2");
2601     snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2602             RT5682_PWR_VREF2 | RT5682_PWR_FV2,
2603             RT5682_PWR_VREF2);
2604     usleep_range(55000, 60000);
2605     snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2606             RT5682_PWR_FV2, RT5682_PWR_FV2);
2607 
2608     snd_soc_dapm_force_enable_pin_unlocked(dapm, "I2S1");
2609     snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2F");
2610     snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2B");
2611     snd_soc_dapm_sync_unlocked(dapm);
2612 
2613     snd_soc_dapm_mutex_unlock(dapm);
2614 
2615     return 0;
2616 }
2617 
2618 static void rt5682_wclk_unprepare(struct clk_hw *hw)
2619 {
2620     struct rt5682_priv *rt5682 =
2621         container_of(hw, struct rt5682_priv,
2622                  dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2623     struct snd_soc_component *component;
2624     struct snd_soc_dapm_context *dapm;
2625 
2626     if (!rt5682_clk_check(rt5682))
2627         return;
2628 
2629     component = rt5682->component;
2630     dapm = snd_soc_component_get_dapm(component);
2631 
2632     snd_soc_dapm_mutex_lock(dapm);
2633 
2634     snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS");
2635     snd_soc_dapm_disable_pin_unlocked(dapm, "Vref2");
2636     if (!rt5682->jack_type)
2637         snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2638                 RT5682_PWR_VREF2 | RT5682_PWR_FV2 |
2639                 RT5682_PWR_MB, 0);
2640 
2641     snd_soc_dapm_disable_pin_unlocked(dapm, "I2S1");
2642     snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2F");
2643     snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2B");
2644     snd_soc_dapm_sync_unlocked(dapm);
2645 
2646     snd_soc_dapm_mutex_unlock(dapm);
2647 }
2648 
2649 static unsigned long rt5682_wclk_recalc_rate(struct clk_hw *hw,
2650                          unsigned long parent_rate)
2651 {
2652     struct rt5682_priv *rt5682 =
2653         container_of(hw, struct rt5682_priv,
2654                  dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2655     const char * const clk_name = clk_hw_get_name(hw);
2656 
2657     if (!rt5682_clk_check(rt5682))
2658         return 0;
2659     /*
2660      * Only accept to set wclk rate to 44.1k or 48kHz.
2661      */
2662     if (rt5682->lrck[RT5682_AIF1] != CLK_48 &&
2663         rt5682->lrck[RT5682_AIF1] != CLK_44) {
2664         dev_warn(rt5682->i2c_dev, "%s: clk %s only support %d or %d Hz output\n",
2665             __func__, clk_name, CLK_44, CLK_48);
2666         return 0;
2667     }
2668 
2669     return rt5682->lrck[RT5682_AIF1];
2670 }
2671 
2672 static long rt5682_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
2673                    unsigned long *parent_rate)
2674 {
2675     struct rt5682_priv *rt5682 =
2676         container_of(hw, struct rt5682_priv,
2677                  dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2678     const char * const clk_name = clk_hw_get_name(hw);
2679 
2680     if (!rt5682_clk_check(rt5682))
2681         return -EINVAL;
2682     /*
2683      * Only accept to set wclk rate to 44.1k or 48kHz.
2684      * It will force to 48kHz if not both.
2685      */
2686     if (rate != CLK_48 && rate != CLK_44) {
2687         dev_warn(rt5682->i2c_dev, "%s: clk %s only support %d or %d Hz output\n",
2688             __func__, clk_name, CLK_44, CLK_48);
2689         rate = CLK_48;
2690     }
2691 
2692     return rate;
2693 }
2694 
2695 static int rt5682_wclk_set_rate(struct clk_hw *hw, unsigned long rate,
2696                 unsigned long parent_rate)
2697 {
2698     struct rt5682_priv *rt5682 =
2699         container_of(hw, struct rt5682_priv,
2700                  dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2701     struct snd_soc_component *component;
2702     struct clk_hw *parent_hw;
2703     const char * const clk_name = clk_hw_get_name(hw);
2704     int pre_div;
2705     unsigned int clk_pll2_out;
2706 
2707     if (!rt5682_clk_check(rt5682))
2708         return -EINVAL;
2709 
2710     component = rt5682->component;
2711 
2712     /*
2713      * Whether the wclk's parent clk (mclk) exists or not, please ensure
2714      * it is fixed or set to 48MHz before setting wclk rate. It's a
2715      * temporary limitation. Only accept 48MHz clk as the clk provider.
2716      *
2717      * It will set the codec anyway by assuming mclk is 48MHz.
2718      */
2719     parent_hw = clk_hw_get_parent(hw);
2720     if (!parent_hw)
2721         dev_warn(rt5682->i2c_dev,
2722             "Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n",
2723             CLK_PLL2_FIN);
2724 
2725     if (parent_rate != CLK_PLL2_FIN)
2726         dev_warn(rt5682->i2c_dev, "clk %s only support %d Hz input\n",
2727             clk_name, CLK_PLL2_FIN);
2728 
2729     /*
2730      * To achieve the rate conversion from 48MHz to 44.1k or 48kHz,
2731      * PLL2 is needed.
2732      */
2733     clk_pll2_out = rate * 512;
2734     rt5682_set_component_pll(component, RT5682_PLL2, RT5682_PLL2_S_MCLK,
2735         CLK_PLL2_FIN, clk_pll2_out);
2736 
2737     rt5682_set_component_sysclk(component, RT5682_SCLK_S_PLL2, 0,
2738         clk_pll2_out, SND_SOC_CLOCK_IN);
2739 
2740     rt5682->lrck[RT5682_AIF1] = rate;
2741 
2742     pre_div = rl6231_get_clk_info(rt5682->sysclk, rate);
2743 
2744     snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
2745         RT5682_I2S_M_DIV_MASK | RT5682_I2S_CLK_SRC_MASK,
2746         pre_div << RT5682_I2S_M_DIV_SFT |
2747         (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);
2748 
2749     return 0;
2750 }
2751 
2752 static unsigned long rt5682_bclk_recalc_rate(struct clk_hw *hw,
2753                          unsigned long parent_rate)
2754 {
2755     struct rt5682_priv *rt5682 =
2756         container_of(hw, struct rt5682_priv,
2757                  dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2758     unsigned int bclks_per_wclk;
2759 
2760     regmap_read(rt5682->regmap, RT5682_TDM_TCON_CTRL, &bclks_per_wclk);
2761 
2762     switch (bclks_per_wclk & RT5682_TDM_BCLK_MS1_MASK) {
2763     case RT5682_TDM_BCLK_MS1_256:
2764         return parent_rate * 256;
2765     case RT5682_TDM_BCLK_MS1_128:
2766         return parent_rate * 128;
2767     case RT5682_TDM_BCLK_MS1_64:
2768         return parent_rate * 64;
2769     case RT5682_TDM_BCLK_MS1_32:
2770         return parent_rate * 32;
2771     default:
2772         return 0;
2773     }
2774 }
2775 
2776 static unsigned long rt5682_bclk_get_factor(unsigned long rate,
2777                         unsigned long parent_rate)
2778 {
2779     unsigned long factor;
2780 
2781     factor = rate / parent_rate;
2782     if (factor < 64)
2783         return 32;
2784     else if (factor < 128)
2785         return 64;
2786     else if (factor < 256)
2787         return 128;
2788     else
2789         return 256;
2790 }
2791 
2792 static long rt5682_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
2793                    unsigned long *parent_rate)
2794 {
2795     struct rt5682_priv *rt5682 =
2796         container_of(hw, struct rt5682_priv,
2797                  dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2798     unsigned long factor;
2799 
2800     if (!*parent_rate || !rt5682_clk_check(rt5682))
2801         return -EINVAL;
2802 
2803     /*
2804      * BCLK rates are set as a multiplier of WCLK in HW.
2805      * We don't allow changing the parent WCLK. We just do
2806      * some rounding down based on the parent WCLK rate
2807      * and find the appropriate multiplier of BCLK to
2808      * get the rounded down BCLK value.
2809      */
2810     factor = rt5682_bclk_get_factor(rate, *parent_rate);
2811 
2812     return *parent_rate * factor;
2813 }
2814 
2815 static int rt5682_bclk_set_rate(struct clk_hw *hw, unsigned long rate,
2816                 unsigned long parent_rate)
2817 {
2818     struct rt5682_priv *rt5682 =
2819         container_of(hw, struct rt5682_priv,
2820                  dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2821     struct snd_soc_component *component;
2822     struct snd_soc_dai *dai;
2823     unsigned long factor;
2824 
2825     if (!rt5682_clk_check(rt5682))
2826         return -EINVAL;
2827 
2828     component = rt5682->component;
2829 
2830     factor = rt5682_bclk_get_factor(rate, parent_rate);
2831 
2832     for_each_component_dais(component, dai)
2833         if (dai->id == RT5682_AIF1)
2834             return rt5682_set_bclk1_ratio(dai, factor);
2835 
2836     dev_err(rt5682->i2c_dev, "dai %d not found in component\n",
2837         RT5682_AIF1);
2838     return -ENODEV;
2839 }
2840 
2841 static const struct clk_ops rt5682_dai_clk_ops[RT5682_DAI_NUM_CLKS] = {
2842     [RT5682_DAI_WCLK_IDX] = {
2843         .prepare = rt5682_wclk_prepare,
2844         .unprepare = rt5682_wclk_unprepare,
2845         .recalc_rate = rt5682_wclk_recalc_rate,
2846         .round_rate = rt5682_wclk_round_rate,
2847         .set_rate = rt5682_wclk_set_rate,
2848     },
2849     [RT5682_DAI_BCLK_IDX] = {
2850         .recalc_rate = rt5682_bclk_recalc_rate,
2851         .round_rate = rt5682_bclk_round_rate,
2852         .set_rate = rt5682_bclk_set_rate,
2853     },
2854 };
2855 
2856 int rt5682_register_dai_clks(struct rt5682_priv *rt5682)
2857 {
2858     struct device *dev = rt5682->i2c_dev;
2859     struct rt5682_platform_data *pdata = &rt5682->pdata;
2860     struct clk_hw *dai_clk_hw;
2861     int i, ret;
2862 
2863     for (i = 0; i < RT5682_DAI_NUM_CLKS; ++i) {
2864         struct clk_init_data init = { };
2865         const struct clk_hw *parent;
2866 
2867         dai_clk_hw = &rt5682->dai_clks_hw[i];
2868 
2869         switch (i) {
2870         case RT5682_DAI_WCLK_IDX:
2871             /* Make MCLK the parent of WCLK */
2872             if (rt5682->mclk) {
2873                 parent = __clk_get_hw(rt5682->mclk);
2874                 init.parent_hws = &parent;
2875                 init.num_parents = 1;
2876             }
2877             break;
2878         case RT5682_DAI_BCLK_IDX:
2879             /* Make WCLK the parent of BCLK */
2880             parent = &rt5682->dai_clks_hw[RT5682_DAI_WCLK_IDX];
2881             init.parent_hws = &parent;
2882             init.num_parents = 1;
2883             break;
2884         default:
2885             dev_err(dev, "Invalid clock index\n");
2886             return -EINVAL;
2887         }
2888 
2889         init.name = pdata->dai_clk_names[i];
2890         init.ops = &rt5682_dai_clk_ops[i];
2891         init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE;
2892         dai_clk_hw->init = &init;
2893 
2894         ret = devm_clk_hw_register(dev, dai_clk_hw);
2895         if (ret) {
2896             dev_warn(dev, "Failed to register %s: %d\n",
2897                  init.name, ret);
2898             return ret;
2899         }
2900 
2901         if (dev->of_node) {
2902             devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
2903                             dai_clk_hw);
2904         } else {
2905             ret = devm_clk_hw_register_clkdev(dev, dai_clk_hw,
2906                               init.name,
2907                               dev_name(dev));
2908             if (ret)
2909                 return ret;
2910         }
2911     }
2912 
2913     return 0;
2914 }
2915 EXPORT_SYMBOL_GPL(rt5682_register_dai_clks);
2916 #endif /* CONFIG_COMMON_CLK */
2917 
2918 static int rt5682_probe(struct snd_soc_component *component)
2919 {
2920     struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2921     struct sdw_slave *slave;
2922     unsigned long time;
2923     struct snd_soc_dapm_context *dapm = &component->dapm;
2924 
2925     rt5682->component = component;
2926 
2927     if (rt5682->is_sdw) {
2928         slave = rt5682->slave;
2929         time = wait_for_completion_timeout(
2930             &slave->initialization_complete,
2931             msecs_to_jiffies(RT5682_PROBE_TIMEOUT));
2932         if (!time) {
2933             dev_err(&slave->dev, "Initialization not complete, timed out\n");
2934             return -ETIMEDOUT;
2935         }
2936     }
2937 
2938     snd_soc_dapm_disable_pin(dapm, "MICBIAS");
2939     snd_soc_dapm_disable_pin(dapm, "Vref2");
2940     snd_soc_dapm_sync(dapm);
2941     return 0;
2942 }
2943 
2944 static void rt5682_remove(struct snd_soc_component *component)
2945 {
2946     struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2947 
2948     rt5682_reset(rt5682);
2949 }
2950 
2951 #ifdef CONFIG_PM
2952 static int rt5682_suspend(struct snd_soc_component *component)
2953 {
2954     struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2955     unsigned int val;
2956 
2957     if (rt5682->is_sdw)
2958         return 0;
2959 
2960     cancel_delayed_work_sync(&rt5682->jack_detect_work);
2961     cancel_delayed_work_sync(&rt5682->jd_check_work);
2962     if (rt5682->hs_jack && (rt5682->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) {
2963         val = snd_soc_component_read(component,
2964                 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK;
2965 
2966         switch (val) {
2967         case 0x1:
2968             snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
2969                 RT5682_SAR_SEL_MB1_MASK | RT5682_SAR_SEL_MB2_MASK,
2970                 RT5682_SAR_SEL_MB1_NOSEL | RT5682_SAR_SEL_MB2_SEL);
2971             break;
2972         case 0x2:
2973             snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
2974                 RT5682_SAR_SEL_MB1_MASK | RT5682_SAR_SEL_MB2_MASK,
2975                 RT5682_SAR_SEL_MB1_SEL | RT5682_SAR_SEL_MB2_NOSEL);
2976             break;
2977         default:
2978             break;
2979         }
2980 
2981         /* enter SAR ADC power saving mode */
2982         snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
2983             RT5682_SAR_BUTT_DET_MASK | RT5682_SAR_BUTDET_MODE_MASK |
2984             RT5682_SAR_SEL_MB1_MB2_MASK, 0);
2985         usleep_range(5000, 6000);
2986         snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
2987             RT5682_MB1_PATH_MASK | RT5682_MB2_PATH_MASK,
2988             RT5682_CTRL_MB1_REG | RT5682_CTRL_MB2_REG);
2989         usleep_range(10000, 12000);
2990         snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
2991             RT5682_SAR_BUTT_DET_MASK | RT5682_SAR_BUTDET_MODE_MASK,
2992             RT5682_SAR_BUTT_DET_EN | RT5682_SAR_BUTDET_POW_SAV);
2993         snd_soc_component_update_bits(component, RT5682_HP_CHARGE_PUMP_1,
2994             RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 0);
2995     }
2996 
2997     regcache_cache_only(rt5682->regmap, true);
2998     regcache_mark_dirty(rt5682->regmap);
2999     return 0;
3000 }
3001 
3002 static int rt5682_resume(struct snd_soc_component *component)
3003 {
3004     struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
3005 
3006     if (rt5682->is_sdw)
3007         return 0;
3008 
3009     regcache_cache_only(rt5682->regmap, false);
3010     regcache_sync(rt5682->regmap);
3011 
3012     if (rt5682->hs_jack && (rt5682->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) {
3013         snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
3014             RT5682_SAR_BUTDET_MODE_MASK | RT5682_SAR_SEL_MB1_MB2_MASK,
3015             RT5682_SAR_BUTDET_POW_NORM | RT5682_SAR_SEL_MB1_MB2_AUTO);
3016         usleep_range(5000, 6000);
3017         snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
3018             RT5682_MB1_PATH_MASK | RT5682_MB2_PATH_MASK,
3019             RT5682_CTRL_MB1_FSM | RT5682_CTRL_MB2_FSM);
3020         snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
3021             RT5682_PWR_CBJ, RT5682_PWR_CBJ);
3022     }
3023 
3024     rt5682->jack_type = 0;
3025     mod_delayed_work(system_power_efficient_wq,
3026         &rt5682->jack_detect_work, msecs_to_jiffies(0));
3027 
3028     return 0;
3029 }
3030 #else
3031 #define rt5682_suspend NULL
3032 #define rt5682_resume NULL
3033 #endif
3034 
3035 const struct snd_soc_dai_ops rt5682_aif1_dai_ops = {
3036     .hw_params = rt5682_hw_params,
3037     .set_fmt = rt5682_set_dai_fmt,
3038     .set_tdm_slot = rt5682_set_tdm_slot,
3039     .set_bclk_ratio = rt5682_set_bclk1_ratio,
3040 };
3041 EXPORT_SYMBOL_GPL(rt5682_aif1_dai_ops);
3042 
3043 const struct snd_soc_dai_ops rt5682_aif2_dai_ops = {
3044     .hw_params = rt5682_hw_params,
3045     .set_fmt = rt5682_set_dai_fmt,
3046     .set_bclk_ratio = rt5682_set_bclk2_ratio,
3047 };
3048 EXPORT_SYMBOL_GPL(rt5682_aif2_dai_ops);
3049 
3050 const struct snd_soc_component_driver rt5682_soc_component_dev = {
3051     .probe = rt5682_probe,
3052     .remove = rt5682_remove,
3053     .suspend = rt5682_suspend,
3054     .resume = rt5682_resume,
3055     .set_bias_level = rt5682_set_bias_level,
3056     .controls = rt5682_snd_controls,
3057     .num_controls = ARRAY_SIZE(rt5682_snd_controls),
3058     .dapm_widgets = rt5682_dapm_widgets,
3059     .num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets),
3060     .dapm_routes = rt5682_dapm_routes,
3061     .num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes),
3062     .set_sysclk = rt5682_set_component_sysclk,
3063     .set_pll = rt5682_set_component_pll,
3064     .set_jack = rt5682_set_jack_detect,
3065     .use_pmdown_time    = 1,
3066     .endianness     = 1,
3067 };
3068 EXPORT_SYMBOL_GPL(rt5682_soc_component_dev);
3069 
3070 int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev)
3071 {
3072 
3073     device_property_read_u32(dev, "realtek,dmic1-data-pin",
3074         &rt5682->pdata.dmic1_data_pin);
3075     device_property_read_u32(dev, "realtek,dmic1-clk-pin",
3076         &rt5682->pdata.dmic1_clk_pin);
3077     device_property_read_u32(dev, "realtek,jd-src",
3078         &rt5682->pdata.jd_src);
3079     device_property_read_u32(dev, "realtek,btndet-delay",
3080         &rt5682->pdata.btndet_delay);
3081     device_property_read_u32(dev, "realtek,dmic-clk-rate-hz",
3082         &rt5682->pdata.dmic_clk_rate);
3083     device_property_read_u32(dev, "realtek,dmic-delay-ms",
3084         &rt5682->pdata.dmic_delay);
3085 
3086     rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
3087         "realtek,ldo1-en-gpios", 0);
3088 
3089     if (device_property_read_string_array(dev, "clock-output-names",
3090                           rt5682->pdata.dai_clk_names,
3091                           RT5682_DAI_NUM_CLKS) < 0)
3092         dev_warn(dev, "Using default DAI clk names: %s, %s\n",
3093              rt5682->pdata.dai_clk_names[RT5682_DAI_WCLK_IDX],
3094              rt5682->pdata.dai_clk_names[RT5682_DAI_BCLK_IDX]);
3095 
3096     rt5682->pdata.dmic_clk_driving_high = device_property_read_bool(dev,
3097         "realtek,dmic-clk-driving-high");
3098 
3099     return 0;
3100 }
3101 EXPORT_SYMBOL_GPL(rt5682_parse_dt);
3102 
3103 void rt5682_calibrate(struct rt5682_priv *rt5682)
3104 {
3105     int value, count;
3106 
3107     mutex_lock(&rt5682->calibrate_mutex);
3108 
3109     rt5682_reset(rt5682);
3110     regmap_write(rt5682->regmap, RT5682_I2C_CTRL, 0x000f);
3111     regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af);
3112     usleep_range(15000, 20000);
3113     regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af);
3114     regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300);
3115     regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000);
3116     regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100);
3117     regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800);
3118     regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000);
3119     regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005);
3120     regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c);
3121     regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d);
3122     regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321);
3123     regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004);
3124     regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
3125     regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1);
3126     regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311);
3127     regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
3128 
3129     regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00);
3130 
3131     for (count = 0; count < 60; count++) {
3132         regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value);
3133         if (!(value & 0x8000))
3134             break;
3135 
3136         usleep_range(10000, 10005);
3137     }
3138 
3139     if (count >= 60)
3140         dev_err(rt5682->component->dev, "HP Calibration Failure\n");
3141 
3142     /* restore settings */
3143     regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x002f);
3144     regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080);
3145     regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000);
3146     regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000);
3147     regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000);
3148     regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005);
3149     regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4);
3150     regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0c0c);
3151 
3152     mutex_unlock(&rt5682->calibrate_mutex);
3153 }
3154 EXPORT_SYMBOL_GPL(rt5682_calibrate);
3155 
3156 MODULE_DESCRIPTION("ASoC RT5682 driver");
3157 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
3158 MODULE_LICENSE("GPL v2");
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