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0009 #ifndef __RT5670_DSP_H__
0010 #define __RT5670_DSP_H__
0011
0012 #define RT5670_DSP_CTRL1 0xe0
0013 #define RT5670_DSP_CTRL2 0xe1
0014 #define RT5670_DSP_CTRL3 0xe2
0015 #define RT5670_DSP_CTRL4 0xe3
0016 #define RT5670_DSP_CTRL5 0xe4
0017
0018
0019 #define RT5670_DSP_CMD_MASK (0xff << 8)
0020 #define RT5670_DSP_CMD_PE (0x0d << 8)
0021 #define RT5670_DSP_CMD_MW (0x3b << 8)
0022 #define RT5670_DSP_CMD_MR (0x37 << 8)
0023 #define RT5670_DSP_CMD_RR (0x60 << 8)
0024 #define RT5670_DSP_CMD_RW (0x68 << 8)
0025 #define RT5670_DSP_REG_DATHI (0x26 << 8)
0026 #define RT5670_DSP_REG_DATLO (0x25 << 8)
0027 #define RT5670_DSP_CLK_MASK (0x3 << 6)
0028 #define RT5670_DSP_CLK_SFT 6
0029 #define RT5670_DSP_CLK_768K (0x0 << 6)
0030 #define RT5670_DSP_CLK_384K (0x1 << 6)
0031 #define RT5670_DSP_CLK_192K (0x2 << 6)
0032 #define RT5670_DSP_CLK_96K (0x3 << 6)
0033 #define RT5670_DSP_BUSY_MASK (0x1 << 5)
0034 #define RT5670_DSP_RW_MASK (0x1 << 4)
0035 #define RT5670_DSP_DL_MASK (0x3 << 2)
0036 #define RT5670_DSP_DL_0 (0x0 << 2)
0037 #define RT5670_DSP_DL_1 (0x1 << 2)
0038 #define RT5670_DSP_DL_2 (0x2 << 2)
0039 #define RT5670_DSP_DL_3 (0x3 << 2)
0040 #define RT5670_DSP_I2C_AL_16 (0x1 << 1)
0041 #define RT5670_DSP_CMD_EN (0x1)
0042
0043 struct rt5670_dsp_param {
0044 u16 cmd_fmt;
0045 u16 addr;
0046 u16 data;
0047 u8 cmd;
0048 };
0049
0050 #endif
0051