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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * rt5663.c  --  RT5663 ALSA SoC audio codec driver
0004  *
0005  * Copyright 2016 Realtek Semiconductor Corp.
0006  * Author: Jack Yu <jack.yu@realtek.com>
0007  */
0008 #include <linux/module.h>
0009 #include <linux/moduleparam.h>
0010 #include <linux/init.h>
0011 #include <linux/delay.h>
0012 #include <linux/pm.h>
0013 #include <linux/i2c.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/spi/spi.h>
0016 #include <linux/acpi.h>
0017 #include <linux/regulator/consumer.h>
0018 #include <linux/workqueue.h>
0019 #include <sound/core.h>
0020 #include <sound/pcm.h>
0021 #include <sound/pcm_params.h>
0022 #include <sound/jack.h>
0023 #include <sound/soc.h>
0024 #include <sound/soc-dapm.h>
0025 #include <sound/initval.h>
0026 #include <sound/tlv.h>
0027 
0028 #include "rt5663.h"
0029 #include "rl6231.h"
0030 
0031 #define RT5663_DEVICE_ID_2 0x6451
0032 #define RT5663_DEVICE_ID_1 0x6406
0033 
0034 #define RT5663_POWER_ON_DELAY_MS 300
0035 #define RT5663_SUPPLY_CURRENT_UA 500000
0036 
0037 enum {
0038     CODEC_VER_1,
0039     CODEC_VER_0,
0040 };
0041 
0042 struct impedance_mapping_table {
0043     unsigned int imp_min;
0044     unsigned int imp_max;
0045     unsigned int vol;
0046     unsigned int dc_offset_l_manual;
0047     unsigned int dc_offset_r_manual;
0048     unsigned int dc_offset_l_manual_mic;
0049     unsigned int dc_offset_r_manual_mic;
0050 };
0051 
0052 static const char *const rt5663_supply_names[] = {
0053     "avdd",
0054     "cpvdd",
0055 };
0056 
0057 struct rt5663_priv {
0058     struct snd_soc_component *component;
0059     struct rt5663_platform_data pdata;
0060     struct regmap *regmap;
0061     struct delayed_work jack_detect_work, jd_unplug_work;
0062     struct snd_soc_jack *hs_jack;
0063     struct timer_list btn_check_timer;
0064     struct impedance_mapping_table *imp_table;
0065     struct regulator_bulk_data supplies[ARRAY_SIZE(rt5663_supply_names)];
0066 
0067     int codec_ver;
0068     int sysclk;
0069     int sysclk_src;
0070     int lrck;
0071 
0072     int pll_src;
0073     int pll_in;
0074     int pll_out;
0075 
0076     int jack_type;
0077 };
0078 
0079 static const struct reg_sequence rt5663_patch_list[] = {
0080     { 0x002a, 0x8020 },
0081     { 0x0086, 0x0028 },
0082     { 0x0100, 0xa020 },
0083     { 0x0117, 0x0f28 },
0084     { 0x02fb, 0x8089 },
0085 };
0086 
0087 static const struct reg_default rt5663_v2_reg[] = {
0088     { 0x0000, 0x0000 },
0089     { 0x0001, 0xc8c8 },
0090     { 0x0002, 0x8080 },
0091     { 0x0003, 0x8000 },
0092     { 0x0004, 0xc80a },
0093     { 0x0005, 0x0000 },
0094     { 0x0006, 0x0000 },
0095     { 0x0007, 0x0000 },
0096     { 0x000a, 0x0000 },
0097     { 0x000b, 0x0000 },
0098     { 0x000c, 0x0000 },
0099     { 0x000d, 0x0000 },
0100     { 0x000f, 0x0808 },
0101     { 0x0010, 0x4000 },
0102     { 0x0011, 0x0000 },
0103     { 0x0012, 0x1404 },
0104     { 0x0013, 0x1000 },
0105     { 0x0014, 0xa00a },
0106     { 0x0015, 0x0404 },
0107     { 0x0016, 0x0404 },
0108     { 0x0017, 0x0011 },
0109     { 0x0018, 0xafaf },
0110     { 0x0019, 0xafaf },
0111     { 0x001a, 0xafaf },
0112     { 0x001b, 0x0011 },
0113     { 0x001c, 0x2f2f },
0114     { 0x001d, 0x2f2f },
0115     { 0x001e, 0x2f2f },
0116     { 0x001f, 0x0000 },
0117     { 0x0020, 0x0000 },
0118     { 0x0021, 0x0000 },
0119     { 0x0022, 0x5757 },
0120     { 0x0023, 0x0039 },
0121     { 0x0024, 0x000b },
0122     { 0x0026, 0xc0c0 },
0123     { 0x0027, 0xc0c0 },
0124     { 0x0028, 0xc0c0 },
0125     { 0x0029, 0x8080 },
0126     { 0x002a, 0xaaaa },
0127     { 0x002b, 0xaaaa },
0128     { 0x002c, 0xaba8 },
0129     { 0x002d, 0x0000 },
0130     { 0x002e, 0x0000 },
0131     { 0x002f, 0x0000 },
0132     { 0x0030, 0x0000 },
0133     { 0x0031, 0x5000 },
0134     { 0x0032, 0x0000 },
0135     { 0x0033, 0x0000 },
0136     { 0x0034, 0x0000 },
0137     { 0x0035, 0x0000 },
0138     { 0x003a, 0x0000 },
0139     { 0x003b, 0x0000 },
0140     { 0x003c, 0x00ff },
0141     { 0x003d, 0x0000 },
0142     { 0x003e, 0x00ff },
0143     { 0x003f, 0x0000 },
0144     { 0x0040, 0x0000 },
0145     { 0x0041, 0x00ff },
0146     { 0x0042, 0x0000 },
0147     { 0x0043, 0x00ff },
0148     { 0x0044, 0x0c0c },
0149     { 0x0049, 0xc00b },
0150     { 0x004a, 0x0000 },
0151     { 0x004b, 0x031f },
0152     { 0x004d, 0x0000 },
0153     { 0x004e, 0x001f },
0154     { 0x004f, 0x0000 },
0155     { 0x0050, 0x001f },
0156     { 0x0052, 0xf000 },
0157     { 0x0061, 0x0000 },
0158     { 0x0062, 0x0000 },
0159     { 0x0063, 0x003e },
0160     { 0x0064, 0x0000 },
0161     { 0x0065, 0x0000 },
0162     { 0x0066, 0x003f },
0163     { 0x0067, 0x0000 },
0164     { 0x006b, 0x0000 },
0165     { 0x006d, 0xff00 },
0166     { 0x006e, 0x2808 },
0167     { 0x006f, 0x000a },
0168     { 0x0070, 0x8000 },
0169     { 0x0071, 0x8000 },
0170     { 0x0072, 0x8000 },
0171     { 0x0073, 0x7000 },
0172     { 0x0074, 0x7770 },
0173     { 0x0075, 0x0002 },
0174     { 0x0076, 0x0001 },
0175     { 0x0078, 0x00f0 },
0176     { 0x0079, 0x0000 },
0177     { 0x007a, 0x0000 },
0178     { 0x007b, 0x0000 },
0179     { 0x007c, 0x0000 },
0180     { 0x007d, 0x0123 },
0181     { 0x007e, 0x4500 },
0182     { 0x007f, 0x8003 },
0183     { 0x0080, 0x0000 },
0184     { 0x0081, 0x0000 },
0185     { 0x0082, 0x0000 },
0186     { 0x0083, 0x0000 },
0187     { 0x0084, 0x0000 },
0188     { 0x0085, 0x0000 },
0189     { 0x0086, 0x0008 },
0190     { 0x0087, 0x0000 },
0191     { 0x0088, 0x0000 },
0192     { 0x0089, 0x0000 },
0193     { 0x008a, 0x0000 },
0194     { 0x008b, 0x0000 },
0195     { 0x008c, 0x0003 },
0196     { 0x008e, 0x0060 },
0197     { 0x008f, 0x1000 },
0198     { 0x0091, 0x0c26 },
0199     { 0x0092, 0x0073 },
0200     { 0x0093, 0x0000 },
0201     { 0x0094, 0x0080 },
0202     { 0x0098, 0x0000 },
0203     { 0x0099, 0x0000 },
0204     { 0x009a, 0x0007 },
0205     { 0x009f, 0x0000 },
0206     { 0x00a0, 0x0000 },
0207     { 0x00a1, 0x0002 },
0208     { 0x00a2, 0x0001 },
0209     { 0x00a3, 0x0002 },
0210     { 0x00a4, 0x0001 },
0211     { 0x00ae, 0x2040 },
0212     { 0x00af, 0x0000 },
0213     { 0x00b6, 0x0000 },
0214     { 0x00b7, 0x0000 },
0215     { 0x00b8, 0x0000 },
0216     { 0x00b9, 0x0000 },
0217     { 0x00ba, 0x0002 },
0218     { 0x00bb, 0x0000 },
0219     { 0x00be, 0x0000 },
0220     { 0x00c0, 0x0000 },
0221     { 0x00c1, 0x0aaa },
0222     { 0x00c2, 0xaa80 },
0223     { 0x00c3, 0x0003 },
0224     { 0x00c4, 0x0000 },
0225     { 0x00d0, 0x0000 },
0226     { 0x00d1, 0x2244 },
0227     { 0x00d2, 0x0000 },
0228     { 0x00d3, 0x3300 },
0229     { 0x00d4, 0x2200 },
0230     { 0x00d9, 0x0809 },
0231     { 0x00da, 0x0000 },
0232     { 0x00db, 0x0008 },
0233     { 0x00dc, 0x00c0 },
0234     { 0x00dd, 0x6724 },
0235     { 0x00de, 0x3131 },
0236     { 0x00df, 0x0008 },
0237     { 0x00e0, 0x4000 },
0238     { 0x00e1, 0x3131 },
0239     { 0x00e2, 0x600c },
0240     { 0x00ea, 0xb320 },
0241     { 0x00eb, 0x0000 },
0242     { 0x00ec, 0xb300 },
0243     { 0x00ed, 0x0000 },
0244     { 0x00ee, 0xb320 },
0245     { 0x00ef, 0x0000 },
0246     { 0x00f0, 0x0201 },
0247     { 0x00f1, 0x0ddd },
0248     { 0x00f2, 0x0ddd },
0249     { 0x00f6, 0x0000 },
0250     { 0x00f7, 0x0000 },
0251     { 0x00f8, 0x0000 },
0252     { 0x00fa, 0x0000 },
0253     { 0x00fb, 0x0000 },
0254     { 0x00fc, 0x0000 },
0255     { 0x00fd, 0x0000 },
0256     { 0x00fe, 0x10ec },
0257     { 0x00ff, 0x6451 },
0258     { 0x0100, 0xaaaa },
0259     { 0x0101, 0x000a },
0260     { 0x010a, 0xaaaa },
0261     { 0x010b, 0xa0a0 },
0262     { 0x010c, 0xaeae },
0263     { 0x010d, 0xaaaa },
0264     { 0x010e, 0xaaaa },
0265     { 0x010f, 0xaaaa },
0266     { 0x0110, 0xe002 },
0267     { 0x0111, 0xa602 },
0268     { 0x0112, 0xaaaa },
0269     { 0x0113, 0x2000 },
0270     { 0x0117, 0x0f00 },
0271     { 0x0125, 0x0420 },
0272     { 0x0132, 0x0000 },
0273     { 0x0133, 0x0000 },
0274     { 0x0136, 0x5555 },
0275     { 0x0137, 0x5540 },
0276     { 0x0138, 0x3700 },
0277     { 0x0139, 0x79a1 },
0278     { 0x013a, 0x2020 },
0279     { 0x013b, 0x2020 },
0280     { 0x013c, 0x2005 },
0281     { 0x013f, 0x0000 },
0282     { 0x0145, 0x0002 },
0283     { 0x0146, 0x0000 },
0284     { 0x0147, 0x0000 },
0285     { 0x0148, 0x0000 },
0286     { 0x0160, 0x4ec0 },
0287     { 0x0161, 0x0080 },
0288     { 0x0162, 0x0200 },
0289     { 0x0163, 0x0800 },
0290     { 0x0164, 0x0000 },
0291     { 0x0165, 0x0000 },
0292     { 0x0166, 0x0000 },
0293     { 0x0167, 0x000f },
0294     { 0x0168, 0x000f },
0295     { 0x0170, 0x4e80 },
0296     { 0x0171, 0x0080 },
0297     { 0x0172, 0x0200 },
0298     { 0x0173, 0x0800 },
0299     { 0x0174, 0x00ff },
0300     { 0x0175, 0x0000 },
0301     { 0x0190, 0x4131 },
0302     { 0x0191, 0x4131 },
0303     { 0x0192, 0x4131 },
0304     { 0x0193, 0x4131 },
0305     { 0x0194, 0x0000 },
0306     { 0x0195, 0x0000 },
0307     { 0x0196, 0x0000 },
0308     { 0x0197, 0x0000 },
0309     { 0x0198, 0x0000 },
0310     { 0x0199, 0x0000 },
0311     { 0x01a0, 0x1e64 },
0312     { 0x01a1, 0x06a3 },
0313     { 0x01a2, 0x0000 },
0314     { 0x01a3, 0x0000 },
0315     { 0x01a4, 0x0000 },
0316     { 0x01a5, 0x0000 },
0317     { 0x01a6, 0x0000 },
0318     { 0x01a7, 0x0000 },
0319     { 0x01a8, 0x0000 },
0320     { 0x01a9, 0x0000 },
0321     { 0x01aa, 0x0000 },
0322     { 0x01ab, 0x0000 },
0323     { 0x01b5, 0x0000 },
0324     { 0x01b6, 0x01c3 },
0325     { 0x01b7, 0x02a0 },
0326     { 0x01b8, 0x03e9 },
0327     { 0x01b9, 0x1389 },
0328     { 0x01ba, 0xc351 },
0329     { 0x01bb, 0x0009 },
0330     { 0x01bc, 0x0018 },
0331     { 0x01bd, 0x002a },
0332     { 0x01be, 0x004c },
0333     { 0x01bf, 0x0097 },
0334     { 0x01c0, 0x433d },
0335     { 0x01c1, 0x0000 },
0336     { 0x01c2, 0x0000 },
0337     { 0x01c3, 0x0000 },
0338     { 0x01c4, 0x0000 },
0339     { 0x01c5, 0x0000 },
0340     { 0x01c6, 0x0000 },
0341     { 0x01c7, 0x0000 },
0342     { 0x01c8, 0x40af },
0343     { 0x01c9, 0x0702 },
0344     { 0x01ca, 0x0000 },
0345     { 0x01cb, 0x0000 },
0346     { 0x01cc, 0x5757 },
0347     { 0x01cd, 0x5757 },
0348     { 0x01ce, 0x5757 },
0349     { 0x01cf, 0x5757 },
0350     { 0x01d0, 0x5757 },
0351     { 0x01d1, 0x5757 },
0352     { 0x01d2, 0x5757 },
0353     { 0x01d3, 0x5757 },
0354     { 0x01d4, 0x5757 },
0355     { 0x01d5, 0x5757 },
0356     { 0x01d6, 0x003c },
0357     { 0x01da, 0x0000 },
0358     { 0x01db, 0x0000 },
0359     { 0x01dc, 0x0000 },
0360     { 0x01de, 0x7c00 },
0361     { 0x01df, 0x0320 },
0362     { 0x01e0, 0x06a1 },
0363     { 0x01e1, 0x0000 },
0364     { 0x01e2, 0x0000 },
0365     { 0x01e3, 0x0000 },
0366     { 0x01e4, 0x0000 },
0367     { 0x01e5, 0x0000 },
0368     { 0x01e6, 0x0001 },
0369     { 0x01e7, 0x0000 },
0370     { 0x01e8, 0x0000 },
0371     { 0x01ea, 0x0000 },
0372     { 0x01eb, 0x0000 },
0373     { 0x01ec, 0x0000 },
0374     { 0x01ed, 0x0000 },
0375     { 0x01ee, 0x0000 },
0376     { 0x01ef, 0x0000 },
0377     { 0x01f0, 0x0000 },
0378     { 0x01f1, 0x0000 },
0379     { 0x01f2, 0x0000 },
0380     { 0x01f3, 0x0000 },
0381     { 0x01f4, 0x0000 },
0382     { 0x0200, 0x0000 },
0383     { 0x0201, 0x0000 },
0384     { 0x0202, 0x0000 },
0385     { 0x0203, 0x0000 },
0386     { 0x0204, 0x0000 },
0387     { 0x0205, 0x0000 },
0388     { 0x0206, 0x0000 },
0389     { 0x0207, 0x0000 },
0390     { 0x0208, 0x0000 },
0391     { 0x0210, 0x60b1 },
0392     { 0x0211, 0xa000 },
0393     { 0x0212, 0x024c },
0394     { 0x0213, 0xf7ff },
0395     { 0x0214, 0x024c },
0396     { 0x0215, 0x0102 },
0397     { 0x0216, 0x00a3 },
0398     { 0x0217, 0x0048 },
0399     { 0x0218, 0x92c0 },
0400     { 0x0219, 0x0000 },
0401     { 0x021a, 0x00c8 },
0402     { 0x021b, 0x0020 },
0403     { 0x02fa, 0x0000 },
0404     { 0x02fb, 0x0000 },
0405     { 0x02fc, 0x0000 },
0406     { 0x02ff, 0x0110 },
0407     { 0x0300, 0x001f },
0408     { 0x0301, 0x032c },
0409     { 0x0302, 0x5f21 },
0410     { 0x0303, 0x4000 },
0411     { 0x0304, 0x4000 },
0412     { 0x0305, 0x06d5 },
0413     { 0x0306, 0x8000 },
0414     { 0x0307, 0x0700 },
0415     { 0x0310, 0x4560 },
0416     { 0x0311, 0xa4a8 },
0417     { 0x0312, 0x7418 },
0418     { 0x0313, 0x0000 },
0419     { 0x0314, 0x0006 },
0420     { 0x0315, 0xffff },
0421     { 0x0316, 0xc400 },
0422     { 0x0317, 0x0000 },
0423     { 0x0330, 0x00a6 },
0424     { 0x0331, 0x04c3 },
0425     { 0x0332, 0x27c8 },
0426     { 0x0333, 0xbf50 },
0427     { 0x0334, 0x0045 },
0428     { 0x0335, 0x0007 },
0429     { 0x0336, 0x7418 },
0430     { 0x0337, 0x0501 },
0431     { 0x0338, 0x0000 },
0432     { 0x0339, 0x0010 },
0433     { 0x033a, 0x1010 },
0434     { 0x03c0, 0x7e00 },
0435     { 0x03c1, 0x8000 },
0436     { 0x03c2, 0x8000 },
0437     { 0x03c3, 0x8000 },
0438     { 0x03c4, 0x8000 },
0439     { 0x03c5, 0x8000 },
0440     { 0x03c6, 0x8000 },
0441     { 0x03c7, 0x8000 },
0442     { 0x03c8, 0x8000 },
0443     { 0x03c9, 0x8000 },
0444     { 0x03ca, 0x8000 },
0445     { 0x03cb, 0x8000 },
0446     { 0x03cc, 0x8000 },
0447     { 0x03d0, 0x0000 },
0448     { 0x03d1, 0x0000 },
0449     { 0x03d2, 0x0000 },
0450     { 0x03d3, 0x0000 },
0451     { 0x03d4, 0x2000 },
0452     { 0x03d5, 0x2000 },
0453     { 0x03d6, 0x0000 },
0454     { 0x03d7, 0x0000 },
0455     { 0x03d8, 0x2000 },
0456     { 0x03d9, 0x2000 },
0457     { 0x03da, 0x2000 },
0458     { 0x03db, 0x2000 },
0459     { 0x03dc, 0x0000 },
0460     { 0x03dd, 0x0000 },
0461     { 0x03de, 0x0000 },
0462     { 0x03df, 0x2000 },
0463     { 0x03e0, 0x0000 },
0464     { 0x03e1, 0x0000 },
0465     { 0x03e2, 0x0000 },
0466     { 0x03e3, 0x0000 },
0467     { 0x03e4, 0x0000 },
0468     { 0x03e5, 0x0000 },
0469     { 0x03e6, 0x0000 },
0470     { 0x03e7, 0x0000 },
0471     { 0x03e8, 0x0000 },
0472     { 0x03e9, 0x0000 },
0473     { 0x03ea, 0x0000 },
0474     { 0x03eb, 0x0000 },
0475     { 0x03ec, 0x0000 },
0476     { 0x03ed, 0x0000 },
0477     { 0x03ee, 0x0000 },
0478     { 0x03ef, 0x0000 },
0479     { 0x03f0, 0x0800 },
0480     { 0x03f1, 0x0800 },
0481     { 0x03f2, 0x0800 },
0482     { 0x03f3, 0x0800 },
0483     { 0x03fe, 0x0000 },
0484     { 0x03ff, 0x0000 },
0485     { 0x07f0, 0x0000 },
0486     { 0x07fa, 0x0000 },
0487 };
0488 
0489 static const struct reg_default rt5663_reg[] = {
0490     { 0x0000, 0x0000 },
0491     { 0x0002, 0x0008 },
0492     { 0x0005, 0x1000 },
0493     { 0x0006, 0x1000 },
0494     { 0x000a, 0x0000 },
0495     { 0x0010, 0x000f },
0496     { 0x0015, 0x42f1 },
0497     { 0x0016, 0x0000 },
0498     { 0x0018, 0x000b },
0499     { 0x0019, 0xafaf },
0500     { 0x001c, 0x2f2f },
0501     { 0x001f, 0x0000 },
0502     { 0x0022, 0x5757 },
0503     { 0x0023, 0x0039 },
0504     { 0x0026, 0xc0c0 },
0505     { 0x0029, 0x8080 },
0506     { 0x002a, 0x8020 },
0507     { 0x002c, 0x000c },
0508     { 0x002d, 0x0000 },
0509     { 0x0040, 0x0808 },
0510     { 0x0061, 0x0000 },
0511     { 0x0062, 0x0000 },
0512     { 0x0063, 0x003e },
0513     { 0x0064, 0x0000 },
0514     { 0x0065, 0x0000 },
0515     { 0x0066, 0x0000 },
0516     { 0x006b, 0x0000 },
0517     { 0x006e, 0x0000 },
0518     { 0x006f, 0x0000 },
0519     { 0x0070, 0x8020 },
0520     { 0x0073, 0x1000 },
0521     { 0x0074, 0xe400 },
0522     { 0x0075, 0x0002 },
0523     { 0x0076, 0x0001 },
0524     { 0x0077, 0x00f0 },
0525     { 0x0078, 0x0000 },
0526     { 0x0079, 0x0000 },
0527     { 0x007a, 0x0123 },
0528     { 0x007b, 0x8003 },
0529     { 0x0080, 0x0000 },
0530     { 0x0081, 0x0000 },
0531     { 0x0082, 0x0000 },
0532     { 0x0083, 0x0000 },
0533     { 0x0084, 0x0000 },
0534     { 0x0086, 0x0028 },
0535     { 0x0087, 0x0000 },
0536     { 0x008a, 0x0000 },
0537     { 0x008b, 0x0000 },
0538     { 0x008c, 0x0003 },
0539     { 0x008e, 0x0008 },
0540     { 0x008f, 0x1000 },
0541     { 0x0090, 0x0646 },
0542     { 0x0091, 0x0e3e },
0543     { 0x0092, 0x1071 },
0544     { 0x0093, 0x0000 },
0545     { 0x0094, 0x0080 },
0546     { 0x0097, 0x0000 },
0547     { 0x0098, 0x0000 },
0548     { 0x009a, 0x0000 },
0549     { 0x009f, 0x0000 },
0550     { 0x00ae, 0x6000 },
0551     { 0x00af, 0x0000 },
0552     { 0x00b6, 0x0000 },
0553     { 0x00b7, 0x0000 },
0554     { 0x00b8, 0x0000 },
0555     { 0x00ba, 0x0000 },
0556     { 0x00bb, 0x0000 },
0557     { 0x00be, 0x0000 },
0558     { 0x00bf, 0x0000 },
0559     { 0x00c0, 0x0000 },
0560     { 0x00c1, 0x0000 },
0561     { 0x00c5, 0x0000 },
0562     { 0x00cb, 0xa02f },
0563     { 0x00cc, 0x0000 },
0564     { 0x00cd, 0x0e02 },
0565     { 0x00d9, 0x08f9 },
0566     { 0x00db, 0x0008 },
0567     { 0x00dc, 0x00c0 },
0568     { 0x00dd, 0x6729 },
0569     { 0x00de, 0x3131 },
0570     { 0x00df, 0x0008 },
0571     { 0x00e0, 0x4000 },
0572     { 0x00e1, 0x3131 },
0573     { 0x00e2, 0x0043 },
0574     { 0x00e4, 0x400b },
0575     { 0x00e5, 0x8031 },
0576     { 0x00e6, 0x3080 },
0577     { 0x00e7, 0x4100 },
0578     { 0x00e8, 0x1400 },
0579     { 0x00e9, 0xe00a },
0580     { 0x00ea, 0x0404 },
0581     { 0x00eb, 0x0404 },
0582     { 0x00ec, 0xb320 },
0583     { 0x00ed, 0x0000 },
0584     { 0x00f4, 0x0000 },
0585     { 0x00f6, 0x0000 },
0586     { 0x00f8, 0x0000 },
0587     { 0x00fa, 0x8000 },
0588     { 0x00fd, 0x0001 },
0589     { 0x00fe, 0x10ec },
0590     { 0x00ff, 0x6406 },
0591     { 0x0100, 0xa020 },
0592     { 0x0108, 0x4444 },
0593     { 0x0109, 0x4444 },
0594     { 0x010a, 0xaaaa },
0595     { 0x010b, 0x00a0 },
0596     { 0x010c, 0x8aaa },
0597     { 0x010d, 0xaaaa },
0598     { 0x010e, 0x2aaa },
0599     { 0x010f, 0x002a },
0600     { 0x0110, 0xa0a4 },
0601     { 0x0111, 0x4602 },
0602     { 0x0112, 0x0101 },
0603     { 0x0113, 0x2000 },
0604     { 0x0114, 0x0000 },
0605     { 0x0116, 0x0000 },
0606     { 0x0117, 0x0f28 },
0607     { 0x0118, 0x0006 },
0608     { 0x0125, 0x2424 },
0609     { 0x0126, 0x5550 },
0610     { 0x0127, 0x0400 },
0611     { 0x0128, 0x7711 },
0612     { 0x0132, 0x0004 },
0613     { 0x0137, 0x5441 },
0614     { 0x0139, 0x79a1 },
0615     { 0x013a, 0x30c0 },
0616     { 0x013b, 0x2000 },
0617     { 0x013c, 0x2005 },
0618     { 0x013d, 0x30c0 },
0619     { 0x013e, 0x0000 },
0620     { 0x0140, 0x3700 },
0621     { 0x0141, 0x1f00 },
0622     { 0x0144, 0x0000 },
0623     { 0x0145, 0x0002 },
0624     { 0x0146, 0x0000 },
0625     { 0x0160, 0x0e80 },
0626     { 0x0161, 0x0080 },
0627     { 0x0162, 0x0200 },
0628     { 0x0163, 0x0800 },
0629     { 0x0164, 0x0000 },
0630     { 0x0165, 0x0000 },
0631     { 0x0166, 0x0000 },
0632     { 0x0167, 0x1417 },
0633     { 0x0168, 0x0017 },
0634     { 0x0169, 0x0017 },
0635     { 0x0180, 0x2000 },
0636     { 0x0181, 0x0000 },
0637     { 0x0182, 0x0000 },
0638     { 0x0183, 0x2000 },
0639     { 0x0184, 0x0000 },
0640     { 0x0185, 0x0000 },
0641     { 0x01b0, 0x4b30 },
0642     { 0x01b1, 0x0000 },
0643     { 0x01b2, 0xd870 },
0644     { 0x01b3, 0x0000 },
0645     { 0x01b4, 0x0030 },
0646     { 0x01b5, 0x5757 },
0647     { 0x01b6, 0x5757 },
0648     { 0x01b7, 0x5757 },
0649     { 0x01b8, 0x5757 },
0650     { 0x01c0, 0x433d },
0651     { 0x01c1, 0x0540 },
0652     { 0x01c2, 0x0000 },
0653     { 0x01c3, 0x0000 },
0654     { 0x01c4, 0x0000 },
0655     { 0x01c5, 0x0009 },
0656     { 0x01c6, 0x0018 },
0657     { 0x01c7, 0x002a },
0658     { 0x01c8, 0x004c },
0659     { 0x01c9, 0x0097 },
0660     { 0x01ca, 0x01c3 },
0661     { 0x01cb, 0x03e9 },
0662     { 0x01cc, 0x1389 },
0663     { 0x01cd, 0xc351 },
0664     { 0x01ce, 0x0000 },
0665     { 0x01cf, 0x0000 },
0666     { 0x01d0, 0x0000 },
0667     { 0x01d1, 0x0000 },
0668     { 0x01d2, 0x0000 },
0669     { 0x01d3, 0x003c },
0670     { 0x01d4, 0x5757 },
0671     { 0x01d5, 0x5757 },
0672     { 0x01d6, 0x5757 },
0673     { 0x01d7, 0x5757 },
0674     { 0x01d8, 0x5757 },
0675     { 0x01d9, 0x5757 },
0676     { 0x01da, 0x0000 },
0677     { 0x01db, 0x0000 },
0678     { 0x01dd, 0x0009 },
0679     { 0x01de, 0x7f00 },
0680     { 0x01df, 0x00c8 },
0681     { 0x01e0, 0x0691 },
0682     { 0x01e1, 0x0000 },
0683     { 0x01e2, 0x0000 },
0684     { 0x01e3, 0x0000 },
0685     { 0x01e4, 0x0000 },
0686     { 0x01e5, 0x0040 },
0687     { 0x01e6, 0x0000 },
0688     { 0x01e7, 0x0000 },
0689     { 0x01e8, 0x0000 },
0690     { 0x01ea, 0x0000 },
0691     { 0x01eb, 0x0000 },
0692     { 0x01ec, 0x0000 },
0693     { 0x01ed, 0x0000 },
0694     { 0x01ee, 0x0000 },
0695     { 0x01ef, 0x0000 },
0696     { 0x01f0, 0x0000 },
0697     { 0x01f1, 0x0000 },
0698     { 0x01f2, 0x0000 },
0699     { 0x0200, 0x0000 },
0700     { 0x0201, 0x2244 },
0701     { 0x0202, 0xaaaa },
0702     { 0x0250, 0x8010 },
0703     { 0x0251, 0x0000 },
0704     { 0x0252, 0x028a },
0705     { 0x02fa, 0x0000 },
0706     { 0x02fb, 0x8089 },
0707     { 0x02fc, 0x0300 },
0708     { 0x0300, 0x0000 },
0709     { 0x03d0, 0x0000 },
0710     { 0x03d1, 0x0000 },
0711     { 0x03d2, 0x0000 },
0712     { 0x03d3, 0x0000 },
0713     { 0x03d4, 0x2000 },
0714     { 0x03d5, 0x2000 },
0715     { 0x03d6, 0x0000 },
0716     { 0x03d7, 0x0000 },
0717     { 0x03d8, 0x2000 },
0718     { 0x03d9, 0x2000 },
0719     { 0x03da, 0x2000 },
0720     { 0x03db, 0x2000 },
0721     { 0x03dc, 0x0000 },
0722     { 0x03dd, 0x0000 },
0723     { 0x03de, 0x0000 },
0724     { 0x03df, 0x2000 },
0725     { 0x03e0, 0x0000 },
0726     { 0x03e1, 0x0000 },
0727     { 0x03e2, 0x0000 },
0728     { 0x03e3, 0x0000 },
0729     { 0x03e4, 0x0000 },
0730     { 0x03e5, 0x0000 },
0731     { 0x03e6, 0x0000 },
0732     { 0x03e7, 0x0000 },
0733     { 0x03e8, 0x0000 },
0734     { 0x03e9, 0x0000 },
0735     { 0x03ea, 0x0000 },
0736     { 0x03eb, 0x0000 },
0737     { 0x03ec, 0x0000 },
0738     { 0x03ed, 0x0000 },
0739     { 0x03ee, 0x0000 },
0740     { 0x03ef, 0x0000 },
0741     { 0x03f0, 0x0800 },
0742     { 0x03f1, 0x0800 },
0743     { 0x03f2, 0x0800 },
0744     { 0x03f3, 0x0800 },
0745 };
0746 
0747 static bool rt5663_volatile_register(struct device *dev, unsigned int reg)
0748 {
0749     switch (reg) {
0750     case RT5663_RESET:
0751     case RT5663_SIL_DET_CTL:
0752     case RT5663_HP_IMP_GAIN_2:
0753     case RT5663_AD_DA_MIXER:
0754     case RT5663_FRAC_DIV_2:
0755     case RT5663_MICBIAS_1:
0756     case RT5663_ASRC_11_2:
0757     case RT5663_ADC_EQ_1:
0758     case RT5663_INT_ST_1:
0759     case RT5663_INT_ST_2:
0760     case RT5663_GPIO_STA1:
0761     case RT5663_SIN_GEN_1:
0762     case RT5663_IL_CMD_1:
0763     case RT5663_IL_CMD_5:
0764     case RT5663_IL_CMD_PWRSAV1:
0765     case RT5663_EM_JACK_TYPE_1:
0766     case RT5663_EM_JACK_TYPE_2:
0767     case RT5663_EM_JACK_TYPE_3:
0768     case RT5663_JD_CTRL2:
0769     case RT5663_VENDOR_ID:
0770     case RT5663_VENDOR_ID_1:
0771     case RT5663_VENDOR_ID_2:
0772     case RT5663_PLL_INT_REG:
0773     case RT5663_SOFT_RAMP:
0774     case RT5663_STO_DRE_1:
0775     case RT5663_STO_DRE_5:
0776     case RT5663_STO_DRE_6:
0777     case RT5663_STO_DRE_7:
0778     case RT5663_MIC_DECRO_1:
0779     case RT5663_MIC_DECRO_4:
0780     case RT5663_HP_IMP_SEN_1:
0781     case RT5663_HP_IMP_SEN_3:
0782     case RT5663_HP_IMP_SEN_4:
0783     case RT5663_HP_IMP_SEN_5:
0784     case RT5663_HP_CALIB_1_1:
0785     case RT5663_HP_CALIB_9:
0786     case RT5663_HP_CALIB_ST1:
0787     case RT5663_HP_CALIB_ST2:
0788     case RT5663_HP_CALIB_ST3:
0789     case RT5663_HP_CALIB_ST4:
0790     case RT5663_HP_CALIB_ST5:
0791     case RT5663_HP_CALIB_ST6:
0792     case RT5663_HP_CALIB_ST7:
0793     case RT5663_HP_CALIB_ST8:
0794     case RT5663_HP_CALIB_ST9:
0795     case RT5663_ANA_JD:
0796         return true;
0797     default:
0798         return false;
0799     }
0800 }
0801 
0802 static bool rt5663_readable_register(struct device *dev, unsigned int reg)
0803 {
0804     switch (reg) {
0805     case RT5663_RESET:
0806     case RT5663_HP_OUT_EN:
0807     case RT5663_HP_LCH_DRE:
0808     case RT5663_HP_RCH_DRE:
0809     case RT5663_CALIB_BST:
0810     case RT5663_RECMIX:
0811     case RT5663_SIL_DET_CTL:
0812     case RT5663_PWR_SAV_SILDET:
0813     case RT5663_SIDETONE_CTL:
0814     case RT5663_STO1_DAC_DIG_VOL:
0815     case RT5663_STO1_ADC_DIG_VOL:
0816     case RT5663_STO1_BOOST:
0817     case RT5663_HP_IMP_GAIN_1:
0818     case RT5663_HP_IMP_GAIN_2:
0819     case RT5663_STO1_ADC_MIXER:
0820     case RT5663_AD_DA_MIXER:
0821     case RT5663_STO_DAC_MIXER:
0822     case RT5663_DIG_SIDE_MIXER:
0823     case RT5663_BYPASS_STO_DAC:
0824     case RT5663_CALIB_REC_MIX:
0825     case RT5663_PWR_DIG_1:
0826     case RT5663_PWR_DIG_2:
0827     case RT5663_PWR_ANLG_1:
0828     case RT5663_PWR_ANLG_2:
0829     case RT5663_PWR_ANLG_3:
0830     case RT5663_PWR_MIXER:
0831     case RT5663_SIG_CLK_DET:
0832     case RT5663_PRE_DIV_GATING_1:
0833     case RT5663_PRE_DIV_GATING_2:
0834     case RT5663_I2S1_SDP:
0835     case RT5663_ADDA_CLK_1:
0836     case RT5663_ADDA_RST:
0837     case RT5663_FRAC_DIV_1:
0838     case RT5663_FRAC_DIV_2:
0839     case RT5663_TDM_1:
0840     case RT5663_TDM_2:
0841     case RT5663_TDM_3:
0842     case RT5663_TDM_4:
0843     case RT5663_TDM_5:
0844     case RT5663_GLB_CLK:
0845     case RT5663_PLL_1:
0846     case RT5663_PLL_2:
0847     case RT5663_ASRC_1:
0848     case RT5663_ASRC_2:
0849     case RT5663_ASRC_4:
0850     case RT5663_DUMMY_REG:
0851     case RT5663_ASRC_8:
0852     case RT5663_ASRC_9:
0853     case RT5663_ASRC_11:
0854     case RT5663_DEPOP_1:
0855     case RT5663_DEPOP_2:
0856     case RT5663_DEPOP_3:
0857     case RT5663_HP_CHARGE_PUMP_1:
0858     case RT5663_HP_CHARGE_PUMP_2:
0859     case RT5663_MICBIAS_1:
0860     case RT5663_RC_CLK:
0861     case RT5663_ASRC_11_2:
0862     case RT5663_DUMMY_REG_2:
0863     case RT5663_REC_PATH_GAIN:
0864     case RT5663_AUTO_1MRC_CLK:
0865     case RT5663_ADC_EQ_1:
0866     case RT5663_ADC_EQ_2:
0867     case RT5663_IRQ_1:
0868     case RT5663_IRQ_2:
0869     case RT5663_IRQ_3:
0870     case RT5663_IRQ_4:
0871     case RT5663_IRQ_5:
0872     case RT5663_INT_ST_1:
0873     case RT5663_INT_ST_2:
0874     case RT5663_GPIO_1:
0875     case RT5663_GPIO_2:
0876     case RT5663_GPIO_STA1:
0877     case RT5663_SIN_GEN_1:
0878     case RT5663_SIN_GEN_2:
0879     case RT5663_SIN_GEN_3:
0880     case RT5663_SOF_VOL_ZC1:
0881     case RT5663_IL_CMD_1:
0882     case RT5663_IL_CMD_2:
0883     case RT5663_IL_CMD_3:
0884     case RT5663_IL_CMD_4:
0885     case RT5663_IL_CMD_5:
0886     case RT5663_IL_CMD_6:
0887     case RT5663_IL_CMD_7:
0888     case RT5663_IL_CMD_8:
0889     case RT5663_IL_CMD_PWRSAV1:
0890     case RT5663_IL_CMD_PWRSAV2:
0891     case RT5663_EM_JACK_TYPE_1:
0892     case RT5663_EM_JACK_TYPE_2:
0893     case RT5663_EM_JACK_TYPE_3:
0894     case RT5663_EM_JACK_TYPE_4:
0895     case RT5663_EM_JACK_TYPE_5:
0896     case RT5663_EM_JACK_TYPE_6:
0897     case RT5663_STO1_HPF_ADJ1:
0898     case RT5663_STO1_HPF_ADJ2:
0899     case RT5663_FAST_OFF_MICBIAS:
0900     case RT5663_JD_CTRL1:
0901     case RT5663_JD_CTRL2:
0902     case RT5663_DIG_MISC:
0903     case RT5663_VENDOR_ID:
0904     case RT5663_VENDOR_ID_1:
0905     case RT5663_VENDOR_ID_2:
0906     case RT5663_DIG_VOL_ZCD:
0907     case RT5663_ANA_BIAS_CUR_1:
0908     case RT5663_ANA_BIAS_CUR_2:
0909     case RT5663_ANA_BIAS_CUR_3:
0910     case RT5663_ANA_BIAS_CUR_4:
0911     case RT5663_ANA_BIAS_CUR_5:
0912     case RT5663_ANA_BIAS_CUR_6:
0913     case RT5663_BIAS_CUR_5:
0914     case RT5663_BIAS_CUR_6:
0915     case RT5663_BIAS_CUR_7:
0916     case RT5663_BIAS_CUR_8:
0917     case RT5663_DACREF_LDO:
0918     case RT5663_DUMMY_REG_3:
0919     case RT5663_BIAS_CUR_9:
0920     case RT5663_DUMMY_REG_4:
0921     case RT5663_VREFADJ_OP:
0922     case RT5663_VREF_RECMIX:
0923     case RT5663_CHARGE_PUMP_1:
0924     case RT5663_CHARGE_PUMP_1_2:
0925     case RT5663_CHARGE_PUMP_1_3:
0926     case RT5663_CHARGE_PUMP_2:
0927     case RT5663_DIG_IN_PIN1:
0928     case RT5663_PAD_DRV_CTL:
0929     case RT5663_PLL_INT_REG:
0930     case RT5663_CHOP_DAC_L:
0931     case RT5663_CHOP_ADC:
0932     case RT5663_CALIB_ADC:
0933     case RT5663_CHOP_DAC_R:
0934     case RT5663_DUMMY_CTL_DACLR:
0935     case RT5663_DUMMY_REG_5:
0936     case RT5663_SOFT_RAMP:
0937     case RT5663_TEST_MODE_1:
0938     case RT5663_TEST_MODE_2:
0939     case RT5663_TEST_MODE_3:
0940     case RT5663_STO_DRE_1:
0941     case RT5663_STO_DRE_2:
0942     case RT5663_STO_DRE_3:
0943     case RT5663_STO_DRE_4:
0944     case RT5663_STO_DRE_5:
0945     case RT5663_STO_DRE_6:
0946     case RT5663_STO_DRE_7:
0947     case RT5663_STO_DRE_8:
0948     case RT5663_STO_DRE_9:
0949     case RT5663_STO_DRE_10:
0950     case RT5663_MIC_DECRO_1:
0951     case RT5663_MIC_DECRO_2:
0952     case RT5663_MIC_DECRO_3:
0953     case RT5663_MIC_DECRO_4:
0954     case RT5663_MIC_DECRO_5:
0955     case RT5663_MIC_DECRO_6:
0956     case RT5663_HP_DECRO_1:
0957     case RT5663_HP_DECRO_2:
0958     case RT5663_HP_DECRO_3:
0959     case RT5663_HP_DECRO_4:
0960     case RT5663_HP_DECOUP:
0961     case RT5663_HP_IMP_SEN_MAP8:
0962     case RT5663_HP_IMP_SEN_MAP9:
0963     case RT5663_HP_IMP_SEN_MAP10:
0964     case RT5663_HP_IMP_SEN_MAP11:
0965     case RT5663_HP_IMP_SEN_1:
0966     case RT5663_HP_IMP_SEN_2:
0967     case RT5663_HP_IMP_SEN_3:
0968     case RT5663_HP_IMP_SEN_4:
0969     case RT5663_HP_IMP_SEN_5:
0970     case RT5663_HP_IMP_SEN_6:
0971     case RT5663_HP_IMP_SEN_7:
0972     case RT5663_HP_IMP_SEN_8:
0973     case RT5663_HP_IMP_SEN_9:
0974     case RT5663_HP_IMP_SEN_10:
0975     case RT5663_HP_IMP_SEN_11:
0976     case RT5663_HP_IMP_SEN_12:
0977     case RT5663_HP_IMP_SEN_13:
0978     case RT5663_HP_IMP_SEN_14:
0979     case RT5663_HP_IMP_SEN_15:
0980     case RT5663_HP_IMP_SEN_16:
0981     case RT5663_HP_IMP_SEN_17:
0982     case RT5663_HP_IMP_SEN_18:
0983     case RT5663_HP_IMP_SEN_19:
0984     case RT5663_HP_IMPSEN_DIG5:
0985     case RT5663_HP_IMPSEN_MAP1:
0986     case RT5663_HP_IMPSEN_MAP2:
0987     case RT5663_HP_IMPSEN_MAP3:
0988     case RT5663_HP_IMPSEN_MAP4:
0989     case RT5663_HP_IMPSEN_MAP5:
0990     case RT5663_HP_IMPSEN_MAP7:
0991     case RT5663_HP_LOGIC_1:
0992     case RT5663_HP_LOGIC_2:
0993     case RT5663_HP_CALIB_1:
0994     case RT5663_HP_CALIB_1_1:
0995     case RT5663_HP_CALIB_2:
0996     case RT5663_HP_CALIB_3:
0997     case RT5663_HP_CALIB_4:
0998     case RT5663_HP_CALIB_5:
0999     case RT5663_HP_CALIB_5_1:
1000     case RT5663_HP_CALIB_6:
1001     case RT5663_HP_CALIB_7:
1002     case RT5663_HP_CALIB_9:
1003     case RT5663_HP_CALIB_10:
1004     case RT5663_HP_CALIB_11:
1005     case RT5663_HP_CALIB_ST1:
1006     case RT5663_HP_CALIB_ST2:
1007     case RT5663_HP_CALIB_ST3:
1008     case RT5663_HP_CALIB_ST4:
1009     case RT5663_HP_CALIB_ST5:
1010     case RT5663_HP_CALIB_ST6:
1011     case RT5663_HP_CALIB_ST7:
1012     case RT5663_HP_CALIB_ST8:
1013     case RT5663_HP_CALIB_ST9:
1014     case RT5663_HP_AMP_DET:
1015     case RT5663_DUMMY_REG_6:
1016     case RT5663_HP_BIAS:
1017     case RT5663_CBJ_1:
1018     case RT5663_CBJ_2:
1019     case RT5663_CBJ_3:
1020     case RT5663_DUMMY_1:
1021     case RT5663_DUMMY_2:
1022     case RT5663_DUMMY_3:
1023     case RT5663_ANA_JD:
1024     case RT5663_ADC_LCH_LPF1_A1:
1025     case RT5663_ADC_RCH_LPF1_A1:
1026     case RT5663_ADC_LCH_LPF1_H0:
1027     case RT5663_ADC_RCH_LPF1_H0:
1028     case RT5663_ADC_LCH_BPF1_A1:
1029     case RT5663_ADC_RCH_BPF1_A1:
1030     case RT5663_ADC_LCH_BPF1_A2:
1031     case RT5663_ADC_RCH_BPF1_A2:
1032     case RT5663_ADC_LCH_BPF1_H0:
1033     case RT5663_ADC_RCH_BPF1_H0:
1034     case RT5663_ADC_LCH_BPF2_A1:
1035     case RT5663_ADC_RCH_BPF2_A1:
1036     case RT5663_ADC_LCH_BPF2_A2:
1037     case RT5663_ADC_RCH_BPF2_A2:
1038     case RT5663_ADC_LCH_BPF2_H0:
1039     case RT5663_ADC_RCH_BPF2_H0:
1040     case RT5663_ADC_LCH_BPF3_A1:
1041     case RT5663_ADC_RCH_BPF3_A1:
1042     case RT5663_ADC_LCH_BPF3_A2:
1043     case RT5663_ADC_RCH_BPF3_A2:
1044     case RT5663_ADC_LCH_BPF3_H0:
1045     case RT5663_ADC_RCH_BPF3_H0:
1046     case RT5663_ADC_LCH_BPF4_A1:
1047     case RT5663_ADC_RCH_BPF4_A1:
1048     case RT5663_ADC_LCH_BPF4_A2:
1049     case RT5663_ADC_RCH_BPF4_A2:
1050     case RT5663_ADC_LCH_BPF4_H0:
1051     case RT5663_ADC_RCH_BPF4_H0:
1052     case RT5663_ADC_LCH_HPF1_A1:
1053     case RT5663_ADC_RCH_HPF1_A1:
1054     case RT5663_ADC_LCH_HPF1_H0:
1055     case RT5663_ADC_RCH_HPF1_H0:
1056     case RT5663_ADC_EQ_PRE_VOL_L:
1057     case RT5663_ADC_EQ_PRE_VOL_R:
1058     case RT5663_ADC_EQ_POST_VOL_L:
1059     case RT5663_ADC_EQ_POST_VOL_R:
1060         return true;
1061     default:
1062         return false;
1063     }
1064 }
1065 
1066 static bool rt5663_v2_volatile_register(struct device *dev, unsigned int reg)
1067 {
1068     switch (reg) {
1069     case RT5663_RESET:
1070     case RT5663_CBJ_TYPE_2:
1071     case RT5663_PDM_OUT_CTL:
1072     case RT5663_PDM_I2C_DATA_CTL1:
1073     case RT5663_PDM_I2C_DATA_CTL4:
1074     case RT5663_ALC_BK_GAIN:
1075     case RT5663_PLL_2:
1076     case RT5663_MICBIAS_1:
1077     case RT5663_ADC_EQ_1:
1078     case RT5663_INT_ST_1:
1079     case RT5663_GPIO_STA2:
1080     case RT5663_IL_CMD_1:
1081     case RT5663_IL_CMD_5:
1082     case RT5663_A_JD_CTRL:
1083     case RT5663_JD_CTRL2:
1084     case RT5663_VENDOR_ID:
1085     case RT5663_VENDOR_ID_1:
1086     case RT5663_VENDOR_ID_2:
1087     case RT5663_STO_DRE_1:
1088     case RT5663_STO_DRE_5:
1089     case RT5663_STO_DRE_6:
1090     case RT5663_STO_DRE_7:
1091     case RT5663_MONO_DYNA_6:
1092     case RT5663_STO1_SIL_DET:
1093     case RT5663_MONOL_SIL_DET:
1094     case RT5663_MONOR_SIL_DET:
1095     case RT5663_STO2_DAC_SIL:
1096     case RT5663_MONO_AMP_CAL_ST1:
1097     case RT5663_MONO_AMP_CAL_ST2:
1098     case RT5663_MONO_AMP_CAL_ST3:
1099     case RT5663_MONO_AMP_CAL_ST4:
1100     case RT5663_HP_IMP_SEN_2:
1101     case RT5663_HP_IMP_SEN_3:
1102     case RT5663_HP_IMP_SEN_4:
1103     case RT5663_HP_IMP_SEN_10:
1104     case RT5663_HP_CALIB_1:
1105     case RT5663_HP_CALIB_10:
1106     case RT5663_HP_CALIB_ST1:
1107     case RT5663_HP_CALIB_ST4:
1108     case RT5663_HP_CALIB_ST5:
1109     case RT5663_HP_CALIB_ST6:
1110     case RT5663_HP_CALIB_ST7:
1111     case RT5663_HP_CALIB_ST8:
1112     case RT5663_HP_CALIB_ST9:
1113     case RT5663_HP_CALIB_ST10:
1114     case RT5663_HP_CALIB_ST11:
1115         return true;
1116     default:
1117         return false;
1118     }
1119 }
1120 
1121 static bool rt5663_v2_readable_register(struct device *dev, unsigned int reg)
1122 {
1123     switch (reg) {
1124     case RT5663_LOUT_CTRL:
1125     case RT5663_HP_AMP_2:
1126     case RT5663_MONO_OUT:
1127     case RT5663_MONO_GAIN:
1128     case RT5663_AEC_BST:
1129     case RT5663_IN1_IN2:
1130     case RT5663_IN3_IN4:
1131     case RT5663_INL1_INR1:
1132     case RT5663_CBJ_TYPE_2:
1133     case RT5663_CBJ_TYPE_3:
1134     case RT5663_CBJ_TYPE_4:
1135     case RT5663_CBJ_TYPE_5:
1136     case RT5663_CBJ_TYPE_8:
1137     case RT5663_DAC3_DIG_VOL:
1138     case RT5663_DAC3_CTRL:
1139     case RT5663_MONO_ADC_DIG_VOL:
1140     case RT5663_STO2_ADC_DIG_VOL:
1141     case RT5663_MONO_ADC_BST_GAIN:
1142     case RT5663_STO2_ADC_BST_GAIN:
1143     case RT5663_SIDETONE_CTRL:
1144     case RT5663_MONO1_ADC_MIXER:
1145     case RT5663_STO2_ADC_MIXER:
1146     case RT5663_MONO_DAC_MIXER:
1147     case RT5663_DAC2_SRC_CTRL:
1148     case RT5663_IF_3_4_DATA_CTL:
1149     case RT5663_IF_5_DATA_CTL:
1150     case RT5663_PDM_OUT_CTL:
1151     case RT5663_PDM_I2C_DATA_CTL1:
1152     case RT5663_PDM_I2C_DATA_CTL2:
1153     case RT5663_PDM_I2C_DATA_CTL3:
1154     case RT5663_PDM_I2C_DATA_CTL4:
1155     case RT5663_RECMIX1_NEW:
1156     case RT5663_RECMIX1L_0:
1157     case RT5663_RECMIX1L:
1158     case RT5663_RECMIX1R_0:
1159     case RT5663_RECMIX1R:
1160     case RT5663_RECMIX2_NEW:
1161     case RT5663_RECMIX2_L_2:
1162     case RT5663_RECMIX2_R:
1163     case RT5663_RECMIX2_R_2:
1164     case RT5663_CALIB_REC_LR:
1165     case RT5663_ALC_BK_GAIN:
1166     case RT5663_MONOMIX_GAIN:
1167     case RT5663_MONOMIX_IN_GAIN:
1168     case RT5663_OUT_MIXL_GAIN:
1169     case RT5663_OUT_LMIX_IN_GAIN:
1170     case RT5663_OUT_RMIX_IN_GAIN:
1171     case RT5663_OUT_RMIX_IN_GAIN1:
1172     case RT5663_LOUT_MIXER_CTRL:
1173     case RT5663_PWR_VOL:
1174     case RT5663_ADCDAC_RST:
1175     case RT5663_I2S34_SDP:
1176     case RT5663_I2S5_SDP:
1177     case RT5663_TDM_6:
1178     case RT5663_TDM_7:
1179     case RT5663_TDM_8:
1180     case RT5663_TDM_9:
1181     case RT5663_ASRC_3:
1182     case RT5663_ASRC_6:
1183     case RT5663_ASRC_7:
1184     case RT5663_PLL_TRK_13:
1185     case RT5663_I2S_M_CLK_CTL:
1186     case RT5663_FDIV_I2S34_M_CLK:
1187     case RT5663_FDIV_I2S34_M_CLK2:
1188     case RT5663_FDIV_I2S5_M_CLK:
1189     case RT5663_FDIV_I2S5_M_CLK2:
1190     case RT5663_V2_IRQ_4:
1191     case RT5663_GPIO_3:
1192     case RT5663_GPIO_4:
1193     case RT5663_GPIO_STA2:
1194     case RT5663_HP_AMP_DET1:
1195     case RT5663_HP_AMP_DET2:
1196     case RT5663_HP_AMP_DET3:
1197     case RT5663_MID_BD_HP_AMP:
1198     case RT5663_LOW_BD_HP_AMP:
1199     case RT5663_SOF_VOL_ZC2:
1200     case RT5663_ADC_STO2_ADJ1:
1201     case RT5663_ADC_STO2_ADJ2:
1202     case RT5663_A_JD_CTRL:
1203     case RT5663_JD1_TRES_CTRL:
1204     case RT5663_JD2_TRES_CTRL:
1205     case RT5663_V2_JD_CTRL2:
1206     case RT5663_DUM_REG_2:
1207     case RT5663_DUM_REG_3:
1208     case RT5663_VENDOR_ID:
1209     case RT5663_VENDOR_ID_1:
1210     case RT5663_VENDOR_ID_2:
1211     case RT5663_DACADC_DIG_VOL2:
1212     case RT5663_DIG_IN_PIN2:
1213     case RT5663_PAD_DRV_CTL1:
1214     case RT5663_SOF_RAM_DEPOP:
1215     case RT5663_VOL_TEST:
1216     case RT5663_TEST_MODE_4:
1217     case RT5663_TEST_MODE_5:
1218     case RT5663_STO_DRE_9:
1219     case RT5663_MONO_DYNA_1:
1220     case RT5663_MONO_DYNA_2:
1221     case RT5663_MONO_DYNA_3:
1222     case RT5663_MONO_DYNA_4:
1223     case RT5663_MONO_DYNA_5:
1224     case RT5663_MONO_DYNA_6:
1225     case RT5663_STO1_SIL_DET:
1226     case RT5663_MONOL_SIL_DET:
1227     case RT5663_MONOR_SIL_DET:
1228     case RT5663_STO2_DAC_SIL:
1229     case RT5663_PWR_SAV_CTL1:
1230     case RT5663_PWR_SAV_CTL2:
1231     case RT5663_PWR_SAV_CTL3:
1232     case RT5663_PWR_SAV_CTL4:
1233     case RT5663_PWR_SAV_CTL5:
1234     case RT5663_PWR_SAV_CTL6:
1235     case RT5663_MONO_AMP_CAL1:
1236     case RT5663_MONO_AMP_CAL2:
1237     case RT5663_MONO_AMP_CAL3:
1238     case RT5663_MONO_AMP_CAL4:
1239     case RT5663_MONO_AMP_CAL5:
1240     case RT5663_MONO_AMP_CAL6:
1241     case RT5663_MONO_AMP_CAL7:
1242     case RT5663_MONO_AMP_CAL_ST1:
1243     case RT5663_MONO_AMP_CAL_ST2:
1244     case RT5663_MONO_AMP_CAL_ST3:
1245     case RT5663_MONO_AMP_CAL_ST4:
1246     case RT5663_MONO_AMP_CAL_ST5:
1247     case RT5663_V2_HP_IMP_SEN_13:
1248     case RT5663_V2_HP_IMP_SEN_14:
1249     case RT5663_V2_HP_IMP_SEN_6:
1250     case RT5663_V2_HP_IMP_SEN_7:
1251     case RT5663_V2_HP_IMP_SEN_8:
1252     case RT5663_V2_HP_IMP_SEN_9:
1253     case RT5663_V2_HP_IMP_SEN_10:
1254     case RT5663_HP_LOGIC_3:
1255     case RT5663_HP_CALIB_ST10:
1256     case RT5663_HP_CALIB_ST11:
1257     case RT5663_PRO_REG_TBL_4:
1258     case RT5663_PRO_REG_TBL_5:
1259     case RT5663_PRO_REG_TBL_6:
1260     case RT5663_PRO_REG_TBL_7:
1261     case RT5663_PRO_REG_TBL_8:
1262     case RT5663_PRO_REG_TBL_9:
1263     case RT5663_SAR_ADC_INL_1:
1264     case RT5663_SAR_ADC_INL_2:
1265     case RT5663_SAR_ADC_INL_3:
1266     case RT5663_SAR_ADC_INL_4:
1267     case RT5663_SAR_ADC_INL_5:
1268     case RT5663_SAR_ADC_INL_6:
1269     case RT5663_SAR_ADC_INL_7:
1270     case RT5663_SAR_ADC_INL_8:
1271     case RT5663_SAR_ADC_INL_9:
1272     case RT5663_SAR_ADC_INL_10:
1273     case RT5663_SAR_ADC_INL_11:
1274     case RT5663_SAR_ADC_INL_12:
1275     case RT5663_DRC_CTRL_1:
1276     case RT5663_DRC1_CTRL_2:
1277     case RT5663_DRC1_CTRL_3:
1278     case RT5663_DRC1_CTRL_4:
1279     case RT5663_DRC1_CTRL_5:
1280     case RT5663_DRC1_CTRL_6:
1281     case RT5663_DRC1_HD_CTRL_1:
1282     case RT5663_DRC1_HD_CTRL_2:
1283     case RT5663_DRC1_PRI_REG_1:
1284     case RT5663_DRC1_PRI_REG_2:
1285     case RT5663_DRC1_PRI_REG_3:
1286     case RT5663_DRC1_PRI_REG_4:
1287     case RT5663_DRC1_PRI_REG_5:
1288     case RT5663_DRC1_PRI_REG_6:
1289     case RT5663_DRC1_PRI_REG_7:
1290     case RT5663_DRC1_PRI_REG_8:
1291     case RT5663_ALC_PGA_CTL_1:
1292     case RT5663_ALC_PGA_CTL_2:
1293     case RT5663_ALC_PGA_CTL_3:
1294     case RT5663_ALC_PGA_CTL_4:
1295     case RT5663_ALC_PGA_CTL_5:
1296     case RT5663_ALC_PGA_CTL_6:
1297     case RT5663_ALC_PGA_CTL_7:
1298     case RT5663_ALC_PGA_CTL_8:
1299     case RT5663_ALC_PGA_REG_1:
1300     case RT5663_ALC_PGA_REG_2:
1301     case RT5663_ALC_PGA_REG_3:
1302     case RT5663_ADC_EQ_RECOV_1:
1303     case RT5663_ADC_EQ_RECOV_2:
1304     case RT5663_ADC_EQ_RECOV_3:
1305     case RT5663_ADC_EQ_RECOV_4:
1306     case RT5663_ADC_EQ_RECOV_5:
1307     case RT5663_ADC_EQ_RECOV_6:
1308     case RT5663_ADC_EQ_RECOV_7:
1309     case RT5663_ADC_EQ_RECOV_8:
1310     case RT5663_ADC_EQ_RECOV_9:
1311     case RT5663_ADC_EQ_RECOV_10:
1312     case RT5663_ADC_EQ_RECOV_11:
1313     case RT5663_ADC_EQ_RECOV_12:
1314     case RT5663_ADC_EQ_RECOV_13:
1315     case RT5663_VID_HIDDEN:
1316     case RT5663_VID_CUSTOMER:
1317     case RT5663_SCAN_MODE:
1318     case RT5663_I2C_BYPA:
1319         return true;
1320     case RT5663_TDM_1:
1321     case RT5663_DEPOP_3:
1322     case RT5663_ASRC_11_2:
1323     case RT5663_INT_ST_2:
1324     case RT5663_GPIO_STA1:
1325     case RT5663_SIN_GEN_1:
1326     case RT5663_SIN_GEN_2:
1327     case RT5663_SIN_GEN_3:
1328     case RT5663_IL_CMD_PWRSAV1:
1329     case RT5663_IL_CMD_PWRSAV2:
1330     case RT5663_EM_JACK_TYPE_1:
1331     case RT5663_EM_JACK_TYPE_2:
1332     case RT5663_EM_JACK_TYPE_3:
1333     case RT5663_EM_JACK_TYPE_4:
1334     case RT5663_FAST_OFF_MICBIAS:
1335     case RT5663_ANA_BIAS_CUR_1:
1336     case RT5663_ANA_BIAS_CUR_2:
1337     case RT5663_BIAS_CUR_9:
1338     case RT5663_DUMMY_REG_4:
1339     case RT5663_VREF_RECMIX:
1340     case RT5663_CHARGE_PUMP_1_2:
1341     case RT5663_CHARGE_PUMP_1_3:
1342     case RT5663_CHARGE_PUMP_2:
1343     case RT5663_CHOP_DAC_R:
1344     case RT5663_DUMMY_CTL_DACLR:
1345     case RT5663_DUMMY_REG_5:
1346     case RT5663_SOFT_RAMP:
1347     case RT5663_TEST_MODE_1:
1348     case RT5663_STO_DRE_10:
1349     case RT5663_MIC_DECRO_1:
1350     case RT5663_MIC_DECRO_2:
1351     case RT5663_MIC_DECRO_3:
1352     case RT5663_MIC_DECRO_4:
1353     case RT5663_MIC_DECRO_5:
1354     case RT5663_MIC_DECRO_6:
1355     case RT5663_HP_DECRO_1:
1356     case RT5663_HP_DECRO_2:
1357     case RT5663_HP_DECRO_3:
1358     case RT5663_HP_DECRO_4:
1359     case RT5663_HP_DECOUP:
1360     case RT5663_HP_IMPSEN_MAP4:
1361     case RT5663_HP_IMPSEN_MAP5:
1362     case RT5663_HP_IMPSEN_MAP7:
1363     case RT5663_HP_CALIB_1:
1364     case RT5663_CBJ_1:
1365     case RT5663_CBJ_2:
1366     case RT5663_CBJ_3:
1367         return false;
1368     default:
1369         return rt5663_readable_register(dev, reg);
1370     }
1371 }
1372 
1373 static const DECLARE_TLV_DB_SCALE(rt5663_hp_vol_tlv, -2400, 150, 0);
1374 static const DECLARE_TLV_DB_SCALE(rt5663_v2_hp_vol_tlv, -2250, 150, 0);
1375 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
1376 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
1377 
1378 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
1379 static const DECLARE_TLV_DB_RANGE(in_bst_tlv,
1380     0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1381     1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
1382     2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
1383     3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
1384     6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
1385     7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
1386     8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
1387 );
1388 
1389 /* Interface data select */
1390 static const char * const rt5663_if1_adc_data_select[] = {
1391     "L/R", "R/L", "L/L", "R/R"
1392 };
1393 
1394 static SOC_ENUM_SINGLE_DECL(rt5663_if1_adc_enum, RT5663_TDM_2,
1395     RT5663_DATA_SWAP_ADCDAT1_SHIFT, rt5663_if1_adc_data_select);
1396 
1397 static void rt5663_enable_push_button_irq(struct snd_soc_component *component,
1398     bool enable)
1399 {
1400     struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1401 
1402     if (enable) {
1403         snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1404             RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_EN);
1405         /* reset in-line command */
1406         snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1407             RT5663_RESET_4BTN_INL_MASK,
1408             RT5663_RESET_4BTN_INL_RESET);
1409         snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1410             RT5663_RESET_4BTN_INL_MASK,
1411             RT5663_RESET_4BTN_INL_NOR);
1412         switch (rt5663->codec_ver) {
1413         case CODEC_VER_1:
1414             snd_soc_component_update_bits(component, RT5663_IRQ_3,
1415                 RT5663_V2_EN_IRQ_INLINE_MASK,
1416                 RT5663_V2_EN_IRQ_INLINE_NOR);
1417             break;
1418         case CODEC_VER_0:
1419             snd_soc_component_update_bits(component, RT5663_IRQ_2,
1420                 RT5663_EN_IRQ_INLINE_MASK,
1421                 RT5663_EN_IRQ_INLINE_NOR);
1422             break;
1423         default:
1424             dev_err(component->dev, "Unknown CODEC Version\n");
1425         }
1426     } else {
1427         switch (rt5663->codec_ver) {
1428         case CODEC_VER_1:
1429             snd_soc_component_update_bits(component, RT5663_IRQ_3,
1430                 RT5663_V2_EN_IRQ_INLINE_MASK,
1431                 RT5663_V2_EN_IRQ_INLINE_BYP);
1432             break;
1433         case CODEC_VER_0:
1434             snd_soc_component_update_bits(component, RT5663_IRQ_2,
1435                 RT5663_EN_IRQ_INLINE_MASK,
1436                 RT5663_EN_IRQ_INLINE_BYP);
1437             break;
1438         default:
1439             dev_err(component->dev, "Unknown CODEC Version\n");
1440         }
1441         snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1442             RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_DIS);
1443         /* reset in-line command */
1444         snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1445             RT5663_RESET_4BTN_INL_MASK,
1446             RT5663_RESET_4BTN_INL_RESET);
1447         snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1448             RT5663_RESET_4BTN_INL_MASK,
1449             RT5663_RESET_4BTN_INL_NOR);
1450     }
1451 }
1452 
1453 /**
1454  * rt5663_v2_jack_detect - Detect headset.
1455  * @component: SoC audio component device.
1456  * @jack_insert: Jack insert or not.
1457  *
1458  * Detect whether is headset or not when jack inserted.
1459  *
1460  * Returns detect status.
1461  */
1462 
1463 static int rt5663_v2_jack_detect(struct snd_soc_component *component, int jack_insert)
1464 {
1465     struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1466     struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1467     int val, i = 0, sleep_time[5] = {300, 150, 100, 50, 30};
1468 
1469     dev_dbg(component->dev, "%s jack_insert:%d\n", __func__, jack_insert);
1470     if (jack_insert) {
1471         snd_soc_component_write(component, RT5663_CBJ_TYPE_2, 0x8040);
1472         snd_soc_component_write(component, RT5663_CBJ_TYPE_3, 0x1484);
1473 
1474         snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
1475         snd_soc_dapm_force_enable_pin(dapm, "MICBIAS2");
1476         snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power");
1477         snd_soc_dapm_force_enable_pin(dapm, "CBJ Power");
1478         snd_soc_dapm_sync(dapm);
1479         snd_soc_component_update_bits(component, RT5663_RC_CLK,
1480             RT5663_DIG_1M_CLK_MASK, RT5663_DIG_1M_CLK_EN);
1481         snd_soc_component_update_bits(component, RT5663_RECMIX, 0x8, 0x8);
1482 
1483         while (i < 5) {
1484             msleep(sleep_time[i]);
1485             val = snd_soc_component_read(component, RT5663_CBJ_TYPE_2) & 0x0003;
1486             if (val == 0x1 || val == 0x2 || val == 0x3)
1487                 break;
1488             dev_dbg(component->dev, "%s: MX-0011 val=%x sleep %d\n",
1489                 __func__, val, sleep_time[i]);
1490             i++;
1491         }
1492         dev_dbg(component->dev, "%s val = %d\n", __func__, val);
1493         switch (val) {
1494         case 1:
1495         case 2:
1496             rt5663->jack_type = SND_JACK_HEADSET;
1497             rt5663_enable_push_button_irq(component, true);
1498             break;
1499         default:
1500             snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1501             snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
1502             snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1503             snd_soc_dapm_disable_pin(dapm, "CBJ Power");
1504             snd_soc_dapm_sync(dapm);
1505             rt5663->jack_type = SND_JACK_HEADPHONE;
1506             break;
1507         }
1508     } else {
1509         snd_soc_component_update_bits(component, RT5663_RECMIX, 0x8, 0x0);
1510 
1511         if (rt5663->jack_type == SND_JACK_HEADSET) {
1512             rt5663_enable_push_button_irq(component, false);
1513             snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1514             snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
1515             snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1516             snd_soc_dapm_disable_pin(dapm, "CBJ Power");
1517             snd_soc_dapm_sync(dapm);
1518         }
1519         rt5663->jack_type = 0;
1520     }
1521 
1522     dev_dbg(component->dev, "jack_type = %d\n", rt5663->jack_type);
1523     return rt5663->jack_type;
1524 }
1525 
1526 /**
1527  * rt5663_jack_detect - Detect headset.
1528  * @component: SoC audio component device.
1529  * @jack_insert: Jack insert or not.
1530  *
1531  * Detect whether is headset or not when jack inserted.
1532  *
1533  * Returns detect status.
1534  */
1535 static int rt5663_jack_detect(struct snd_soc_component *component, int jack_insert)
1536 {
1537     struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1538     int val, i = 0;
1539 
1540     dev_dbg(component->dev, "%s jack_insert:%d\n", __func__, jack_insert);
1541 
1542     if (jack_insert) {
1543         snd_soc_component_update_bits(component, RT5663_DIG_MISC,
1544             RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN);
1545         snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
1546             RT5663_SI_HP_MASK | RT5663_OSW_HP_L_MASK |
1547             RT5663_OSW_HP_R_MASK, RT5663_SI_HP_EN |
1548             RT5663_OSW_HP_L_DIS | RT5663_OSW_HP_R_DIS);
1549         snd_soc_component_update_bits(component, RT5663_DUMMY_1,
1550             RT5663_EMB_CLK_MASK | RT5663_HPA_CPL_BIAS_MASK |
1551             RT5663_HPA_CPR_BIAS_MASK, RT5663_EMB_CLK_EN |
1552             RT5663_HPA_CPL_BIAS_1 | RT5663_HPA_CPR_BIAS_1);
1553         snd_soc_component_update_bits(component, RT5663_CBJ_1,
1554             RT5663_INBUF_CBJ_BST1_MASK | RT5663_CBJ_SENSE_BST1_MASK,
1555             RT5663_INBUF_CBJ_BST1_ON | RT5663_CBJ_SENSE_BST1_L);
1556         snd_soc_component_update_bits(component, RT5663_IL_CMD_2,
1557             RT5663_PWR_MIC_DET_MASK, RT5663_PWR_MIC_DET_ON);
1558         /* BST1 power on for JD */
1559         snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
1560             RT5663_PWR_BST1_MASK, RT5663_PWR_BST1_ON);
1561         snd_soc_component_update_bits(component, RT5663_EM_JACK_TYPE_1,
1562             RT5663_CBJ_DET_MASK | RT5663_EXT_JD_MASK |
1563             RT5663_POL_EXT_JD_MASK, RT5663_CBJ_DET_EN |
1564             RT5663_EXT_JD_EN | RT5663_POL_EXT_JD_EN);
1565         snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1566             RT5663_PWR_MB_MASK | RT5663_LDO1_DVO_MASK |
1567             RT5663_AMP_HP_MASK, RT5663_PWR_MB |
1568             RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X);
1569         snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1570             RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
1571             RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
1572             RT5663_PWR_VREF1 | RT5663_PWR_VREF2);
1573         msleep(20);
1574         snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1575             RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
1576             RT5663_PWR_FV1 | RT5663_PWR_FV2);
1577         snd_soc_component_update_bits(component, RT5663_AUTO_1MRC_CLK,
1578             RT5663_IRQ_POW_SAV_MASK, RT5663_IRQ_POW_SAV_EN);
1579         snd_soc_component_update_bits(component, RT5663_IRQ_1,
1580             RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN);
1581         snd_soc_component_update_bits(component, RT5663_EM_JACK_TYPE_1,
1582             RT5663_EM_JD_MASK, RT5663_EM_JD_RST);
1583         snd_soc_component_update_bits(component, RT5663_EM_JACK_TYPE_1,
1584             RT5663_EM_JD_MASK, RT5663_EM_JD_NOR);
1585 
1586         while (true) {
1587             regmap_read(rt5663->regmap, RT5663_INT_ST_2, &val);
1588             if (!(val & 0x80))
1589                 usleep_range(10000, 10005);
1590             else
1591                 break;
1592 
1593             if (i > 200)
1594                 break;
1595             i++;
1596         }
1597 
1598         val = snd_soc_component_read(component, RT5663_EM_JACK_TYPE_2) & 0x0003;
1599         dev_dbg(component->dev, "%s val = %d\n", __func__, val);
1600 
1601         snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
1602             RT5663_OSW_HP_L_MASK | RT5663_OSW_HP_R_MASK,
1603             RT5663_OSW_HP_L_EN | RT5663_OSW_HP_R_EN);
1604 
1605         switch (val) {
1606         case 1:
1607         case 2:
1608             rt5663->jack_type = SND_JACK_HEADSET;
1609             rt5663_enable_push_button_irq(component, true);
1610 
1611             if (rt5663->pdata.impedance_sensing_num)
1612                 break;
1613 
1614             if (rt5663->pdata.dc_offset_l_manual_mic) {
1615                 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_2,
1616                     rt5663->pdata.dc_offset_l_manual_mic >>
1617                     16);
1618                 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_3,
1619                     rt5663->pdata.dc_offset_l_manual_mic &
1620                     0xffff);
1621             }
1622 
1623             if (rt5663->pdata.dc_offset_r_manual_mic) {
1624                 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_5,
1625                     rt5663->pdata.dc_offset_r_manual_mic >>
1626                     16);
1627                 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_6,
1628                     rt5663->pdata.dc_offset_r_manual_mic &
1629                     0xffff);
1630             }
1631             break;
1632         default:
1633             rt5663->jack_type = SND_JACK_HEADPHONE;
1634             snd_soc_component_update_bits(component,
1635                 RT5663_PWR_ANLG_1,
1636                 RT5663_PWR_MB_MASK | RT5663_PWR_VREF1_MASK |
1637                 RT5663_PWR_VREF2_MASK, 0);
1638             if (rt5663->pdata.impedance_sensing_num)
1639                 break;
1640 
1641             if (rt5663->pdata.dc_offset_l_manual) {
1642                 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_2,
1643                     rt5663->pdata.dc_offset_l_manual >> 16);
1644                 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_3,
1645                     rt5663->pdata.dc_offset_l_manual &
1646                     0xffff);
1647             }
1648 
1649             if (rt5663->pdata.dc_offset_r_manual) {
1650                 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_5,
1651                     rt5663->pdata.dc_offset_r_manual >> 16);
1652                 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_6,
1653                     rt5663->pdata.dc_offset_r_manual &
1654                     0xffff);
1655             }
1656             break;
1657         }
1658     } else {
1659         if (rt5663->jack_type == SND_JACK_HEADSET)
1660             rt5663_enable_push_button_irq(component, false);
1661         rt5663->jack_type = 0;
1662         snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1663             RT5663_PWR_MB_MASK | RT5663_PWR_VREF1_MASK |
1664             RT5663_PWR_VREF2_MASK, 0);
1665     }
1666 
1667     dev_dbg(component->dev, "jack_type = %d\n", rt5663->jack_type);
1668     return rt5663->jack_type;
1669 }
1670 
1671 static int rt5663_impedance_sensing(struct snd_soc_component *component)
1672 {
1673     struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1674     unsigned int value, i, reg84, reg26, reg2fa, reg91, reg10, reg80;
1675 
1676     for (i = 0; i < rt5663->pdata.impedance_sensing_num; i++) {
1677         if (rt5663->imp_table[i].vol == 7)
1678             break;
1679     }
1680 
1681     if (rt5663->jack_type == SND_JACK_HEADSET) {
1682         snd_soc_component_write(component, RT5663_MIC_DECRO_2,
1683             rt5663->imp_table[i].dc_offset_l_manual_mic >> 16);
1684         snd_soc_component_write(component, RT5663_MIC_DECRO_3,
1685             rt5663->imp_table[i].dc_offset_l_manual_mic & 0xffff);
1686         snd_soc_component_write(component, RT5663_MIC_DECRO_5,
1687             rt5663->imp_table[i].dc_offset_r_manual_mic >> 16);
1688         snd_soc_component_write(component, RT5663_MIC_DECRO_6,
1689             rt5663->imp_table[i].dc_offset_r_manual_mic & 0xffff);
1690     } else {
1691         snd_soc_component_write(component, RT5663_MIC_DECRO_2,
1692             rt5663->imp_table[i].dc_offset_l_manual >> 16);
1693         snd_soc_component_write(component, RT5663_MIC_DECRO_3,
1694             rt5663->imp_table[i].dc_offset_l_manual & 0xffff);
1695         snd_soc_component_write(component, RT5663_MIC_DECRO_5,
1696             rt5663->imp_table[i].dc_offset_r_manual >> 16);
1697         snd_soc_component_write(component, RT5663_MIC_DECRO_6,
1698             rt5663->imp_table[i].dc_offset_r_manual & 0xffff);
1699     }
1700 
1701     reg84 = snd_soc_component_read(component, RT5663_ASRC_2);
1702     reg26 = snd_soc_component_read(component, RT5663_STO1_ADC_MIXER);
1703     reg2fa = snd_soc_component_read(component, RT5663_DUMMY_1);
1704     reg91 = snd_soc_component_read(component, RT5663_HP_CHARGE_PUMP_1);
1705     reg10 = snd_soc_component_read(component, RT5663_RECMIX);
1706     reg80 = snd_soc_component_read(component, RT5663_GLB_CLK);
1707 
1708     snd_soc_component_update_bits(component, RT5663_STO_DRE_1, 0x8000, 0);
1709     snd_soc_component_write(component, RT5663_ASRC_2, 0);
1710     snd_soc_component_write(component, RT5663_STO1_ADC_MIXER, 0x4040);
1711     snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1712         RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
1713         RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
1714         RT5663_PWR_VREF1 | RT5663_PWR_VREF2);
1715     usleep_range(10000, 10005);
1716     snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1717         RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
1718         RT5663_PWR_FV1 | RT5663_PWR_FV2);
1719     snd_soc_component_update_bits(component, RT5663_GLB_CLK, RT5663_SCLK_SRC_MASK,
1720         RT5663_SCLK_SRC_RCCLK);
1721     snd_soc_component_update_bits(component, RT5663_RC_CLK, RT5663_DIG_25M_CLK_MASK,
1722         RT5663_DIG_25M_CLK_EN);
1723     snd_soc_component_update_bits(component, RT5663_ADDA_CLK_1, RT5663_I2S_PD1_MASK, 0);
1724     snd_soc_component_write(component, RT5663_PRE_DIV_GATING_1, 0xff00);
1725     snd_soc_component_write(component, RT5663_PRE_DIV_GATING_2, 0xfffc);
1726     snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_1, 0x1232);
1727     snd_soc_component_write(component, RT5663_HP_LOGIC_2, 0x0005);
1728     snd_soc_component_write(component, RT5663_DEPOP_2, 0x3003);
1729     snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030, 0x0030);
1730     snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003, 0x0003);
1731     snd_soc_component_update_bits(component, RT5663_PWR_DIG_2,
1732         RT5663_PWR_ADC_S1F | RT5663_PWR_DAC_S1F,
1733         RT5663_PWR_ADC_S1F | RT5663_PWR_DAC_S1F);
1734     snd_soc_component_update_bits(component, RT5663_PWR_DIG_1,
1735         RT5663_PWR_DAC_L1 | RT5663_PWR_DAC_R1 |
1736         RT5663_PWR_LDO_DACREF_MASK | RT5663_PWR_ADC_L1 |
1737         RT5663_PWR_ADC_R1,
1738         RT5663_PWR_DAC_L1 | RT5663_PWR_DAC_R1 |
1739         RT5663_PWR_LDO_DACREF_ON | RT5663_PWR_ADC_L1 |
1740         RT5663_PWR_ADC_R1);
1741     msleep(40);
1742     snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
1743         RT5663_PWR_RECMIX1 | RT5663_PWR_RECMIX2,
1744         RT5663_PWR_RECMIX1 | RT5663_PWR_RECMIX2);
1745     msleep(30);
1746     snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_2, 0x1371);
1747     snd_soc_component_write(component, RT5663_STO_DAC_MIXER, 0);
1748     snd_soc_component_write(component, RT5663_BYPASS_STO_DAC, 0x000c);
1749     snd_soc_component_write(component, RT5663_HP_BIAS, 0xafaa);
1750     snd_soc_component_write(component, RT5663_CHARGE_PUMP_1, 0x2224);
1751     snd_soc_component_write(component, RT5663_HP_OUT_EN, 0x8088);
1752     snd_soc_component_write(component, RT5663_CHOP_ADC, 0x3000);
1753     snd_soc_component_write(component, RT5663_ADDA_RST, 0xc000);
1754     snd_soc_component_write(component, RT5663_STO1_HPF_ADJ1, 0x3320);
1755     snd_soc_component_write(component, RT5663_HP_CALIB_2, 0x00c9);
1756     snd_soc_component_write(component, RT5663_DUMMY_1, 0x004c);
1757     snd_soc_component_write(component, RT5663_ANA_BIAS_CUR_1, 0x7733);
1758     snd_soc_component_write(component, RT5663_CHARGE_PUMP_2, 0x7777);
1759     snd_soc_component_write(component, RT5663_STO_DRE_9, 0x0007);
1760     snd_soc_component_write(component, RT5663_STO_DRE_10, 0x0007);
1761     snd_soc_component_write(component, RT5663_DUMMY_2, 0x02a4);
1762     snd_soc_component_write(component, RT5663_RECMIX, 0x0005);
1763     snd_soc_component_write(component, RT5663_HP_IMP_SEN_1, 0x4334);
1764     snd_soc_component_update_bits(component, RT5663_IRQ_3, 0x0004, 0x0004);
1765     snd_soc_component_write(component, RT5663_HP_LOGIC_1, 0x2200);
1766     snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000, 0x3000);
1767     snd_soc_component_write(component, RT5663_HP_LOGIC_1, 0x6200);
1768 
1769     for (i = 0; i < 100; i++) {
1770         msleep(20);
1771         if (snd_soc_component_read(component, RT5663_INT_ST_1) & 0x2)
1772             break;
1773     }
1774 
1775     value = snd_soc_component_read(component, RT5663_HP_IMP_SEN_4);
1776 
1777     snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000, 0);
1778     snd_soc_component_write(component, RT5663_INT_ST_1, 0);
1779     snd_soc_component_write(component, RT5663_HP_LOGIC_1, 0);
1780     snd_soc_component_update_bits(component, RT5663_RC_CLK, RT5663_DIG_25M_CLK_MASK,
1781         RT5663_DIG_25M_CLK_DIS);
1782     snd_soc_component_write(component, RT5663_GLB_CLK, reg80);
1783     snd_soc_component_write(component, RT5663_RECMIX, reg10);
1784     snd_soc_component_write(component, RT5663_DUMMY_2, 0x00a4);
1785     snd_soc_component_write(component, RT5663_DUMMY_1, reg2fa);
1786     snd_soc_component_write(component, RT5663_HP_CALIB_2, 0x00c8);
1787     snd_soc_component_write(component, RT5663_STO1_HPF_ADJ1, 0xb320);
1788     snd_soc_component_write(component, RT5663_ADDA_RST, 0xe400);
1789     snd_soc_component_write(component, RT5663_CHOP_ADC, 0x2000);
1790     snd_soc_component_write(component, RT5663_HP_OUT_EN, 0x0008);
1791     snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
1792         RT5663_PWR_RECMIX1 | RT5663_PWR_RECMIX2, 0);
1793     snd_soc_component_update_bits(component, RT5663_PWR_DIG_1,
1794         RT5663_PWR_DAC_L1 | RT5663_PWR_DAC_R1 |
1795         RT5663_PWR_LDO_DACREF_MASK | RT5663_PWR_ADC_L1 |
1796         RT5663_PWR_ADC_R1, 0);
1797     snd_soc_component_update_bits(component, RT5663_PWR_DIG_2,
1798         RT5663_PWR_ADC_S1F | RT5663_PWR_DAC_S1F, 0);
1799     snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003, 0);
1800     snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030, 0);
1801     snd_soc_component_write(component, RT5663_HP_LOGIC_2, 0);
1802     snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_1, reg91);
1803     snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1804         RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK, 0);
1805     snd_soc_component_write(component, RT5663_STO1_ADC_MIXER, reg26);
1806     snd_soc_component_write(component, RT5663_ASRC_2, reg84);
1807 
1808     for (i = 0; i < rt5663->pdata.impedance_sensing_num; i++) {
1809         if (value >= rt5663->imp_table[i].imp_min &&
1810             value <= rt5663->imp_table[i].imp_max)
1811             break;
1812     }
1813 
1814     snd_soc_component_update_bits(component, RT5663_STO_DRE_9, RT5663_DRE_GAIN_HP_MASK,
1815         rt5663->imp_table[i].vol);
1816     snd_soc_component_update_bits(component, RT5663_STO_DRE_10, RT5663_DRE_GAIN_HP_MASK,
1817         rt5663->imp_table[i].vol);
1818 
1819     if (rt5663->jack_type == SND_JACK_HEADSET) {
1820         snd_soc_component_write(component, RT5663_MIC_DECRO_2,
1821             rt5663->imp_table[i].dc_offset_l_manual_mic >> 16);
1822         snd_soc_component_write(component, RT5663_MIC_DECRO_3,
1823             rt5663->imp_table[i].dc_offset_l_manual_mic & 0xffff);
1824         snd_soc_component_write(component, RT5663_MIC_DECRO_5,
1825             rt5663->imp_table[i].dc_offset_r_manual_mic >> 16);
1826         snd_soc_component_write(component, RT5663_MIC_DECRO_6,
1827             rt5663->imp_table[i].dc_offset_r_manual_mic & 0xffff);
1828     } else {
1829         snd_soc_component_write(component, RT5663_MIC_DECRO_2,
1830             rt5663->imp_table[i].dc_offset_l_manual >> 16);
1831         snd_soc_component_write(component, RT5663_MIC_DECRO_3,
1832             rt5663->imp_table[i].dc_offset_l_manual & 0xffff);
1833         snd_soc_component_write(component, RT5663_MIC_DECRO_5,
1834             rt5663->imp_table[i].dc_offset_r_manual >> 16);
1835         snd_soc_component_write(component, RT5663_MIC_DECRO_6,
1836             rt5663->imp_table[i].dc_offset_r_manual & 0xffff);
1837     }
1838 
1839     return 0;
1840 }
1841 
1842 static int rt5663_button_detect(struct snd_soc_component *component)
1843 {
1844     int btn_type, val;
1845 
1846     val = snd_soc_component_read(component, RT5663_IL_CMD_5);
1847     dev_dbg(component->dev, "%s: val=0x%x\n", __func__, val);
1848     btn_type = val & 0xfff0;
1849     snd_soc_component_write(component, RT5663_IL_CMD_5, val);
1850 
1851     return btn_type;
1852 }
1853 
1854 static irqreturn_t rt5663_irq(int irq, void *data)
1855 {
1856     struct rt5663_priv *rt5663 = data;
1857 
1858     dev_dbg(regmap_get_device(rt5663->regmap), "%s IRQ queue work\n",
1859         __func__);
1860 
1861     queue_delayed_work(system_wq, &rt5663->jack_detect_work,
1862         msecs_to_jiffies(250));
1863 
1864     return IRQ_HANDLED;
1865 }
1866 
1867 static int rt5663_set_jack_detect(struct snd_soc_component *component,
1868     struct snd_soc_jack *hs_jack, void *data)
1869 {
1870     struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1871 
1872     rt5663->hs_jack = hs_jack;
1873 
1874     rt5663_irq(0, rt5663);
1875 
1876     return 0;
1877 }
1878 
1879 static bool rt5663_check_jd_status(struct snd_soc_component *component)
1880 {
1881     struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1882     int val = snd_soc_component_read(component, RT5663_INT_ST_1);
1883 
1884     dev_dbg(component->dev, "%s val=%x\n", __func__, val);
1885 
1886     /* JD1 */
1887     switch (rt5663->codec_ver) {
1888     case CODEC_VER_1:
1889         return !(val & 0x2000);
1890     case CODEC_VER_0:
1891         return !(val & 0x1000);
1892     default:
1893         dev_err(component->dev, "Unknown CODEC Version\n");
1894     }
1895 
1896     return false;
1897 }
1898 
1899 static void rt5663_jack_detect_work(struct work_struct *work)
1900 {
1901     struct rt5663_priv *rt5663 =
1902         container_of(work, struct rt5663_priv, jack_detect_work.work);
1903     struct snd_soc_component *component = rt5663->component;
1904     int btn_type, report = 0;
1905 
1906     if (!component)
1907         return;
1908 
1909     if (rt5663_check_jd_status(component)) {
1910         /* jack in */
1911         if (rt5663->jack_type == 0) {
1912             /* jack was out, report jack type */
1913             switch (rt5663->codec_ver) {
1914             case CODEC_VER_1:
1915                 report = rt5663_v2_jack_detect(
1916                         rt5663->component, 1);
1917                 break;
1918             case CODEC_VER_0:
1919                 report = rt5663_jack_detect(rt5663->component, 1);
1920                 if (rt5663->pdata.impedance_sensing_num)
1921                     rt5663_impedance_sensing(rt5663->component);
1922                 break;
1923             default:
1924                 dev_err(component->dev, "Unknown CODEC Version\n");
1925             }
1926 
1927             /* Delay the jack insert report to avoid pop noise */
1928             msleep(30);
1929         } else {
1930             /* jack is already in, report button event */
1931             report = SND_JACK_HEADSET;
1932             btn_type = rt5663_button_detect(rt5663->component);
1933             /**
1934              * rt5663 can report three kinds of button behavior,
1935              * one click, double click and hold. However,
1936              * currently we will report button pressed/released
1937              * event. So all the three button behaviors are
1938              * treated as button pressed.
1939              */
1940             switch (btn_type) {
1941             case 0x8000:
1942             case 0x4000:
1943             case 0x2000:
1944                 report |= SND_JACK_BTN_0;
1945                 break;
1946             case 0x1000:
1947             case 0x0800:
1948             case 0x0400:
1949                 report |= SND_JACK_BTN_1;
1950                 break;
1951             case 0x0200:
1952             case 0x0100:
1953             case 0x0080:
1954                 report |= SND_JACK_BTN_2;
1955                 break;
1956             case 0x0040:
1957             case 0x0020:
1958             case 0x0010:
1959                 report |= SND_JACK_BTN_3;
1960                 break;
1961             case 0x0000: /* unpressed */
1962                 break;
1963             default:
1964                 btn_type = 0;
1965                 dev_err(rt5663->component->dev,
1966                     "Unexpected button code 0x%04x\n",
1967                     btn_type);
1968                 break;
1969             }
1970             /* button release or spurious interrput*/
1971             if (btn_type == 0) {
1972                 report =  rt5663->jack_type;
1973                 cancel_delayed_work_sync(
1974                     &rt5663->jd_unplug_work);
1975             } else {
1976                 queue_delayed_work(system_wq,
1977                     &rt5663->jd_unplug_work,
1978                     msecs_to_jiffies(500));
1979             }
1980         }
1981     } else {
1982         /* jack out */
1983         switch (rt5663->codec_ver) {
1984         case CODEC_VER_1:
1985             report = rt5663_v2_jack_detect(rt5663->component, 0);
1986             break;
1987         case CODEC_VER_0:
1988             report = rt5663_jack_detect(rt5663->component, 0);
1989             break;
1990         default:
1991             dev_err(component->dev, "Unknown CODEC Version\n");
1992         }
1993     }
1994     dev_dbg(component->dev, "%s jack report: 0x%04x\n", __func__, report);
1995     snd_soc_jack_report(rt5663->hs_jack, report, SND_JACK_HEADSET |
1996                 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1997                 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1998 }
1999 
2000 static void rt5663_jd_unplug_work(struct work_struct *work)
2001 {
2002     struct rt5663_priv *rt5663 =
2003         container_of(work, struct rt5663_priv, jd_unplug_work.work);
2004     struct snd_soc_component *component = rt5663->component;
2005 
2006     if (!component)
2007         return;
2008 
2009     if (!rt5663_check_jd_status(component)) {
2010         /* jack out */
2011         switch (rt5663->codec_ver) {
2012         case CODEC_VER_1:
2013             rt5663_v2_jack_detect(rt5663->component, 0);
2014             break;
2015         case CODEC_VER_0:
2016             rt5663_jack_detect(rt5663->component, 0);
2017             break;
2018         default:
2019             dev_err(component->dev, "Unknown CODEC Version\n");
2020         }
2021 
2022         snd_soc_jack_report(rt5663->hs_jack, 0, SND_JACK_HEADSET |
2023                     SND_JACK_BTN_0 | SND_JACK_BTN_1 |
2024                     SND_JACK_BTN_2 | SND_JACK_BTN_3);
2025     } else {
2026         queue_delayed_work(system_wq, &rt5663->jd_unplug_work,
2027             msecs_to_jiffies(500));
2028     }
2029 }
2030 
2031 static const struct snd_kcontrol_new rt5663_snd_controls[] = {
2032     /* DAC Digital Volume */
2033     SOC_DOUBLE_TLV("DAC Playback Volume", RT5663_STO1_DAC_DIG_VOL,
2034         RT5663_DAC_L1_VOL_SHIFT + 1, RT5663_DAC_R1_VOL_SHIFT + 1,
2035         87, 0, dac_vol_tlv),
2036     /* ADC Digital Volume Control */
2037     SOC_DOUBLE("ADC Capture Switch", RT5663_STO1_ADC_DIG_VOL,
2038         RT5663_ADC_L_MUTE_SHIFT, RT5663_ADC_R_MUTE_SHIFT, 1, 1),
2039     SOC_DOUBLE_TLV("ADC Capture Volume", RT5663_STO1_ADC_DIG_VOL,
2040         RT5663_ADC_L_VOL_SHIFT + 1, RT5663_ADC_R_VOL_SHIFT + 1,
2041         63, 0, adc_vol_tlv),
2042 };
2043 
2044 static const struct snd_kcontrol_new rt5663_v2_specific_controls[] = {
2045     /* Headphone Output Volume */
2046     SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_HP_LCH_DRE,
2047         RT5663_HP_RCH_DRE, RT5663_GAIN_HP_SHIFT, 15, 1,
2048         rt5663_v2_hp_vol_tlv),
2049     /* Mic Boost Volume */
2050     SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_AEC_BST,
2051         RT5663_GAIN_CBJ_SHIFT, 8, 0, in_bst_tlv),
2052 };
2053 
2054 static const struct snd_kcontrol_new rt5663_specific_controls[] = {
2055     /* Mic Boost Volume*/
2056     SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_CBJ_2,
2057         RT5663_GAIN_BST1_SHIFT, 8, 0, in_bst_tlv),
2058     /* Data Swap for Slot0/1 in ADCDAT1 */
2059     SOC_ENUM("IF1 ADC Data Swap", rt5663_if1_adc_enum),
2060 };
2061 
2062 static const struct snd_kcontrol_new rt5663_hpvol_controls[] = {
2063     /* Headphone Output Volume */
2064     SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_STO_DRE_9,
2065         RT5663_STO_DRE_10, RT5663_DRE_GAIN_HP_SHIFT, 23, 1,
2066         rt5663_hp_vol_tlv),
2067 };
2068 
2069 static int rt5663_is_sys_clk_from_pll(struct snd_soc_dapm_widget *w,
2070     struct snd_soc_dapm_widget *sink)
2071 {
2072     unsigned int val;
2073     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2074 
2075     val = snd_soc_component_read(component, RT5663_GLB_CLK);
2076     val &= RT5663_SCLK_SRC_MASK;
2077     if (val == RT5663_SCLK_SRC_PLL1)
2078         return 1;
2079     else
2080         return 0;
2081 }
2082 
2083 static int rt5663_is_using_asrc(struct snd_soc_dapm_widget *w,
2084     struct snd_soc_dapm_widget *sink)
2085 {
2086     unsigned int reg, shift, val;
2087     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2088     struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2089 
2090     if (rt5663->codec_ver == CODEC_VER_1) {
2091         switch (w->shift) {
2092         case RT5663_ADC_STO1_ASRC_SHIFT:
2093             reg = RT5663_ASRC_3;
2094             shift = RT5663_V2_AD_STO1_TRACK_SHIFT;
2095             break;
2096         case RT5663_DAC_STO1_ASRC_SHIFT:
2097             reg = RT5663_ASRC_2;
2098             shift = RT5663_DA_STO1_TRACK_SHIFT;
2099             break;
2100         default:
2101             return 0;
2102         }
2103     } else {
2104         switch (w->shift) {
2105         case RT5663_ADC_STO1_ASRC_SHIFT:
2106             reg = RT5663_ASRC_2;
2107             shift = RT5663_AD_STO1_TRACK_SHIFT;
2108             break;
2109         case RT5663_DAC_STO1_ASRC_SHIFT:
2110             reg = RT5663_ASRC_2;
2111             shift = RT5663_DA_STO1_TRACK_SHIFT;
2112             break;
2113         default:
2114             return 0;
2115         }
2116     }
2117 
2118     val = (snd_soc_component_read(component, reg) >> shift) & 0x7;
2119 
2120     if (val)
2121         return 1;
2122 
2123     return 0;
2124 }
2125 
2126 static int rt5663_i2s_use_asrc(struct snd_soc_dapm_widget *source,
2127     struct snd_soc_dapm_widget *sink)
2128 {
2129     struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
2130     struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2131     int da_asrc_en, ad_asrc_en;
2132 
2133     da_asrc_en = (snd_soc_component_read(component, RT5663_ASRC_2) &
2134         RT5663_DA_STO1_TRACK_MASK) ? 1 : 0;
2135     switch (rt5663->codec_ver) {
2136     case CODEC_VER_1:
2137         ad_asrc_en = (snd_soc_component_read(component, RT5663_ASRC_3) &
2138             RT5663_V2_AD_STO1_TRACK_MASK) ? 1 : 0;
2139         break;
2140     case CODEC_VER_0:
2141         ad_asrc_en = (snd_soc_component_read(component, RT5663_ASRC_2) &
2142             RT5663_AD_STO1_TRACK_MASK) ? 1 : 0;
2143         break;
2144     default:
2145         dev_err(component->dev, "Unknown CODEC Version\n");
2146         return 1;
2147     }
2148 
2149     if (da_asrc_en || ad_asrc_en)
2150         if (rt5663->sysclk > rt5663->lrck * 384)
2151             return 1;
2152 
2153     dev_err(component->dev, "sysclk < 384 x fs, disable i2s asrc\n");
2154 
2155     return 0;
2156 }
2157 
2158 /**
2159  * rt5663_sel_asrc_clk_src - select ASRC clock source for a set of filters
2160  * @component: SoC audio component device.
2161  * @filter_mask: mask of filters.
2162  * @clk_src: clock source
2163  *
2164  * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5663 can
2165  * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
2166  * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
2167  * ASRC function will track i2s clock and generate a corresponding system clock
2168  * for codec. This function provides an API to select the clock source for a
2169  * set of filters specified by the mask. And the codec driver will turn on ASRC
2170  * for these filters if ASRC is selected as their clock source.
2171  */
2172 int rt5663_sel_asrc_clk_src(struct snd_soc_component *component,
2173         unsigned int filter_mask, unsigned int clk_src)
2174 {
2175     struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2176     unsigned int asrc2_mask = 0;
2177     unsigned int asrc2_value = 0;
2178     unsigned int asrc3_mask = 0;
2179     unsigned int asrc3_value = 0;
2180 
2181     switch (clk_src) {
2182     case RT5663_CLK_SEL_SYS:
2183     case RT5663_CLK_SEL_I2S1_ASRC:
2184         break;
2185 
2186     default:
2187         return -EINVAL;
2188     }
2189 
2190     if (filter_mask & RT5663_DA_STEREO_FILTER) {
2191         asrc2_mask |= RT5663_DA_STO1_TRACK_MASK;
2192         asrc2_value |= clk_src << RT5663_DA_STO1_TRACK_SHIFT;
2193     }
2194 
2195     if (filter_mask & RT5663_AD_STEREO_FILTER) {
2196         switch (rt5663->codec_ver) {
2197         case CODEC_VER_1:
2198             asrc3_mask |= RT5663_V2_AD_STO1_TRACK_MASK;
2199             asrc3_value |= clk_src << RT5663_V2_AD_STO1_TRACK_SHIFT;
2200             break;
2201         case CODEC_VER_0:
2202             asrc2_mask |= RT5663_AD_STO1_TRACK_MASK;
2203             asrc2_value |= clk_src << RT5663_AD_STO1_TRACK_SHIFT;
2204             break;
2205         default:
2206             dev_err(component->dev, "Unknown CODEC Version\n");
2207         }
2208     }
2209 
2210     if (asrc2_mask)
2211         snd_soc_component_update_bits(component, RT5663_ASRC_2, asrc2_mask,
2212             asrc2_value);
2213 
2214     if (asrc3_mask)
2215         snd_soc_component_update_bits(component, RT5663_ASRC_3, asrc3_mask,
2216             asrc3_value);
2217 
2218     return 0;
2219 }
2220 EXPORT_SYMBOL_GPL(rt5663_sel_asrc_clk_src);
2221 
2222 /* Analog Mixer */
2223 static const struct snd_kcontrol_new rt5663_recmix1l[] = {
2224     SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1L,
2225         RT5663_RECMIX1L_BST2_SHIFT, 1, 1),
2226     SOC_DAPM_SINGLE("BST1 CBJ Switch", RT5663_RECMIX1L,
2227         RT5663_RECMIX1L_BST1_CBJ_SHIFT, 1, 1),
2228 };
2229 
2230 static const struct snd_kcontrol_new rt5663_recmix1r[] = {
2231     SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1R,
2232         RT5663_RECMIX1R_BST2_SHIFT, 1, 1),
2233 };
2234 
2235 /* Digital Mixer */
2236 static const struct snd_kcontrol_new rt5663_sto1_adc_l_mix[] = {
2237     SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
2238             RT5663_M_STO1_ADC_L1_SHIFT, 1, 1),
2239     SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
2240             RT5663_M_STO1_ADC_L2_SHIFT, 1, 1),
2241 };
2242 
2243 static const struct snd_kcontrol_new rt5663_sto1_adc_r_mix[] = {
2244     SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
2245             RT5663_M_STO1_ADC_R1_SHIFT, 1, 1),
2246     SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
2247             RT5663_M_STO1_ADC_R2_SHIFT, 1, 1),
2248 };
2249 
2250 static const struct snd_kcontrol_new rt5663_adda_l_mix[] = {
2251     SOC_DAPM_SINGLE("ADC L Switch", RT5663_AD_DA_MIXER,
2252             RT5663_M_ADCMIX_L_SHIFT, 1, 1),
2253     SOC_DAPM_SINGLE("DAC L Switch", RT5663_AD_DA_MIXER,
2254             RT5663_M_DAC1_L_SHIFT, 1, 1),
2255 };
2256 
2257 static const struct snd_kcontrol_new rt5663_adda_r_mix[] = {
2258     SOC_DAPM_SINGLE("ADC R Switch", RT5663_AD_DA_MIXER,
2259             RT5663_M_ADCMIX_R_SHIFT, 1, 1),
2260     SOC_DAPM_SINGLE("DAC R Switch", RT5663_AD_DA_MIXER,
2261             RT5663_M_DAC1_R_SHIFT, 1, 1),
2262 };
2263 
2264 static const struct snd_kcontrol_new rt5663_sto1_dac_l_mix[] = {
2265     SOC_DAPM_SINGLE("DAC L Switch", RT5663_STO_DAC_MIXER,
2266             RT5663_M_DAC_L1_STO_L_SHIFT, 1, 1),
2267 };
2268 
2269 static const struct snd_kcontrol_new rt5663_sto1_dac_r_mix[] = {
2270     SOC_DAPM_SINGLE("DAC R Switch", RT5663_STO_DAC_MIXER,
2271             RT5663_M_DAC_R1_STO_R_SHIFT, 1, 1),
2272 };
2273 
2274 /* Out Switch */
2275 static const struct snd_kcontrol_new rt5663_hpo_switch =
2276     SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5663_HP_AMP_2,
2277         RT5663_EN_DAC_HPO_SHIFT, 1, 0);
2278 
2279 /* Stereo ADC source */
2280 static const char * const rt5663_sto1_adc_src[] = {
2281     "ADC L", "ADC R"
2282 };
2283 
2284 static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcl_enum, RT5663_STO1_ADC_MIXER,
2285     RT5663_STO1_ADC_L_SRC_SHIFT, rt5663_sto1_adc_src);
2286 
2287 static const struct snd_kcontrol_new rt5663_sto1_adcl_mux =
2288     SOC_DAPM_ENUM("STO1 ADC L Mux", rt5663_sto1_adcl_enum);
2289 
2290 static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcr_enum, RT5663_STO1_ADC_MIXER,
2291     RT5663_STO1_ADC_R_SRC_SHIFT, rt5663_sto1_adc_src);
2292 
2293 static const struct snd_kcontrol_new rt5663_sto1_adcr_mux =
2294     SOC_DAPM_ENUM("STO1 ADC R Mux", rt5663_sto1_adcr_enum);
2295 
2296 /* RT5663: Analog DACL1 input source */
2297 static const char * const rt5663_alg_dacl_src[] = {
2298     "DAC L", "STO DAC MIXL"
2299 };
2300 
2301 static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacl_enum, RT5663_BYPASS_STO_DAC,
2302     RT5663_DACL1_SRC_SHIFT, rt5663_alg_dacl_src);
2303 
2304 static const struct snd_kcontrol_new rt5663_alg_dacl_mux =
2305     SOC_DAPM_ENUM("DAC L Mux", rt5663_alg_dacl_enum);
2306 
2307 /* RT5663: Analog DACR1 input source */
2308 static const char * const rt5663_alg_dacr_src[] = {
2309     "DAC R", "STO DAC MIXR"
2310 };
2311 
2312 static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacr_enum, RT5663_BYPASS_STO_DAC,
2313     RT5663_DACR1_SRC_SHIFT, rt5663_alg_dacr_src);
2314 
2315 static const struct snd_kcontrol_new rt5663_alg_dacr_mux =
2316     SOC_DAPM_ENUM("DAC R Mux", rt5663_alg_dacr_enum);
2317 
2318 static int rt5663_hp_event(struct snd_soc_dapm_widget *w,
2319     struct snd_kcontrol *kcontrol, int event)
2320 {
2321     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2322     struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2323 
2324     switch (event) {
2325     case SND_SOC_DAPM_POST_PMU:
2326         if (rt5663->codec_ver == CODEC_VER_1) {
2327             snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
2328                 RT5663_SEL_PM_HP_SHIFT, RT5663_SEL_PM_HP_HIGH);
2329             snd_soc_component_update_bits(component, RT5663_HP_LOGIC_2,
2330                 RT5663_HP_SIG_SRC1_MASK,
2331                 RT5663_HP_SIG_SRC1_SILENCE);
2332         } else {
2333             snd_soc_component_update_bits(component,
2334                 RT5663_DACREF_LDO, 0x3e0e, 0x3a0a);
2335             snd_soc_component_write(component, RT5663_DEPOP_2, 0x3003);
2336             snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
2337                 RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_DIS);
2338             snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_2, 0x1371);
2339             snd_soc_component_write(component, RT5663_HP_BIAS, 0xabba);
2340             snd_soc_component_write(component, RT5663_CHARGE_PUMP_1, 0x2224);
2341             snd_soc_component_write(component, RT5663_ANA_BIAS_CUR_1, 0x7766);
2342             snd_soc_component_write(component, RT5663_HP_BIAS, 0xafaa);
2343             snd_soc_component_write(component, RT5663_CHARGE_PUMP_2, 0x7777);
2344             snd_soc_component_update_bits(component, RT5663_STO_DRE_1, 0x8000,
2345                 0x8000);
2346             snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000,
2347                 0x3000);
2348             snd_soc_component_update_bits(component,
2349                 RT5663_DIG_VOL_ZCD, 0x00c0, 0x0080);
2350         }
2351         break;
2352 
2353     case SND_SOC_DAPM_PRE_PMD:
2354         if (rt5663->codec_ver == CODEC_VER_1) {
2355             snd_soc_component_update_bits(component, RT5663_HP_LOGIC_2,
2356                 RT5663_HP_SIG_SRC1_MASK,
2357                 RT5663_HP_SIG_SRC1_REG);
2358         } else {
2359             snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000, 0x0);
2360             snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
2361                 RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_EN);
2362             snd_soc_component_update_bits(component,
2363                 RT5663_DACREF_LDO, 0x3e0e, 0);
2364             snd_soc_component_update_bits(component,
2365                 RT5663_DIG_VOL_ZCD, 0x00c0, 0);
2366         }
2367         break;
2368 
2369     default:
2370         return 0;
2371     }
2372 
2373     return 0;
2374 }
2375 
2376 static int rt5663_charge_pump_event(struct snd_soc_dapm_widget *w,
2377     struct snd_kcontrol *kcontrol, int event)
2378 {
2379     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2380     struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2381 
2382     switch (event) {
2383     case SND_SOC_DAPM_PRE_PMU:
2384         if (rt5663->codec_ver == CODEC_VER_0) {
2385             snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030,
2386                 0x0030);
2387             snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003,
2388                 0x0003);
2389         }
2390         break;
2391 
2392     case SND_SOC_DAPM_POST_PMD:
2393         if (rt5663->codec_ver == CODEC_VER_0) {
2394             snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003, 0);
2395             snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030, 0);
2396         }
2397         break;
2398 
2399     default:
2400         return 0;
2401     }
2402 
2403     return 0;
2404 }
2405 
2406 static int rt5663_bst2_power(struct snd_soc_dapm_widget *w,
2407     struct snd_kcontrol *kcontrol, int event)
2408 {
2409     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2410 
2411     switch (event) {
2412     case SND_SOC_DAPM_POST_PMU:
2413         snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
2414             RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK,
2415             RT5663_PWR_BST2 | RT5663_PWR_BST2_OP);
2416         break;
2417 
2418     case SND_SOC_DAPM_PRE_PMD:
2419         snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
2420             RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK, 0);
2421         break;
2422 
2423     default:
2424         return 0;
2425     }
2426 
2427     return 0;
2428 }
2429 
2430 static int rt5663_pre_div_power(struct snd_soc_dapm_widget *w,
2431     struct snd_kcontrol *kcontrol, int event)
2432 {
2433     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2434 
2435     switch (event) {
2436     case SND_SOC_DAPM_POST_PMU:
2437         snd_soc_component_write(component, RT5663_PRE_DIV_GATING_1, 0xff00);
2438         snd_soc_component_write(component, RT5663_PRE_DIV_GATING_2, 0xfffc);
2439         break;
2440 
2441     case SND_SOC_DAPM_PRE_PMD:
2442         snd_soc_component_write(component, RT5663_PRE_DIV_GATING_1, 0x0000);
2443         snd_soc_component_write(component, RT5663_PRE_DIV_GATING_2, 0x0000);
2444         break;
2445 
2446     default:
2447         return 0;
2448     }
2449 
2450     return 0;
2451 }
2452 
2453 static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
2454     SND_SOC_DAPM_SUPPLY("PLL", RT5663_PWR_ANLG_3, RT5663_PWR_PLL_SHIFT, 0,
2455         NULL, 0),
2456 
2457     /* micbias */
2458     SND_SOC_DAPM_MICBIAS("MICBIAS1", RT5663_PWR_ANLG_2,
2459         RT5663_PWR_MB1_SHIFT, 0),
2460     SND_SOC_DAPM_MICBIAS("MICBIAS2", RT5663_PWR_ANLG_2,
2461         RT5663_PWR_MB2_SHIFT, 0),
2462 
2463     /* Input Lines */
2464     SND_SOC_DAPM_INPUT("IN1P"),
2465     SND_SOC_DAPM_INPUT("IN1N"),
2466 
2467     /* REC Mixer Power */
2468     SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5663_PWR_ANLG_2,
2469         RT5663_PWR_RECMIX1_SHIFT, 0, NULL, 0),
2470 
2471     /* ADCs */
2472     SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
2473     SND_SOC_DAPM_SUPPLY("ADC L Power", RT5663_PWR_DIG_1,
2474         RT5663_PWR_ADC_L1_SHIFT, 0, NULL, 0),
2475     SND_SOC_DAPM_SUPPLY("ADC Clock", RT5663_CHOP_ADC,
2476         RT5663_CKGEN_ADCC_SHIFT, 0, NULL, 0),
2477 
2478     /* ADC Mixer */
2479     SND_SOC_DAPM_MIXER("STO1 ADC MIXL", SND_SOC_NOPM,
2480         0, 0, rt5663_sto1_adc_l_mix,
2481         ARRAY_SIZE(rt5663_sto1_adc_l_mix)),
2482 
2483     /* ADC Filter Power */
2484     SND_SOC_DAPM_SUPPLY("STO1 ADC Filter", RT5663_PWR_DIG_2,
2485         RT5663_PWR_ADC_S1F_SHIFT, 0, NULL, 0),
2486 
2487     /* Digital Interface */
2488     SND_SOC_DAPM_SUPPLY("I2S", RT5663_PWR_DIG_1, RT5663_PWR_I2S1_SHIFT, 0,
2489         NULL, 0),
2490     SND_SOC_DAPM_PGA("IF DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2491     SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2492     SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2493     SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2494     SND_SOC_DAPM_PGA("IF ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2495 
2496     /* Audio Interface */
2497     SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
2498     SND_SOC_DAPM_AIF_OUT("AIFTX", "AIF Capture", 0, SND_SOC_NOPM, 0, 0),
2499 
2500     /* DAC mixer before sound effect  */
2501     SND_SOC_DAPM_MIXER("ADDA MIXL", SND_SOC_NOPM, 0, 0, rt5663_adda_l_mix,
2502         ARRAY_SIZE(rt5663_adda_l_mix)),
2503     SND_SOC_DAPM_MIXER("ADDA MIXR", SND_SOC_NOPM, 0, 0, rt5663_adda_r_mix,
2504         ARRAY_SIZE(rt5663_adda_r_mix)),
2505     SND_SOC_DAPM_PGA("DAC L1", SND_SOC_NOPM, 0, 0, NULL, 0),
2506     SND_SOC_DAPM_PGA("DAC R1", SND_SOC_NOPM, 0, 0, NULL, 0),
2507 
2508     /* DAC Mixer */
2509     SND_SOC_DAPM_SUPPLY("STO1 DAC Filter", RT5663_PWR_DIG_2,
2510         RT5663_PWR_DAC_S1F_SHIFT, 0, NULL, 0),
2511     SND_SOC_DAPM_MIXER("STO1 DAC MIXL", SND_SOC_NOPM, 0, 0,
2512         rt5663_sto1_dac_l_mix, ARRAY_SIZE(rt5663_sto1_dac_l_mix)),
2513     SND_SOC_DAPM_MIXER("STO1 DAC MIXR", SND_SOC_NOPM, 0, 0,
2514         rt5663_sto1_dac_r_mix, ARRAY_SIZE(rt5663_sto1_dac_r_mix)),
2515 
2516     /* DACs */
2517     SND_SOC_DAPM_SUPPLY("STO1 DAC L Power", RT5663_PWR_DIG_1,
2518         RT5663_PWR_DAC_L1_SHIFT, 0, NULL, 0),
2519     SND_SOC_DAPM_SUPPLY("STO1 DAC R Power", RT5663_PWR_DIG_1,
2520         RT5663_PWR_DAC_R1_SHIFT, 0, NULL, 0),
2521     SND_SOC_DAPM_DAC("DAC L", NULL, SND_SOC_NOPM, 0, 0),
2522     SND_SOC_DAPM_DAC("DAC R", NULL, SND_SOC_NOPM, 0, 0),
2523 
2524     /* Headphone*/
2525     SND_SOC_DAPM_SUPPLY("HP Charge Pump", SND_SOC_NOPM, 0, 0,
2526         rt5663_charge_pump_event, SND_SOC_DAPM_PRE_PMU |
2527         SND_SOC_DAPM_POST_PMD),
2528     SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5663_hp_event,
2529         SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2530 
2531     /* Output Lines */
2532     SND_SOC_DAPM_OUTPUT("HPOL"),
2533     SND_SOC_DAPM_OUTPUT("HPOR"),
2534 };
2535 
2536 static const struct snd_soc_dapm_widget rt5663_v2_specific_dapm_widgets[] = {
2537     SND_SOC_DAPM_SUPPLY("LDO2", RT5663_PWR_ANLG_3,
2538         RT5663_PWR_LDO2_SHIFT, 0, NULL, 0),
2539     SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5663_PWR_VOL,
2540         RT5663_V2_PWR_MIC_DET_SHIFT, 0, NULL, 0),
2541     SND_SOC_DAPM_SUPPLY("LDO DAC", RT5663_PWR_DIG_1,
2542         RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
2543 
2544     /* ASRC */
2545     SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
2546         RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0),
2547     SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1,
2548         RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0),
2549     SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1,
2550         RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0),
2551 
2552     /* Input Lines */
2553     SND_SOC_DAPM_INPUT("IN2P"),
2554     SND_SOC_DAPM_INPUT("IN2N"),
2555 
2556     /* Boost */
2557     SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 0, 0, NULL, 0),
2558     SND_SOC_DAPM_SUPPLY("CBJ Power", RT5663_PWR_ANLG_3,
2559         RT5663_PWR_CBJ_SHIFT, 0, NULL, 0),
2560     SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM, 0, 0, NULL, 0),
2561     SND_SOC_DAPM_SUPPLY("BST2 Power", SND_SOC_NOPM, 0, 0,
2562         rt5663_bst2_power, SND_SOC_DAPM_PRE_PMD |
2563         SND_SOC_DAPM_POST_PMU),
2564 
2565     /* REC Mixer */
2566     SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5663_recmix1l,
2567         ARRAY_SIZE(rt5663_recmix1l)),
2568     SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5663_recmix1r,
2569         ARRAY_SIZE(rt5663_recmix1r)),
2570     SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5663_PWR_ANLG_2,
2571         RT5663_PWR_RECMIX2_SHIFT, 0, NULL, 0),
2572 
2573     /* ADC */
2574     SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
2575     SND_SOC_DAPM_SUPPLY("ADC R Power", RT5663_PWR_DIG_1,
2576         RT5663_PWR_ADC_R1_SHIFT, 0, NULL, 0),
2577 
2578     /* ADC Mux */
2579     SND_SOC_DAPM_PGA("STO1 ADC L1", RT5663_STO1_ADC_MIXER,
2580         RT5663_STO1_ADC_L1_SRC_SHIFT, 0, NULL, 0),
2581     SND_SOC_DAPM_PGA("STO1 ADC R1", RT5663_STO1_ADC_MIXER,
2582         RT5663_STO1_ADC_R1_SRC_SHIFT, 0, NULL, 0),
2583     SND_SOC_DAPM_PGA("STO1 ADC L2", RT5663_STO1_ADC_MIXER,
2584         RT5663_STO1_ADC_L2_SRC_SHIFT, 1, NULL, 0),
2585     SND_SOC_DAPM_PGA("STO1 ADC R2", RT5663_STO1_ADC_MIXER,
2586         RT5663_STO1_ADC_R2_SRC_SHIFT, 1, NULL, 0),
2587 
2588     SND_SOC_DAPM_MUX("STO1 ADC L Mux", SND_SOC_NOPM, 0, 0,
2589         &rt5663_sto1_adcl_mux),
2590     SND_SOC_DAPM_MUX("STO1 ADC R Mux", SND_SOC_NOPM, 0, 0,
2591         &rt5663_sto1_adcr_mux),
2592 
2593     /* ADC Mix */
2594     SND_SOC_DAPM_MIXER("STO1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2595         rt5663_sto1_adc_r_mix, ARRAY_SIZE(rt5663_sto1_adc_r_mix)),
2596 
2597     /* Analog DAC Clock */
2598     SND_SOC_DAPM_SUPPLY("DAC Clock", RT5663_CHOP_DAC_L,
2599         RT5663_CKGEN_DAC1_SHIFT, 0, NULL, 0),
2600 
2601     /* Headphone out */
2602     SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0,
2603         &rt5663_hpo_switch),
2604 };
2605 
2606 static const struct snd_soc_dapm_widget rt5663_specific_dapm_widgets[] = {
2607     /* System Clock Pre Divider Gating */
2608     SND_SOC_DAPM_SUPPLY("Pre Div Power", SND_SOC_NOPM, 0, 0,
2609         rt5663_pre_div_power, SND_SOC_DAPM_POST_PMU |
2610         SND_SOC_DAPM_PRE_PMD),
2611 
2612     /* LDO */
2613     SND_SOC_DAPM_SUPPLY("LDO ADC", RT5663_PWR_DIG_1,
2614         RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
2615 
2616     /* ASRC */
2617     SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
2618         RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0),
2619     SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1,
2620         RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0),
2621     SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1,
2622         RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0),
2623 
2624     /* Boost */
2625     SND_SOC_DAPM_PGA("BST1", SND_SOC_NOPM, 0, 0, NULL, 0),
2626 
2627     /* STO ADC */
2628     SND_SOC_DAPM_PGA("STO1 ADC L1", SND_SOC_NOPM, 0, 0, NULL, 0),
2629     SND_SOC_DAPM_PGA("STO1 ADC L2", SND_SOC_NOPM, 0, 0, NULL, 0),
2630 
2631     /* Analog DAC source */
2632     SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacl_mux),
2633     SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacr_mux),
2634 };
2635 
2636 static const struct snd_soc_dapm_route rt5663_dapm_routes[] = {
2637     /* PLL */
2638     { "I2S", NULL, "PLL", rt5663_is_sys_clk_from_pll },
2639 
2640     /* ASRC */
2641     { "STO1 ADC Filter", NULL, "ADC ASRC", rt5663_is_using_asrc },
2642     { "STO1 DAC Filter", NULL, "DAC ASRC", rt5663_is_using_asrc },
2643     { "I2S", NULL, "I2S ASRC", rt5663_i2s_use_asrc },
2644 
2645     { "ADC L", NULL, "ADC L Power" },
2646     { "ADC L", NULL, "ADC Clock" },
2647 
2648     { "STO1 ADC L2", NULL, "STO1 DAC MIXL" },
2649 
2650     { "STO1 ADC MIXL", "ADC1 Switch", "STO1 ADC L1" },
2651     { "STO1 ADC MIXL", "ADC2 Switch", "STO1 ADC L2" },
2652     { "STO1 ADC MIXL", NULL, "STO1 ADC Filter" },
2653 
2654     { "IF1 ADC1", NULL, "STO1 ADC MIXL" },
2655     { "IF ADC", NULL, "IF1 ADC1" },
2656     { "AIFTX", NULL, "IF ADC" },
2657     { "AIFTX", NULL, "I2S" },
2658 
2659     { "AIFRX", NULL, "I2S" },
2660     { "IF DAC", NULL, "AIFRX" },
2661     { "IF1 DAC1 L", NULL, "IF DAC" },
2662     { "IF1 DAC1 R", NULL, "IF DAC" },
2663 
2664     { "ADDA MIXL", "ADC L Switch", "STO1 ADC MIXL" },
2665     { "ADDA MIXL", "DAC L Switch", "IF1 DAC1 L" },
2666     { "ADDA MIXL", NULL, "STO1 DAC Filter" },
2667     { "ADDA MIXL", NULL, "STO1 DAC L Power" },
2668     { "ADDA MIXR", "DAC R Switch", "IF1 DAC1 R" },
2669     { "ADDA MIXR", NULL, "STO1 DAC Filter" },
2670     { "ADDA MIXR", NULL, "STO1 DAC R Power" },
2671 
2672     { "DAC L1", NULL, "ADDA MIXL" },
2673     { "DAC R1", NULL, "ADDA MIXR" },
2674 
2675     { "STO1 DAC MIXL", "DAC L Switch", "DAC L1" },
2676     { "STO1 DAC MIXL", NULL, "STO1 DAC L Power" },
2677     { "STO1 DAC MIXL", NULL, "STO1 DAC Filter" },
2678     { "STO1 DAC MIXR", "DAC R Switch", "DAC R1" },
2679     { "STO1 DAC MIXR", NULL, "STO1 DAC R Power" },
2680     { "STO1 DAC MIXR", NULL, "STO1 DAC Filter" },
2681 
2682     { "HP Amp", NULL, "HP Charge Pump" },
2683     { "HP Amp", NULL, "DAC L" },
2684     { "HP Amp", NULL, "DAC R" },
2685 };
2686 
2687 static const struct snd_soc_dapm_route rt5663_v2_specific_dapm_routes[] = {
2688     { "MICBIAS1", NULL, "LDO2" },
2689     { "MICBIAS2", NULL, "LDO2" },
2690 
2691     { "BST1 CBJ", NULL, "IN1P" },
2692     { "BST1 CBJ", NULL, "IN1N" },
2693     { "BST1 CBJ", NULL, "CBJ Power" },
2694 
2695     { "BST2", NULL, "IN2P" },
2696     { "BST2", NULL, "IN2N" },
2697     { "BST2", NULL, "BST2 Power" },
2698 
2699     { "RECMIX1L", "BST2 Switch", "BST2" },
2700     { "RECMIX1L", "BST1 CBJ Switch", "BST1 CBJ" },
2701     { "RECMIX1L", NULL, "RECMIX1L Power" },
2702     { "RECMIX1R", "BST2 Switch", "BST2" },
2703     { "RECMIX1R", NULL, "RECMIX1R Power" },
2704 
2705     { "ADC L", NULL, "RECMIX1L" },
2706     { "ADC R", NULL, "RECMIX1R" },
2707     { "ADC R", NULL, "ADC R Power" },
2708     { "ADC R", NULL, "ADC Clock" },
2709 
2710     { "STO1 ADC L Mux", "ADC L", "ADC L" },
2711     { "STO1 ADC L Mux", "ADC R", "ADC R" },
2712     { "STO1 ADC L1", NULL, "STO1 ADC L Mux" },
2713 
2714     { "STO1 ADC R Mux", "ADC L", "ADC L" },
2715     { "STO1 ADC R Mux", "ADC R", "ADC R" },
2716     { "STO1 ADC R1", NULL, "STO1 ADC R Mux" },
2717     { "STO1 ADC R2", NULL, "STO1 DAC MIXR" },
2718 
2719     { "STO1 ADC MIXR", "ADC1 Switch", "STO1 ADC R1" },
2720     { "STO1 ADC MIXR", "ADC2 Switch", "STO1 ADC R2" },
2721     { "STO1 ADC MIXR", NULL, "STO1 ADC Filter" },
2722 
2723     { "IF1 ADC1", NULL, "STO1 ADC MIXR" },
2724 
2725     { "ADDA MIXR", "ADC R Switch", "STO1 ADC MIXR" },
2726 
2727     { "DAC L", NULL, "STO1 DAC MIXL" },
2728     { "DAC L", NULL, "LDO DAC" },
2729     { "DAC L", NULL, "DAC Clock" },
2730     { "DAC R", NULL, "STO1 DAC MIXR" },
2731     { "DAC R", NULL, "LDO DAC" },
2732     { "DAC R", NULL, "DAC Clock" },
2733 
2734     { "HPO Playback", "Switch", "HP Amp" },
2735     { "HPOL", NULL, "HPO Playback" },
2736     { "HPOR", NULL, "HPO Playback" },
2737 };
2738 
2739 static const struct snd_soc_dapm_route rt5663_specific_dapm_routes[] = {
2740     { "I2S", NULL, "Pre Div Power" },
2741 
2742     { "BST1", NULL, "IN1P" },
2743     { "BST1", NULL, "IN1N" },
2744     { "BST1", NULL, "RECMIX1L Power" },
2745 
2746     { "ADC L", NULL, "BST1" },
2747 
2748     { "STO1 ADC L1", NULL, "ADC L" },
2749 
2750     { "DAC L Mux", "DAC L",  "DAC L1" },
2751     { "DAC L Mux", "STO DAC MIXL", "STO1 DAC MIXL" },
2752     { "DAC R Mux", "DAC R",  "DAC R1"},
2753     { "DAC R Mux", "STO DAC MIXR", "STO1 DAC MIXR" },
2754 
2755     { "DAC L", NULL, "DAC L Mux" },
2756     { "DAC R", NULL, "DAC R Mux" },
2757 
2758     { "HPOL", NULL, "HP Amp" },
2759     { "HPOR", NULL, "HP Amp" },
2760 };
2761 
2762 static int rt5663_hw_params(struct snd_pcm_substream *substream,
2763     struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2764 {
2765     struct snd_soc_component *component = dai->component;
2766     struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2767     unsigned int val_len = 0;
2768     int pre_div;
2769 
2770     rt5663->lrck = params_rate(params);
2771 
2772     dev_dbg(dai->dev, "bclk is %dHz and sysclk is %dHz\n",
2773         rt5663->lrck, rt5663->sysclk);
2774 
2775     pre_div = rl6231_get_clk_info(rt5663->sysclk, rt5663->lrck);
2776     if (pre_div < 0) {
2777         dev_err(component->dev, "Unsupported clock setting %d for DAI %d\n",
2778             rt5663->lrck, dai->id);
2779         return -EINVAL;
2780     }
2781 
2782     dev_dbg(dai->dev, "pre_div is %d for iis %d\n", pre_div, dai->id);
2783 
2784     switch (params_width(params)) {
2785     case 8:
2786         val_len = RT5663_I2S_DL_8;
2787         break;
2788     case 16:
2789         val_len = RT5663_I2S_DL_16;
2790         break;
2791     case 20:
2792         val_len = RT5663_I2S_DL_20;
2793         break;
2794     case 24:
2795         val_len = RT5663_I2S_DL_24;
2796         break;
2797     default:
2798         return -EINVAL;
2799     }
2800 
2801     snd_soc_component_update_bits(component, RT5663_I2S1_SDP,
2802         RT5663_I2S_DL_MASK, val_len);
2803 
2804     snd_soc_component_update_bits(component, RT5663_ADDA_CLK_1,
2805         RT5663_I2S_PD1_MASK, pre_div << RT5663_I2S_PD1_SHIFT);
2806 
2807     return 0;
2808 }
2809 
2810 static int rt5663_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2811 {
2812     struct snd_soc_component *component = dai->component;
2813     unsigned int reg_val = 0;
2814 
2815     switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2816     case SND_SOC_DAIFMT_CBM_CFM:
2817         break;
2818     case SND_SOC_DAIFMT_CBS_CFS:
2819         reg_val |= RT5663_I2S_MS_S;
2820         break;
2821     default:
2822         return -EINVAL;
2823     }
2824 
2825     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2826     case SND_SOC_DAIFMT_NB_NF:
2827         break;
2828     case SND_SOC_DAIFMT_IB_NF:
2829         reg_val |= RT5663_I2S_BP_INV;
2830         break;
2831     default:
2832         return -EINVAL;
2833     }
2834 
2835     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2836     case SND_SOC_DAIFMT_I2S:
2837         break;
2838     case SND_SOC_DAIFMT_LEFT_J:
2839         reg_val |= RT5663_I2S_DF_LEFT;
2840         break;
2841     case SND_SOC_DAIFMT_DSP_A:
2842         reg_val |= RT5663_I2S_DF_PCM_A;
2843         break;
2844     case SND_SOC_DAIFMT_DSP_B:
2845         reg_val |= RT5663_I2S_DF_PCM_B;
2846         break;
2847     default:
2848         return -EINVAL;
2849     }
2850 
2851     snd_soc_component_update_bits(component, RT5663_I2S1_SDP, RT5663_I2S_MS_MASK |
2852         RT5663_I2S_BP_MASK | RT5663_I2S_DF_MASK, reg_val);
2853 
2854     return 0;
2855 }
2856 
2857 static int rt5663_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
2858     unsigned int freq, int dir)
2859 {
2860     struct snd_soc_component *component = dai->component;
2861     struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2862     unsigned int reg_val = 0;
2863 
2864     if (freq == rt5663->sysclk && clk_id == rt5663->sysclk_src)
2865         return 0;
2866 
2867     switch (clk_id) {
2868     case RT5663_SCLK_S_MCLK:
2869         reg_val |= RT5663_SCLK_SRC_MCLK;
2870         break;
2871     case RT5663_SCLK_S_PLL1:
2872         reg_val |= RT5663_SCLK_SRC_PLL1;
2873         break;
2874     case RT5663_SCLK_S_RCCLK:
2875         reg_val |= RT5663_SCLK_SRC_RCCLK;
2876         break;
2877     default:
2878         dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2879         return -EINVAL;
2880     }
2881     snd_soc_component_update_bits(component, RT5663_GLB_CLK, RT5663_SCLK_SRC_MASK,
2882         reg_val);
2883     rt5663->sysclk = freq;
2884     rt5663->sysclk_src = clk_id;
2885 
2886     dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2887         freq, clk_id);
2888 
2889     return 0;
2890 }
2891 
2892 static int rt5663_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2893             unsigned int freq_in, unsigned int freq_out)
2894 {
2895     struct snd_soc_component *component = dai->component;
2896     struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2897     struct rl6231_pll_code pll_code;
2898     int ret;
2899     int mask, shift, val;
2900 
2901     if (source == rt5663->pll_src && freq_in == rt5663->pll_in &&
2902         freq_out == rt5663->pll_out)
2903         return 0;
2904 
2905     if (!freq_in || !freq_out) {
2906         dev_dbg(component->dev, "PLL disabled\n");
2907 
2908         rt5663->pll_in = 0;
2909         rt5663->pll_out = 0;
2910         snd_soc_component_update_bits(component, RT5663_GLB_CLK,
2911             RT5663_SCLK_SRC_MASK, RT5663_SCLK_SRC_MCLK);
2912         return 0;
2913     }
2914 
2915     switch (rt5663->codec_ver) {
2916     case CODEC_VER_1:
2917         mask = RT5663_V2_PLL1_SRC_MASK;
2918         shift = RT5663_V2_PLL1_SRC_SHIFT;
2919         break;
2920     case CODEC_VER_0:
2921         mask = RT5663_PLL1_SRC_MASK;
2922         shift = RT5663_PLL1_SRC_SHIFT;
2923         break;
2924     default:
2925         dev_err(component->dev, "Unknown CODEC Version\n");
2926         return -EINVAL;
2927     }
2928 
2929     switch (source) {
2930     case RT5663_PLL1_S_MCLK:
2931         val = 0x0;
2932         break;
2933     case RT5663_PLL1_S_BCLK1:
2934         val = 0x1;
2935         break;
2936     default:
2937         dev_err(component->dev, "Unknown PLL source %d\n", source);
2938         return -EINVAL;
2939     }
2940     snd_soc_component_update_bits(component, RT5663_GLB_CLK, mask, (val << shift));
2941 
2942     ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2943     if (ret < 0) {
2944         dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
2945         return ret;
2946     }
2947 
2948     dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", pll_code.m_bp,
2949         (pll_code.m_bp ? 0 : pll_code.m_code), pll_code.n_code,
2950         pll_code.k_code);
2951 
2952     snd_soc_component_write(component, RT5663_PLL_1,
2953         pll_code.n_code << RT5663_PLL_N_SHIFT | pll_code.k_code);
2954     snd_soc_component_write(component, RT5663_PLL_2,
2955         ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5663_PLL_M_SHIFT) |
2956         (pll_code.m_bp << RT5663_PLL_M_BP_SHIFT));
2957 
2958     rt5663->pll_in = freq_in;
2959     rt5663->pll_out = freq_out;
2960     rt5663->pll_src = source;
2961 
2962     return 0;
2963 }
2964 
2965 static int rt5663_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2966     unsigned int rx_mask, int slots, int slot_width)
2967 {
2968     struct snd_soc_component *component = dai->component;
2969     struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2970     unsigned int val = 0, reg;
2971 
2972     if (rx_mask || tx_mask)
2973         val |= RT5663_TDM_MODE_TDM;
2974 
2975     switch (slots) {
2976     case 4:
2977         val |= RT5663_TDM_IN_CH_4;
2978         val |= RT5663_TDM_OUT_CH_4;
2979         break;
2980     case 6:
2981         val |= RT5663_TDM_IN_CH_6;
2982         val |= RT5663_TDM_OUT_CH_6;
2983         break;
2984     case 8:
2985         val |= RT5663_TDM_IN_CH_8;
2986         val |= RT5663_TDM_OUT_CH_8;
2987         break;
2988     case 2:
2989         break;
2990     default:
2991         return -EINVAL;
2992     }
2993 
2994     switch (slot_width) {
2995     case 20:
2996         val |= RT5663_TDM_IN_LEN_20;
2997         val |= RT5663_TDM_OUT_LEN_20;
2998         break;
2999     case 24:
3000         val |= RT5663_TDM_IN_LEN_24;
3001         val |= RT5663_TDM_OUT_LEN_24;
3002         break;
3003     case 32:
3004         val |= RT5663_TDM_IN_LEN_32;
3005         val |= RT5663_TDM_OUT_LEN_32;
3006         break;
3007     case 16:
3008         break;
3009     default:
3010         return -EINVAL;
3011     }
3012 
3013     switch (rt5663->codec_ver) {
3014     case CODEC_VER_1:
3015         reg = RT5663_TDM_2;
3016         break;
3017     case CODEC_VER_0:
3018         reg = RT5663_TDM_1;
3019         break;
3020     default:
3021         dev_err(component->dev, "Unknown CODEC Version\n");
3022         return -EINVAL;
3023     }
3024 
3025     snd_soc_component_update_bits(component, reg, RT5663_TDM_MODE_MASK |
3026         RT5663_TDM_IN_CH_MASK | RT5663_TDM_OUT_CH_MASK |
3027         RT5663_TDM_IN_LEN_MASK | RT5663_TDM_OUT_LEN_MASK, val);
3028 
3029     return 0;
3030 }
3031 
3032 static int rt5663_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
3033 {
3034     struct snd_soc_component *component = dai->component;
3035     struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3036     unsigned int reg;
3037 
3038     dev_dbg(component->dev, "%s ratio = %d\n", __func__, ratio);
3039 
3040     if (rt5663->codec_ver == CODEC_VER_1)
3041         reg = RT5663_TDM_9;
3042     else
3043         reg = RT5663_TDM_5;
3044 
3045     switch (ratio) {
3046     case 32:
3047         snd_soc_component_update_bits(component, reg,
3048             RT5663_TDM_LENGTN_MASK,
3049             RT5663_TDM_LENGTN_16);
3050         break;
3051     case 40:
3052         snd_soc_component_update_bits(component, reg,
3053             RT5663_TDM_LENGTN_MASK,
3054             RT5663_TDM_LENGTN_20);
3055         break;
3056     case 48:
3057         snd_soc_component_update_bits(component, reg,
3058             RT5663_TDM_LENGTN_MASK,
3059             RT5663_TDM_LENGTN_24);
3060         break;
3061     case 64:
3062         snd_soc_component_update_bits(component, reg,
3063             RT5663_TDM_LENGTN_MASK,
3064             RT5663_TDM_LENGTN_32);
3065         break;
3066     default:
3067         dev_err(component->dev, "Invalid ratio!\n");
3068         return -EINVAL;
3069     }
3070 
3071     return 0;
3072 }
3073 
3074 static int rt5663_set_bias_level(struct snd_soc_component *component,
3075             enum snd_soc_bias_level level)
3076 {
3077     struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3078 
3079     switch (level) {
3080     case SND_SOC_BIAS_ON:
3081         snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
3082             RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
3083             RT5663_PWR_FV1 | RT5663_PWR_FV2);
3084         break;
3085 
3086     case SND_SOC_BIAS_PREPARE:
3087         if (rt5663->codec_ver == CODEC_VER_1) {
3088             snd_soc_component_update_bits(component, RT5663_DIG_MISC,
3089                 RT5663_DIG_GATE_CTRL_MASK,
3090                 RT5663_DIG_GATE_CTRL_EN);
3091             snd_soc_component_update_bits(component, RT5663_SIG_CLK_DET,
3092                 RT5663_EN_ANA_CLK_DET_MASK |
3093                 RT5663_PWR_CLK_DET_MASK,
3094                 RT5663_EN_ANA_CLK_DET_AUTO |
3095                 RT5663_PWR_CLK_DET_EN);
3096         }
3097         break;
3098 
3099     case SND_SOC_BIAS_STANDBY:
3100         if (rt5663->codec_ver == CODEC_VER_1)
3101             snd_soc_component_update_bits(component, RT5663_DIG_MISC,
3102                 RT5663_DIG_GATE_CTRL_MASK,
3103                 RT5663_DIG_GATE_CTRL_DIS);
3104         snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
3105             RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
3106             RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK |
3107             RT5663_PWR_MB_MASK, RT5663_PWR_VREF1 |
3108             RT5663_PWR_VREF2 | RT5663_PWR_MB);
3109         usleep_range(10000, 10005);
3110         if (rt5663->codec_ver == CODEC_VER_1) {
3111             snd_soc_component_update_bits(component, RT5663_SIG_CLK_DET,
3112                 RT5663_EN_ANA_CLK_DET_MASK |
3113                 RT5663_PWR_CLK_DET_MASK,
3114                 RT5663_EN_ANA_CLK_DET_DIS |
3115                 RT5663_PWR_CLK_DET_DIS);
3116         }
3117         break;
3118 
3119     case SND_SOC_BIAS_OFF:
3120         if (rt5663->jack_type != SND_JACK_HEADSET)
3121             snd_soc_component_update_bits(component,
3122                 RT5663_PWR_ANLG_1,
3123                 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
3124                 RT5663_PWR_FV1 | RT5663_PWR_FV2 |
3125                 RT5663_PWR_MB_MASK, 0);
3126         else
3127             snd_soc_component_update_bits(component,
3128                 RT5663_PWR_ANLG_1,
3129                 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
3130                 RT5663_PWR_FV1 | RT5663_PWR_FV2);
3131         break;
3132 
3133     default:
3134         break;
3135     }
3136 
3137     return 0;
3138 }
3139 
3140 static int rt5663_probe(struct snd_soc_component *component)
3141 {
3142     struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3143     struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3144 
3145     rt5663->component = component;
3146 
3147     switch (rt5663->codec_ver) {
3148     case CODEC_VER_1:
3149         snd_soc_dapm_new_controls(dapm,
3150             rt5663_v2_specific_dapm_widgets,
3151             ARRAY_SIZE(rt5663_v2_specific_dapm_widgets));
3152         snd_soc_dapm_add_routes(dapm,
3153             rt5663_v2_specific_dapm_routes,
3154             ARRAY_SIZE(rt5663_v2_specific_dapm_routes));
3155         snd_soc_add_component_controls(component, rt5663_v2_specific_controls,
3156             ARRAY_SIZE(rt5663_v2_specific_controls));
3157         break;
3158     case CODEC_VER_0:
3159         snd_soc_dapm_new_controls(dapm,
3160             rt5663_specific_dapm_widgets,
3161             ARRAY_SIZE(rt5663_specific_dapm_widgets));
3162         snd_soc_dapm_add_routes(dapm,
3163             rt5663_specific_dapm_routes,
3164             ARRAY_SIZE(rt5663_specific_dapm_routes));
3165         snd_soc_add_component_controls(component, rt5663_specific_controls,
3166             ARRAY_SIZE(rt5663_specific_controls));
3167 
3168         if (!rt5663->imp_table)
3169             snd_soc_add_component_controls(component, rt5663_hpvol_controls,
3170                 ARRAY_SIZE(rt5663_hpvol_controls));
3171         break;
3172     }
3173 
3174     return 0;
3175 }
3176 
3177 static void rt5663_remove(struct snd_soc_component *component)
3178 {
3179     struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3180 
3181     regmap_write(rt5663->regmap, RT5663_RESET, 0);
3182 }
3183 
3184 #ifdef CONFIG_PM
3185 static int rt5663_suspend(struct snd_soc_component *component)
3186 {
3187     struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3188 
3189     regcache_cache_only(rt5663->regmap, true);
3190     regcache_mark_dirty(rt5663->regmap);
3191 
3192     return 0;
3193 }
3194 
3195 static int rt5663_resume(struct snd_soc_component *component)
3196 {
3197     struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3198 
3199     regcache_cache_only(rt5663->regmap, false);
3200     regcache_sync(rt5663->regmap);
3201 
3202     rt5663_irq(0, rt5663);
3203 
3204     return 0;
3205 }
3206 #else
3207 #define rt5663_suspend NULL
3208 #define rt5663_resume NULL
3209 #endif
3210 
3211 #define RT5663_STEREO_RATES SNDRV_PCM_RATE_8000_192000
3212 #define RT5663_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3213             SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3214 
3215 static const struct snd_soc_dai_ops rt5663_aif_dai_ops = {
3216     .hw_params = rt5663_hw_params,
3217     .set_fmt = rt5663_set_dai_fmt,
3218     .set_sysclk = rt5663_set_dai_sysclk,
3219     .set_pll = rt5663_set_dai_pll,
3220     .set_tdm_slot = rt5663_set_tdm_slot,
3221     .set_bclk_ratio = rt5663_set_bclk_ratio,
3222 };
3223 
3224 static struct snd_soc_dai_driver rt5663_dai[] = {
3225     {
3226         .name = "rt5663-aif",
3227         .id = RT5663_AIF,
3228         .playback = {
3229             .stream_name = "AIF Playback",
3230             .channels_min = 1,
3231             .channels_max = 2,
3232             .rates = RT5663_STEREO_RATES,
3233             .formats = RT5663_FORMATS,
3234         },
3235         .capture = {
3236             .stream_name = "AIF Capture",
3237             .channels_min = 1,
3238             .channels_max = 2,
3239             .rates = RT5663_STEREO_RATES,
3240             .formats = RT5663_FORMATS,
3241         },
3242         .ops = &rt5663_aif_dai_ops,
3243     },
3244 };
3245 
3246 static const struct snd_soc_component_driver soc_component_dev_rt5663 = {
3247     .probe          = rt5663_probe,
3248     .remove         = rt5663_remove,
3249     .suspend        = rt5663_suspend,
3250     .resume         = rt5663_resume,
3251     .set_bias_level     = rt5663_set_bias_level,
3252     .controls       = rt5663_snd_controls,
3253     .num_controls       = ARRAY_SIZE(rt5663_snd_controls),
3254     .dapm_widgets       = rt5663_dapm_widgets,
3255     .num_dapm_widgets   = ARRAY_SIZE(rt5663_dapm_widgets),
3256     .dapm_routes        = rt5663_dapm_routes,
3257     .num_dapm_routes    = ARRAY_SIZE(rt5663_dapm_routes),
3258     .set_jack       = rt5663_set_jack_detect,
3259     .use_pmdown_time    = 1,
3260     .endianness     = 1,
3261 };
3262 
3263 static const struct regmap_config rt5663_v2_regmap = {
3264     .reg_bits = 16,
3265     .val_bits = 16,
3266     .use_single_read = true,
3267     .use_single_write = true,
3268     .max_register = 0x07fa,
3269     .volatile_reg = rt5663_v2_volatile_register,
3270     .readable_reg = rt5663_v2_readable_register,
3271     .cache_type = REGCACHE_RBTREE,
3272     .reg_defaults = rt5663_v2_reg,
3273     .num_reg_defaults = ARRAY_SIZE(rt5663_v2_reg),
3274 };
3275 
3276 static const struct regmap_config rt5663_regmap = {
3277     .reg_bits = 16,
3278     .val_bits = 16,
3279     .use_single_read = true,
3280     .use_single_write = true,
3281     .max_register = 0x03f3,
3282     .volatile_reg = rt5663_volatile_register,
3283     .readable_reg = rt5663_readable_register,
3284     .cache_type = REGCACHE_RBTREE,
3285     .reg_defaults = rt5663_reg,
3286     .num_reg_defaults = ARRAY_SIZE(rt5663_reg),
3287 };
3288 
3289 static const struct regmap_config temp_regmap = {
3290     .name = "nocache",
3291     .reg_bits = 16,
3292     .val_bits = 16,
3293     .use_single_read = true,
3294     .use_single_write = true,
3295     .max_register = 0x03f3,
3296     .cache_type = REGCACHE_NONE,
3297 };
3298 
3299 static const struct i2c_device_id rt5663_i2c_id[] = {
3300     { "rt5663", 0 },
3301     {}
3302 };
3303 MODULE_DEVICE_TABLE(i2c, rt5663_i2c_id);
3304 
3305 #if defined(CONFIG_OF)
3306 static const struct of_device_id rt5663_of_match[] = {
3307     { .compatible = "realtek,rt5663", },
3308     {},
3309 };
3310 MODULE_DEVICE_TABLE(of, rt5663_of_match);
3311 #endif
3312 
3313 #ifdef CONFIG_ACPI
3314 static const struct acpi_device_id rt5663_acpi_match[] = {
3315     { "10EC5663", 0},
3316     {},
3317 };
3318 MODULE_DEVICE_TABLE(acpi, rt5663_acpi_match);
3319 #endif
3320 
3321 static void rt5663_v2_calibrate(struct rt5663_priv *rt5663)
3322 {
3323     regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402);
3324     regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0100);
3325     regmap_write(rt5663->regmap, RT5663_RECMIX, 0x4040);
3326     regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x0001);
3327     regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380);
3328     regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000);
3329     regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000);
3330     regmap_write(rt5663->regmap, RT5663_CHOP_DAC_L, 0x3030);
3331     regmap_write(rt5663->regmap, RT5663_CALIB_ADC, 0x3c05);
3332     regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23e);
3333     msleep(40);
3334     regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23e);
3335     regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x0321);
3336     regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0xfc00);
3337     msleep(500);
3338 }
3339 
3340 static void rt5663_calibrate(struct rt5663_priv *rt5663)
3341 {
3342     int value, count;
3343 
3344     regmap_write(rt5663->regmap, RT5663_RESET, 0x0000);
3345     msleep(20);
3346     regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_4, 0x00a1);
3347     regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380);
3348     regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000);
3349     regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000);
3350     regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032);
3351     regmap_write(rt5663->regmap, RT5663_HP_IMP_SEN_19, 0x000c);
3352     regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x0324);
3353     regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x8001);
3354     regmap_write(rt5663->regmap, RT5663_VREFADJ_OP, 0x0f28);
3355     regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23b);
3356     msleep(30);
3357     regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23b);
3358     regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x8000);
3359     regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x0008);
3360     regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_1, 0xffff);
3361     regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_2, 0xffff);
3362     regmap_write(rt5663->regmap, RT5663_CBJ_1, 0x8c10);
3363     regmap_write(rt5663->regmap, RT5663_IL_CMD_2, 0x00c1);
3364     regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_1, 0xb880);
3365     regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_2, 0x4110);
3366     regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_2, 0x4118);
3367 
3368     count = 0;
3369     while (true) {
3370         regmap_read(rt5663->regmap, RT5663_INT_ST_2, &value);
3371         if (!(value & 0x80))
3372             usleep_range(10000, 10005);
3373         else
3374             break;
3375 
3376         if (++count > 200)
3377             break;
3378     }
3379 
3380     regmap_write(rt5663->regmap, RT5663_HP_IMP_SEN_19, 0x0000);
3381     regmap_write(rt5663->regmap, RT5663_DEPOP_2, 0x3003);
3382     regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x0038);
3383     regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x003b);
3384     regmap_write(rt5663->regmap, RT5663_PWR_DIG_2, 0x8400);
3385     regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x8df8);
3386     regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x8003);
3387     regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x018c);
3388     regmap_write(rt5663->regmap, RT5663_HP_CHARGE_PUMP_1, 0x1e32);
3389     regmap_write(rt5663->regmap, RT5663_DUMMY_2, 0x8089);
3390     regmap_write(rt5663->regmap, RT5663_DACREF_LDO, 0x3b0b);
3391     msleep(40);
3392     regmap_write(rt5663->regmap, RT5663_STO_DAC_MIXER, 0x0000);
3393     regmap_write(rt5663->regmap, RT5663_BYPASS_STO_DAC, 0x000c);
3394     regmap_write(rt5663->regmap, RT5663_HP_BIAS, 0xafaa);
3395     regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_1, 0x2224);
3396     regmap_write(rt5663->regmap, RT5663_HP_OUT_EN, 0x8088);
3397     regmap_write(rt5663->regmap, RT5663_STO_DRE_9, 0x0017);
3398     regmap_write(rt5663->regmap, RT5663_STO_DRE_10, 0x0017);
3399     regmap_write(rt5663->regmap, RT5663_STO1_ADC_MIXER, 0x4040);
3400     regmap_write(rt5663->regmap, RT5663_CHOP_ADC, 0x3000);
3401     regmap_write(rt5663->regmap, RT5663_RECMIX, 0x0005);
3402     regmap_write(rt5663->regmap, RT5663_ADDA_RST, 0xc000);
3403     regmap_write(rt5663->regmap, RT5663_STO1_HPF_ADJ1, 0x3320);
3404     regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x00c9);
3405     regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x004c);
3406     regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_1, 0x1111);
3407     regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0x4402);
3408     regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_2, 0x3311);
3409     regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0x0069);
3410     regmap_write(rt5663->regmap, RT5663_HP_CALIB_3, 0x06ce);
3411     regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x6800);
3412     regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_2, 0x1100);
3413     regmap_write(rt5663->regmap, RT5663_HP_CALIB_7, 0x0057);
3414     regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xe800);
3415 
3416     count = 0;
3417     while (true) {
3418         regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value);
3419         if (value & 0x8000)
3420             usleep_range(10000, 10005);
3421         else
3422             break;
3423 
3424         if (count > 200)
3425             return;
3426         count++;
3427     }
3428 
3429     regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x6200);
3430     regmap_write(rt5663->regmap, RT5663_HP_CALIB_7, 0x0059);
3431     regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xe200);
3432 
3433     count = 0;
3434     while (true) {
3435         regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value);
3436         if (value & 0x8000)
3437             usleep_range(10000, 10005);
3438         else
3439             break;
3440 
3441         if (count > 200)
3442             return;
3443         count++;
3444     }
3445 
3446     regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_1, 0xb8e0);
3447     usleep_range(10000, 10005);
3448     regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0x003b);
3449     usleep_range(10000, 10005);
3450     regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0000);
3451     usleep_range(10000, 10005);
3452     regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x000b);
3453     usleep_range(10000, 10005);
3454     regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x0008);
3455     usleep_range(10000, 10005);
3456     regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x0000);
3457     usleep_range(10000, 10005);
3458 }
3459 
3460 static int rt5663_parse_dp(struct rt5663_priv *rt5663, struct device *dev)
3461 {
3462     int table_size;
3463     int ret;
3464 
3465     device_property_read_u32(dev, "realtek,dc_offset_l_manual",
3466         &rt5663->pdata.dc_offset_l_manual);
3467     device_property_read_u32(dev, "realtek,dc_offset_r_manual",
3468         &rt5663->pdata.dc_offset_r_manual);
3469     device_property_read_u32(dev, "realtek,dc_offset_l_manual_mic",
3470         &rt5663->pdata.dc_offset_l_manual_mic);
3471     device_property_read_u32(dev, "realtek,dc_offset_r_manual_mic",
3472         &rt5663->pdata.dc_offset_r_manual_mic);
3473     device_property_read_u32(dev, "realtek,impedance_sensing_num",
3474         &rt5663->pdata.impedance_sensing_num);
3475 
3476     if (rt5663->pdata.impedance_sensing_num) {
3477         table_size = sizeof(struct impedance_mapping_table) *
3478             rt5663->pdata.impedance_sensing_num;
3479         rt5663->imp_table = devm_kzalloc(dev, table_size, GFP_KERNEL);
3480         if (!rt5663->imp_table)
3481             return -ENOMEM;
3482         ret = device_property_read_u32_array(dev,
3483             "realtek,impedance_sensing_table",
3484             (u32 *)rt5663->imp_table, table_size);
3485         if (ret)
3486             return ret;
3487     }
3488 
3489     return 0;
3490 }
3491 
3492 static int rt5663_i2c_probe(struct i2c_client *i2c)
3493 {
3494     struct rt5663_platform_data *pdata = dev_get_platdata(&i2c->dev);
3495     struct rt5663_priv *rt5663;
3496     int ret, i;
3497     unsigned int val;
3498     struct regmap *regmap;
3499 
3500     rt5663 = devm_kzalloc(&i2c->dev, sizeof(struct rt5663_priv),
3501         GFP_KERNEL);
3502 
3503     if (rt5663 == NULL)
3504         return -ENOMEM;
3505 
3506     i2c_set_clientdata(i2c, rt5663);
3507 
3508     if (pdata)
3509         rt5663->pdata = *pdata;
3510     else {
3511         ret = rt5663_parse_dp(rt5663, &i2c->dev);
3512         if (ret)
3513             return ret;
3514     }
3515 
3516     for (i = 0; i < ARRAY_SIZE(rt5663->supplies); i++)
3517         rt5663->supplies[i].supply = rt5663_supply_names[i];
3518 
3519     ret = devm_regulator_bulk_get(&i2c->dev,
3520                       ARRAY_SIZE(rt5663->supplies),
3521                       rt5663->supplies);
3522     if (ret) {
3523         dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
3524         return ret;
3525     }
3526 
3527     /* Set load for regulator. */
3528     for (i = 0; i < ARRAY_SIZE(rt5663->supplies); i++) {
3529         ret = regulator_set_load(rt5663->supplies[i].consumer,
3530                      RT5663_SUPPLY_CURRENT_UA);
3531         if (ret < 0) {
3532             dev_err(&i2c->dev,
3533                 "Failed to set regulator load on %s, ret: %d\n",
3534                 rt5663->supplies[i].supply, ret);
3535             return ret;
3536         }
3537     }
3538 
3539     ret = regulator_bulk_enable(ARRAY_SIZE(rt5663->supplies),
3540                     rt5663->supplies);
3541 
3542     if (ret) {
3543         dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
3544         return ret;
3545     }
3546     msleep(RT5663_POWER_ON_DELAY_MS);
3547 
3548     regmap = devm_regmap_init_i2c(i2c, &temp_regmap);
3549     if (IS_ERR(regmap)) {
3550         ret = PTR_ERR(regmap);
3551         dev_err(&i2c->dev, "Failed to allocate temp register map: %d\n",
3552             ret);
3553         goto err_enable;
3554     }
3555 
3556     ret = regmap_read(regmap, RT5663_VENDOR_ID_2, &val);
3557     if (ret || (val != RT5663_DEVICE_ID_2 && val != RT5663_DEVICE_ID_1)) {
3558         dev_err(&i2c->dev,
3559             "Device with ID register %#x is not rt5663, retry one time.\n",
3560             val);
3561         msleep(100);
3562         regmap_read(regmap, RT5663_VENDOR_ID_2, &val);
3563     }
3564 
3565     switch (val) {
3566     case RT5663_DEVICE_ID_2:
3567         rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_v2_regmap);
3568         rt5663->codec_ver = CODEC_VER_1;
3569         break;
3570     case RT5663_DEVICE_ID_1:
3571         rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_regmap);
3572         rt5663->codec_ver = CODEC_VER_0;
3573         break;
3574     default:
3575         dev_err(&i2c->dev,
3576             "Device with ID register %#x is not rt5663\n",
3577             val);
3578         ret = -ENODEV;
3579         goto err_enable;
3580     }
3581 
3582     if (IS_ERR(rt5663->regmap)) {
3583         ret = PTR_ERR(rt5663->regmap);
3584         dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
3585             ret);
3586         goto err_enable;
3587     }
3588 
3589     /* reset and calibrate */
3590     regmap_write(rt5663->regmap, RT5663_RESET, 0);
3591     regcache_cache_bypass(rt5663->regmap, true);
3592     switch (rt5663->codec_ver) {
3593     case CODEC_VER_1:
3594         rt5663_v2_calibrate(rt5663);
3595         break;
3596     case CODEC_VER_0:
3597         rt5663_calibrate(rt5663);
3598         break;
3599     default:
3600         dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3601     }
3602     regcache_cache_bypass(rt5663->regmap, false);
3603     regmap_write(rt5663->regmap, RT5663_RESET, 0);
3604     dev_dbg(&i2c->dev, "calibrate done\n");
3605 
3606     switch (rt5663->codec_ver) {
3607     case CODEC_VER_1:
3608         break;
3609     case CODEC_VER_0:
3610         ret = regmap_register_patch(rt5663->regmap, rt5663_patch_list,
3611                         ARRAY_SIZE(rt5663_patch_list));
3612         if (ret != 0)
3613             dev_warn(&i2c->dev,
3614                 "Failed to apply regmap patch: %d\n", ret);
3615         break;
3616     default:
3617         dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3618     }
3619 
3620     /* GPIO1 as IRQ */
3621     regmap_update_bits(rt5663->regmap, RT5663_GPIO_1, RT5663_GP1_PIN_MASK,
3622         RT5663_GP1_PIN_IRQ);
3623     /* 4btn inline command debounce */
3624     regmap_update_bits(rt5663->regmap, RT5663_IL_CMD_5,
3625         RT5663_4BTN_CLK_DEB_MASK, RT5663_4BTN_CLK_DEB_65MS);
3626 
3627     switch (rt5663->codec_ver) {
3628     case CODEC_VER_1:
3629         regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402);
3630         /* JD1 */
3631         regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK,
3632             RT5663_IRQ_POW_SAV_MASK | RT5663_IRQ_POW_SAV_JD1_MASK,
3633             RT5663_IRQ_POW_SAV_EN | RT5663_IRQ_POW_SAV_JD1_EN);
3634         regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_2,
3635             RT5663_PWR_JD1_MASK, RT5663_PWR_JD1);
3636         regmap_update_bits(rt5663->regmap, RT5663_IRQ_1,
3637             RT5663_EN_CB_JD_MASK, RT5663_EN_CB_JD_EN);
3638 
3639         regmap_update_bits(rt5663->regmap, RT5663_HP_LOGIC_2,
3640             RT5663_HP_SIG_SRC1_MASK, RT5663_HP_SIG_SRC1_REG);
3641         regmap_update_bits(rt5663->regmap, RT5663_RECMIX,
3642             RT5663_VREF_BIAS_MASK | RT5663_CBJ_DET_MASK |
3643             RT5663_DET_TYPE_MASK, RT5663_VREF_BIAS_REG |
3644             RT5663_CBJ_DET_EN | RT5663_DET_TYPE_QFN);
3645         /* Set GPIO4 and GPIO8 as input for combo jack */
3646         regmap_update_bits(rt5663->regmap, RT5663_GPIO_2,
3647             RT5663_GP4_PIN_CONF_MASK, RT5663_GP4_PIN_CONF_INPUT);
3648         regmap_update_bits(rt5663->regmap, RT5663_GPIO_3,
3649             RT5663_GP8_PIN_CONF_MASK, RT5663_GP8_PIN_CONF_INPUT);
3650         regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_1,
3651             RT5663_LDO1_DVO_MASK | RT5663_AMP_HP_MASK,
3652             RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X);
3653         break;
3654     case CODEC_VER_0:
3655         regmap_update_bits(rt5663->regmap, RT5663_DIG_MISC,
3656             RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN);
3657         regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK,
3658             RT5663_IRQ_MANUAL_MASK, RT5663_IRQ_MANUAL_EN);
3659         regmap_update_bits(rt5663->regmap, RT5663_IRQ_1,
3660             RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN);
3661         regmap_update_bits(rt5663->regmap, RT5663_GPIO_1,
3662             RT5663_GPIO1_TYPE_MASK, RT5663_GPIO1_TYPE_EN);
3663         regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032);
3664         regmap_update_bits(rt5663->regmap, RT5663_GPIO_2,
3665             RT5663_GP1_PIN_CONF_MASK | RT5663_SEL_GPIO1_MASK,
3666             RT5663_GP1_PIN_CONF_OUTPUT | RT5663_SEL_GPIO1_EN);
3667         regmap_update_bits(rt5663->regmap, RT5663_RECMIX,
3668             RT5663_RECMIX1_BST1_MASK, RT5663_RECMIX1_BST1_ON);
3669         regmap_update_bits(rt5663->regmap, RT5663_TDM_2,
3670             RT5663_DATA_SWAP_ADCDAT1_MASK,
3671             RT5663_DATA_SWAP_ADCDAT1_LL);
3672         break;
3673     default:
3674         dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3675     }
3676 
3677     INIT_DELAYED_WORK(&rt5663->jack_detect_work, rt5663_jack_detect_work);
3678     INIT_DELAYED_WORK(&rt5663->jd_unplug_work, rt5663_jd_unplug_work);
3679 
3680     if (i2c->irq) {
3681         ret = request_irq(i2c->irq, rt5663_irq,
3682             IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
3683             | IRQF_ONESHOT, "rt5663", rt5663);
3684         if (ret) {
3685             dev_err(&i2c->dev, "%s Failed to reguest IRQ: %d\n",
3686                 __func__, ret);
3687             goto err_enable;
3688         }
3689     }
3690 
3691     ret = devm_snd_soc_register_component(&i2c->dev,
3692             &soc_component_dev_rt5663,
3693             rt5663_dai, ARRAY_SIZE(rt5663_dai));
3694 
3695     if (ret)
3696         goto err_enable;
3697 
3698     return 0;
3699 
3700 
3701     /*
3702      * Error after enabling regulators should goto err_enable
3703      * to disable regulators.
3704      */
3705 err_enable:
3706     if (i2c->irq)
3707         free_irq(i2c->irq, rt5663);
3708 
3709     regulator_bulk_disable(ARRAY_SIZE(rt5663->supplies), rt5663->supplies);
3710     return ret;
3711 }
3712 
3713 static int rt5663_i2c_remove(struct i2c_client *i2c)
3714 {
3715     struct rt5663_priv *rt5663 = i2c_get_clientdata(i2c);
3716 
3717     if (i2c->irq)
3718         free_irq(i2c->irq, rt5663);
3719 
3720     regulator_bulk_disable(ARRAY_SIZE(rt5663->supplies), rt5663->supplies);
3721 
3722     return 0;
3723 }
3724 
3725 static void rt5663_i2c_shutdown(struct i2c_client *client)
3726 {
3727     struct rt5663_priv *rt5663 = i2c_get_clientdata(client);
3728 
3729     regmap_write(rt5663->regmap, RT5663_RESET, 0);
3730 }
3731 
3732 static struct i2c_driver rt5663_i2c_driver = {
3733     .driver = {
3734         .name = "rt5663",
3735         .acpi_match_table = ACPI_PTR(rt5663_acpi_match),
3736         .of_match_table = of_match_ptr(rt5663_of_match),
3737     },
3738     .probe_new = rt5663_i2c_probe,
3739     .remove = rt5663_i2c_remove,
3740     .shutdown = rt5663_i2c_shutdown,
3741     .id_table = rt5663_i2c_id,
3742 };
3743 module_i2c_driver(rt5663_i2c_driver);
3744 
3745 MODULE_DESCRIPTION("ASoC RT5663 driver");
3746 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
3747 MODULE_LICENSE("GPL v2");
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