soc/codecs/rt5645.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * rt5645.c  --  RT5645 ALSA SoC audio codec driver
0004  *
0005  * Copyright 2013 Realtek Semiconductor Corp.
0006  * Author: Bard Liao <bardliao@realtek.com>
0007  */
0008
0009 #include <linux/module.h>
0010 #include <linux/moduleparam.h>
0011 #include <linux/init.h>
0012 #include <linux/delay.h>
0013 #include <linux/pm.h>
0014 #include <linux/i2c.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/spi/spi.h>
0017 #include <linux/gpio.h>
0018 #include <linux/gpio/consumer.h>
0019 #include <linux/acpi.h>
0020 #include <linux/dmi.h>
0021 #include <linux/regulator/consumer.h>
0022 #include <sound/core.h>
0023 #include <sound/pcm.h>
0024 #include <sound/pcm_params.h>
0025 #include <sound/jack.h>
0026 #include <sound/soc.h>
0027 #include <sound/soc-dapm.h>
0028 #include <sound/initval.h>
0029 #include <sound/tlv.h>
0030
0031 #include "rl6231.h"
0032 #include "rt5645.h"
0033
0034 #define QUIRK_INV_JD1_1(q)  ((q) & 1)
0035 #define QUIRK_LEVEL_IRQ(q)  (((q) >> 1) & 1)
0036 #define QUIRK_IN2_DIFF(q)   (((q) >> 2) & 1)
0037 #define QUIRK_INV_HP_POL(q) (((q) >> 3) & 1)
0038 #define QUIRK_JD_MODE(q)    (((q) >> 4) & 7)
0039 #define QUIRK_DMIC1_DATA_PIN(q) (((q) >> 8) & 3)
0040 #define QUIRK_DMIC2_DATA_PIN(q) (((q) >> 12) & 3)
0041
0042 static unsigned int quirk = -1;
0043 module_param(quirk, uint, 0444);
0044 MODULE_PARM_DESC(quirk, "RT5645 pdata quirk override");
0045
0046 static const struct acpi_gpio_mapping *cht_rt5645_gpios;
0047
0048 #define RT5645_DEVICE_ID 0x6308
0049 #define RT5650_DEVICE_ID 0x6419
0050
0051 #define RT5645_PR_RANGE_BASE (0xff + 1)
0052 #define RT5645_PR_SPACING 0x100
0053
0054 #define RT5645_PR_BASE (RT5645_PR_RANGE_BASE + (0 * RT5645_PR_SPACING))
0055
0056 #define RT5645_HWEQ_NUM 57
0057
0058 #define TIME_TO_POWER_MS 400
0059
0060 static const struct regmap_range_cfg rt5645_ranges[] = {
0061     {
0062         .name = "PR",
0063         .range_min = RT5645_PR_BASE,
0064         .range_max = RT5645_PR_BASE + 0xf8,
0065         .selector_reg = RT5645_PRIV_INDEX,
0066         .selector_mask = 0xff,
0067         .selector_shift = 0x0,
0068         .window_start = RT5645_PRIV_DATA,
0069         .window_len = 0x1,
0070     },
0071 };
0072
0073 static const struct reg_sequence init_list[] = {
0074     {RT5645_PR_BASE + 0x3d, 0x3600},
0075     {RT5645_PR_BASE + 0x1c, 0xfd70},
0076     {RT5645_PR_BASE + 0x20, 0x611f},
0077     {RT5645_PR_BASE + 0x21, 0x4040},
0078     {RT5645_PR_BASE + 0x23, 0x0004},
0079     {RT5645_ASRC_4, 0x0120},
0080 };
0081
0082 static const struct reg_sequence rt5650_init_list[] = {
0083     {0xf6,  0x0100},
0084 };
0085
0086 static const struct reg_default rt5645_reg[] = {
0087     { 0x00, 0x0000 },
0088     { 0x01, 0xc8c8 },
0089     { 0x02, 0xc8c8 },
0090     { 0x03, 0xc8c8 },
0091     { 0x0a, 0x0002 },
0092     { 0x0b, 0x2827 },
0093     { 0x0c, 0xe000 },
0094     { 0x0d, 0x0000 },
0095     { 0x0e, 0x0000 },
0096     { 0x0f, 0x0808 },
0097     { 0x14, 0x3333 },
0098     { 0x16, 0x4b00 },
0099     { 0x18, 0x018b },
0100     { 0x19, 0xafaf },
0101     { 0x1a, 0xafaf },
0102     { 0x1b, 0x0001 },
0103     { 0x1c, 0x2f2f },
0104     { 0x1d, 0x2f2f },
0105     { 0x1e, 0x0000 },
0106     { 0x20, 0x0000 },
0107     { 0x27, 0x7060 },
0108     { 0x28, 0x7070 },
0109     { 0x29, 0x8080 },
0110     { 0x2a, 0x5656 },
0111     { 0x2b, 0x5454 },
0112     { 0x2c, 0xaaa0 },
0113     { 0x2d, 0x0000 },
0114     { 0x2f, 0x1002 },
0115     { 0x31, 0x5000 },
0116     { 0x32, 0x0000 },
0117     { 0x33, 0x0000 },
0118     { 0x34, 0x0000 },
0119     { 0x35, 0x0000 },
0120     { 0x3b, 0x0000 },
0121     { 0x3c, 0x007f },
0122     { 0x3d, 0x0000 },
0123     { 0x3e, 0x007f },
0124     { 0x3f, 0x0000 },
0125     { 0x40, 0x001f },
0126     { 0x41, 0x0000 },
0127     { 0x42, 0x001f },
0128     { 0x45, 0x6000 },
0129     { 0x46, 0x003e },
0130     { 0x47, 0x003e },
0131     { 0x48, 0xf807 },
0132     { 0x4a, 0x0004 },
0133     { 0x4d, 0x0000 },
0134     { 0x4e, 0x0000 },
0135     { 0x4f, 0x01ff },
0136     { 0x50, 0x0000 },
0137     { 0x51, 0x0000 },
0138     { 0x52, 0x01ff },
0139     { 0x53, 0xf000 },
0140     { 0x56, 0x0111 },
0141     { 0x57, 0x0064 },
0142     { 0x58, 0xef0e },
0143     { 0x59, 0xf0f0 },
0144     { 0x5a, 0xef0e },
0145     { 0x5b, 0xf0f0 },
0146     { 0x5c, 0xef0e },
0147     { 0x5d, 0xf0f0 },
0148     { 0x5e, 0xf000 },
0149     { 0x5f, 0x0000 },
0150     { 0x61, 0x0300 },
0151     { 0x62, 0x0000 },
0152     { 0x63, 0x00c2 },
0153     { 0x64, 0x0000 },
0154     { 0x65, 0x0000 },
0155     { 0x66, 0x0000 },
0156     { 0x6a, 0x0000 },
0157     { 0x6c, 0x0aaa },
0158     { 0x70, 0x8000 },
0159     { 0x71, 0x8000 },
0160     { 0x72, 0x8000 },
0161     { 0x73, 0x7770 },
0162     { 0x74, 0x3e00 },
0163     { 0x75, 0x2409 },
0164     { 0x76, 0x000a },
0165     { 0x77, 0x0c00 },
0166     { 0x78, 0x0000 },
0167     { 0x79, 0x0123 },
0168     { 0x80, 0x0000 },
0169     { 0x81, 0x0000 },
0170     { 0x82, 0x0000 },
0171     { 0x83, 0x0000 },
0172     { 0x84, 0x0000 },
0173     { 0x85, 0x0000 },
0174     { 0x8a, 0x0120 },
0175     { 0x8e, 0x0004 },
0176     { 0x8f, 0x1100 },
0177     { 0x90, 0x0646 },
0178     { 0x91, 0x0c06 },
0179     { 0x93, 0x0000 },
0180     { 0x94, 0x0200 },
0181     { 0x95, 0x0000 },
0182     { 0x9a, 0x2184 },
0183     { 0x9b, 0x010a },
0184     { 0x9c, 0x0aea },
0185     { 0x9d, 0x000c },
0186     { 0x9e, 0x0400 },
0187     { 0xa0, 0xa0a8 },
0188     { 0xa1, 0x0059 },
0189     { 0xa2, 0x0001 },
0190     { 0xae, 0x6000 },
0191     { 0xaf, 0x0000 },
0192     { 0xb0, 0x6000 },
0193     { 0xb1, 0x0000 },
0194     { 0xb2, 0x0000 },
0195     { 0xb3, 0x001f },
0196     { 0xb4, 0x020c },
0197     { 0xb5, 0x1f00 },
0198     { 0xb6, 0x0000 },
0199     { 0xbb, 0x0000 },
0200     { 0xbc, 0x0000 },
0201     { 0xbd, 0x0000 },
0202     { 0xbe, 0x0000 },
0203     { 0xbf, 0x3100 },
0204     { 0xc0, 0x0000 },
0205     { 0xc1, 0x0000 },
0206     { 0xc2, 0x0000 },
0207     { 0xc3, 0x2000 },
0208     { 0xcd, 0x0000 },
0209     { 0xce, 0x0000 },
0210     { 0xcf, 0x1813 },
0211     { 0xd0, 0x0690 },
0212     { 0xd1, 0x1c17 },
0213     { 0xd3, 0xb320 },
0214     { 0xd4, 0x0000 },
0215     { 0xd6, 0x0400 },
0216     { 0xd9, 0x0809 },
0217     { 0xda, 0x0000 },
0218     { 0xdb, 0x0003 },
0219     { 0xdc, 0x0049 },
0220     { 0xdd, 0x001b },
0221     { 0xdf, 0x0008 },
0222     { 0xe0, 0x4000 },
0223     { 0xe6, 0x8000 },
0224     { 0xe7, 0x0200 },
0225     { 0xec, 0xb300 },
0226     { 0xed, 0x0000 },
0227     { 0xf0, 0x001f },
0228     { 0xf1, 0x020c },
0229     { 0xf2, 0x1f00 },
0230     { 0xf3, 0x0000 },
0231     { 0xf4, 0x4000 },
0232     { 0xf8, 0x0000 },
0233     { 0xf9, 0x0000 },
0234     { 0xfa, 0x2060 },
0235     { 0xfb, 0x4040 },
0236     { 0xfc, 0x0000 },
0237     { 0xfd, 0x0002 },
0238     { 0xfe, 0x10ec },
0239     { 0xff, 0x6308 },
0240 };
0241
0242 static const struct reg_default rt5650_reg[] = {
0243     { 0x00, 0x0000 },
0244     { 0x01, 0xc8c8 },
0245     { 0x02, 0xc8c8 },
0246     { 0x03, 0xc8c8 },
0247     { 0x0a, 0x0002 },
0248     { 0x0b, 0x2827 },
0249     { 0x0c, 0xe000 },
0250     { 0x0d, 0x0000 },
0251     { 0x0e, 0x0000 },
0252     { 0x0f, 0x0808 },
0253     { 0x14, 0x3333 },
0254     { 0x16, 0x4b00 },
0255     { 0x18, 0x018b },
0256     { 0x19, 0xafaf },
0257     { 0x1a, 0xafaf },
0258     { 0x1b, 0x0001 },
0259     { 0x1c, 0x2f2f },
0260     { 0x1d, 0x2f2f },
0261     { 0x1e, 0x0000 },
0262     { 0x20, 0x0000 },
0263     { 0x27, 0x7060 },
0264     { 0x28, 0x7070 },
0265     { 0x29, 0x8080 },
0266     { 0x2a, 0x5656 },
0267     { 0x2b, 0x5454 },
0268     { 0x2c, 0xaaa0 },
0269     { 0x2d, 0x0000 },
0270     { 0x2f, 0x5002 },
0271     { 0x31, 0x5000 },
0272     { 0x32, 0x0000 },
0273     { 0x33, 0x0000 },
0274     { 0x34, 0x0000 },
0275     { 0x35, 0x0000 },
0276     { 0x3b, 0x0000 },
0277     { 0x3c, 0x007f },
0278     { 0x3d, 0x0000 },
0279     { 0x3e, 0x007f },
0280     { 0x3f, 0x0000 },
0281     { 0x40, 0x001f },
0282     { 0x41, 0x0000 },
0283     { 0x42, 0x001f },
0284     { 0x45, 0x6000 },
0285     { 0x46, 0x003e },
0286     { 0x47, 0x003e },
0287     { 0x48, 0xf807 },
0288     { 0x4a, 0x0004 },
0289     { 0x4d, 0x0000 },
0290     { 0x4e, 0x0000 },
0291     { 0x4f, 0x01ff },
0292     { 0x50, 0x0000 },
0293     { 0x51, 0x0000 },
0294     { 0x52, 0x01ff },
0295     { 0x53, 0xf000 },
0296     { 0x56, 0x0111 },
0297     { 0x57, 0x0064 },
0298     { 0x58, 0xef0e },
0299     { 0x59, 0xf0f0 },
0300     { 0x5a, 0xef0e },
0301     { 0x5b, 0xf0f0 },
0302     { 0x5c, 0xef0e },
0303     { 0x5d, 0xf0f0 },
0304     { 0x5e, 0xf000 },
0305     { 0x5f, 0x0000 },
0306     { 0x61, 0x0300 },
0307     { 0x62, 0x0000 },
0308     { 0x63, 0x00c2 },
0309     { 0x64, 0x0000 },
0310     { 0x65, 0x0000 },
0311     { 0x66, 0x0000 },
0312     { 0x6a, 0x0000 },
0313     { 0x6c, 0x0aaa },
0314     { 0x70, 0x8000 },
0315     { 0x71, 0x8000 },
0316     { 0x72, 0x8000 },
0317     { 0x73, 0x7770 },
0318     { 0x74, 0x3e00 },
0319     { 0x75, 0x2409 },
0320     { 0x76, 0x000a },
0321     { 0x77, 0x0c00 },
0322     { 0x78, 0x0000 },
0323     { 0x79, 0x0123 },
0324     { 0x7a, 0x0123 },
0325     { 0x80, 0x0000 },
0326     { 0x81, 0x0000 },
0327     { 0x82, 0x0000 },
0328     { 0x83, 0x0000 },
0329     { 0x84, 0x0000 },
0330     { 0x85, 0x0000 },
0331     { 0x8a, 0x0120 },
0332     { 0x8e, 0x0004 },
0333     { 0x8f, 0x1100 },
0334     { 0x90, 0x0646 },
0335     { 0x91, 0x0c06 },
0336     { 0x93, 0x0000 },
0337     { 0x94, 0x0200 },
0338     { 0x95, 0x0000 },
0339     { 0x9a, 0x2184 },
0340     { 0x9b, 0x010a },
0341     { 0x9c, 0x0aea },
0342     { 0x9d, 0x000c },
0343     { 0x9e, 0x0400 },
0344     { 0xa0, 0xa0a8 },
0345     { 0xa1, 0x0059 },
0346     { 0xa2, 0x0001 },
0347     { 0xae, 0x6000 },
0348     { 0xaf, 0x0000 },
0349     { 0xb0, 0x6000 },
0350     { 0xb1, 0x0000 },
0351     { 0xb2, 0x0000 },
0352     { 0xb3, 0x001f },
0353     { 0xb4, 0x020c },
0354     { 0xb5, 0x1f00 },
0355     { 0xb6, 0x0000 },
0356     { 0xbb, 0x0000 },
0357     { 0xbc, 0x0000 },
0358     { 0xbd, 0x0000 },
0359     { 0xbe, 0x0000 },
0360     { 0xbf, 0x3100 },
0361     { 0xc0, 0x0000 },
0362     { 0xc1, 0x0000 },
0363     { 0xc2, 0x0000 },
0364     { 0xc3, 0x2000 },
0365     { 0xcd, 0x0000 },
0366     { 0xce, 0x0000 },
0367     { 0xcf, 0x1813 },
0368     { 0xd0, 0x0690 },
0369     { 0xd1, 0x1c17 },
0370     { 0xd3, 0xb320 },
0371     { 0xd4, 0x0000 },
0372     { 0xd6, 0x0400 },
0373     { 0xd9, 0x0809 },
0374     { 0xda, 0x0000 },
0375     { 0xdb, 0x0003 },
0376     { 0xdc, 0x0049 },
0377     { 0xdd, 0x001b },
0378     { 0xdf, 0x0008 },
0379     { 0xe0, 0x4000 },
0380     { 0xe6, 0x8000 },
0381     { 0xe7, 0x0200 },
0382     { 0xec, 0xb300 },
0383     { 0xed, 0x0000 },
0384     { 0xf0, 0x001f },
0385     { 0xf1, 0x020c },
0386     { 0xf2, 0x1f00 },
0387     { 0xf3, 0x0000 },
0388     { 0xf4, 0x4000 },
0389     { 0xf8, 0x0000 },
0390     { 0xf9, 0x0000 },
0391     { 0xfa, 0x2060 },
0392     { 0xfb, 0x4040 },
0393     { 0xfc, 0x0000 },
0394     { 0xfd, 0x0002 },
0395     { 0xfe, 0x10ec },
0396     { 0xff, 0x6308 },
0397 };
0398
0399 struct rt5645_eq_param_s {
0400     unsigned short reg;
0401     unsigned short val;
0402 };
0403
0404 struct rt5645_eq_param_s_be16 {
0405     __be16 reg;
0406     __be16 val;
0407 };
0408
0409 static const char *const rt5645_supply_names[] = {
0410     "avdd",
0411     "cpvdd",
0412 };
0413
0414 struct rt5645_platform_data {
0415     /* IN2 can optionally be differential */
0416     bool in2_diff;
0417
0418     unsigned int dmic1_data_pin;
0419     /* 0 = IN2N; 1 = GPIO5; 2 = GPIO11 */
0420     unsigned int dmic2_data_pin;
0421     /* 0 = IN2P; 1 = GPIO6; 2 = GPIO10; 3 = GPIO12 */
0422
0423     unsigned int jd_mode;
0424     /* Use level triggered irq */
0425     bool level_trigger_irq;
0426     /* Invert JD1_1 status polarity */
0427     bool inv_jd1_1;
0428     /* Invert HP detect status polarity */
0429     bool inv_hp_pol;
0430
0431     /* Value to assign to snd_soc_card.long_name */
0432     const char *long_name;
0433
0434     /* Some (package) variants have the headset-mic pin not-connected */
0435     bool no_headset_mic;
0436 };
0437
0438 struct rt5645_priv {
0439     struct snd_soc_component *component;
0440     struct rt5645_platform_data pdata;
0441     struct regmap *regmap;
0442     struct i2c_client *i2c;
0443     struct gpio_desc *gpiod_hp_det;
0444     struct snd_soc_jack *hp_jack;
0445     struct snd_soc_jack *mic_jack;
0446     struct snd_soc_jack *btn_jack;
0447     struct delayed_work jack_detect_work, rcclock_work;
0448     struct regulator_bulk_data supplies[ARRAY_SIZE(rt5645_supply_names)];
0449     struct rt5645_eq_param_s *eq_param;
0450     struct timer_list btn_check_timer;
0451
0452     int codec_type;
0453     int sysclk;
0454     int sysclk_src;
0455     int lrck[RT5645_AIFS];
0456     int bclk[RT5645_AIFS];
0457     int master[RT5645_AIFS];
0458
0459     int pll_src;
0460     int pll_in;
0461     int pll_out;
0462
0463     int jack_type;
0464     bool en_button_func;
0465     int v_id;
0466 };
0467
0468 static int rt5645_reset(struct snd_soc_component *component)
0469 {
0470     return snd_soc_component_write(component, RT5645_RESET, 0);
0471 }
0472
0473 static bool rt5645_volatile_register(struct device *dev, unsigned int reg)
0474 {
0475     int i;
0476
0477     for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
0478         if (reg >= rt5645_ranges[i].range_min &&
0479             reg <= rt5645_ranges[i].range_max) {
0480             return true;
0481         }
0482     }
0483
0484     switch (reg) {
0485     case RT5645_RESET:
0486     case RT5645_PRIV_INDEX:
0487     case RT5645_PRIV_DATA:
0488     case RT5645_IN1_CTRL1:
0489     case RT5645_IN1_CTRL2:
0490     case RT5645_IN1_CTRL3:
0491     case RT5645_A_JD_CTRL1:
0492     case RT5645_ADC_EQ_CTRL1:
0493     case RT5645_EQ_CTRL1:
0494     case RT5645_ALC_CTRL_1:
0495     case RT5645_IRQ_CTRL2:
0496     case RT5645_IRQ_CTRL3:
0497     case RT5645_INT_IRQ_ST:
0498     case RT5645_IL_CMD:
0499     case RT5650_4BTN_IL_CMD1:
0500     case RT5645_VENDOR_ID:
0501     case RT5645_VENDOR_ID1:
0502     case RT5645_VENDOR_ID2:
0503         return true;
0504     default:
0505         return false;
0506     }
0507 }
0508
0509 static bool rt5645_readable_register(struct device *dev, unsigned int reg)
0510 {
0511     int i;
0512
0513     for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
0514         if (reg >= rt5645_ranges[i].range_min &&
0515             reg <= rt5645_ranges[i].range_max) {
0516             return true;
0517         }
0518     }
0519
0520     switch (reg) {
0521     case RT5645_RESET:
0522     case RT5645_SPK_VOL:
0523     case RT5645_HP_VOL:
0524     case RT5645_LOUT1:
0525     case RT5645_IN1_CTRL1:
0526     case RT5645_IN1_CTRL2:
0527     case RT5645_IN1_CTRL3:
0528     case RT5645_IN2_CTRL:
0529     case RT5645_INL1_INR1_VOL:
0530     case RT5645_SPK_FUNC_LIM:
0531     case RT5645_ADJ_HPF_CTRL:
0532     case RT5645_DAC1_DIG_VOL:
0533     case RT5645_DAC2_DIG_VOL:
0534     case RT5645_DAC_CTRL:
0535     case RT5645_STO1_ADC_DIG_VOL:
0536     case RT5645_MONO_ADC_DIG_VOL:
0537     case RT5645_ADC_BST_VOL1:
0538     case RT5645_ADC_BST_VOL2:
0539     case RT5645_STO1_ADC_MIXER:
0540     case RT5645_MONO_ADC_MIXER:
0541     case RT5645_AD_DA_MIXER:
0542     case RT5645_STO_DAC_MIXER:
0543     case RT5645_MONO_DAC_MIXER:
0544     case RT5645_DIG_MIXER:
0545     case RT5650_A_DAC_SOUR:
0546     case RT5645_DIG_INF1_DATA:
0547     case RT5645_PDM_OUT_CTRL:
0548     case RT5645_REC_L1_MIXER:
0549     case RT5645_REC_L2_MIXER:
0550     case RT5645_REC_R1_MIXER:
0551     case RT5645_REC_R2_MIXER:
0552     case RT5645_HPMIXL_CTRL:
0553     case RT5645_HPOMIXL_CTRL:
0554     case RT5645_HPMIXR_CTRL:
0555     case RT5645_HPOMIXR_CTRL:
0556     case RT5645_HPO_MIXER:
0557     case RT5645_SPK_L_MIXER:
0558     case RT5645_SPK_R_MIXER:
0559     case RT5645_SPO_MIXER:
0560     case RT5645_SPO_CLSD_RATIO:
0561     case RT5645_OUT_L1_MIXER:
0562     case RT5645_OUT_R1_MIXER:
0563     case RT5645_OUT_L_GAIN1:
0564     case RT5645_OUT_L_GAIN2:
0565     case RT5645_OUT_R_GAIN1:
0566     case RT5645_OUT_R_GAIN2:
0567     case RT5645_LOUT_MIXER:
0568     case RT5645_HAPTIC_CTRL1:
0569     case RT5645_HAPTIC_CTRL2:
0570     case RT5645_HAPTIC_CTRL3:
0571     case RT5645_HAPTIC_CTRL4:
0572     case RT5645_HAPTIC_CTRL5:
0573     case RT5645_HAPTIC_CTRL6:
0574     case RT5645_HAPTIC_CTRL7:
0575     case RT5645_HAPTIC_CTRL8:
0576     case RT5645_HAPTIC_CTRL9:
0577     case RT5645_HAPTIC_CTRL10:
0578     case RT5645_PWR_DIG1:
0579     case RT5645_PWR_DIG2:
0580     case RT5645_PWR_ANLG1:
0581     case RT5645_PWR_ANLG2:
0582     case RT5645_PWR_MIXER:
0583     case RT5645_PWR_VOL:
0584     case RT5645_PRIV_INDEX:
0585     case RT5645_PRIV_DATA:
0586     case RT5645_I2S1_SDP:
0587     case RT5645_I2S2_SDP:
0588     case RT5645_ADDA_CLK1:
0589     case RT5645_ADDA_CLK2:
0590     case RT5645_DMIC_CTRL1:
0591     case RT5645_DMIC_CTRL2:
0592     case RT5645_TDM_CTRL_1:
0593     case RT5645_TDM_CTRL_2:
0594     case RT5645_TDM_CTRL_3:
0595     case RT5650_TDM_CTRL_4:
0596     case RT5645_GLB_CLK:
0597     case RT5645_PLL_CTRL1:
0598     case RT5645_PLL_CTRL2:
0599     case RT5645_ASRC_1:
0600     case RT5645_ASRC_2:
0601     case RT5645_ASRC_3:
0602     case RT5645_ASRC_4:
0603     case RT5645_DEPOP_M1:
0604     case RT5645_DEPOP_M2:
0605     case RT5645_DEPOP_M3:
0606     case RT5645_CHARGE_PUMP:
0607     case RT5645_MICBIAS:
0608     case RT5645_A_JD_CTRL1:
0609     case RT5645_VAD_CTRL4:
0610     case RT5645_CLSD_OUT_CTRL:
0611     case RT5645_ADC_EQ_CTRL1:
0612     case RT5645_ADC_EQ_CTRL2:
0613     case RT5645_EQ_CTRL1:
0614     case RT5645_EQ_CTRL2:
0615     case RT5645_ALC_CTRL_1:
0616     case RT5645_ALC_CTRL_2:
0617     case RT5645_ALC_CTRL_3:
0618     case RT5645_ALC_CTRL_4:
0619     case RT5645_ALC_CTRL_5:
0620     case RT5645_JD_CTRL:
0621     case RT5645_IRQ_CTRL1:
0622     case RT5645_IRQ_CTRL2:
0623     case RT5645_IRQ_CTRL3:
0624     case RT5645_INT_IRQ_ST:
0625     case RT5645_GPIO_CTRL1:
0626     case RT5645_GPIO_CTRL2:
0627     case RT5645_GPIO_CTRL3:
0628     case RT5645_BASS_BACK:
0629     case RT5645_MP3_PLUS1:
0630     case RT5645_MP3_PLUS2:
0631     case RT5645_ADJ_HPF1:
0632     case RT5645_ADJ_HPF2:
0633     case RT5645_HP_CALIB_AMP_DET:
0634     case RT5645_SV_ZCD1:
0635     case RT5645_SV_ZCD2:
0636     case RT5645_IL_CMD:
0637     case RT5645_IL_CMD2:
0638     case RT5645_IL_CMD3:
0639     case RT5650_4BTN_IL_CMD1:
0640     case RT5650_4BTN_IL_CMD2:
0641     case RT5645_DRC1_HL_CTRL1:
0642     case RT5645_DRC2_HL_CTRL1:
0643     case RT5645_ADC_MONO_HP_CTRL1:
0644     case RT5645_ADC_MONO_HP_CTRL2:
0645     case RT5645_DRC2_CTRL1:
0646     case RT5645_DRC2_CTRL2:
0647     case RT5645_DRC2_CTRL3:
0648     case RT5645_DRC2_CTRL4:
0649     case RT5645_DRC2_CTRL5:
0650     case RT5645_JD_CTRL3:
0651     case RT5645_JD_CTRL4:
0652     case RT5645_GEN_CTRL1:
0653     case RT5645_GEN_CTRL2:
0654     case RT5645_GEN_CTRL3:
0655     case RT5645_VENDOR_ID:
0656     case RT5645_VENDOR_ID1:
0657     case RT5645_VENDOR_ID2:
0658         return true;
0659     default:
0660         return false;
0661     }
0662 }
0663
0664 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
0665 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
0666 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
0667 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
0668 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
0669
0670 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
0671 static const DECLARE_TLV_DB_RANGE(bst_tlv,
0672     0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
0673     1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
0674     2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
0675     3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
0676     6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
0677     7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
0678     8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
0679 );
0680
0681 /* {-6, -4.5, -3, -1.5, 0, 0.82, 1.58, 2.28} dB */
0682 static const DECLARE_TLV_DB_RANGE(spk_clsd_tlv,
0683     0, 4, TLV_DB_SCALE_ITEM(-600, 150, 0),
0684     5, 5, TLV_DB_SCALE_ITEM(82, 0, 0),
0685     6, 6, TLV_DB_SCALE_ITEM(158, 0, 0),
0686     7, 7, TLV_DB_SCALE_ITEM(228, 0, 0)
0687 );
0688
0689 static int rt5645_hweq_info(struct snd_kcontrol *kcontrol,
0690              struct snd_ctl_elem_info *uinfo)
0691 {
0692     uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
0693     uinfo->count = RT5645_HWEQ_NUM * sizeof(struct rt5645_eq_param_s);
0694
0695     return 0;
0696 }
0697
0698 static int rt5645_hweq_get(struct snd_kcontrol *kcontrol,
0699             struct snd_ctl_elem_value *ucontrol)
0700 {
0701     struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
0702     struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
0703     struct rt5645_eq_param_s_be16 *eq_param =
0704         (struct rt5645_eq_param_s_be16 *)ucontrol->value.bytes.data;
0705     int i;
0706
0707     for (i = 0; i < RT5645_HWEQ_NUM; i++) {
0708         eq_param[i].reg = cpu_to_be16(rt5645->eq_param[i].reg);
0709         eq_param[i].val = cpu_to_be16(rt5645->eq_param[i].val);
0710     }
0711
0712     return 0;
0713 }
0714
0715 static bool rt5645_validate_hweq(unsigned short reg)
0716 {
0717     if ((reg >= 0x1a4 && reg <= 0x1cd) || (reg >= 0x1e5 && reg <= 0x1f8) ||
0718         (reg == RT5645_EQ_CTRL2))
0719         return true;
0720
0721     return false;
0722 }
0723
0724 static int rt5645_hweq_put(struct snd_kcontrol *kcontrol,
0725             struct snd_ctl_elem_value *ucontrol)
0726 {
0727     struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
0728     struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
0729     struct rt5645_eq_param_s_be16 *eq_param =
0730         (struct rt5645_eq_param_s_be16 *)ucontrol->value.bytes.data;
0731     int i;
0732
0733     for (i = 0; i < RT5645_HWEQ_NUM; i++) {
0734         rt5645->eq_param[i].reg = be16_to_cpu(eq_param[i].reg);
0735         rt5645->eq_param[i].val = be16_to_cpu(eq_param[i].val);
0736     }
0737
0738     /* The final setting of the table should be RT5645_EQ_CTRL2 */
0739     for (i = RT5645_HWEQ_NUM - 1; i >= 0; i--) {
0740         if (rt5645->eq_param[i].reg == 0)
0741             continue;
0742         else if (rt5645->eq_param[i].reg != RT5645_EQ_CTRL2)
0743             return 0;
0744         else
0745             break;
0746     }
0747
0748     for (i = 0; i < RT5645_HWEQ_NUM; i++) {
0749         if (!rt5645_validate_hweq(rt5645->eq_param[i].reg) &&
0750             rt5645->eq_param[i].reg != 0)
0751             return 0;
0752         else if (rt5645->eq_param[i].reg == 0)
0753             break;
0754     }
0755
0756     return 0;
0757 }
0758
0759 #define RT5645_HWEQ(xname) \
0760 {   .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
0761     .info = rt5645_hweq_info, \
0762     .get = rt5645_hweq_get, \
0763     .put = rt5645_hweq_put \
0764 }
0765
0766 static int rt5645_spk_put_volsw(struct snd_kcontrol *kcontrol,
0767         struct snd_ctl_elem_value *ucontrol)
0768 {
0769     struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
0770     struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
0771     int ret;
0772
0773     regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
0774         RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PU);
0775
0776     ret = snd_soc_put_volsw(kcontrol, ucontrol);
0777
0778     mod_delayed_work(system_power_efficient_wq, &rt5645->rcclock_work,
0779         msecs_to_jiffies(200));
0780
0781     return ret;
0782 }
0783
0784 static const char * const rt5645_dac1_vol_ctrl_mode_text[] = {
0785     "immediately", "zero crossing", "soft ramp"
0786 };
0787
0788 static SOC_ENUM_SINGLE_DECL(
0789     rt5645_dac1_vol_ctrl_mode, RT5645_PR_BASE,
0790     RT5645_DA1_ZDET_SFT, rt5645_dac1_vol_ctrl_mode_text);
0791
0792 static const struct snd_kcontrol_new rt5645_snd_controls[] = {
0793     /* Speaker Output Volume */
0794     SOC_DOUBLE("Speaker Channel Switch", RT5645_SPK_VOL,
0795         RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
0796     SOC_DOUBLE_EXT_TLV("Speaker Playback Volume", RT5645_SPK_VOL,
0797         RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, snd_soc_get_volsw,
0798         rt5645_spk_put_volsw, out_vol_tlv),
0799
0800     /* ClassD modulator Speaker Gain Ratio */
0801     SOC_SINGLE_TLV("Speaker ClassD Playback Volume", RT5645_SPO_CLSD_RATIO,
0802         RT5645_SPK_G_CLSD_SFT, 7, 0, spk_clsd_tlv),
0803
0804     /* Headphone Output Volume */
0805     SOC_DOUBLE("Headphone Channel Switch", RT5645_HP_VOL,
0806         RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
0807     SOC_DOUBLE_TLV("Headphone Playback Volume", RT5645_HP_VOL,
0808         RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
0809
0810     /* OUTPUT Control */
0811     SOC_DOUBLE("OUT Playback Switch", RT5645_LOUT1,
0812         RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
0813     SOC_DOUBLE("OUT Channel Switch", RT5645_LOUT1,
0814         RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
0815     SOC_DOUBLE_TLV("OUT Playback Volume", RT5645_LOUT1,
0816         RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
0817
0818     /* DAC Digital Volume */
0819     SOC_DOUBLE("DAC2 Playback Switch", RT5645_DAC_CTRL,
0820         RT5645_M_DAC_L2_VOL_SFT, RT5645_M_DAC_R2_VOL_SFT, 1, 1),
0821     SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5645_DAC1_DIG_VOL,
0822         RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
0823     SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5645_DAC2_DIG_VOL,
0824         RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
0825
0826     /* IN1/IN2 Control */
0827     SOC_SINGLE_TLV("IN1 Boost", RT5645_IN1_CTRL1,
0828         RT5645_BST_SFT1, 12, 0, bst_tlv),
0829     SOC_SINGLE_TLV("IN2 Boost", RT5645_IN2_CTRL,
0830         RT5645_BST_SFT2, 8, 0, bst_tlv),
0831
0832     /* INL/INR Volume Control */
0833     SOC_DOUBLE_TLV("IN Capture Volume", RT5645_INL1_INR1_VOL,
0834         RT5645_INL_VOL_SFT, RT5645_INR_VOL_SFT, 31, 1, in_vol_tlv),
0835
0836     /* ADC Digital Volume Control */
0837     SOC_DOUBLE("ADC Capture Switch", RT5645_STO1_ADC_DIG_VOL,
0838         RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
0839     SOC_DOUBLE_TLV("ADC Capture Volume", RT5645_STO1_ADC_DIG_VOL,
0840         RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
0841     SOC_DOUBLE("Mono ADC Capture Switch", RT5645_MONO_ADC_DIG_VOL,
0842         RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
0843     SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5645_MONO_ADC_DIG_VOL,
0844         RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
0845
0846     /* ADC Boost Volume Control */
0847     SOC_DOUBLE_TLV("ADC Boost Capture Volume", RT5645_ADC_BST_VOL1,
0848         RT5645_STO1_ADC_L_BST_SFT, RT5645_STO1_ADC_R_BST_SFT, 3, 0,
0849         adc_bst_tlv),
0850     SOC_DOUBLE_TLV("Mono ADC Boost Capture Volume", RT5645_ADC_BST_VOL2,
0851         RT5645_MONO_ADC_L_BST_SFT, RT5645_MONO_ADC_R_BST_SFT, 3, 0,
0852         adc_bst_tlv),
0853
0854     /* I2S2 function select */
0855     SOC_SINGLE("I2S2 Func Switch", RT5645_GPIO_CTRL1, RT5645_I2S2_SEL_SFT,
0856         1, 1),
0857     RT5645_HWEQ("Speaker HWEQ"),
0858
0859     /* Digital Soft Volume Control */
0860     SOC_ENUM("DAC1 Digital Volume Control Func", rt5645_dac1_vol_ctrl_mode),
0861 };
0862
0863 /**
0864  * set_dmic_clk - Set parameter of dmic.
0865  *
0866  * @w: DAPM widget.
0867  * @kcontrol: The kcontrol of this widget.
0868  * @event: Event id.
0869  *
0870  */
0871 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
0872     struct snd_kcontrol *kcontrol, int event)
0873 {
0874     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0875     struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
0876     int idx, rate;
0877
0878     rate = rt5645->sysclk / rl6231_get_pre_div(rt5645->regmap,
0879         RT5645_ADDA_CLK1, RT5645_I2S_PD1_SFT);
0880     idx = rl6231_calc_dmic_clk(rate);
0881     if (idx < 0)
0882         dev_err(component->dev, "Failed to set DMIC clock\n");
0883     else
0884         snd_soc_component_update_bits(component, RT5645_DMIC_CTRL1,
0885             RT5645_DMIC_CLK_MASK, idx << RT5645_DMIC_CLK_SFT);
0886     return idx;
0887 }
0888
0889 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
0890              struct snd_soc_dapm_widget *sink)
0891 {
0892     struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
0893     unsigned int val;
0894
0895     val = snd_soc_component_read(component, RT5645_GLB_CLK);
0896     val &= RT5645_SCLK_SRC_MASK;
0897     if (val == RT5645_SCLK_SRC_PLL1)
0898         return 1;
0899     else
0900         return 0;
0901 }
0902
0903 static int is_using_asrc(struct snd_soc_dapm_widget *source,
0904              struct snd_soc_dapm_widget *sink)
0905 {
0906     struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
0907     unsigned int reg, shift, val;
0908
0909     switch (source->shift) {
0910     case 0:
0911         reg = RT5645_ASRC_3;
0912         shift = 0;
0913         break;
0914     case 1:
0915         reg = RT5645_ASRC_3;
0916         shift = 4;
0917         break;
0918     case 3:
0919         reg = RT5645_ASRC_2;
0920         shift = 0;
0921         break;
0922     case 8:
0923         reg = RT5645_ASRC_2;
0924         shift = 4;
0925         break;
0926     case 9:
0927         reg = RT5645_ASRC_2;
0928         shift = 8;
0929         break;
0930     case 10:
0931         reg = RT5645_ASRC_2;
0932         shift = 12;
0933         break;
0934     default:
0935         return 0;
0936     }
0937
0938     val = (snd_soc_component_read(component, reg) >> shift) & 0xf;
0939     switch (val) {
0940     case 1:
0941     case 2:
0942     case 3:
0943     case 4:
0944         return 1;
0945     default:
0946         return 0;
0947     }
0948
0949 }
0950
0951 static int rt5645_enable_hweq(struct snd_soc_component *component)
0952 {
0953     struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
0954     int i;
0955
0956     for (i = 0; i < RT5645_HWEQ_NUM; i++) {
0957         if (rt5645_validate_hweq(rt5645->eq_param[i].reg))
0958             regmap_write(rt5645->regmap, rt5645->eq_param[i].reg,
0959                     rt5645->eq_param[i].val);
0960         else
0961             break;
0962     }
0963
0964     return 0;
0965 }
0966
0967 /**
0968  * rt5645_sel_asrc_clk_src - select ASRC clock source for a set of filters
0969  * @component: SoC audio component device.
0970  * @filter_mask: mask of filters.
0971  * @clk_src: clock source
0972  *
0973  * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5645 can
0974  * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
0975  * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
0976  * ASRC function will track i2s clock and generate a corresponding system clock
0977  * for codec. This function provides an API to select the clock source for a
0978  * set of filters specified by the mask. And the codec driver will turn on ASRC
0979  * for these filters if ASRC is selected as their clock source.
0980  */
0981 int rt5645_sel_asrc_clk_src(struct snd_soc_component *component,
0982         unsigned int filter_mask, unsigned int clk_src)
0983 {
0984     unsigned int asrc2_mask = 0;
0985     unsigned int asrc2_value = 0;
0986     unsigned int asrc3_mask = 0;
0987     unsigned int asrc3_value = 0;
0988
0989     switch (clk_src) {
0990     case RT5645_CLK_SEL_SYS:
0991     case RT5645_CLK_SEL_I2S1_ASRC:
0992     case RT5645_CLK_SEL_I2S2_ASRC:
0993     case RT5645_CLK_SEL_SYS2:
0994         break;
0995
0996     default:
0997         return -EINVAL;
0998     }
0999
1000     if (filter_mask & RT5645_DA_STEREO_FILTER) {
1001         asrc2_mask |= RT5645_DA_STO_CLK_SEL_MASK;
1002         asrc2_value = (asrc2_value & ~RT5645_DA_STO_CLK_SEL_MASK)
1003             | (clk_src << RT5645_DA_STO_CLK_SEL_SFT);
1004     }
1005
1006     if (filter_mask & RT5645_DA_MONO_L_FILTER) {
1007         asrc2_mask |= RT5645_DA_MONOL_CLK_SEL_MASK;
1008         asrc2_value = (asrc2_value & ~RT5645_DA_MONOL_CLK_SEL_MASK)
1009             | (clk_src << RT5645_DA_MONOL_CLK_SEL_SFT);
1010     }
1011
1012     if (filter_mask & RT5645_DA_MONO_R_FILTER) {
1013         asrc2_mask |= RT5645_DA_MONOR_CLK_SEL_MASK;
1014         asrc2_value = (asrc2_value & ~RT5645_DA_MONOR_CLK_SEL_MASK)
1015             | (clk_src << RT5645_DA_MONOR_CLK_SEL_SFT);
1016     }
1017
1018     if (filter_mask & RT5645_AD_STEREO_FILTER) {
1019         asrc2_mask |= RT5645_AD_STO1_CLK_SEL_MASK;
1020         asrc2_value = (asrc2_value & ~RT5645_AD_STO1_CLK_SEL_MASK)
1021             | (clk_src << RT5645_AD_STO1_CLK_SEL_SFT);
1022     }
1023
1024     if (filter_mask & RT5645_AD_MONO_L_FILTER) {
1025         asrc3_mask |= RT5645_AD_MONOL_CLK_SEL_MASK;
1026         asrc3_value = (asrc3_value & ~RT5645_AD_MONOL_CLK_SEL_MASK)
1027             | (clk_src << RT5645_AD_MONOL_CLK_SEL_SFT);
1028     }
1029
1030     if (filter_mask & RT5645_AD_MONO_R_FILTER)  {
1031         asrc3_mask |= RT5645_AD_MONOR_CLK_SEL_MASK;
1032         asrc3_value = (asrc3_value & ~RT5645_AD_MONOR_CLK_SEL_MASK)
1033             | (clk_src << RT5645_AD_MONOR_CLK_SEL_SFT);
1034     }
1035
1036     if (asrc2_mask)
1037         snd_soc_component_update_bits(component, RT5645_ASRC_2,
1038             asrc2_mask, asrc2_value);
1039
1040     if (asrc3_mask)
1041         snd_soc_component_update_bits(component, RT5645_ASRC_3,
1042             asrc3_mask, asrc3_value);
1043
1044     return 0;
1045 }
1046 EXPORT_SYMBOL_GPL(rt5645_sel_asrc_clk_src);
1047
1048 /* Digital Mixer */
1049 static const struct snd_kcontrol_new rt5645_sto1_adc_l_mix[] = {
1050     SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
1051             RT5645_M_ADC_L1_SFT, 1, 1),
1052     SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
1053             RT5645_M_ADC_L2_SFT, 1, 1),
1054 };
1055
1056 static const struct snd_kcontrol_new rt5645_sto1_adc_r_mix[] = {
1057     SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
1058             RT5645_M_ADC_R1_SFT, 1, 1),
1059     SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
1060             RT5645_M_ADC_R2_SFT, 1, 1),
1061 };
1062
1063 static const struct snd_kcontrol_new rt5645_mono_adc_l_mix[] = {
1064     SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
1065             RT5645_M_MONO_ADC_L1_SFT, 1, 1),
1066     SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
1067             RT5645_M_MONO_ADC_L2_SFT, 1, 1),
1068 };
1069
1070 static const struct snd_kcontrol_new rt5645_mono_adc_r_mix[] = {
1071     SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
1072             RT5645_M_MONO_ADC_R1_SFT, 1, 1),
1073     SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
1074             RT5645_M_MONO_ADC_R2_SFT, 1, 1),
1075 };
1076
1077 static const struct snd_kcontrol_new rt5645_dac_l_mix[] = {
1078     SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
1079             RT5645_M_ADCMIX_L_SFT, 1, 1),
1080     SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER,
1081             RT5645_M_DAC1_L_SFT, 1, 1),
1082 };
1083
1084 static const struct snd_kcontrol_new rt5645_dac_r_mix[] = {
1085     SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
1086             RT5645_M_ADCMIX_R_SFT, 1, 1),
1087     SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER,
1088             RT5645_M_DAC1_R_SFT, 1, 1),
1089 };
1090
1091 static const struct snd_kcontrol_new rt5645_sto_dac_l_mix[] = {
1092     SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
1093             RT5645_M_DAC_L1_SFT, 1, 1),
1094     SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_STO_DAC_MIXER,
1095             RT5645_M_DAC_L2_SFT, 1, 1),
1096     SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
1097             RT5645_M_DAC_R1_STO_L_SFT, 1, 1),
1098 };
1099
1100 static const struct snd_kcontrol_new rt5645_sto_dac_r_mix[] = {
1101     SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
1102             RT5645_M_DAC_R1_SFT, 1, 1),
1103     SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_STO_DAC_MIXER,
1104             RT5645_M_DAC_R2_SFT, 1, 1),
1105     SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
1106             RT5645_M_DAC_L1_STO_R_SFT, 1, 1),
1107 };
1108
1109 static const struct snd_kcontrol_new rt5645_mono_dac_l_mix[] = {
1110     SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_MONO_DAC_MIXER,
1111             RT5645_M_DAC_L1_MONO_L_SFT, 1, 1),
1112     SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
1113             RT5645_M_DAC_L2_MONO_L_SFT, 1, 1),
1114     SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
1115             RT5645_M_DAC_R2_MONO_L_SFT, 1, 1),
1116 };
1117
1118 static const struct snd_kcontrol_new rt5645_mono_dac_r_mix[] = {
1119     SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_MONO_DAC_MIXER,
1120             RT5645_M_DAC_R1_MONO_R_SFT, 1, 1),
1121     SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
1122             RT5645_M_DAC_R2_MONO_R_SFT, 1, 1),
1123     SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
1124             RT5645_M_DAC_L2_MONO_R_SFT, 1, 1),
1125 };
1126
1127 static const struct snd_kcontrol_new rt5645_dig_l_mix[] = {
1128     SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5645_DIG_MIXER,
1129             RT5645_M_STO_L_DAC_L_SFT, 1, 1),
1130     SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
1131             RT5645_M_DAC_L2_DAC_L_SFT, 1, 1),
1132     SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
1133             RT5645_M_DAC_R2_DAC_L_SFT, 1, 1),
1134 };
1135
1136 static const struct snd_kcontrol_new rt5645_dig_r_mix[] = {
1137     SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5645_DIG_MIXER,
1138             RT5645_M_STO_R_DAC_R_SFT, 1, 1),
1139     SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
1140             RT5645_M_DAC_R2_DAC_R_SFT, 1, 1),
1141     SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
1142             RT5645_M_DAC_L2_DAC_R_SFT, 1, 1),
1143 };
1144
1145 /* Analog Input Mixer */
1146 static const struct snd_kcontrol_new rt5645_rec_l_mix[] = {
1147     SOC_DAPM_SINGLE("HPOL Switch", RT5645_REC_L2_MIXER,
1148             RT5645_M_HP_L_RM_L_SFT, 1, 1),
1149     SOC_DAPM_SINGLE("INL Switch", RT5645_REC_L2_MIXER,
1150             RT5645_M_IN_L_RM_L_SFT, 1, 1),
1151     SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_L2_MIXER,
1152             RT5645_M_BST2_RM_L_SFT, 1, 1),
1153     SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_L2_MIXER,
1154             RT5645_M_BST1_RM_L_SFT, 1, 1),
1155     SOC_DAPM_SINGLE("OUT MIXL Switch", RT5645_REC_L2_MIXER,
1156             RT5645_M_OM_L_RM_L_SFT, 1, 1),
1157 };
1158
1159 static const struct snd_kcontrol_new rt5645_rec_r_mix[] = {
1160     SOC_DAPM_SINGLE("HPOR Switch", RT5645_REC_R2_MIXER,
1161             RT5645_M_HP_R_RM_R_SFT, 1, 1),
1162     SOC_DAPM_SINGLE("INR Switch", RT5645_REC_R2_MIXER,
1163             RT5645_M_IN_R_RM_R_SFT, 1, 1),
1164     SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_R2_MIXER,
1165             RT5645_M_BST2_RM_R_SFT, 1, 1),
1166     SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_R2_MIXER,
1167             RT5645_M_BST1_RM_R_SFT, 1, 1),
1168     SOC_DAPM_SINGLE("OUT MIXR Switch", RT5645_REC_R2_MIXER,
1169             RT5645_M_OM_R_RM_R_SFT, 1, 1),
1170 };
1171
1172 static const struct snd_kcontrol_new rt5645_spk_l_mix[] = {
1173     SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPK_L_MIXER,
1174             RT5645_M_DAC_L1_SM_L_SFT, 1, 1),
1175     SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_SPK_L_MIXER,
1176             RT5645_M_DAC_L2_SM_L_SFT, 1, 1),
1177     SOC_DAPM_SINGLE("INL Switch", RT5645_SPK_L_MIXER,
1178             RT5645_M_IN_L_SM_L_SFT, 1, 1),
1179     SOC_DAPM_SINGLE("BST1 Switch", RT5645_SPK_L_MIXER,
1180             RT5645_M_BST1_L_SM_L_SFT, 1, 1),
1181 };
1182
1183 static const struct snd_kcontrol_new rt5645_spk_r_mix[] = {
1184     SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPK_R_MIXER,
1185             RT5645_M_DAC_R1_SM_R_SFT, 1, 1),
1186     SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_SPK_R_MIXER,
1187             RT5645_M_DAC_R2_SM_R_SFT, 1, 1),
1188     SOC_DAPM_SINGLE("INR Switch", RT5645_SPK_R_MIXER,
1189             RT5645_M_IN_R_SM_R_SFT, 1, 1),
1190     SOC_DAPM_SINGLE("BST2 Switch", RT5645_SPK_R_MIXER,
1191             RT5645_M_BST2_R_SM_R_SFT, 1, 1),
1192 };
1193
1194 static const struct snd_kcontrol_new rt5645_out_l_mix[] = {
1195     SOC_DAPM_SINGLE("BST1 Switch", RT5645_OUT_L1_MIXER,
1196             RT5645_M_BST1_OM_L_SFT, 1, 1),
1197     SOC_DAPM_SINGLE("INL Switch", RT5645_OUT_L1_MIXER,
1198             RT5645_M_IN_L_OM_L_SFT, 1, 1),
1199     SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_OUT_L1_MIXER,
1200             RT5645_M_DAC_L2_OM_L_SFT, 1, 1),
1201     SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_OUT_L1_MIXER,
1202             RT5645_M_DAC_L1_OM_L_SFT, 1, 1),
1203 };
1204
1205 static const struct snd_kcontrol_new rt5645_out_r_mix[] = {
1206     SOC_DAPM_SINGLE("BST2 Switch", RT5645_OUT_R1_MIXER,
1207             RT5645_M_BST2_OM_R_SFT, 1, 1),
1208     SOC_DAPM_SINGLE("INR Switch", RT5645_OUT_R1_MIXER,
1209             RT5645_M_IN_R_OM_R_SFT, 1, 1),
1210     SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_OUT_R1_MIXER,
1211             RT5645_M_DAC_R2_OM_R_SFT, 1, 1),
1212     SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_OUT_R1_MIXER,
1213             RT5645_M_DAC_R1_OM_R_SFT, 1, 1),
1214 };
1215
1216 static const struct snd_kcontrol_new rt5645_spo_l_mix[] = {
1217     SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
1218             RT5645_M_DAC_R1_SPM_L_SFT, 1, 1),
1219     SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPO_MIXER,
1220             RT5645_M_DAC_L1_SPM_L_SFT, 1, 1),
1221     SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
1222             RT5645_M_SV_R_SPM_L_SFT, 1, 1),
1223     SOC_DAPM_SINGLE("SPKVOL L Switch", RT5645_SPO_MIXER,
1224             RT5645_M_SV_L_SPM_L_SFT, 1, 1),
1225 };
1226
1227 static const struct snd_kcontrol_new rt5645_spo_r_mix[] = {
1228     SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
1229             RT5645_M_DAC_R1_SPM_R_SFT, 1, 1),
1230     SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
1231             RT5645_M_SV_R_SPM_R_SFT, 1, 1),
1232 };
1233
1234 static const struct snd_kcontrol_new rt5645_hpo_mix[] = {
1235     SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPO_MIXER,
1236             RT5645_M_DAC1_HM_SFT, 1, 1),
1237     SOC_DAPM_SINGLE("HPVOL Switch", RT5645_HPO_MIXER,
1238             RT5645_M_HPVOL_HM_SFT, 1, 1),
1239 };
1240
1241 static const struct snd_kcontrol_new rt5645_hpvoll_mix[] = {
1242     SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXL_CTRL,
1243             RT5645_M_DAC1_HV_SFT, 1, 1),
1244     SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXL_CTRL,
1245             RT5645_M_DAC2_HV_SFT, 1, 1),
1246     SOC_DAPM_SINGLE("INL Switch", RT5645_HPOMIXL_CTRL,
1247             RT5645_M_IN_HV_SFT, 1, 1),
1248     SOC_DAPM_SINGLE("BST1 Switch", RT5645_HPOMIXL_CTRL,
1249             RT5645_M_BST1_HV_SFT, 1, 1),
1250 };
1251
1252 static const struct snd_kcontrol_new rt5645_hpvolr_mix[] = {
1253     SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXR_CTRL,
1254             RT5645_M_DAC1_HV_SFT, 1, 1),
1255     SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXR_CTRL,
1256             RT5645_M_DAC2_HV_SFT, 1, 1),
1257     SOC_DAPM_SINGLE("INR Switch", RT5645_HPOMIXR_CTRL,
1258             RT5645_M_IN_HV_SFT, 1, 1),
1259     SOC_DAPM_SINGLE("BST2 Switch", RT5645_HPOMIXR_CTRL,
1260             RT5645_M_BST2_HV_SFT, 1, 1),
1261 };
1262
1263 static const struct snd_kcontrol_new rt5645_lout_mix[] = {
1264     SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_LOUT_MIXER,
1265             RT5645_M_DAC_L1_LM_SFT, 1, 1),
1266     SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_LOUT_MIXER,
1267             RT5645_M_DAC_R1_LM_SFT, 1, 1),
1268     SOC_DAPM_SINGLE("OUTMIX L Switch", RT5645_LOUT_MIXER,
1269             RT5645_M_OV_L_LM_SFT, 1, 1),
1270     SOC_DAPM_SINGLE("OUTMIX R Switch", RT5645_LOUT_MIXER,
1271             RT5645_M_OV_R_LM_SFT, 1, 1),
1272 };
1273
1274 /*DAC1 L/R source*/ /* MX-29 [9:8] [11:10] */
1275 static const char * const rt5645_dac1_src[] = {
1276     "IF1 DAC", "IF2 DAC", "IF3 DAC"
1277 };
1278
1279 static SOC_ENUM_SINGLE_DECL(
1280     rt5645_dac1l_enum, RT5645_AD_DA_MIXER,
1281     RT5645_DAC1_L_SEL_SFT, rt5645_dac1_src);
1282
1283 static const struct snd_kcontrol_new rt5645_dac1l_mux =
1284     SOC_DAPM_ENUM("DAC1 L source", rt5645_dac1l_enum);
1285
1286 static SOC_ENUM_SINGLE_DECL(
1287     rt5645_dac1r_enum, RT5645_AD_DA_MIXER,
1288     RT5645_DAC1_R_SEL_SFT, rt5645_dac1_src);
1289
1290 static const struct snd_kcontrol_new rt5645_dac1r_mux =
1291     SOC_DAPM_ENUM("DAC1 R source", rt5645_dac1r_enum);
1292
1293 /*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */
1294 static const char * const rt5645_dac12_src[] = {
1295     "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "VAD_ADC"
1296 };
1297
1298 static SOC_ENUM_SINGLE_DECL(
1299     rt5645_dac2l_enum, RT5645_DAC_CTRL,
1300     RT5645_DAC2_L_SEL_SFT, rt5645_dac12_src);
1301
1302 static const struct snd_kcontrol_new rt5645_dac_l2_mux =
1303     SOC_DAPM_ENUM("DAC2 L source", rt5645_dac2l_enum);
1304
1305 static const char * const rt5645_dacr2_src[] = {
1306     "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "Haptic"
1307 };
1308
1309 static SOC_ENUM_SINGLE_DECL(
1310     rt5645_dac2r_enum, RT5645_DAC_CTRL,
1311     RT5645_DAC2_R_SEL_SFT, rt5645_dacr2_src);
1312
1313 static const struct snd_kcontrol_new rt5645_dac_r2_mux =
1314     SOC_DAPM_ENUM("DAC2 R source", rt5645_dac2r_enum);
1315
1316 /* Stereo1 ADC source */
1317 /* MX-27 [12] */
1318 static const char * const rt5645_stereo_adc1_src[] = {
1319     "DAC MIX", "ADC"
1320 };
1321
1322 static SOC_ENUM_SINGLE_DECL(
1323     rt5645_stereo1_adc1_enum, RT5645_STO1_ADC_MIXER,
1324     RT5645_ADC_1_SRC_SFT, rt5645_stereo_adc1_src);
1325
1326 static const struct snd_kcontrol_new rt5645_sto_adc1_mux =
1327     SOC_DAPM_ENUM("Stereo1 ADC1 Mux", rt5645_stereo1_adc1_enum);
1328
1329 /* MX-27 [11] */
1330 static const char * const rt5645_stereo_adc2_src[] = {
1331     "DAC MIX", "DMIC"
1332 };
1333
1334 static SOC_ENUM_SINGLE_DECL(
1335     rt5645_stereo1_adc2_enum, RT5645_STO1_ADC_MIXER,
1336     RT5645_ADC_2_SRC_SFT, rt5645_stereo_adc2_src);
1337
1338 static const struct snd_kcontrol_new rt5645_sto_adc2_mux =
1339     SOC_DAPM_ENUM("Stereo1 ADC2 Mux", rt5645_stereo1_adc2_enum);
1340
1341 /* MX-27 [8] */
1342 static const char * const rt5645_stereo_dmic_src[] = {
1343     "DMIC1", "DMIC2"
1344 };
1345
1346 static SOC_ENUM_SINGLE_DECL(
1347     rt5645_stereo1_dmic_enum, RT5645_STO1_ADC_MIXER,
1348     RT5645_DMIC_SRC_SFT, rt5645_stereo_dmic_src);
1349
1350 static const struct snd_kcontrol_new rt5645_sto1_dmic_mux =
1351     SOC_DAPM_ENUM("Stereo1 DMIC source", rt5645_stereo1_dmic_enum);
1352
1353 /* Mono ADC source */
1354 /* MX-28 [12] */
1355 static const char * const rt5645_mono_adc_l1_src[] = {
1356     "Mono DAC MIXL", "ADC"
1357 };
1358
1359 static SOC_ENUM_SINGLE_DECL(
1360     rt5645_mono_adc_l1_enum, RT5645_MONO_ADC_MIXER,
1361     RT5645_MONO_ADC_L1_SRC_SFT, rt5645_mono_adc_l1_src);
1362
1363 static const struct snd_kcontrol_new rt5645_mono_adc_l1_mux =
1364     SOC_DAPM_ENUM("Mono ADC1 left source", rt5645_mono_adc_l1_enum);
1365 /* MX-28 [11] */
1366 static const char * const rt5645_mono_adc_l2_src[] = {
1367     "Mono DAC MIXL", "DMIC"
1368 };
1369
1370 static SOC_ENUM_SINGLE_DECL(
1371     rt5645_mono_adc_l2_enum, RT5645_MONO_ADC_MIXER,
1372     RT5645_MONO_ADC_L2_SRC_SFT, rt5645_mono_adc_l2_src);
1373
1374 static const struct snd_kcontrol_new rt5645_mono_adc_l2_mux =
1375     SOC_DAPM_ENUM("Mono ADC2 left source", rt5645_mono_adc_l2_enum);
1376
1377 /* MX-28 [8] */
1378 static const char * const rt5645_mono_dmic_src[] = {
1379     "DMIC1", "DMIC2"
1380 };
1381
1382 static SOC_ENUM_SINGLE_DECL(
1383     rt5645_mono_dmic_l_enum, RT5645_MONO_ADC_MIXER,
1384     RT5645_MONO_DMIC_L_SRC_SFT, rt5645_mono_dmic_src);
1385
1386 static const struct snd_kcontrol_new rt5645_mono_dmic_l_mux =
1387     SOC_DAPM_ENUM("Mono DMIC left source", rt5645_mono_dmic_l_enum);
1388 /* MX-28 [1:0] */
1389 static SOC_ENUM_SINGLE_DECL(
1390     rt5645_mono_dmic_r_enum, RT5645_MONO_ADC_MIXER,
1391     RT5645_MONO_DMIC_R_SRC_SFT, rt5645_mono_dmic_src);
1392
1393 static const struct snd_kcontrol_new rt5645_mono_dmic_r_mux =
1394     SOC_DAPM_ENUM("Mono DMIC Right source", rt5645_mono_dmic_r_enum);
1395 /* MX-28 [4] */
1396 static const char * const rt5645_mono_adc_r1_src[] = {
1397     "Mono DAC MIXR", "ADC"
1398 };
1399
1400 static SOC_ENUM_SINGLE_DECL(
1401     rt5645_mono_adc_r1_enum, RT5645_MONO_ADC_MIXER,
1402     RT5645_MONO_ADC_R1_SRC_SFT, rt5645_mono_adc_r1_src);
1403
1404 static const struct snd_kcontrol_new rt5645_mono_adc_r1_mux =
1405     SOC_DAPM_ENUM("Mono ADC1 right source", rt5645_mono_adc_r1_enum);
1406 /* MX-28 [3] */
1407 static const char * const rt5645_mono_adc_r2_src[] = {
1408     "Mono DAC MIXR", "DMIC"
1409 };
1410
1411 static SOC_ENUM_SINGLE_DECL(
1412     rt5645_mono_adc_r2_enum, RT5645_MONO_ADC_MIXER,
1413     RT5645_MONO_ADC_R2_SRC_SFT, rt5645_mono_adc_r2_src);
1414
1415 static const struct snd_kcontrol_new rt5645_mono_adc_r2_mux =
1416     SOC_DAPM_ENUM("Mono ADC2 right source", rt5645_mono_adc_r2_enum);
1417
1418 /* MX-77 [9:8] */
1419 static const char * const rt5645_if1_adc_in_src[] = {
1420     "IF_ADC1/IF_ADC2/VAD_ADC", "IF_ADC2/IF_ADC1/VAD_ADC",
1421     "VAD_ADC/IF_ADC1/IF_ADC2", "VAD_ADC/IF_ADC2/IF_ADC1"
1422 };
1423
1424 static SOC_ENUM_SINGLE_DECL(
1425     rt5645_if1_adc_in_enum, RT5645_TDM_CTRL_1,
1426     RT5645_IF1_ADC_IN_SFT, rt5645_if1_adc_in_src);
1427
1428 static const struct snd_kcontrol_new rt5645_if1_adc_in_mux =
1429     SOC_DAPM_ENUM("IF1 ADC IN source", rt5645_if1_adc_in_enum);
1430
1431 /* MX-78 [4:0] */
1432 static const char * const rt5650_if1_adc_in_src[] = {
1433     "IF_ADC1/IF_ADC2/DAC_REF/Null",
1434     "IF_ADC1/IF_ADC2/Null/DAC_REF",
1435     "IF_ADC1/DAC_REF/IF_ADC2/Null",
1436     "IF_ADC1/DAC_REF/Null/IF_ADC2",
1437     "IF_ADC1/Null/DAC_REF/IF_ADC2",
1438     "IF_ADC1/Null/IF_ADC2/DAC_REF",
1439
1440     "IF_ADC2/IF_ADC1/DAC_REF/Null",
1441     "IF_ADC2/IF_ADC1/Null/DAC_REF",
1442     "IF_ADC2/DAC_REF/IF_ADC1/Null",
1443     "IF_ADC2/DAC_REF/Null/IF_ADC1",
1444     "IF_ADC2/Null/DAC_REF/IF_ADC1",
1445     "IF_ADC2/Null/IF_ADC1/DAC_REF",
1446
1447     "DAC_REF/IF_ADC1/IF_ADC2/Null",
1448     "DAC_REF/IF_ADC1/Null/IF_ADC2",
1449     "DAC_REF/IF_ADC2/IF_ADC1/Null",
1450     "DAC_REF/IF_ADC2/Null/IF_ADC1",
1451     "DAC_REF/Null/IF_ADC1/IF_ADC2",
1452     "DAC_REF/Null/IF_ADC2/IF_ADC1",
1453
1454     "Null/IF_ADC1/IF_ADC2/DAC_REF",
1455     "Null/IF_ADC1/DAC_REF/IF_ADC2",
1456     "Null/IF_ADC2/IF_ADC1/DAC_REF",
1457     "Null/IF_ADC2/DAC_REF/IF_ADC1",
1458     "Null/DAC_REF/IF_ADC1/IF_ADC2",
1459     "Null/DAC_REF/IF_ADC2/IF_ADC1",
1460 };
1461
1462 static SOC_ENUM_SINGLE_DECL(
1463     rt5650_if1_adc_in_enum, RT5645_TDM_CTRL_2,
1464     0, rt5650_if1_adc_in_src);
1465
1466 static const struct snd_kcontrol_new rt5650_if1_adc_in_mux =
1467     SOC_DAPM_ENUM("IF1 ADC IN source", rt5650_if1_adc_in_enum);
1468
1469 /* MX-78 [15:14][13:12][11:10] */
1470 static const char * const rt5645_tdm_adc_swap_select[] = {
1471     "L/R", "R/L", "L/L", "R/R"
1472 };
1473
1474 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot0_1_enum,
1475     RT5645_TDM_CTRL_2, 14, rt5645_tdm_adc_swap_select);
1476
1477 static const struct snd_kcontrol_new rt5650_if1_adc1_in_mux =
1478     SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5650_tdm_adc_slot0_1_enum);
1479
1480 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot2_3_enum,
1481     RT5645_TDM_CTRL_2, 12, rt5645_tdm_adc_swap_select);
1482
1483 static const struct snd_kcontrol_new rt5650_if1_adc2_in_mux =
1484     SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5650_tdm_adc_slot2_3_enum);
1485
1486 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot4_5_enum,
1487     RT5645_TDM_CTRL_2, 10, rt5645_tdm_adc_swap_select);
1488
1489 static const struct snd_kcontrol_new rt5650_if1_adc3_in_mux =
1490     SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5650_tdm_adc_slot4_5_enum);
1491
1492 /* MX-77 [7:6][5:4][3:2] */
1493 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot0_1_enum,
1494     RT5645_TDM_CTRL_1, 6, rt5645_tdm_adc_swap_select);
1495
1496 static const struct snd_kcontrol_new rt5645_if1_adc1_in_mux =
1497     SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5645_tdm_adc_slot0_1_enum);
1498
1499 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot2_3_enum,
1500     RT5645_TDM_CTRL_1, 4, rt5645_tdm_adc_swap_select);
1501
1502 static const struct snd_kcontrol_new rt5645_if1_adc2_in_mux =
1503     SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5645_tdm_adc_slot2_3_enum);
1504
1505 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot4_5_enum,
1506     RT5645_TDM_CTRL_1, 2, rt5645_tdm_adc_swap_select);
1507
1508 static const struct snd_kcontrol_new rt5645_if1_adc3_in_mux =
1509     SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5645_tdm_adc_slot4_5_enum);
1510
1511 /* MX-79 [14:12][10:8][6:4][2:0] */
1512 static const char * const rt5645_tdm_dac_swap_select[] = {
1513     "Slot0", "Slot1", "Slot2", "Slot3"
1514 };
1515
1516 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac0_enum,
1517     RT5645_TDM_CTRL_3, 12, rt5645_tdm_dac_swap_select);
1518
1519 static const struct snd_kcontrol_new rt5645_if1_dac0_tdm_sel_mux =
1520     SOC_DAPM_ENUM("IF1 DAC0 source", rt5645_tdm_dac0_enum);
1521
1522 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac1_enum,
1523     RT5645_TDM_CTRL_3, 8, rt5645_tdm_dac_swap_select);
1524
1525 static const struct snd_kcontrol_new rt5645_if1_dac1_tdm_sel_mux =
1526     SOC_DAPM_ENUM("IF1 DAC1 source", rt5645_tdm_dac1_enum);
1527
1528 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac2_enum,
1529     RT5645_TDM_CTRL_3, 4, rt5645_tdm_dac_swap_select);
1530
1531 static const struct snd_kcontrol_new rt5645_if1_dac2_tdm_sel_mux =
1532     SOC_DAPM_ENUM("IF1 DAC2 source", rt5645_tdm_dac2_enum);
1533
1534 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac3_enum,
1535     RT5645_TDM_CTRL_3, 0, rt5645_tdm_dac_swap_select);
1536
1537 static const struct snd_kcontrol_new rt5645_if1_dac3_tdm_sel_mux =
1538     SOC_DAPM_ENUM("IF1 DAC3 source", rt5645_tdm_dac3_enum);
1539
1540 /* MX-7a [14:12][10:8][6:4][2:0] */
1541 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac0_enum,
1542     RT5650_TDM_CTRL_4, 12, rt5645_tdm_dac_swap_select);
1543
1544 static const struct snd_kcontrol_new rt5650_if1_dac0_tdm_sel_mux =
1545     SOC_DAPM_ENUM("IF1 DAC0 source", rt5650_tdm_dac0_enum);
1546
1547 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac1_enum,
1548     RT5650_TDM_CTRL_4, 8, rt5645_tdm_dac_swap_select);
1549
1550 static const struct snd_kcontrol_new rt5650_if1_dac1_tdm_sel_mux =
1551     SOC_DAPM_ENUM("IF1 DAC1 source", rt5650_tdm_dac1_enum);
1552
1553 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac2_enum,
1554     RT5650_TDM_CTRL_4, 4, rt5645_tdm_dac_swap_select);
1555
1556 static const struct snd_kcontrol_new rt5650_if1_dac2_tdm_sel_mux =
1557     SOC_DAPM_ENUM("IF1 DAC2 source", rt5650_tdm_dac2_enum);
1558
1559 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac3_enum,
1560     RT5650_TDM_CTRL_4, 0, rt5645_tdm_dac_swap_select);
1561
1562 static const struct snd_kcontrol_new rt5650_if1_dac3_tdm_sel_mux =
1563     SOC_DAPM_ENUM("IF1 DAC3 source", rt5650_tdm_dac3_enum);
1564
1565 /* MX-2d [3] [2] */
1566 static const char * const rt5650_a_dac1_src[] = {
1567     "DAC1", "Stereo DAC Mixer"
1568 };
1569
1570 static SOC_ENUM_SINGLE_DECL(
1571     rt5650_a_dac1_l_enum, RT5650_A_DAC_SOUR,
1572     RT5650_A_DAC1_L_IN_SFT, rt5650_a_dac1_src);
1573
1574 static const struct snd_kcontrol_new rt5650_a_dac1_l_mux =
1575     SOC_DAPM_ENUM("A DAC1 L source", rt5650_a_dac1_l_enum);
1576
1577 static SOC_ENUM_SINGLE_DECL(
1578     rt5650_a_dac1_r_enum, RT5650_A_DAC_SOUR,
1579     RT5650_A_DAC1_R_IN_SFT, rt5650_a_dac1_src);
1580
1581 static const struct snd_kcontrol_new rt5650_a_dac1_r_mux =
1582     SOC_DAPM_ENUM("A DAC1 R source", rt5650_a_dac1_r_enum);
1583
1584 /* MX-2d [1] [0] */
1585 static const char * const rt5650_a_dac2_src[] = {
1586     "Stereo DAC Mixer", "Mono DAC Mixer"
1587 };
1588
1589 static SOC_ENUM_SINGLE_DECL(
1590     rt5650_a_dac2_l_enum, RT5650_A_DAC_SOUR,
1591     RT5650_A_DAC2_L_IN_SFT, rt5650_a_dac2_src);
1592
1593 static const struct snd_kcontrol_new rt5650_a_dac2_l_mux =
1594     SOC_DAPM_ENUM("A DAC2 L source", rt5650_a_dac2_l_enum);
1595
1596 static SOC_ENUM_SINGLE_DECL(
1597     rt5650_a_dac2_r_enum, RT5650_A_DAC_SOUR,
1598     RT5650_A_DAC2_R_IN_SFT, rt5650_a_dac2_src);
1599
1600 static const struct snd_kcontrol_new rt5650_a_dac2_r_mux =
1601     SOC_DAPM_ENUM("A DAC2 R source", rt5650_a_dac2_r_enum);
1602
1603 /* MX-2F [13:12] */
1604 static const char * const rt5645_if2_adc_in_src[] = {
1605     "IF_ADC1", "IF_ADC2", "VAD_ADC"
1606 };
1607
1608 static SOC_ENUM_SINGLE_DECL(
1609     rt5645_if2_adc_in_enum, RT5645_DIG_INF1_DATA,
1610     RT5645_IF2_ADC_IN_SFT, rt5645_if2_adc_in_src);
1611
1612 static const struct snd_kcontrol_new rt5645_if2_adc_in_mux =
1613     SOC_DAPM_ENUM("IF2 ADC IN source", rt5645_if2_adc_in_enum);
1614
1615 /* MX-31 [15] [13] [11] [9] */
1616 static const char * const rt5645_pdm_src[] = {
1617     "Mono DAC", "Stereo DAC"
1618 };
1619
1620 static SOC_ENUM_SINGLE_DECL(
1621     rt5645_pdm1_l_enum, RT5645_PDM_OUT_CTRL,
1622     RT5645_PDM1_L_SFT, rt5645_pdm_src);
1623
1624 static const struct snd_kcontrol_new rt5645_pdm1_l_mux =
1625     SOC_DAPM_ENUM("PDM1 L source", rt5645_pdm1_l_enum);
1626
1627 static SOC_ENUM_SINGLE_DECL(
1628     rt5645_pdm1_r_enum, RT5645_PDM_OUT_CTRL,
1629     RT5645_PDM1_R_SFT, rt5645_pdm_src);
1630
1631 static const struct snd_kcontrol_new rt5645_pdm1_r_mux =
1632     SOC_DAPM_ENUM("PDM1 R source", rt5645_pdm1_r_enum);
1633
1634 /* MX-9D [9:8] */
1635 static const char * const rt5645_vad_adc_src[] = {
1636     "Sto1 ADC L", "Mono ADC L", "Mono ADC R"
1637 };
1638
1639 static SOC_ENUM_SINGLE_DECL(
1640     rt5645_vad_adc_enum, RT5645_VAD_CTRL4,
1641     RT5645_VAD_SEL_SFT, rt5645_vad_adc_src);
1642
1643 static const struct snd_kcontrol_new rt5645_vad_adc_mux =
1644     SOC_DAPM_ENUM("VAD ADC source", rt5645_vad_adc_enum);
1645
1646 static const struct snd_kcontrol_new spk_l_vol_control =
1647     SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1648         RT5645_L_MUTE_SFT, 1, 1);
1649
1650 static const struct snd_kcontrol_new spk_r_vol_control =
1651     SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1652         RT5645_R_MUTE_SFT, 1, 1);
1653
1654 static const struct snd_kcontrol_new hp_l_vol_control =
1655     SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1656         RT5645_L_MUTE_SFT, 1, 1);
1657
1658 static const struct snd_kcontrol_new hp_r_vol_control =
1659     SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1660         RT5645_R_MUTE_SFT, 1, 1);
1661
1662 static const struct snd_kcontrol_new pdm1_l_vol_control =
1663     SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1664         RT5645_M_PDM1_L, 1, 1);
1665
1666 static const struct snd_kcontrol_new pdm1_r_vol_control =
1667     SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1668         RT5645_M_PDM1_R, 1, 1);
1669
1670 static void hp_amp_power(struct snd_soc_component *component, int on)
1671 {
1672     static int hp_amp_power_count;
1673     struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
1674     int i, val;
1675
1676     if (on) {
1677         if (hp_amp_power_count <= 0) {
1678             if (rt5645->codec_type == CODEC_TYPE_RT5650) {
1679                 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x3100);
1680                 snd_soc_component_write(component, RT5645_CHARGE_PUMP,
1681                     0x0e06);
1682                 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x000d);
1683                 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1684                     RT5645_HP_DCC_INT1, 0x9f01);
1685                 for (i = 0; i < 20; i++) {
1686                     usleep_range(1000, 1500);
1687                     regmap_read(rt5645->regmap, RT5645_PR_BASE +
1688                         RT5645_HP_DCC_INT1, &val);
1689                     if (!(val & 0x8000))
1690                         break;
1691                 }
1692                 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1693                     RT5645_HP_CO_MASK, RT5645_HP_CO_EN);
1694                 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1695                     0x3e, 0x7400);
1696                 snd_soc_component_write(component, RT5645_DEPOP_M3, 0x0737);
1697                 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1698                     RT5645_MAMP_INT_REG2, 0xfc00);
1699                 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140);
1700                 msleep(90);
1701             } else {
1702                 /* depop parameters */
1703                 snd_soc_component_update_bits(component, RT5645_DEPOP_M2,
1704                     RT5645_DEPOP_MASK, RT5645_DEPOP_MAN);
1705                 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x000d);
1706                 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1707                     RT5645_HP_DCC_INT1, 0x9f01);
1708                 mdelay(150);
1709                 /* headphone amp power on */
1710                 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1711                     RT5645_PWR_FV1 | RT5645_PWR_FV2, 0);
1712                 snd_soc_component_update_bits(component, RT5645_PWR_VOL,
1713                     RT5645_PWR_HV_L | RT5645_PWR_HV_R,
1714                     RT5645_PWR_HV_L | RT5645_PWR_HV_R);
1715                 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1716                     RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1717                     RT5645_PWR_HA,
1718                     RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1719                     RT5645_PWR_HA);
1720                 mdelay(5);
1721                 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1722                     RT5645_PWR_FV1 | RT5645_PWR_FV2,
1723                     RT5645_PWR_FV1 | RT5645_PWR_FV2);
1724
1725                 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1726                     RT5645_HP_CO_MASK | RT5645_HP_SG_MASK,
1727                     RT5645_HP_CO_EN | RT5645_HP_SG_EN);
1728                 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1729                     0x14, 0x1aaa);
1730                 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1731                     0x24, 0x0430);
1732             }
1733         }
1734         hp_amp_power_count++;
1735     } else {
1736         hp_amp_power_count--;
1737         if (hp_amp_power_count <= 0) {
1738             if (rt5645->codec_type == CODEC_TYPE_RT5650) {
1739                 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1740                     0x3e, 0x7400);
1741                 snd_soc_component_write(component, RT5645_DEPOP_M3, 0x0737);
1742                 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1743                     RT5645_MAMP_INT_REG2, 0xfc00);
1744                 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140);
1745                 msleep(100);
1746                 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x0001);
1747
1748             } else {
1749                 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1750                     RT5645_HP_SG_MASK |
1751                     RT5645_HP_L_SMT_MASK |
1752                     RT5645_HP_R_SMT_MASK,
1753                     RT5645_HP_SG_DIS |
1754                     RT5645_HP_L_SMT_DIS |
1755                     RT5645_HP_R_SMT_DIS);
1756                 /* headphone amp power down */
1757                 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x0000);
1758                 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1759                     RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1760                     RT5645_PWR_HA, 0);
1761                 snd_soc_component_update_bits(component, RT5645_DEPOP_M2,
1762                     RT5645_DEPOP_MASK, 0);
1763             }
1764         }
1765     }
1766 }
1767
1768 static int rt5645_hp_event(struct snd_soc_dapm_widget *w,
1769     struct snd_kcontrol *kcontrol, int event)
1770 {
1771     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1772     struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
1773
1774     switch (event) {
1775     case SND_SOC_DAPM_POST_PMU:
1776         hp_amp_power(component, 1);
1777         /* headphone unmute sequence */
1778         if (rt5645->codec_type == CODEC_TYPE_RT5645) {
1779             snd_soc_component_update_bits(component, RT5645_DEPOP_M3,
1780                 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1781                 RT5645_CP_FQ3_MASK,
1782                 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ1_SFT) |
1783                 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1784                 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ3_SFT));
1785             regmap_write(rt5645->regmap, RT5645_PR_BASE +
1786                 RT5645_MAMP_INT_REG2, 0xfc00);
1787             snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1788                 RT5645_SMT_TRIG_MASK, RT5645_SMT_TRIG_EN);
1789             snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1790                 RT5645_RSTN_MASK, RT5645_RSTN_EN);
1791             snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1792                 RT5645_RSTN_MASK | RT5645_HP_L_SMT_MASK |
1793                 RT5645_HP_R_SMT_MASK, RT5645_RSTN_DIS |
1794                 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1795             msleep(40);
1796             snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1797                 RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK |
1798                 RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS |
1799                 RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS);
1800         }
1801         break;
1802
1803     case SND_SOC_DAPM_PRE_PMD:
1804         /* headphone mute sequence */
1805         if (rt5645->codec_type == CODEC_TYPE_RT5645) {
1806             snd_soc_component_update_bits(component, RT5645_DEPOP_M3,
1807                 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1808                 RT5645_CP_FQ3_MASK,
1809                 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ1_SFT) |
1810                 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1811                 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ3_SFT));
1812             regmap_write(rt5645->regmap, RT5645_PR_BASE +
1813                 RT5645_MAMP_INT_REG2, 0xfc00);
1814             snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1815                 RT5645_HP_SG_MASK, RT5645_HP_SG_EN);
1816             snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1817                 RT5645_RSTP_MASK, RT5645_RSTP_EN);
1818             snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1819                 RT5645_RSTP_MASK | RT5645_HP_L_SMT_MASK |
1820                 RT5645_HP_R_SMT_MASK, RT5645_RSTP_DIS |
1821                 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1822             msleep(30);
1823         }
1824         hp_amp_power(component, 0);
1825         break;
1826
1827     default:
1828         return 0;
1829     }
1830
1831     return 0;
1832 }
1833
1834 static int rt5645_spk_event(struct snd_soc_dapm_widget *w,
1835     struct snd_kcontrol *kcontrol, int event)
1836 {
1837     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1838
1839     switch (event) {
1840     case SND_SOC_DAPM_POST_PMU:
1841         rt5645_enable_hweq(component);
1842         snd_soc_component_update_bits(component, RT5645_PWR_DIG1,
1843             RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1844             RT5645_PWR_CLS_D_L,
1845             RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1846             RT5645_PWR_CLS_D_L);
1847         snd_soc_component_update_bits(component, RT5645_GEN_CTRL3,
1848             RT5645_DET_CLK_MASK, RT5645_DET_CLK_MODE1);
1849         break;
1850
1851     case SND_SOC_DAPM_PRE_PMD:
1852         snd_soc_component_update_bits(component, RT5645_GEN_CTRL3,
1853             RT5645_DET_CLK_MASK, RT5645_DET_CLK_DIS);
1854         snd_soc_component_write(component, RT5645_EQ_CTRL2, 0);
1855         snd_soc_component_update_bits(component, RT5645_PWR_DIG1,
1856             RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1857             RT5645_PWR_CLS_D_L, 0);
1858         break;
1859
1860     default:
1861         return 0;
1862     }
1863
1864     return 0;
1865 }
1866
1867 static int rt5645_lout_event(struct snd_soc_dapm_widget *w,
1868     struct snd_kcontrol *kcontrol, int event)
1869 {
1870     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1871
1872     switch (event) {
1873     case SND_SOC_DAPM_POST_PMU:
1874         hp_amp_power(component, 1);
1875         snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1876             RT5645_PWR_LM, RT5645_PWR_LM);
1877         snd_soc_component_update_bits(component, RT5645_LOUT1,
1878             RT5645_L_MUTE | RT5645_R_MUTE, 0);
1879         break;
1880
1881     case SND_SOC_DAPM_PRE_PMD:
1882         snd_soc_component_update_bits(component, RT5645_LOUT1,
1883             RT5645_L_MUTE | RT5645_R_MUTE,
1884             RT5645_L_MUTE | RT5645_R_MUTE);
1885         snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1886             RT5645_PWR_LM, 0);
1887         hp_amp_power(component, 0);
1888         break;
1889
1890     default:
1891         return 0;
1892     }
1893
1894     return 0;
1895 }
1896
1897 static int rt5645_bst2_event(struct snd_soc_dapm_widget *w,
1898     struct snd_kcontrol *kcontrol, int event)
1899 {
1900     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1901
1902     switch (event) {
1903     case SND_SOC_DAPM_POST_PMU:
1904         snd_soc_component_update_bits(component, RT5645_PWR_ANLG2,
1905             RT5645_PWR_BST2_P, RT5645_PWR_BST2_P);
1906         break;
1907
1908     case SND_SOC_DAPM_PRE_PMD:
1909         snd_soc_component_update_bits(component, RT5645_PWR_ANLG2,
1910             RT5645_PWR_BST2_P, 0);
1911         break;
1912
1913     default:
1914         return 0;
1915     }
1916
1917     return 0;
1918 }
1919
1920 static int rt5645_set_micbias1_event(struct snd_soc_dapm_widget *w,
1921         struct snd_kcontrol *k, int  event)
1922 {
1923     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1924
1925     switch (event) {
1926     case SND_SOC_DAPM_PRE_PMU:
1927         snd_soc_component_update_bits(component, RT5645_GEN_CTRL2,
1928             RT5645_MICBIAS1_POW_CTRL_SEL_MASK,
1929             RT5645_MICBIAS1_POW_CTRL_SEL_M);
1930         break;
1931
1932     case SND_SOC_DAPM_POST_PMD:
1933         snd_soc_component_update_bits(component, RT5645_GEN_CTRL2,
1934             RT5645_MICBIAS1_POW_CTRL_SEL_MASK,
1935             RT5645_MICBIAS1_POW_CTRL_SEL_A);
1936         break;
1937
1938     default:
1939         return 0;
1940     }
1941
1942     return 0;
1943 }
1944
1945 static int rt5645_set_micbias2_event(struct snd_soc_dapm_widget *w,
1946         struct snd_kcontrol *k, int  event)
1947 {
1948     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1949
1950     switch (event) {
1951     case SND_SOC_DAPM_PRE_PMU:
1952         snd_soc_component_update_bits(component, RT5645_GEN_CTRL2,
1953             RT5645_MICBIAS2_POW_CTRL_SEL_MASK,
1954             RT5645_MICBIAS2_POW_CTRL_SEL_M);
1955         break;
1956
1957     case SND_SOC_DAPM_POST_PMD:
1958         snd_soc_component_update_bits(component, RT5645_GEN_CTRL2,
1959             RT5645_MICBIAS2_POW_CTRL_SEL_MASK,
1960             RT5645_MICBIAS2_POW_CTRL_SEL_A);
1961         break;
1962
1963     default:
1964         return 0;
1965     }
1966
1967     return 0;
1968 }
1969
1970 static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = {
1971     SND_SOC_DAPM_SUPPLY("LDO2", RT5645_PWR_MIXER,
1972         RT5645_PWR_LDO2_BIT, 0, NULL, 0),
1973     SND_SOC_DAPM_SUPPLY("PLL1", RT5645_PWR_ANLG2,
1974         RT5645_PWR_PLL_BIT, 0, NULL, 0),
1975
1976     SND_SOC_DAPM_SUPPLY("JD Power", RT5645_PWR_ANLG2,
1977         RT5645_PWR_JD1_BIT, 0, NULL, 0),
1978     SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5645_PWR_VOL,
1979         RT5645_PWR_MIC_DET_BIT, 0, NULL, 0),
1980
1981     /* ASRC */
1982     SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5645_ASRC_1,
1983                   11, 0, NULL, 0),
1984     SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5645_ASRC_1,
1985                   12, 0, NULL, 0),
1986     SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5645_ASRC_1,
1987                   10, 0, NULL, 0),
1988     SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC", 1, RT5645_ASRC_1,
1989                   9, 0, NULL, 0),
1990     SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC", 1, RT5645_ASRC_1,
1991                   8, 0, NULL, 0),
1992     SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5645_ASRC_1,
1993                   7, 0, NULL, 0),
1994     SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5645_ASRC_1,
1995                   5, 0, NULL, 0),
1996     SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5645_ASRC_1,
1997                   4, 0, NULL, 0),
1998     SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5645_ASRC_1,
1999                   3, 0, NULL, 0),
2000     SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5645_ASRC_1,
2001                   1, 0, NULL, 0),
2002     SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5645_ASRC_1,
2003                   0, 0, NULL, 0),
2004
2005     /* Input Side */
2006     /* micbias */
2007     SND_SOC_DAPM_SUPPLY("micbias1", RT5645_PWR_ANLG2,
2008             RT5645_PWR_MB1_BIT, 0, rt5645_set_micbias1_event,
2009             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2010     SND_SOC_DAPM_SUPPLY("micbias2", RT5645_PWR_ANLG2,
2011             RT5645_PWR_MB2_BIT, 0, rt5645_set_micbias2_event,
2012             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2013     /* Input Lines */
2014     SND_SOC_DAPM_INPUT("DMIC L1"),
2015     SND_SOC_DAPM_INPUT("DMIC R1"),
2016     SND_SOC_DAPM_INPUT("DMIC L2"),
2017     SND_SOC_DAPM_INPUT("DMIC R2"),
2018
2019     SND_SOC_DAPM_INPUT("IN1P"),
2020     SND_SOC_DAPM_INPUT("IN1N"),
2021     SND_SOC_DAPM_INPUT("IN2P"),
2022     SND_SOC_DAPM_INPUT("IN2N"),
2023
2024     SND_SOC_DAPM_INPUT("Haptic Generator"),
2025
2026     SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2027     SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2028     SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2029         set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2030     SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5645_DMIC_CTRL1,
2031         RT5645_DMIC_1_EN_SFT, 0, NULL, 0),
2032     SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5645_DMIC_CTRL1,
2033         RT5645_DMIC_2_EN_SFT, 0, NULL, 0),
2034     /* Boost */
2035     SND_SOC_DAPM_PGA("BST1", RT5645_PWR_ANLG2,
2036         RT5645_PWR_BST1_BIT, 0, NULL, 0),
2037     SND_SOC_DAPM_PGA_E("BST2", RT5645_PWR_ANLG2,
2038         RT5645_PWR_BST2_BIT, 0, NULL, 0, rt5645_bst2_event,
2039         SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2040     /* Input Volume */
2041     SND_SOC_DAPM_PGA("INL VOL", RT5645_PWR_VOL,
2042         RT5645_PWR_IN_L_BIT, 0, NULL, 0),
2043     SND_SOC_DAPM_PGA("INR VOL", RT5645_PWR_VOL,
2044         RT5645_PWR_IN_R_BIT, 0, NULL, 0),
2045     /* REC Mixer */
2046     SND_SOC_DAPM_MIXER("RECMIXL", RT5645_PWR_MIXER, RT5645_PWR_RM_L_BIT,
2047             0, rt5645_rec_l_mix, ARRAY_SIZE(rt5645_rec_l_mix)),
2048     SND_SOC_DAPM_MIXER("RECMIXR", RT5645_PWR_MIXER, RT5645_PWR_RM_R_BIT,
2049             0, rt5645_rec_r_mix, ARRAY_SIZE(rt5645_rec_r_mix)),
2050     /* ADCs */
2051     SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
2052     SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
2053
2054     SND_SOC_DAPM_SUPPLY("ADC L power", RT5645_PWR_DIG1,
2055         RT5645_PWR_ADC_L_BIT, 0, NULL, 0),
2056     SND_SOC_DAPM_SUPPLY("ADC R power", RT5645_PWR_DIG1,
2057         RT5645_PWR_ADC_R_BIT, 0, NULL, 0),
2058
2059     /* ADC Mux */
2060     SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
2061         &rt5645_sto1_dmic_mux),
2062     SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2063         &rt5645_sto_adc2_mux),
2064     SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2065         &rt5645_sto_adc2_mux),
2066     SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2067         &rt5645_sto_adc1_mux),
2068     SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2069         &rt5645_sto_adc1_mux),
2070     SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2071         &rt5645_mono_dmic_l_mux),
2072     SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2073         &rt5645_mono_dmic_r_mux),
2074     SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2075         &rt5645_mono_adc_l2_mux),
2076     SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2077         &rt5645_mono_adc_l1_mux),
2078     SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2079         &rt5645_mono_adc_r1_mux),
2080     SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2081         &rt5645_mono_adc_r2_mux),
2082     /* ADC Mixer */
2083
2084     SND_SOC_DAPM_SUPPLY_S("adc stereo1 filter", 1, RT5645_PWR_DIG2,
2085         RT5645_PWR_ADC_S1F_BIT, 0, NULL, 0),
2086     SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
2087         rt5645_sto1_adc_l_mix, ARRAY_SIZE(rt5645_sto1_adc_l_mix),
2088         NULL, 0),
2089     SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2090         rt5645_sto1_adc_r_mix, ARRAY_SIZE(rt5645_sto1_adc_r_mix),
2091         NULL, 0),
2092     SND_SOC_DAPM_SUPPLY_S("adc mono left filter", 1, RT5645_PWR_DIG2,
2093         RT5645_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2094     SND_SOC_DAPM_MIXER_E("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
2095         rt5645_mono_adc_l_mix, ARRAY_SIZE(rt5645_mono_adc_l_mix),
2096         NULL, 0),
2097     SND_SOC_DAPM_SUPPLY_S("adc mono right filter", 1, RT5645_PWR_DIG2,
2098         RT5645_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2099     SND_SOC_DAPM_MIXER_E("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
2100         rt5645_mono_adc_r_mix, ARRAY_SIZE(rt5645_mono_adc_r_mix),
2101         NULL, 0),
2102
2103     /* ADC PGA */
2104     SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2105     SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2106     SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2107     SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2108     SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2109     SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2110     SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2111     SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2112     SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2113     SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2114
2115     /* IF1 2 Mux */
2116     SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM,
2117         0, 0, &rt5645_if2_adc_in_mux),
2118
2119     /* Digital Interface */
2120     SND_SOC_DAPM_SUPPLY("I2S1", RT5645_PWR_DIG1,
2121         RT5645_PWR_I2S1_BIT, 0, NULL, 0),
2122     SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2123     SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2124     SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2125     SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2126     SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2127     SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2128     SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2129     SND_SOC_DAPM_SUPPLY("I2S2", RT5645_PWR_DIG1,
2130         RT5645_PWR_I2S2_BIT, 0, NULL, 0),
2131     SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2132     SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2133     SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2134     SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2135
2136     /* Digital Interface Select */
2137     SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM,
2138         0, 0, &rt5645_vad_adc_mux),
2139
2140     /* Audio Interface */
2141     SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
2142     SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
2143     SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
2144     SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
2145
2146     /* Output Side */
2147     /* DAC mixer before sound effect  */
2148     SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
2149         rt5645_dac_l_mix, ARRAY_SIZE(rt5645_dac_l_mix)),
2150     SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
2151         rt5645_dac_r_mix, ARRAY_SIZE(rt5645_dac_r_mix)),
2152
2153     /* DAC2 channel Mux */
2154     SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_l2_mux),
2155     SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_r2_mux),
2156     SND_SOC_DAPM_PGA("DAC L2 Volume", RT5645_PWR_DIG1,
2157         RT5645_PWR_DAC_L2_BIT, 0, NULL, 0),
2158     SND_SOC_DAPM_PGA("DAC R2 Volume", RT5645_PWR_DIG1,
2159         RT5645_PWR_DAC_R2_BIT, 0, NULL, 0),
2160
2161     SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1l_mux),
2162     SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1r_mux),
2163
2164     /* DAC Mixer */
2165     SND_SOC_DAPM_SUPPLY_S("dac stereo1 filter", 1, RT5645_PWR_DIG2,
2166         RT5645_PWR_DAC_S1F_BIT, 0, NULL, 0),
2167     SND_SOC_DAPM_SUPPLY_S("dac mono left filter", 1, RT5645_PWR_DIG2,
2168         RT5645_PWR_DAC_MF_L_BIT, 0, NULL, 0),
2169     SND_SOC_DAPM_SUPPLY_S("dac mono right filter", 1, RT5645_PWR_DIG2,
2170         RT5645_PWR_DAC_MF_R_BIT, 0, NULL, 0),
2171     SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
2172         rt5645_sto_dac_l_mix, ARRAY_SIZE(rt5645_sto_dac_l_mix)),
2173     SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
2174         rt5645_sto_dac_r_mix, ARRAY_SIZE(rt5645_sto_dac_r_mix)),
2175     SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
2176         rt5645_mono_dac_l_mix, ARRAY_SIZE(rt5645_mono_dac_l_mix)),
2177     SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
2178         rt5645_mono_dac_r_mix, ARRAY_SIZE(rt5645_mono_dac_r_mix)),
2179     SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
2180         rt5645_dig_l_mix, ARRAY_SIZE(rt5645_dig_l_mix)),
2181     SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
2182         rt5645_dig_r_mix, ARRAY_SIZE(rt5645_dig_r_mix)),
2183
2184     /* DACs */
2185     SND_SOC_DAPM_DAC("DAC L1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L1_BIT,
2186         0),
2187     SND_SOC_DAPM_DAC("DAC L2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L2_BIT,
2188         0),
2189     SND_SOC_DAPM_DAC("DAC R1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R1_BIT,
2190         0),
2191     SND_SOC_DAPM_DAC("DAC R2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R2_BIT,
2192         0),
2193     /* OUT Mixer */
2194     SND_SOC_DAPM_MIXER("SPK MIXL", RT5645_PWR_MIXER, RT5645_PWR_SM_L_BIT,
2195         0, rt5645_spk_l_mix, ARRAY_SIZE(rt5645_spk_l_mix)),
2196     SND_SOC_DAPM_MIXER("SPK MIXR", RT5645_PWR_MIXER, RT5645_PWR_SM_R_BIT,
2197         0, rt5645_spk_r_mix, ARRAY_SIZE(rt5645_spk_r_mix)),
2198     SND_SOC_DAPM_MIXER("OUT MIXL", RT5645_PWR_MIXER, RT5645_PWR_OM_L_BIT,
2199         0, rt5645_out_l_mix, ARRAY_SIZE(rt5645_out_l_mix)),
2200     SND_SOC_DAPM_MIXER("OUT MIXR", RT5645_PWR_MIXER, RT5645_PWR_OM_R_BIT,
2201         0, rt5645_out_r_mix, ARRAY_SIZE(rt5645_out_r_mix)),
2202     /* Ouput Volume */
2203     SND_SOC_DAPM_SWITCH("SPKVOL L", RT5645_PWR_VOL, RT5645_PWR_SV_L_BIT, 0,
2204         &spk_l_vol_control),
2205     SND_SOC_DAPM_SWITCH("SPKVOL R", RT5645_PWR_VOL, RT5645_PWR_SV_R_BIT, 0,
2206         &spk_r_vol_control),
2207     SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5645_PWR_VOL, RT5645_PWR_HV_L_BIT,
2208         0, rt5645_hpvoll_mix, ARRAY_SIZE(rt5645_hpvoll_mix)),
2209     SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5645_PWR_VOL, RT5645_PWR_HV_R_BIT,
2210         0, rt5645_hpvolr_mix, ARRAY_SIZE(rt5645_hpvolr_mix)),
2211     SND_SOC_DAPM_SUPPLY("HPOVOL MIXL Power", RT5645_PWR_MIXER,
2212         RT5645_PWR_HM_L_BIT, 0, NULL, 0),
2213     SND_SOC_DAPM_SUPPLY("HPOVOL MIXR Power", RT5645_PWR_MIXER,
2214         RT5645_PWR_HM_R_BIT, 0, NULL, 0),
2215     SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0),
2216     SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0),
2217     SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0),
2218     SND_SOC_DAPM_SWITCH("HPOVOL L", SND_SOC_NOPM, 0, 0, &hp_l_vol_control),
2219     SND_SOC_DAPM_SWITCH("HPOVOL R", SND_SOC_NOPM, 0, 0, &hp_r_vol_control),
2220
2221     /* HPO/LOUT/Mono Mixer */
2222     SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_l_mix,
2223         ARRAY_SIZE(rt5645_spo_l_mix)),
2224     SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_r_mix,
2225         ARRAY_SIZE(rt5645_spo_r_mix)),
2226     SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0, rt5645_hpo_mix,
2227         ARRAY_SIZE(rt5645_hpo_mix)),
2228     SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0, rt5645_lout_mix,
2229         ARRAY_SIZE(rt5645_lout_mix)),
2230
2231     SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0, rt5645_hp_event,
2232         SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2233     SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0, rt5645_lout_event,
2234         SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2235     SND_SOC_DAPM_PGA_S("SPK amp", 2, SND_SOC_NOPM, 0, 0, rt5645_spk_event,
2236         SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2237
2238     /* PDM */
2239     SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5645_PWR_DIG2, RT5645_PWR_PDM1_BIT,
2240         0, NULL, 0),
2241     SND_SOC_DAPM_MUX("PDM1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_l_mux),
2242     SND_SOC_DAPM_MUX("PDM1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_r_mux),
2243
2244     SND_SOC_DAPM_SWITCH("PDM1 L", SND_SOC_NOPM, 0, 0, &pdm1_l_vol_control),
2245     SND_SOC_DAPM_SWITCH("PDM1 R", SND_SOC_NOPM, 0, 0, &pdm1_r_vol_control),
2246
2247     /* Output Lines */
2248     SND_SOC_DAPM_OUTPUT("HPOL"),
2249     SND_SOC_DAPM_OUTPUT("HPOR"),
2250     SND_SOC_DAPM_OUTPUT("LOUTL"),
2251     SND_SOC_DAPM_OUTPUT("LOUTR"),
2252     SND_SOC_DAPM_OUTPUT("PDM1L"),
2253     SND_SOC_DAPM_OUTPUT("PDM1R"),
2254     SND_SOC_DAPM_OUTPUT("SPOL"),
2255     SND_SOC_DAPM_OUTPUT("SPOR"),
2256 };
2257
2258 static const struct snd_soc_dapm_widget rt5645_specific_dapm_widgets[] = {
2259     SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0,
2260         &rt5645_if1_dac0_tdm_sel_mux),
2261     SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0,
2262         &rt5645_if1_dac1_tdm_sel_mux),
2263     SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0,
2264         &rt5645_if1_dac2_tdm_sel_mux),
2265     SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0,
2266         &rt5645_if1_dac3_tdm_sel_mux),
2267     SND_SOC_DAPM_MUX("RT5645 IF1 ADC Mux", SND_SOC_NOPM,
2268         0, 0, &rt5645_if1_adc_in_mux),
2269     SND_SOC_DAPM_MUX("RT5645 IF1 ADC1 Swap Mux", SND_SOC_NOPM,
2270         0, 0, &rt5645_if1_adc1_in_mux),
2271     SND_SOC_DAPM_MUX("RT5645 IF1 ADC2 Swap Mux", SND_SOC_NOPM,
2272         0, 0, &rt5645_if1_adc2_in_mux),
2273     SND_SOC_DAPM_MUX("RT5645 IF1 ADC3 Swap Mux", SND_SOC_NOPM,
2274         0, 0, &rt5645_if1_adc3_in_mux),
2275 };
2276
2277 static const struct snd_soc_dapm_widget rt5650_specific_dapm_widgets[] = {
2278     SND_SOC_DAPM_MUX("A DAC1 L Mux", SND_SOC_NOPM,
2279         0, 0, &rt5650_a_dac1_l_mux),
2280     SND_SOC_DAPM_MUX("A DAC1 R Mux", SND_SOC_NOPM,
2281         0, 0, &rt5650_a_dac1_r_mux),
2282     SND_SOC_DAPM_MUX("A DAC2 L Mux", SND_SOC_NOPM,
2283         0, 0, &rt5650_a_dac2_l_mux),
2284     SND_SOC_DAPM_MUX("A DAC2 R Mux", SND_SOC_NOPM,
2285         0, 0, &rt5650_a_dac2_r_mux),
2286
2287     SND_SOC_DAPM_MUX("RT5650 IF1 ADC1 Swap Mux", SND_SOC_NOPM,
2288         0, 0, &rt5650_if1_adc1_in_mux),
2289     SND_SOC_DAPM_MUX("RT5650 IF1 ADC2 Swap Mux", SND_SOC_NOPM,
2290         0, 0, &rt5650_if1_adc2_in_mux),
2291     SND_SOC_DAPM_MUX("RT5650 IF1 ADC3 Swap Mux", SND_SOC_NOPM,
2292         0, 0, &rt5650_if1_adc3_in_mux),
2293     SND_SOC_DAPM_MUX("RT5650 IF1 ADC Mux", SND_SOC_NOPM,
2294         0, 0, &rt5650_if1_adc_in_mux),
2295
2296     SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0,
2297         &rt5650_if1_dac0_tdm_sel_mux),
2298     SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0,
2299         &rt5650_if1_dac1_tdm_sel_mux),
2300     SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0,
2301         &rt5650_if1_dac2_tdm_sel_mux),
2302     SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0,
2303         &rt5650_if1_dac3_tdm_sel_mux),
2304 };
2305
2306 static const struct snd_soc_dapm_route rt5645_dapm_routes[] = {
2307     { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
2308     { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
2309     { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
2310     { "dac mono left filter", NULL, "DAC MONO L ASRC", is_using_asrc },
2311     { "dac mono right filter", NULL, "DAC MONO R ASRC", is_using_asrc },
2312     { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
2313
2314     { "I2S1", NULL, "I2S1 ASRC" },
2315     { "I2S2", NULL, "I2S2 ASRC" },
2316
2317     { "IN1P", NULL, "LDO2" },
2318     { "IN2P", NULL, "LDO2" },
2319
2320     { "DMIC1", NULL, "DMIC L1" },
2321     { "DMIC1", NULL, "DMIC R1" },
2322     { "DMIC2", NULL, "DMIC L2" },
2323     { "DMIC2", NULL, "DMIC R2" },
2324
2325     { "BST1", NULL, "IN1P" },
2326     { "BST1", NULL, "IN1N" },
2327     { "BST1", NULL, "JD Power" },
2328     { "BST1", NULL, "Mic Det Power" },
2329     { "BST2", NULL, "IN2P" },
2330     { "BST2", NULL, "IN2N" },
2331
2332     { "INL VOL", NULL, "IN2P" },
2333     { "INR VOL", NULL, "IN2N" },
2334
2335     { "RECMIXL", "HPOL Switch", "HPOL" },
2336     { "RECMIXL", "INL Switch", "INL VOL" },
2337     { "RECMIXL", "BST2 Switch", "BST2" },
2338     { "RECMIXL", "BST1 Switch", "BST1" },
2339     { "RECMIXL", "OUT MIXL Switch", "OUT MIXL" },
2340
2341     { "RECMIXR", "HPOR Switch", "HPOR" },
2342     { "RECMIXR", "INR Switch", "INR VOL" },
2343     { "RECMIXR", "BST2 Switch", "BST2" },
2344     { "RECMIXR", "BST1 Switch", "BST1" },
2345     { "RECMIXR", "OUT MIXR Switch", "OUT MIXR" },
2346
2347     { "ADC L", NULL, "RECMIXL" },
2348     { "ADC L", NULL, "ADC L power" },
2349     { "ADC R", NULL, "RECMIXR" },
2350     { "ADC R", NULL, "ADC R power" },
2351
2352     {"DMIC L1", NULL, "DMIC CLK"},
2353     {"DMIC L1", NULL, "DMIC1 Power"},
2354     {"DMIC R1", NULL, "DMIC CLK"},
2355     {"DMIC R1", NULL, "DMIC1 Power"},
2356     {"DMIC L2", NULL, "DMIC CLK"},
2357     {"DMIC L2", NULL, "DMIC2 Power"},
2358     {"DMIC R2", NULL, "DMIC CLK"},
2359     {"DMIC R2", NULL, "DMIC2 Power"},
2360
2361     { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
2362     { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
2363     { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC" },
2364
2365     { "Mono DMIC L Mux", "DMIC1", "DMIC L1" },
2366     { "Mono DMIC L Mux", "DMIC2", "DMIC L2" },
2367     { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC" },
2368
2369     { "Mono DMIC R Mux", "DMIC1", "DMIC R1" },
2370     { "Mono DMIC R Mux", "DMIC2", "DMIC R2" },
2371     { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC" },
2372
2373     { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2374     { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
2375     { "Stereo1 ADC L1 Mux", "ADC", "ADC L" },
2376     { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
2377
2378     { "Stereo1 ADC R1 Mux", "ADC", "ADC R" },
2379     { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
2380     { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2381     { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
2382
2383     { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
2384     { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
2385     { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
2386     { "Mono ADC L1 Mux", "ADC", "ADC L" },
2387
2388     { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2389     { "Mono ADC R1 Mux", "ADC", "ADC R" },
2390     { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
2391     { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2392
2393     { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" },
2394     { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
2395     { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
2396     { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
2397
2398     { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
2399     { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
2400     { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2401
2402     { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
2403     { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
2404     { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2405
2406     { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },
2407     { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
2408     { "Mono ADC MIXL", NULL, "adc mono left filter" },
2409     { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
2410
2411     { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
2412     { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
2413     { "Mono ADC MIXR", NULL, "adc mono right filter" },
2414     { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
2415
2416     { "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" },
2417     { "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" },
2418     { "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" },
2419
2420     { "IF_ADC1", NULL, "Stereo1 ADC MIXL" },
2421     { "IF_ADC1", NULL, "Stereo1 ADC MIXR" },
2422     { "IF_ADC2", NULL, "Mono ADC MIXL" },
2423     { "IF_ADC2", NULL, "Mono ADC MIXR" },
2424     { "VAD_ADC", NULL, "VAD ADC Mux" },
2425
2426     { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
2427     { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
2428     { "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" },
2429
2430     { "IF1 ADC", NULL, "I2S1" },
2431     { "IF2 ADC", NULL, "I2S2" },
2432     { "IF2 ADC", NULL, "IF2 ADC Mux" },
2433
2434     { "AIF2TX", NULL, "IF2 ADC" },
2435
2436     { "IF1 DAC0", NULL, "AIF1RX" },
2437     { "IF1 DAC1", NULL, "AIF1RX" },
2438     { "IF1 DAC2", NULL, "AIF1RX" },
2439     { "IF1 DAC3", NULL, "AIF1RX" },
2440     { "IF2 DAC", NULL, "AIF2RX" },
2441
2442     { "IF1 DAC0", NULL, "I2S1" },
2443     { "IF1 DAC1", NULL, "I2S1" },
2444     { "IF1 DAC2", NULL, "I2S1" },
2445     { "IF1 DAC3", NULL, "I2S1" },
2446     { "IF2 DAC", NULL, "I2S2" },
2447
2448     { "IF2 DAC L", NULL, "IF2 DAC" },
2449     { "IF2 DAC R", NULL, "IF2 DAC" },
2450
2451     { "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" },
2452     { "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" },
2453
2454     { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" },
2455     { "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" },
2456     { "DAC1 MIXL", NULL, "dac stereo1 filter" },
2457     { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" },
2458     { "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" },
2459     { "DAC1 MIXR", NULL, "dac stereo1 filter" },
2460
2461     { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
2462     { "DAC L2 Mux", "Mono ADC", "Mono ADC MIXL" },
2463     { "DAC L2 Mux", "VAD_ADC", "VAD_ADC" },
2464     { "DAC L2 Volume", NULL, "DAC L2 Mux" },
2465     { "DAC L2 Volume", NULL, "dac mono left filter" },
2466
2467     { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
2468     { "DAC R2 Mux", "Mono ADC", "Mono ADC MIXR" },
2469     { "DAC R2 Mux", "Haptic", "Haptic Generator" },
2470     { "DAC R2 Volume", NULL, "DAC R2 Mux" },
2471     { "DAC R2 Volume", NULL, "dac mono right filter" },
2472
2473     { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
2474     { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
2475     { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2476     { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
2477     { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
2478     { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
2479     { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2480     { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
2481
2482     { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
2483     { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2484     { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
2485     { "Mono DAC MIXL", NULL, "dac mono left filter" },
2486     { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
2487     { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2488     { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
2489     { "Mono DAC MIXR", NULL, "dac mono right filter" },
2490
2491     { "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
2492     { "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2493     { "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
2494     { "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
2495     { "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2496     { "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
2497
2498     { "DAC L1", NULL, "PLL1", is_sys_clk_from_pll },
2499     { "DAC R1", NULL, "PLL1", is_sys_clk_from_pll },
2500     { "DAC L2", NULL, "PLL1", is_sys_clk_from_pll },
2501     { "DAC R2", NULL, "PLL1", is_sys_clk_from_pll },
2502
2503     { "SPK MIXL", "BST1 Switch", "BST1" },
2504     { "SPK MIXL", "INL Switch", "INL VOL" },
2505     { "SPK MIXL", "DAC L1 Switch", "DAC L1" },
2506     { "SPK MIXL", "DAC L2 Switch", "DAC L2" },
2507     { "SPK MIXR", "BST2 Switch", "BST2" },
2508     { "SPK MIXR", "INR Switch", "INR VOL" },
2509     { "SPK MIXR", "DAC R1 Switch", "DAC R1" },
2510     { "SPK MIXR", "DAC R2 Switch", "DAC R2" },
2511
2512     { "OUT MIXL", "BST1 Switch", "BST1" },
2513     { "OUT MIXL", "INL Switch", "INL VOL" },
2514     { "OUT MIXL", "DAC L2 Switch", "DAC L2" },
2515     { "OUT MIXL", "DAC L1 Switch", "DAC L1" },
2516
2517     { "OUT MIXR", "BST2 Switch", "BST2" },
2518     { "OUT MIXR", "INR Switch", "INR VOL" },
2519     { "OUT MIXR", "DAC R2 Switch", "DAC R2" },
2520     { "OUT MIXR", "DAC R1 Switch", "DAC R1" },
2521
2522     { "HPOVOL MIXL", "DAC1 Switch", "DAC L1" },
2523     { "HPOVOL MIXL", "DAC2 Switch", "DAC L2" },
2524     { "HPOVOL MIXL", "INL Switch", "INL VOL" },
2525     { "HPOVOL MIXL", "BST1 Switch", "BST1" },
2526     { "HPOVOL MIXL", NULL, "HPOVOL MIXL Power" },
2527     { "HPOVOL MIXR", "DAC1 Switch", "DAC R1" },
2528     { "HPOVOL MIXR", "DAC2 Switch", "DAC R2" },
2529     { "HPOVOL MIXR", "INR Switch", "INR VOL" },
2530     { "HPOVOL MIXR", "BST2 Switch", "BST2" },
2531     { "HPOVOL MIXR", NULL, "HPOVOL MIXR Power" },
2532
2533     { "DAC 2", NULL, "DAC L2" },
2534     { "DAC 2", NULL, "DAC R2" },
2535     { "DAC 1", NULL, "DAC L1" },
2536     { "DAC 1", NULL, "DAC R1" },
2537     { "HPOVOL L", "Switch", "HPOVOL MIXL" },
2538     { "HPOVOL R", "Switch", "HPOVOL MIXR" },
2539     { "HPOVOL", NULL, "HPOVOL L" },
2540     { "HPOVOL", NULL, "HPOVOL R" },
2541     { "HPO MIX", "DAC1 Switch", "DAC 1" },
2542     { "HPO MIX", "HPVOL Switch", "HPOVOL" },
2543
2544     { "SPKVOL L", "Switch", "SPK MIXL" },
2545     { "SPKVOL R", "Switch", "SPK MIXR" },
2546
2547     { "SPOL MIX", "DAC L1 Switch", "DAC L1" },
2548     { "SPOL MIX", "SPKVOL L Switch", "SPKVOL L" },
2549     { "SPOR MIX", "DAC R1 Switch", "DAC R1" },
2550     { "SPOR MIX", "SPKVOL R Switch", "SPKVOL R" },
2551
2552     { "LOUT MIX", "DAC L1 Switch", "DAC L1" },
2553     { "LOUT MIX", "DAC R1 Switch", "DAC R1" },
2554     { "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" },
2555     { "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" },
2556
2557     { "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" },
2558     { "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" },
2559     { "PDM1 L Mux", NULL, "PDM1 Power" },
2560     { "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" },
2561     { "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" },
2562     { "PDM1 R Mux", NULL, "PDM1 Power" },
2563
2564     { "HP amp", NULL, "HPO MIX" },
2565     { "HP amp", NULL, "JD Power" },
2566     { "HP amp", NULL, "Mic Det Power" },
2567     { "HP amp", NULL, "LDO2" },
2568     { "HPOL", NULL, "HP amp" },
2569     { "HPOR", NULL, "HP amp" },
2570
2571     { "LOUT amp", NULL, "LOUT MIX" },
2572     { "LOUTL", NULL, "LOUT amp" },
2573     { "LOUTR", NULL, "LOUT amp" },
2574
2575     { "PDM1 L", "Switch", "PDM1 L Mux" },
2576     { "PDM1 R", "Switch", "PDM1 R Mux" },
2577
2578     { "PDM1L", NULL, "PDM1 L" },
2579     { "PDM1R", NULL, "PDM1 R" },
2580
2581     { "SPK amp", NULL, "SPOL MIX" },
2582     { "SPK amp", NULL, "SPOR MIX" },
2583     { "SPOL", NULL, "SPK amp" },
2584     { "SPOR", NULL, "SPK amp" },
2585 };
2586
2587 static const struct snd_soc_dapm_route rt5650_specific_dapm_routes[] = {
2588     { "A DAC1 L Mux", "DAC1",  "DAC1 MIXL"},
2589     { "A DAC1 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
2590     { "A DAC1 R Mux", "DAC1",  "DAC1 MIXR"},
2591     { "A DAC1 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
2592
2593     { "A DAC2 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
2594     { "A DAC2 L Mux", "Mono DAC Mixer", "Mono DAC MIXL"},
2595     { "A DAC2 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
2596     { "A DAC2 R Mux", "Mono DAC Mixer", "Mono DAC MIXR"},
2597
2598     { "DAC L1", NULL, "A DAC1 L Mux" },
2599     { "DAC R1", NULL, "A DAC1 R Mux" },
2600     { "DAC L2", NULL, "A DAC2 L Mux" },
2601     { "DAC R2", NULL, "A DAC2 R Mux" },
2602
2603     { "RT5650 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" },
2604     { "RT5650 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" },
2605     { "RT5650 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" },
2606     { "RT5650 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" },
2607
2608     { "RT5650 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" },
2609     { "RT5650 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" },
2610     { "RT5650 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" },
2611     { "RT5650 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" },
2612
2613     { "RT5650 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" },
2614     { "RT5650 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" },
2615     { "RT5650 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" },
2616     { "RT5650 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" },
2617
2618     { "IF1 ADC", NULL, "RT5650 IF1 ADC1 Swap Mux" },
2619     { "IF1 ADC", NULL, "RT5650 IF1 ADC2 Swap Mux" },
2620     { "IF1 ADC", NULL, "RT5650 IF1 ADC3 Swap Mux" },
2621
2622     { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/DAC_REF/Null", "IF1 ADC" },
2623     { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/Null/DAC_REF", "IF1 ADC" },
2624     { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/IF_ADC2/Null", "IF1 ADC" },
2625     { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/Null/IF_ADC2", "IF1 ADC" },
2626     { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/DAC_REF/IF_ADC2", "IF1 ADC" },
2627     { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/IF_ADC2/DAC_REF", "IF1 ADC" },
2628
2629     { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/DAC_REF/Null", "IF1 ADC" },
2630     { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/Null/DAC_REF", "IF1 ADC" },
2631     { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/IF_ADC1/Null", "IF1 ADC" },
2632     { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/Null/IF_ADC1", "IF1 ADC" },
2633     { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/DAC_REF/IF_ADC1", "IF1 ADC" },
2634     { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/IF_ADC1/DAC_REF", "IF1 ADC" },
2635
2636     { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/IF_ADC2/Null", "IF1 ADC" },
2637     { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/Null/IF_ADC2", "IF1 ADC" },
2638     { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/IF_ADC1/Null", "IF1 ADC" },
2639     { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/Null/IF_ADC1", "IF1 ADC" },
2640     { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC1/IF_ADC2", "IF1 ADC" },
2641     { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC2/IF_ADC1", "IF1 ADC" },
2642
2643     { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/IF_ADC2/DAC_REF", "IF1 ADC" },
2644     { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/DAC_REF/IF_ADC2", "IF1 ADC" },
2645     { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/IF_ADC1/DAC_REF", "IF1 ADC" },
2646     { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/DAC_REF/IF_ADC1", "IF1 ADC" },
2647     { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC1/IF_ADC2", "IF1 ADC" },
2648     { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC2/IF_ADC1", "IF1 ADC" },
2649     { "AIF1TX", NULL, "RT5650 IF1 ADC Mux" },
2650
2651     { "RT5650 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" },
2652     { "RT5650 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" },
2653     { "RT5650 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" },
2654     { "RT5650 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" },
2655
2656     { "RT5650 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" },
2657     { "RT5650 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" },
2658     { "RT5650 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" },
2659     { "RT5650 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" },
2660
2661     { "RT5650 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" },
2662     { "RT5650 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" },
2663     { "RT5650 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" },
2664     { "RT5650 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" },
2665
2666     { "RT5650 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" },
2667     { "RT5650 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" },
2668     { "RT5650 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" },
2669     { "RT5650 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" },
2670
2671     { "DAC1 L Mux", "IF1 DAC", "RT5650 IF1 DAC1 L Mux" },
2672     { "DAC1 R Mux", "IF1 DAC", "RT5650 IF1 DAC1 R Mux" },
2673
2674     { "DAC L2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 L Mux" },
2675     { "DAC R2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 R Mux" },
2676 };
2677
2678 static const struct snd_soc_dapm_route rt5645_specific_dapm_routes[] = {
2679     { "DAC L1", NULL, "Stereo DAC MIXL" },
2680     { "DAC R1", NULL, "Stereo DAC MIXR" },
2681     { "DAC L2", NULL, "Mono DAC MIXL" },
2682     { "DAC R2", NULL, "Mono DAC MIXR" },
2683
2684     { "RT5645 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" },
2685     { "RT5645 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" },
2686     { "RT5645 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" },
2687     { "RT5645 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" },
2688
2689     { "RT5645 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" },
2690     { "RT5645 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" },
2691     { "RT5645 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" },
2692     { "RT5645 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" },
2693
2694     { "RT5645 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" },
2695     { "RT5645 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" },
2696     { "RT5645 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" },
2697     { "RT5645 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" },
2698
2699     { "IF1 ADC", NULL, "RT5645 IF1 ADC1 Swap Mux" },
2700     { "IF1 ADC", NULL, "RT5645 IF1 ADC2 Swap Mux" },
2701     { "IF1 ADC", NULL, "RT5645 IF1 ADC3 Swap Mux" },
2702
2703     { "RT5645 IF1 ADC Mux", "IF_ADC1/IF_ADC2/VAD_ADC", "IF1 ADC" },
2704     { "RT5645 IF1 ADC Mux", "IF_ADC2/IF_ADC1/VAD_ADC", "IF1 ADC" },
2705     { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC1/IF_ADC2", "IF1 ADC" },
2706     { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC2/IF_ADC1", "IF1 ADC" },
2707     { "AIF1TX", NULL, "RT5645 IF1 ADC Mux" },
2708
2709     { "RT5645 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" },
2710     { "RT5645 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" },
2711     { "RT5645 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" },
2712     { "RT5645 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" },
2713
2714     { "RT5645 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" },
2715     { "RT5645 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" },
2716     { "RT5645 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" },
2717     { "RT5645 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" },
2718
2719     { "RT5645 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" },
2720     { "RT5645 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" },
2721     { "RT5645 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" },
2722     { "RT5645 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" },
2723
2724     { "RT5645 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" },
2725     { "RT5645 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" },
2726     { "RT5645 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" },
2727     { "RT5645 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" },
2728
2729     { "DAC1 L Mux", "IF1 DAC", "RT5645 IF1 DAC1 L Mux" },
2730     { "DAC1 R Mux", "IF1 DAC", "RT5645 IF1 DAC1 R Mux" },
2731
2732     { "DAC L2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 L Mux" },
2733     { "DAC R2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 R Mux" },
2734 };
2735
2736 static const struct snd_soc_dapm_route rt5645_old_dapm_routes[] = {
2737     { "SPOL MIX", "DAC R1 Switch", "DAC R1" },
2738     { "SPOL MIX", "SPKVOL R Switch", "SPKVOL R" },
2739 };
2740
2741 static int rt5645_hw_params(struct snd_pcm_substream *substream,
2742     struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2743 {
2744     struct snd_soc_component *component = dai->component;
2745     struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
2746     unsigned int val_len = 0, val_clk, mask_clk, dl_sft;
2747     int pre_div, bclk_ms, frame_size;
2748
2749     rt5645->lrck[dai->id] = params_rate(params);
2750     pre_div = rl6231_get_clk_info(rt5645->sysclk, rt5645->lrck[dai->id]);
2751     if (pre_div < 0) {
2752         dev_err(component->dev, "Unsupported clock setting\n");
2753         return -EINVAL;
2754     }
2755     frame_size = snd_soc_params_to_frame_size(params);
2756     if (frame_size < 0) {
2757         dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
2758         return -EINVAL;
2759     }
2760
2761     switch (rt5645->codec_type) {
2762     case CODEC_TYPE_RT5650:
2763         dl_sft = 4;
2764         break;
2765     default:
2766         dl_sft = 2;
2767         break;
2768     }
2769
2770     bclk_ms = frame_size > 32;
2771     rt5645->bclk[dai->id] = rt5645->lrck[dai->id] * (32 << bclk_ms);
2772
2773     dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
2774         rt5645->bclk[dai->id], rt5645->lrck[dai->id]);
2775     dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
2776                 bclk_ms, pre_div, dai->id);
2777
2778     switch (params_width(params)) {
2779     case 16:
2780         break;
2781     case 20:
2782         val_len = 0x1;
2783         break;
2784     case 24:
2785         val_len = 0x2;
2786         break;
2787     case 8:
2788         val_len = 0x3;
2789         break;
2790     default:
2791         return -EINVAL;
2792     }
2793
2794     switch (dai->id) {
2795     case RT5645_AIF1:
2796         mask_clk = RT5645_I2S_PD1_MASK;
2797         val_clk = pre_div << RT5645_I2S_PD1_SFT;
2798         snd_soc_component_update_bits(component, RT5645_I2S1_SDP,
2799             (0x3 << dl_sft), (val_len << dl_sft));
2800         snd_soc_component_update_bits(component, RT5645_ADDA_CLK1, mask_clk, val_clk);
2801         break;
2802     case  RT5645_AIF2:
2803         mask_clk = RT5645_I2S_BCLK_MS2_MASK | RT5645_I2S_PD2_MASK;
2804         val_clk = bclk_ms << RT5645_I2S_BCLK_MS2_SFT |
2805             pre_div << RT5645_I2S_PD2_SFT;
2806         snd_soc_component_update_bits(component, RT5645_I2S2_SDP,
2807             (0x3 << dl_sft), (val_len << dl_sft));
2808         snd_soc_component_update_bits(component, RT5645_ADDA_CLK1, mask_clk, val_clk);
2809         break;
2810     default:
2811         dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2812         return -EINVAL;
2813     }
2814
2815     return 0;
2816 }
2817
2818 static int rt5645_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2819 {
2820     struct snd_soc_component *component = dai->component;
2821     struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
2822     unsigned int reg_val = 0, pol_sft;
2823
2824     switch (rt5645->codec_type) {
2825     case CODEC_TYPE_RT5650:
2826         pol_sft = 8;
2827         break;
2828     default:
2829         pol_sft = 7;
2830         break;
2831     }
2832
2833     switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2834     case SND_SOC_DAIFMT_CBM_CFM:
2835         rt5645->master[dai->id] = 1;
2836         break;
2837     case SND_SOC_DAIFMT_CBS_CFS:
2838         reg_val |= RT5645_I2S_MS_S;
2839         rt5645->master[dai->id] = 0;
2840         break;
2841     default:
2842         return -EINVAL;
2843     }
2844
2845     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2846     case SND_SOC_DAIFMT_NB_NF:
2847         break;
2848     case SND_SOC_DAIFMT_IB_NF:
2849         reg_val |= (1 << pol_sft);
2850         break;
2851     default:
2852         return -EINVAL;
2853     }
2854
2855     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2856     case SND_SOC_DAIFMT_I2S:
2857         break;
2858     case SND_SOC_DAIFMT_LEFT_J:
2859         reg_val |= RT5645_I2S_DF_LEFT;
2860         break;
2861     case SND_SOC_DAIFMT_DSP_A:
2862         reg_val |= RT5645_I2S_DF_PCM_A;
2863         break;
2864     case SND_SOC_DAIFMT_DSP_B:
2865         reg_val |= RT5645_I2S_DF_PCM_B;
2866         break;
2867     default:
2868         return -EINVAL;
2869     }
2870     switch (dai->id) {
2871     case RT5645_AIF1:
2872         snd_soc_component_update_bits(component, RT5645_I2S1_SDP,
2873             RT5645_I2S_MS_MASK | (1 << pol_sft) |
2874             RT5645_I2S_DF_MASK, reg_val);
2875         break;
2876     case RT5645_AIF2:
2877         snd_soc_component_update_bits(component, RT5645_I2S2_SDP,
2878             RT5645_I2S_MS_MASK | (1 << pol_sft) |
2879             RT5645_I2S_DF_MASK, reg_val);
2880         break;
2881     default:
2882         dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2883         return -EINVAL;
2884     }
2885     return 0;
2886 }
2887
2888 static int rt5645_set_dai_sysclk(struct snd_soc_dai *dai,
2889         int clk_id, unsigned int freq, int dir)
2890 {
2891     struct snd_soc_component *component = dai->component;
2892     struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
2893     unsigned int reg_val = 0;
2894
2895     if (freq == rt5645->sysclk && clk_id == rt5645->sysclk_src)
2896         return 0;
2897
2898     switch (clk_id) {
2899     case RT5645_SCLK_S_MCLK:
2900         reg_val |= RT5645_SCLK_SRC_MCLK;
2901         break;
2902     case RT5645_SCLK_S_PLL1:
2903         reg_val |= RT5645_SCLK_SRC_PLL1;
2904         break;
2905     case RT5645_SCLK_S_RCCLK:
2906         reg_val |= RT5645_SCLK_SRC_RCCLK;
2907         break;
2908     default:
2909         dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2910         return -EINVAL;
2911     }
2912     snd_soc_component_update_bits(component, RT5645_GLB_CLK,
2913         RT5645_SCLK_SRC_MASK, reg_val);
2914     rt5645->sysclk = freq;
2915     rt5645->sysclk_src = clk_id;
2916
2917     dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
2918
2919     return 0;
2920 }
2921
2922 static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2923             unsigned int freq_in, unsigned int freq_out)
2924 {
2925     struct snd_soc_component *component = dai->component;
2926     struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
2927     struct rl6231_pll_code pll_code;
2928     int ret;
2929
2930     if (source == rt5645->pll_src && freq_in == rt5645->pll_in &&
2931         freq_out == rt5645->pll_out)
2932         return 0;
2933
2934     if (!freq_in || !freq_out) {
2935         dev_dbg(component->dev, "PLL disabled\n");
2936
2937         rt5645->pll_in = 0;
2938         rt5645->pll_out = 0;
2939         snd_soc_component_update_bits(component, RT5645_GLB_CLK,
2940             RT5645_SCLK_SRC_MASK, RT5645_SCLK_SRC_MCLK);
2941         return 0;
2942     }
2943
2944     switch (source) {
2945     case RT5645_PLL1_S_MCLK:
2946         snd_soc_component_update_bits(component, RT5645_GLB_CLK,
2947             RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_MCLK);
2948         break;
2949     case RT5645_PLL1_S_BCLK1:
2950     case RT5645_PLL1_S_BCLK2:
2951         switch (dai->id) {
2952         case RT5645_AIF1:
2953             snd_soc_component_update_bits(component, RT5645_GLB_CLK,
2954                 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK1);
2955             break;
2956         case  RT5645_AIF2:
2957             snd_soc_component_update_bits(component, RT5645_GLB_CLK,
2958                 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK2);
2959             break;
2960         default:
2961             dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2962             return -EINVAL;
2963         }
2964         break;
2965     default:
2966         dev_err(component->dev, "Unknown PLL source %d\n", source);
2967         return -EINVAL;
2968     }
2969
2970     ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2971     if (ret < 0) {
2972         dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
2973         return ret;
2974     }
2975
2976     dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
2977         pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2978         pll_code.n_code, pll_code.k_code);
2979
2980     snd_soc_component_write(component, RT5645_PLL_CTRL1,
2981         pll_code.n_code << RT5645_PLL_N_SFT | pll_code.k_code);
2982     snd_soc_component_write(component, RT5645_PLL_CTRL2,
2983         ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5645_PLL_M_SFT) |
2984         (pll_code.m_bp << RT5645_PLL_M_BP_SFT));
2985
2986     rt5645->pll_in = freq_in;
2987     rt5645->pll_out = freq_out;
2988     rt5645->pll_src = source;
2989
2990     return 0;
2991 }
2992
2993 static int rt5645_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2994             unsigned int rx_mask, int slots, int slot_width)
2995 {
2996     struct snd_soc_component *component = dai->component;
2997     struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
2998     unsigned int i_slot_sft, o_slot_sft, i_width_sht, o_width_sht, en_sft;
2999     unsigned int mask, val = 0;
3000
3001     switch (rt5645->codec_type) {
3002     case CODEC_TYPE_RT5650:
3003         en_sft = 15;
3004         i_slot_sft = 10;
3005         o_slot_sft = 8;
3006         i_width_sht = 6;
3007         o_width_sht = 4;
3008         mask = 0x8ff0;
3009         break;
3010     default:
3011         en_sft = 14;
3012         i_slot_sft = o_slot_sft = 12;
3013         i_width_sht = o_width_sht = 10;
3014         mask = 0x7c00;
3015         break;
3016     }
3017     if (rx_mask || tx_mask) {
3018         val |= (1 << en_sft);
3019         if (rt5645->codec_type == CODEC_TYPE_RT5645)
3020             snd_soc_component_update_bits(component, RT5645_BASS_BACK,
3021                 RT5645_G_BB_BST_MASK, RT5645_G_BB_BST_25DB);
3022     }
3023
3024     switch (slots) {
3025     case 4:
3026         val |= (1 << i_slot_sft) | (1 << o_slot_sft);
3027         break;
3028     case 6:
3029         val |= (2 << i_slot_sft) | (2 << o_slot_sft);
3030         break;
3031     case 8:
3032         val |= (3 << i_slot_sft) | (3 << o_slot_sft);
3033         break;
3034     case 2:
3035     default:
3036         break;
3037     }
3038
3039     switch (slot_width) {
3040     case 20:
3041         val |= (1 << i_width_sht) | (1 << o_width_sht);
3042         break;
3043     case 24:
3044         val |= (2 << i_width_sht) | (2 << o_width_sht);
3045         break;
3046     case 32:
3047         val |= (3 << i_width_sht) | (3 << o_width_sht);
3048         break;
3049     case 16:
3050     default:
3051         break;
3052     }
3053
3054     snd_soc_component_update_bits(component, RT5645_TDM_CTRL_1, mask, val);
3055
3056     return 0;
3057 }
3058
3059 static int rt5645_set_bias_level(struct snd_soc_component *component,
3060             enum snd_soc_bias_level level)
3061 {
3062     struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
3063
3064     switch (level) {
3065     case SND_SOC_BIAS_PREPARE:
3066         if (SND_SOC_BIAS_STANDBY == snd_soc_component_get_bias_level(component)) {
3067             snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
3068                 RT5645_PWR_VREF1 | RT5645_PWR_MB |
3069                 RT5645_PWR_BG | RT5645_PWR_VREF2,
3070                 RT5645_PWR_VREF1 | RT5645_PWR_MB |
3071                 RT5645_PWR_BG | RT5645_PWR_VREF2);
3072             mdelay(10);
3073             snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
3074                 RT5645_PWR_FV1 | RT5645_PWR_FV2,
3075                 RT5645_PWR_FV1 | RT5645_PWR_FV2);
3076             snd_soc_component_update_bits(component, RT5645_GEN_CTRL1,
3077                 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
3078         }
3079         break;
3080
3081     case SND_SOC_BIAS_STANDBY:
3082         snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
3083             RT5645_PWR_VREF1 | RT5645_PWR_MB |
3084             RT5645_PWR_BG | RT5645_PWR_VREF2,
3085             RT5645_PWR_VREF1 | RT5645_PWR_MB |
3086             RT5645_PWR_BG | RT5645_PWR_VREF2);
3087         mdelay(10);
3088         snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
3089             RT5645_PWR_FV1 | RT5645_PWR_FV2,
3090             RT5645_PWR_FV1 | RT5645_PWR_FV2);
3091         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
3092             snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140);
3093             msleep(40);
3094             if (rt5645->en_button_func)
3095                 queue_delayed_work(system_power_efficient_wq,
3096                     &rt5645->jack_detect_work,
3097                     msecs_to_jiffies(0));
3098         }
3099         break;
3100
3101     case SND_SOC_BIAS_OFF:
3102         snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1100);
3103         if (!rt5645->en_button_func)
3104             snd_soc_component_update_bits(component, RT5645_GEN_CTRL1,
3105                     RT5645_DIG_GATE_CTRL, 0);
3106         snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
3107                 RT5645_PWR_VREF1 | RT5645_PWR_MB |
3108                 RT5645_PWR_BG | RT5645_PWR_VREF2 |
3109                 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0x0);
3110         break;
3111
3112     default:
3113         break;
3114     }
3115
3116     return 0;
3117 }
3118
3119 static void rt5645_enable_push_button_irq(struct snd_soc_component *component,
3120     bool enable)
3121 {
3122     struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3123
3124     if (enable) {
3125         snd_soc_dapm_force_enable_pin(dapm, "ADC L power");
3126         snd_soc_dapm_force_enable_pin(dapm, "ADC R power");
3127         snd_soc_dapm_sync(dapm);
3128
3129         snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD1, 0x3, 0x3);
3130         snd_soc_component_update_bits(component,
3131                     RT5645_INT_IRQ_ST, 0x8, 0x8);
3132         snd_soc_component_update_bits(component,
3133                     RT5650_4BTN_IL_CMD2, 0x8000, 0x8000);
3134         snd_soc_component_read(component, RT5650_4BTN_IL_CMD1);
3135         pr_debug("%s read %x = %x\n", __func__, RT5650_4BTN_IL_CMD1,
3136             snd_soc_component_read(component, RT5650_4BTN_IL_CMD1));
3137     } else {
3138         snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD2, 0x8000, 0x0);
3139         snd_soc_component_update_bits(component, RT5645_INT_IRQ_ST, 0x8, 0x0);
3140
3141         snd_soc_dapm_disable_pin(dapm, "ADC L power");
3142         snd_soc_dapm_disable_pin(dapm, "ADC R power");
3143         snd_soc_dapm_sync(dapm);
3144     }
3145 }
3146
3147 static int rt5645_jack_detect(struct snd_soc_component *component, int jack_insert)
3148 {
3149     struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3150     struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
3151     unsigned int val;
3152
3153     if (jack_insert) {
3154         regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0e06);
3155
3156         /* for jack type detect */
3157         snd_soc_dapm_force_enable_pin(dapm, "LDO2");
3158         snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power");
3159         snd_soc_dapm_sync(dapm);
3160         if (!dapm->card->instantiated) {
3161             /* Power up necessary bits for JD if dapm is
3162                not ready yet */
3163             regmap_update_bits(rt5645->regmap, RT5645_PWR_ANLG1,
3164                 RT5645_PWR_MB | RT5645_PWR_VREF2,
3165                 RT5645_PWR_MB | RT5645_PWR_VREF2);
3166             regmap_update_bits(rt5645->regmap, RT5645_PWR_MIXER,
3167                 RT5645_PWR_LDO2, RT5645_PWR_LDO2);
3168             regmap_update_bits(rt5645->regmap, RT5645_PWR_VOL,
3169                 RT5645_PWR_MIC_DET, RT5645_PWR_MIC_DET);
3170         }
3171
3172         regmap_write(rt5645->regmap, RT5645_JD_CTRL3, 0x00f0);
3173         regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2,
3174             RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD);
3175         regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1,
3176             RT5645_CBJ_BST1_EN, RT5645_CBJ_BST1_EN);
3177         msleep(100);
3178         regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2,
3179             RT5645_CBJ_MN_JD, 0);
3180
3181         msleep(600);
3182         regmap_read(rt5645->regmap, RT5645_IN1_CTRL3, &val);
3183         val &= 0x7;
3184         dev_dbg(component->dev, "val = %d\n", val);
3185
3186         if ((val == 1 || val == 2) && !rt5645->pdata.no_headset_mic) {
3187             rt5645->jack_type = SND_JACK_HEADSET;
3188             if (rt5645->en_button_func) {
3189                 rt5645_enable_push_button_irq(component, true);
3190             }
3191         } else {
3192             snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
3193             snd_soc_dapm_sync(dapm);
3194             rt5645->jack_type = SND_JACK_HEADPHONE;
3195         }
3196         if (rt5645->pdata.level_trigger_irq)
3197             regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
3198                 RT5645_JD_1_1_MASK, RT5645_JD_1_1_NOR);
3199     } else { /* jack out */
3200         rt5645->jack_type = 0;
3201
3202         regmap_update_bits(rt5645->regmap, RT5645_HP_VOL,
3203             RT5645_L_MUTE | RT5645_R_MUTE,
3204             RT5645_L_MUTE | RT5645_R_MUTE);
3205         regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2,
3206             RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD);
3207         regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1,
3208             RT5645_CBJ_BST1_EN, 0);
3209
3210         if (rt5645->en_button_func)
3211             rt5645_enable_push_button_irq(component, false);
3212
3213         if (rt5645->pdata.jd_mode == 0)
3214             snd_soc_dapm_disable_pin(dapm, "LDO2");
3215         snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
3216         snd_soc_dapm_sync(dapm);
3217         if (rt5645->pdata.level_trigger_irq)
3218             regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
3219                 RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV);
3220     }
3221
3222     return rt5645->jack_type;
3223 }
3224
3225 static int rt5645_button_detect(struct snd_soc_component *component)
3226 {
3227     int btn_type, val;
3228
3229     val = snd_soc_component_read(component, RT5650_4BTN_IL_CMD1);
3230     pr_debug("val=0x%x\n", val);
3231     btn_type = val & 0xfff0;
3232     snd_soc_component_write(component, RT5650_4BTN_IL_CMD1, val);
3233
3234     return btn_type;
3235 }
3236
3237 static irqreturn_t rt5645_irq(int irq, void *data);
3238
3239 int rt5645_set_jack_detect(struct snd_soc_component *component,
3240     struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack,
3241     struct snd_soc_jack *btn_jack)
3242 {
3243     struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
3244
3245     rt5645->hp_jack = hp_jack;
3246     rt5645->mic_jack = mic_jack;
3247     rt5645->btn_jack = btn_jack;
3248     if (rt5645->btn_jack && rt5645->codec_type == CODEC_TYPE_RT5650) {
3249         rt5645->en_button_func = true;
3250         regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3251                 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
3252         regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL1,
3253                 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
3254     }
3255     rt5645_irq(0, rt5645);
3256
3257     return 0;
3258 }
3259 EXPORT_SYMBOL_GPL(rt5645_set_jack_detect);
3260
3261 static void rt5645_jack_detect_work(struct work_struct *work)
3262 {
3263     struct rt5645_priv *rt5645 =
3264         container_of(work, struct rt5645_priv, jack_detect_work.work);
3265     int val, btn_type, gpio_state = 0, report = 0;
3266
3267     if (!rt5645->component)
3268         return;
3269
3270     switch (rt5645->pdata.jd_mode) {
3271     case 0: /* Not using rt5645 JD */
3272         if (rt5645->gpiod_hp_det) {
3273             gpio_state = gpiod_get_value(rt5645->gpiod_hp_det);
3274             if (rt5645->pdata.inv_hp_pol)
3275                 gpio_state ^= 1;
3276             dev_dbg(rt5645->component->dev, "gpio_state = %d\n",
3277                 gpio_state);
3278             report = rt5645_jack_detect(rt5645->component, gpio_state);
3279         }
3280         snd_soc_jack_report(rt5645->hp_jack,
3281                     report, SND_JACK_HEADPHONE);
3282         snd_soc_jack_report(rt5645->mic_jack,
3283                     report, SND_JACK_MICROPHONE);
3284         return;
3285     case 4:
3286         val = snd_soc_component_read(rt5645->component, RT5645_A_JD_CTRL1) & 0x0020;
3287         break;
3288     default: /* read rt5645 jd1_1 status */
3289         val = snd_soc_component_read(rt5645->component, RT5645_INT_IRQ_ST) & 0x1000;
3290         break;
3291
3292     }
3293
3294     if (!val && (rt5645->jack_type == 0)) { /* jack in */
3295         report = rt5645_jack_detect(rt5645->component, 1);
3296     } else if (!val && rt5645->jack_type != 0) {
3297         /* for push button and jack out */
3298         btn_type = 0;
3299         if (snd_soc_component_read(rt5645->component, RT5645_INT_IRQ_ST) & 0x4) {
3300             /* button pressed */
3301             report = SND_JACK_HEADSET;
3302             btn_type = rt5645_button_detect(rt5645->component);
3303             /* rt5650 can report three kinds of button behavior,
3304                one click, double click and hold. However,
3305                currently we will report button pressed/released
3306                event. So all the three button behaviors are
3307                treated as button pressed. */
3308             switch (btn_type) {
3309             case 0x8000:
3310             case 0x4000:
3311             case 0x2000:
3312                 report |= SND_JACK_BTN_0;
3313                 break;
3314             case 0x1000:
3315             case 0x0800:
3316             case 0x0400:
3317                 report |= SND_JACK_BTN_1;
3318                 break;
3319             case 0x0200:
3320             case 0x0100:
3321             case 0x0080:
3322                 report |= SND_JACK_BTN_2;
3323                 break;
3324             case 0x0040:
3325             case 0x0020:
3326             case 0x0010:
3327                 report |= SND_JACK_BTN_3;
3328                 break;
3329             case 0x0000: /* unpressed */
3330                 break;
3331             default:
3332                 dev_err(rt5645->component->dev,
3333                     "Unexpected button code 0x%04x\n",
3334                     btn_type);
3335                 break;
3336             }
3337         }
3338         if (btn_type == 0)/* button release */
3339             report =  rt5645->jack_type;
3340         else {
3341             mod_timer(&rt5645->btn_check_timer,
3342                 msecs_to_jiffies(100));
3343         }
3344     } else {
3345         /* jack out */
3346         report = 0;
3347         snd_soc_component_update_bits(rt5645->component,
3348                     RT5645_INT_IRQ_ST, 0x1, 0x0);
3349         rt5645_jack_detect(rt5645->component, 0);
3350     }
3351
3352     snd_soc_jack_report(rt5645->hp_jack, report, SND_JACK_HEADPHONE);
3353     snd_soc_jack_report(rt5645->mic_jack, report, SND_JACK_MICROPHONE);
3354     if (rt5645->en_button_func)
3355         snd_soc_jack_report(rt5645->btn_jack,
3356             report, SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3357                 SND_JACK_BTN_2 | SND_JACK_BTN_3);
3358 }
3359
3360 static void rt5645_rcclock_work(struct work_struct *work)
3361 {
3362     struct rt5645_priv *rt5645 =
3363         container_of(work, struct rt5645_priv, rcclock_work.work);
3364
3365     regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
3366         RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PD);
3367 }
3368
3369 static irqreturn_t rt5645_irq(int irq, void *data)
3370 {
3371     struct rt5645_priv *rt5645 = data;
3372
3373     queue_delayed_work(system_power_efficient_wq,
3374                &rt5645->jack_detect_work, msecs_to_jiffies(250));
3375
3376     return IRQ_HANDLED;
3377 }
3378
3379 static void rt5645_btn_check_callback(struct timer_list *t)
3380 {
3381     struct rt5645_priv *rt5645 = from_timer(rt5645, t, btn_check_timer);
3382
3383     queue_delayed_work(system_power_efficient_wq,
3384            &rt5645->jack_detect_work, msecs_to_jiffies(5));
3385 }
3386
3387 static int rt5645_probe(struct snd_soc_component *component)
3388 {
3389     struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3390     struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
3391
3392     rt5645->component = component;
3393
3394     switch (rt5645->codec_type) {
3395     case CODEC_TYPE_RT5645:
3396         snd_soc_dapm_new_controls(dapm,
3397             rt5645_specific_dapm_widgets,
3398             ARRAY_SIZE(rt5645_specific_dapm_widgets));
3399         snd_soc_dapm_add_routes(dapm,
3400             rt5645_specific_dapm_routes,
3401             ARRAY_SIZE(rt5645_specific_dapm_routes));
3402         if (rt5645->v_id < 3) {
3403             snd_soc_dapm_add_routes(dapm,
3404                 rt5645_old_dapm_routes,
3405                 ARRAY_SIZE(rt5645_old_dapm_routes));
3406         }
3407         break;
3408     case CODEC_TYPE_RT5650:
3409         snd_soc_dapm_new_controls(dapm,
3410             rt5650_specific_dapm_widgets,
3411             ARRAY_SIZE(rt5650_specific_dapm_widgets));
3412         snd_soc_dapm_add_routes(dapm,
3413             rt5650_specific_dapm_routes,
3414             ARRAY_SIZE(rt5650_specific_dapm_routes));
3415         break;
3416     }
3417
3418     snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
3419
3420     /* for JD function */
3421     if (rt5645->pdata.jd_mode) {
3422         snd_soc_dapm_force_enable_pin(dapm, "JD Power");
3423         snd_soc_dapm_force_enable_pin(dapm, "LDO2");
3424         snd_soc_dapm_sync(dapm);
3425     }
3426
3427     if (rt5645->pdata.long_name)
3428         component->card->long_name = rt5645->pdata.long_name;
3429
3430     rt5645->eq_param = devm_kcalloc(component->dev,
3431         RT5645_HWEQ_NUM, sizeof(struct rt5645_eq_param_s),
3432         GFP_KERNEL);
3433
3434     if (!rt5645->eq_param)
3435         return -ENOMEM;
3436
3437     return 0;
3438 }
3439
3440 static void rt5645_remove(struct snd_soc_component *component)
3441 {
3442     rt5645_reset(component);
3443 }
3444
3445 #ifdef CONFIG_PM
3446 static int rt5645_suspend(struct snd_soc_component *component)
3447 {
3448     struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
3449
3450     regcache_cache_only(rt5645->regmap, true);
3451     regcache_mark_dirty(rt5645->regmap);
3452
3453     return 0;
3454 }
3455
3456 static int rt5645_resume(struct snd_soc_component *component)
3457 {
3458     struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
3459
3460     regcache_cache_only(rt5645->regmap, false);
3461     regcache_sync(rt5645->regmap);
3462
3463     return 0;
3464 }
3465 #else
3466 #define rt5645_suspend NULL
3467 #define rt5645_resume NULL
3468 #endif
3469
3470 #define RT5645_STEREO_RATES SNDRV_PCM_RATE_8000_96000
3471 #define RT5645_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3472             SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3473
3474 static const struct snd_soc_dai_ops rt5645_aif_dai_ops = {
3475     .hw_params = rt5645_hw_params,
3476     .set_fmt = rt5645_set_dai_fmt,
3477     .set_sysclk = rt5645_set_dai_sysclk,
3478     .set_tdm_slot = rt5645_set_tdm_slot,
3479     .set_pll = rt5645_set_dai_pll,
3480 };
3481
3482 static struct snd_soc_dai_driver rt5645_dai[] = {
3483     {
3484         .name = "rt5645-aif1",
3485         .id = RT5645_AIF1,
3486         .playback = {
3487             .stream_name = "AIF1 Playback",
3488             .channels_min = 1,
3489             .channels_max = 2,
3490             .rates = RT5645_STEREO_RATES,
3491             .formats = RT5645_FORMATS,
3492         },
3493         .capture = {
3494             .stream_name = "AIF1 Capture",
3495             .channels_min = 1,
3496             .channels_max = 4,
3497             .rates = RT5645_STEREO_RATES,
3498             .formats = RT5645_FORMATS,
3499         },
3500         .ops = &rt5645_aif_dai_ops,
3501     },
3502     {
3503         .name = "rt5645-aif2",
3504         .id = RT5645_AIF2,
3505         .playback = {
3506             .stream_name = "AIF2 Playback",
3507             .channels_min = 1,
3508             .channels_max = 2,
3509             .rates = RT5645_STEREO_RATES,
3510             .formats = RT5645_FORMATS,
3511         },
3512         .capture = {
3513             .stream_name = "AIF2 Capture",
3514             .channels_min = 1,
3515             .channels_max = 2,
3516             .rates = RT5645_STEREO_RATES,
3517             .formats = RT5645_FORMATS,
3518         },
3519         .ops = &rt5645_aif_dai_ops,
3520     },
3521 };
3522
3523 static const struct snd_soc_component_driver soc_component_dev_rt5645 = {
3524     .probe          = rt5645_probe,
3525     .remove         = rt5645_remove,
3526     .suspend        = rt5645_suspend,
3527     .resume         = rt5645_resume,
3528     .set_bias_level     = rt5645_set_bias_level,
3529     .controls       = rt5645_snd_controls,
3530     .num_controls       = ARRAY_SIZE(rt5645_snd_controls),
3531     .dapm_widgets       = rt5645_dapm_widgets,
3532     .num_dapm_widgets   = ARRAY_SIZE(rt5645_dapm_widgets),
3533     .dapm_routes        = rt5645_dapm_routes,
3534     .num_dapm_routes    = ARRAY_SIZE(rt5645_dapm_routes),
3535     .use_pmdown_time    = 1,
3536     .endianness     = 1,
3537 };
3538
3539 static const struct regmap_config rt5645_regmap = {
3540     .reg_bits = 8,
3541     .val_bits = 16,
3542     .use_single_read = true,
3543     .use_single_write = true,
3544     .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) *
3545                            RT5645_PR_SPACING),
3546     .volatile_reg = rt5645_volatile_register,
3547     .readable_reg = rt5645_readable_register,
3548
3549     .cache_type = REGCACHE_RBTREE,
3550     .reg_defaults = rt5645_reg,
3551     .num_reg_defaults = ARRAY_SIZE(rt5645_reg),
3552     .ranges = rt5645_ranges,
3553     .num_ranges = ARRAY_SIZE(rt5645_ranges),
3554 };
3555
3556 static const struct regmap_config rt5650_regmap = {
3557     .reg_bits = 8,
3558     .val_bits = 16,
3559     .use_single_read = true,
3560     .use_single_write = true,
3561     .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) *
3562                            RT5645_PR_SPACING),
3563     .volatile_reg = rt5645_volatile_register,
3564     .readable_reg = rt5645_readable_register,
3565
3566     .cache_type = REGCACHE_RBTREE,
3567     .reg_defaults = rt5650_reg,
3568     .num_reg_defaults = ARRAY_SIZE(rt5650_reg),
3569     .ranges = rt5645_ranges,
3570     .num_ranges = ARRAY_SIZE(rt5645_ranges),
3571 };
3572
3573 static const struct regmap_config temp_regmap = {
3574     .name="nocache",
3575     .reg_bits = 8,
3576     .val_bits = 16,
3577     .use_single_read = true,
3578     .use_single_write = true,
3579     .max_register = RT5645_VENDOR_ID2 + 1,
3580     .cache_type = REGCACHE_NONE,
3581 };
3582
3583 static const struct i2c_device_id rt5645_i2c_id[] = {
3584     { "rt5645", 0 },
3585     { "rt5650", 0 },
3586     { }
3587 };
3588 MODULE_DEVICE_TABLE(i2c, rt5645_i2c_id);
3589
3590 #ifdef CONFIG_OF
3591 static const struct of_device_id rt5645_of_match[] = {
3592     { .compatible = "realtek,rt5645", },
3593     { .compatible = "realtek,rt5650", },
3594     { }
3595 };
3596 MODULE_DEVICE_TABLE(of, rt5645_of_match);
3597 #endif
3598
3599 #ifdef CONFIG_ACPI
3600 static const struct acpi_device_id rt5645_acpi_match[] = {
3601     { "10EC5645", 0 },
3602     { "10EC5648", 0 },
3603     { "10EC5650", 0 },
3604     { "10EC5640", 0 },
3605     { "10EC3270", 0 },
3606     {},
3607 };
3608 MODULE_DEVICE_TABLE(acpi, rt5645_acpi_match);
3609 #endif
3610
3611 static const struct rt5645_platform_data intel_braswell_platform_data = {
3612     .dmic1_data_pin = RT5645_DMIC1_DISABLE,
3613     .dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
3614     .jd_mode = 3,
3615 };
3616
3617 static const struct rt5645_platform_data buddy_platform_data = {
3618     .dmic1_data_pin = RT5645_DMIC_DATA_GPIO5,
3619     .dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
3620     .jd_mode = 4,
3621     .level_trigger_irq = true,
3622 };
3623
3624 static const struct rt5645_platform_data gpd_win_platform_data = {
3625     .jd_mode = 3,
3626     .inv_jd1_1 = true,
3627     .long_name = "gpd-win-pocket-rt5645",
3628     /* The GPD pocket has a diff. mic, for the win this does not matter. */
3629     .in2_diff = true,
3630 };
3631
3632 static const struct rt5645_platform_data asus_t100ha_platform_data = {
3633     .dmic1_data_pin = RT5645_DMIC_DATA_IN2N,
3634     .dmic2_data_pin = RT5645_DMIC2_DISABLE,
3635     .jd_mode = 3,
3636     .inv_jd1_1 = true,
3637 };
3638
3639 static const struct rt5645_platform_data asus_t101ha_platform_data = {
3640     .dmic1_data_pin = RT5645_DMIC_DATA_IN2N,
3641     .dmic2_data_pin = RT5645_DMIC2_DISABLE,
3642     .jd_mode = 3,
3643 };
3644
3645 static const struct rt5645_platform_data lenovo_ideapad_miix_310_pdata = {
3646     .jd_mode = 3,
3647     .in2_diff = true,
3648 };
3649
3650 static const struct rt5645_platform_data jd_mode3_platform_data = {
3651     .jd_mode = 3,
3652 };
3653
3654 static const struct rt5645_platform_data lattepanda_board_platform_data = {
3655     .jd_mode = 2,
3656     .inv_jd1_1 = true
3657 };
3658
3659 static const struct rt5645_platform_data kahlee_platform_data = {
3660     .dmic1_data_pin = RT5645_DMIC_DATA_GPIO5,
3661     .dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
3662     .jd_mode = 3,
3663 };
3664
3665 static const struct rt5645_platform_data ecs_ef20_platform_data = {
3666     .dmic1_data_pin = RT5645_DMIC1_DISABLE,
3667     .dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
3668     .inv_hp_pol = 1,
3669 };
3670
3671 static const struct acpi_gpio_params ef20_hp_detect = { 1, 0, false };
3672
3673 static const struct acpi_gpio_mapping cht_rt5645_ef20_gpios[] = {
3674     { "hp-detect-gpios", &ef20_hp_detect, 1 },
3675     { },
3676 };
3677
3678 static int cht_rt5645_ef20_quirk_cb(const struct dmi_system_id *id)
3679 {
3680     cht_rt5645_gpios = cht_rt5645_ef20_gpios;
3681     return 1;
3682 }
3683
3684 static const struct dmi_system_id dmi_platform_data[] = {
3685     {
3686         .ident = "Chrome Buddy",
3687         .matches = {
3688             DMI_MATCH(DMI_PRODUCT_NAME, "Buddy"),
3689         },
3690         .driver_data = (void *)&buddy_platform_data,
3691     },
3692     {
3693         .ident = "Intel Strago",
3694         .matches = {
3695             DMI_MATCH(DMI_PRODUCT_NAME, "Strago"),
3696         },
3697         .driver_data = (void *)&intel_braswell_platform_data,
3698     },
3699     {
3700         .ident = "Google Chrome",
3701         .matches = {
3702             DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
3703         },
3704         .driver_data = (void *)&intel_braswell_platform_data,
3705     },
3706     {
3707         .ident = "Google Setzer",
3708         .matches = {
3709             DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"),
3710         },
3711         .driver_data = (void *)&intel_braswell_platform_data,
3712     },
3713     {
3714         .ident = "Microsoft Surface 3",
3715         .matches = {
3716             DMI_MATCH(DMI_PRODUCT_NAME, "Surface 3"),
3717         },
3718         .driver_data = (void *)&intel_braswell_platform_data,
3719     },
3720     {
3721         /*
3722          * Match for the GPDwin which unfortunately uses somewhat
3723          * generic dmi strings, which is why we test for 4 strings.
3724          * Comparing against 23 other byt/cht boards, board_vendor
3725          * and board_name are unique to the GPDwin, where as only one
3726          * other board has the same board_serial and 3 others have
3727          * the same default product_name. Also the GPDwin is the
3728          * only device to have both board_ and product_name not set.
3729          */
3730         .ident = "GPD Win / Pocket",
3731         .matches = {
3732             DMI_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),
3733             DMI_MATCH(DMI_BOARD_NAME, "Default string"),
3734             DMI_MATCH(DMI_BOARD_SERIAL, "Default string"),
3735             DMI_MATCH(DMI_PRODUCT_NAME, "Default string"),
3736         },
3737         .driver_data = (void *)&gpd_win_platform_data,
3738     },
3739     {
3740         .ident = "ASUS T100HAN",
3741         .matches = {
3742             DMI_EXACT_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
3743             DMI_MATCH(DMI_PRODUCT_NAME, "T100HAN"),
3744         },
3745         .driver_data = (void *)&asus_t100ha_platform_data,
3746     },
3747     {
3748         .ident = "ASUS T101HA",
3749         .matches = {
3750             DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
3751             DMI_MATCH(DMI_PRODUCT_NAME, "T101HA"),
3752         },
3753         .driver_data = (void *)&asus_t101ha_platform_data,
3754     },
3755     {
3756         .ident = "MINIX Z83-4",
3757         .matches = {
3758             DMI_EXACT_MATCH(DMI_SYS_VENDOR, "MINIX"),
3759             DMI_MATCH(DMI_PRODUCT_NAME, "Z83-4"),
3760         },
3761         .driver_data = (void *)&jd_mode3_platform_data,
3762     },
3763     {
3764         .ident = "Teclast X80 Pro",
3765         .matches = {
3766             DMI_MATCH(DMI_SYS_VENDOR, "TECLAST"),
3767             DMI_MATCH(DMI_PRODUCT_NAME, "X80 Pro"),
3768         },
3769         .driver_data = (void *)&jd_mode3_platform_data,
3770     },
3771     {
3772         .ident = "Lenovo Ideapad Miix 310",
3773         .matches = {
3774           DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"),
3775           DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "80SG"),
3776           DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "MIIX 310-10ICR"),
3777         },
3778         .driver_data = (void *)&lenovo_ideapad_miix_310_pdata,
3779     },
3780     {
3781         .ident = "Lenovo Ideapad Miix 320",
3782         .matches = {
3783           DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"),
3784           DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "80XF"),
3785           DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "Lenovo MIIX 320-10ICR"),
3786         },
3787         .driver_data = (void *)&intel_braswell_platform_data,
3788     },
3789     {
3790         .ident = "LattePanda board",
3791         .matches = {
3792           DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),
3793           DMI_EXACT_MATCH(DMI_BOARD_NAME, "Cherry Trail CR"),
3794           DMI_EXACT_MATCH(DMI_BOARD_VERSION, "Default string"),
3795         },
3796         .driver_data = (void *)&lattepanda_board_platform_data,
3797     },
3798     {
3799         .ident = "Chrome Kahlee",
3800         .matches = {
3801             DMI_MATCH(DMI_PRODUCT_NAME, "Kahlee"),
3802         },
3803         .driver_data = (void *)&kahlee_platform_data,
3804     },
3805     {
3806         .ident = "Medion E1239T",
3807         .matches = {
3808             DMI_EXACT_MATCH(DMI_SYS_VENDOR, "MEDION"),
3809             DMI_MATCH(DMI_PRODUCT_NAME, "E1239T MD60568"),
3810         },
3811         .driver_data = (void *)&intel_braswell_platform_data,
3812     },
3813     {
3814         .ident = "EF20",
3815         .callback = cht_rt5645_ef20_quirk_cb,
3816         .matches = {
3817             DMI_MATCH(DMI_PRODUCT_NAME, "EF20"),
3818         },
3819         .driver_data = (void *)&ecs_ef20_platform_data,
3820     },
3821     {
3822         .ident = "EF20EA",
3823         .callback = cht_rt5645_ef20_quirk_cb,
3824         .matches = {
3825             DMI_MATCH(DMI_PRODUCT_NAME, "EF20EA"),
3826         },
3827         .driver_data = (void *)&ecs_ef20_platform_data,
3828     },
3829     { }
3830 };
3831
3832 static bool rt5645_check_dp(struct device *dev)
3833 {
3834     if (device_property_present(dev, "realtek,in2-differential") ||
3835         device_property_present(dev, "realtek,dmic1-data-pin") ||
3836         device_property_present(dev, "realtek,dmic2-data-pin") ||
3837         device_property_present(dev, "realtek,jd-mode"))
3838         return true;
3839
3840     return false;
3841 }
3842
3843 static int rt5645_parse_dt(struct rt5645_priv *rt5645, struct device *dev)
3844 {
3845     rt5645->pdata.in2_diff = device_property_read_bool(dev,
3846         "realtek,in2-differential");
3847     device_property_read_u32(dev,
3848         "realtek,dmic1-data-pin", &rt5645->pdata.dmic1_data_pin);
3849     device_property_read_u32(dev,
3850         "realtek,dmic2-data-pin", &rt5645->pdata.dmic2_data_pin);
3851     device_property_read_u32(dev,
3852         "realtek,jd-mode", &rt5645->pdata.jd_mode);
3853
3854     return 0;
3855 }
3856
3857 static int rt5645_i2c_probe(struct i2c_client *i2c)
3858 {
3859     struct rt5645_platform_data *pdata = NULL;
3860     const struct dmi_system_id *dmi_data;
3861     struct rt5645_priv *rt5645;
3862     int ret, i;
3863     unsigned int val;
3864     struct regmap *regmap;
3865
3866     rt5645 = devm_kzalloc(&i2c->dev, sizeof(struct rt5645_priv),
3867                 GFP_KERNEL);
3868     if (rt5645 == NULL)
3869         return -ENOMEM;
3870
3871     rt5645->i2c = i2c;
3872     i2c_set_clientdata(i2c, rt5645);
3873
3874     dmi_data = dmi_first_match(dmi_platform_data);
3875     if (dmi_data) {
3876         dev_info(&i2c->dev, "Detected %s platform\n", dmi_data->ident);
3877         pdata = dmi_data->driver_data;
3878     }
3879
3880     if (pdata)
3881         rt5645->pdata = *pdata;
3882     else if (rt5645_check_dp(&i2c->dev))
3883         rt5645_parse_dt(rt5645, &i2c->dev);
3884     else
3885         rt5645->pdata = jd_mode3_platform_data;
3886
3887     if (quirk != -1) {
3888         rt5645->pdata.in2_diff = QUIRK_IN2_DIFF(quirk);
3889         rt5645->pdata.level_trigger_irq = QUIRK_LEVEL_IRQ(quirk);
3890         rt5645->pdata.inv_jd1_1 = QUIRK_INV_JD1_1(quirk);
3891         rt5645->pdata.inv_hp_pol = QUIRK_INV_HP_POL(quirk);
3892         rt5645->pdata.jd_mode = QUIRK_JD_MODE(quirk);
3893         rt5645->pdata.dmic1_data_pin = QUIRK_DMIC1_DATA_PIN(quirk);
3894         rt5645->pdata.dmic2_data_pin = QUIRK_DMIC2_DATA_PIN(quirk);
3895     }
3896
3897     if (has_acpi_companion(&i2c->dev)) {
3898         if (cht_rt5645_gpios) {
3899             if (devm_acpi_dev_add_driver_gpios(&i2c->dev, cht_rt5645_gpios))
3900                 dev_dbg(&i2c->dev, "Failed to add driver gpios\n");
3901         }
3902
3903         /* The ALC3270 package has the headset-mic pin not-connected */
3904         if (acpi_dev_hid_uid_match(ACPI_COMPANION(&i2c->dev), "10EC3270", NULL))
3905             rt5645->pdata.no_headset_mic = true;
3906     }
3907
3908     rt5645->gpiod_hp_det = devm_gpiod_get_optional(&i2c->dev, "hp-detect",
3909                                GPIOD_IN);
3910
3911     if (IS_ERR(rt5645->gpiod_hp_det)) {
3912         dev_info(&i2c->dev, "failed to initialize gpiod\n");
3913         ret = PTR_ERR(rt5645->gpiod_hp_det);
3914         /*
3915          * Continue if optional gpiod is missing, bail for all other
3916          * errors, including -EPROBE_DEFER
3917          */
3918         if (ret != -ENOENT)
3919             return ret;
3920     }
3921
3922     for (i = 0; i < ARRAY_SIZE(rt5645->supplies); i++)
3923         rt5645->supplies[i].supply = rt5645_supply_names[i];
3924
3925     ret = devm_regulator_bulk_get(&i2c->dev,
3926                       ARRAY_SIZE(rt5645->supplies),
3927                       rt5645->supplies);
3928     if (ret) {
3929         dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
3930         return ret;
3931     }
3932
3933     ret = regulator_bulk_enable(ARRAY_SIZE(rt5645->supplies),
3934                     rt5645->supplies);
3935     if (ret) {
3936         dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
3937         return ret;
3938     }
3939
3940     regmap = devm_regmap_init_i2c(i2c, &temp_regmap);
3941     if (IS_ERR(regmap)) {
3942         ret = PTR_ERR(regmap);
3943         dev_err(&i2c->dev, "Failed to allocate temp register map: %d\n",
3944             ret);
3945         goto err_enable;
3946     }
3947
3948     /*
3949      * Read after 400msec, as it is the interval required between
3950      * read and power On.
3951      */
3952     msleep(TIME_TO_POWER_MS);
3953     regmap_read(regmap, RT5645_VENDOR_ID2, &val);
3954
3955     switch (val) {
3956     case RT5645_DEVICE_ID:
3957         rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5645_regmap);
3958         rt5645->codec_type = CODEC_TYPE_RT5645;
3959         break;
3960     case RT5650_DEVICE_ID:
3961         rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5650_regmap);
3962         rt5645->codec_type = CODEC_TYPE_RT5650;
3963         break;
3964     default:
3965         dev_err(&i2c->dev,
3966             "Device with ID register %#x is not rt5645 or rt5650\n",
3967             val);
3968         ret = -ENODEV;
3969         goto err_enable;
3970     }
3971
3972     if (IS_ERR(rt5645->regmap)) {
3973         ret = PTR_ERR(rt5645->regmap);
3974         dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
3975             ret);
3976         goto err_enable;
3977     }
3978
3979     regmap_write(rt5645->regmap, RT5645_RESET, 0);
3980
3981     regmap_read(regmap, RT5645_VENDOR_ID, &val);
3982     rt5645->v_id = val & 0xff;
3983
3984     regmap_write(rt5645->regmap, RT5645_AD_DA_MIXER, 0x8080);
3985
3986     ret = regmap_register_patch(rt5645->regmap, init_list,
3987                     ARRAY_SIZE(init_list));
3988     if (ret != 0)
3989         dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
3990
3991     if (rt5645->codec_type == CODEC_TYPE_RT5650) {
3992         ret = regmap_register_patch(rt5645->regmap, rt5650_init_list,
3993                     ARRAY_SIZE(rt5650_init_list));
3994         if (ret != 0)
3995             dev_warn(&i2c->dev, "Apply rt5650 patch failed: %d\n",
3996                        ret);
3997     }
3998
3999     regmap_update_bits(rt5645->regmap, RT5645_CLSD_OUT_CTRL, 0xc0, 0xc0);
4000
4001     if (rt5645->pdata.in2_diff)
4002         regmap_update_bits(rt5645->regmap, RT5645_IN2_CTRL,
4003                     RT5645_IN_DF2, RT5645_IN_DF2);
4004
4005     if (rt5645->pdata.dmic1_data_pin || rt5645->pdata.dmic2_data_pin) {
4006         regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
4007             RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL);
4008     }
4009     switch (rt5645->pdata.dmic1_data_pin) {
4010     case RT5645_DMIC_DATA_IN2N:
4011         regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
4012             RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N);
4013         break;
4014
4015     case RT5645_DMIC_DATA_GPIO5:
4016         regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
4017             RT5645_I2S2_DAC_PIN_MASK, RT5645_I2S2_DAC_PIN_GPIO);
4018         regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
4019             RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5);
4020         regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
4021             RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA);
4022         break;
4023
4024     case RT5645_DMIC_DATA_GPIO11:
4025         regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
4026             RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11);
4027         regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
4028             RT5645_GP11_PIN_MASK,
4029             RT5645_GP11_PIN_DMIC1_SDA);
4030         break;
4031
4032     default:
4033         break;
4034     }
4035
4036     switch (rt5645->pdata.dmic2_data_pin) {
4037     case RT5645_DMIC_DATA_IN2P:
4038         regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
4039             RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P);
4040         break;
4041
4042     case RT5645_DMIC_DATA_GPIO6:
4043         regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
4044             RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6);
4045         regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
4046             RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA);
4047         break;
4048
4049     case RT5645_DMIC_DATA_GPIO10:
4050         regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
4051             RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10);
4052         regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
4053             RT5645_GP10_PIN_MASK,
4054             RT5645_GP10_PIN_DMIC2_SDA);
4055         break;
4056
4057     case RT5645_DMIC_DATA_GPIO12:
4058         regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
4059             RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO12);
4060         regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
4061             RT5645_GP12_PIN_MASK,
4062             RT5645_GP12_PIN_DMIC2_SDA);
4063         break;
4064
4065     default:
4066         break;
4067     }
4068
4069     if (rt5645->pdata.jd_mode) {
4070         regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
4071                    RT5645_IRQ_CLK_GATE_CTRL,
4072                    RT5645_IRQ_CLK_GATE_CTRL);
4073         regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
4074                    RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT);
4075         regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
4076                    RT5645_IRQ_JD_1_1_EN, RT5645_IRQ_JD_1_1_EN);
4077         regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
4078                    RT5645_JD_PSV_MODE, RT5645_JD_PSV_MODE);
4079         regmap_update_bits(rt5645->regmap, RT5645_HPO_MIXER,
4080                    RT5645_IRQ_PSV_MODE, RT5645_IRQ_PSV_MODE);
4081         regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
4082                    RT5645_MIC2_OVCD_EN, RT5645_MIC2_OVCD_EN);
4083         regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
4084                    RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
4085         switch (rt5645->pdata.jd_mode) {
4086         case 1:
4087             regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
4088                        RT5645_JD1_MODE_MASK,
4089                        RT5645_JD1_MODE_0);
4090             break;
4091         case 2:
4092             regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
4093                        RT5645_JD1_MODE_MASK,
4094                        RT5645_JD1_MODE_1);
4095             break;
4096         case 3:
4097         case 4:
4098             regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
4099                        RT5645_JD1_MODE_MASK,
4100                        RT5645_JD1_MODE_2);
4101             break;
4102         default:
4103             break;
4104         }
4105         if (rt5645->pdata.inv_jd1_1) {
4106             regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
4107                 RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV);
4108         }
4109     }
4110
4111     regmap_update_bits(rt5645->regmap, RT5645_ADDA_CLK1,
4112         RT5645_I2S_PD1_MASK, RT5645_I2S_PD1_2);
4113
4114     if (rt5645->pdata.level_trigger_irq) {
4115         regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
4116             RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV);
4117     }
4118     timer_setup(&rt5645->btn_check_timer, rt5645_btn_check_callback, 0);
4119
4120     INIT_DELAYED_WORK(&rt5645->jack_detect_work, rt5645_jack_detect_work);
4121     INIT_DELAYED_WORK(&rt5645->rcclock_work, rt5645_rcclock_work);
4122
4123     if (rt5645->i2c->irq) {
4124         ret = request_threaded_irq(rt5645->i2c->irq, NULL, rt5645_irq,
4125             IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
4126             | IRQF_ONESHOT, "rt5645", rt5645);
4127         if (ret) {
4128             dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
4129             goto err_enable;
4130         }
4131     }
4132
4133     ret = devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_rt5645,
4134                      rt5645_dai, ARRAY_SIZE(rt5645_dai));
4135     if (ret)
4136         goto err_irq;
4137
4138     return 0;
4139
4140 err_irq:
4141     if (rt5645->i2c->irq)
4142         free_irq(rt5645->i2c->irq, rt5645);
4143 err_enable:
4144     regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies);
4145     return ret;
4146 }
4147
4148 static int rt5645_i2c_remove(struct i2c_client *i2c)
4149 {
4150     struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c);
4151
4152     if (i2c->irq)
4153         free_irq(i2c->irq, rt5645);
4154
4155     /*
4156      * Since the rt5645_btn_check_callback() can queue jack_detect_work,
4157      * the timer need to be delted first
4158      */
4159     del_timer_sync(&rt5645->btn_check_timer);
4160
4161     cancel_delayed_work_sync(&rt5645->jack_detect_work);
4162     cancel_delayed_work_sync(&rt5645->rcclock_work);
4163
4164     regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies);
4165
4166     return 0;
4167 }
4168
4169 static void rt5645_i2c_shutdown(struct i2c_client *i2c)
4170 {
4171     struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c);
4172
4173     regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
4174         RT5645_RING2_SLEEVE_GND, RT5645_RING2_SLEEVE_GND);
4175     regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, RT5645_CBJ_MN_JD,
4176         RT5645_CBJ_MN_JD);
4177     regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, RT5645_CBJ_BST1_EN,
4178         0);
4179     msleep(20);
4180     regmap_write(rt5645->regmap, RT5645_RESET, 0);
4181 }
4182
4183 static struct i2c_driver rt5645_i2c_driver = {
4184     .driver = {
4185         .name = "rt5645",
4186         .of_match_table = of_match_ptr(rt5645_of_match),
4187         .acpi_match_table = ACPI_PTR(rt5645_acpi_match),
4188     },
4189     .probe_new = rt5645_i2c_probe,
4190     .remove = rt5645_i2c_remove,
4191     .shutdown = rt5645_i2c_shutdown,
4192     .id_table = rt5645_i2c_id,
4193 };
4194 module_i2c_driver(rt5645_i2c_driver);
4195
4196 MODULE_DESCRIPTION("ASoC RT5645 driver");
4197 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
4198 MODULE_LICENSE("GPL v2");