Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * rt5514.c  --  RT5514 ALSA SoC audio codec driver
0004  *
0005  * Copyright 2015 Realtek Semiconductor Corp.
0006  * Author: Oder Chiou <oder_chiou@realtek.com>
0007  */
0008 
0009 #include <linux/acpi.h>
0010 #include <linux/fs.h>
0011 #include <linux/module.h>
0012 #include <linux/moduleparam.h>
0013 #include <linux/init.h>
0014 #include <linux/delay.h>
0015 #include <linux/pm.h>
0016 #include <linux/regmap.h>
0017 #include <linux/i2c.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/firmware.h>
0020 #include <linux/gpio.h>
0021 #include <sound/core.h>
0022 #include <sound/pcm.h>
0023 #include <sound/pcm_params.h>
0024 #include <sound/soc.h>
0025 #include <sound/soc-dapm.h>
0026 #include <sound/initval.h>
0027 #include <sound/tlv.h>
0028 
0029 #include "rl6231.h"
0030 #include "rt5514.h"
0031 #if IS_ENABLED(CONFIG_SND_SOC_RT5514_SPI)
0032 #include "rt5514-spi.h"
0033 #endif
0034 
0035 static const struct reg_sequence rt5514_i2c_patch[] = {
0036     {0x1800101c, 0x00000000},
0037     {0x18001100, 0x0000031f},
0038     {0x18001104, 0x00000007},
0039     {0x18001108, 0x00000000},
0040     {0x1800110c, 0x00000000},
0041     {0x18001110, 0x00000000},
0042     {0x18001114, 0x00000001},
0043     {0x18001118, 0x00000000},
0044     {0x18002f08, 0x00000006},
0045     {0x18002f00, 0x00055149},
0046     {0x18002f00, 0x0005514b},
0047     {0x18002f00, 0x00055149},
0048     {0xfafafafa, 0x00000001},
0049     {0x18002f10, 0x00000001},
0050     {0x18002f10, 0x00000000},
0051     {0x18002f10, 0x00000001},
0052     {0xfafafafa, 0x00000001},
0053     {0x18002000, 0x000010ec},
0054     {0xfafafafa, 0x00000000},
0055 };
0056 
0057 static const struct reg_sequence rt5514_patch[] = {
0058     {RT5514_DIG_IO_CTRL,        0x00000040},
0059     {RT5514_CLK_CTRL1,      0x38020041},
0060     {RT5514_SRC_CTRL,       0x44000eee},
0061     {RT5514_ANA_CTRL_LDO10,     0x00028604},
0062     {RT5514_ANA_CTRL_ADCFED,    0x00000800},
0063     {RT5514_ASRC_IN_CTRL1,      0x00000003},
0064     {RT5514_DOWNFILTER0_CTRL3,  0x10000342},
0065     {RT5514_DOWNFILTER1_CTRL3,  0x10000342},
0066 };
0067 
0068 static const struct reg_default rt5514_reg[] = {
0069     {RT5514_RESET,          0x00000000},
0070     {RT5514_PWR_ANA1,       0x00808880},
0071     {RT5514_PWR_ANA2,       0x00220000},
0072     {RT5514_I2S_CTRL1,      0x00000330},
0073     {RT5514_I2S_CTRL2,      0x20000000},
0074     {RT5514_VAD_CTRL6,      0xc00007d2},
0075     {RT5514_EXT_VAD_CTRL,       0x80000080},
0076     {RT5514_DIG_IO_CTRL,        0x00000040},
0077     {RT5514_PAD_CTRL1,      0x00804000},
0078     {RT5514_DMIC_DATA_CTRL,     0x00000005},
0079     {RT5514_DIG_SOURCE_CTRL,    0x00000002},
0080     {RT5514_SRC_CTRL,       0x44000eee},
0081     {RT5514_DOWNFILTER2_CTRL1,  0x0000882f},
0082     {RT5514_PLL_SOURCE_CTRL,    0x00000004},
0083     {RT5514_CLK_CTRL1,      0x38020041},
0084     {RT5514_CLK_CTRL2,      0x00000000},
0085     {RT5514_PLL3_CALIB_CTRL1,   0x00400200},
0086     {RT5514_PLL3_CALIB_CTRL5,   0x40220012},
0087     {RT5514_DELAY_BUF_CTRL1,    0x7fff006a},
0088     {RT5514_DELAY_BUF_CTRL3,    0x00000000},
0089     {RT5514_ASRC_IN_CTRL1,      0x00000003},
0090     {RT5514_DOWNFILTER0_CTRL1,  0x00020c2f},
0091     {RT5514_DOWNFILTER0_CTRL2,  0x00020c2f},
0092     {RT5514_DOWNFILTER0_CTRL3,  0x10000342},
0093     {RT5514_DOWNFILTER1_CTRL1,  0x00020c2f},
0094     {RT5514_DOWNFILTER1_CTRL2,  0x00020c2f},
0095     {RT5514_DOWNFILTER1_CTRL3,  0x10000342},
0096     {RT5514_ANA_CTRL_LDO10,     0x00028604},
0097     {RT5514_ANA_CTRL_LDO18_16,  0x02000345},
0098     {RT5514_ANA_CTRL_ADC12,     0x0000a2a8},
0099     {RT5514_ANA_CTRL_ADC21,     0x00001180},
0100     {RT5514_ANA_CTRL_ADC22,     0x0000aaa8},
0101     {RT5514_ANA_CTRL_ADC23,     0x00151427},
0102     {RT5514_ANA_CTRL_MICBST,    0x00002000},
0103     {RT5514_ANA_CTRL_ADCFED,    0x00000800},
0104     {RT5514_ANA_CTRL_INBUF,     0x00000143},
0105     {RT5514_ANA_CTRL_VREF,      0x00008d50},
0106     {RT5514_ANA_CTRL_PLL3,      0x0000000e},
0107     {RT5514_ANA_CTRL_PLL1_1,    0x00000000},
0108     {RT5514_ANA_CTRL_PLL1_2,    0x00030220},
0109     {RT5514_DMIC_LP_CTRL,       0x00000000},
0110     {RT5514_MISC_CTRL_DSP,      0x00000000},
0111     {RT5514_DSP_CTRL1,      0x00055149},
0112     {RT5514_DSP_CTRL3,      0x00000006},
0113     {RT5514_DSP_CTRL4,      0x00000001},
0114     {RT5514_VENDOR_ID1,     0x00000001},
0115     {RT5514_VENDOR_ID2,     0x10ec5514},
0116 };
0117 
0118 static void rt5514_enable_dsp_prepare(struct rt5514_priv *rt5514)
0119 {
0120     /* Reset */
0121     regmap_write(rt5514->i2c_regmap, 0x18002000, 0x000010ec);
0122     /* LDO_I_limit */
0123     regmap_write(rt5514->i2c_regmap, 0x18002200, 0x00028604);
0124     /* I2C bypass enable */
0125     regmap_write(rt5514->i2c_regmap, 0xfafafafa, 0x00000001);
0126     /* mini-core reset */
0127     regmap_write(rt5514->i2c_regmap, 0x18002f00, 0x0005514b);
0128     regmap_write(rt5514->i2c_regmap, 0x18002f00, 0x00055149);
0129     /* I2C bypass disable */
0130     regmap_write(rt5514->i2c_regmap, 0xfafafafa, 0x00000000);
0131     /* PIN config */
0132     regmap_write(rt5514->i2c_regmap, 0x18002070, 0x00000040);
0133     /* PLL3(QN)=RCOSC*(10+2) */
0134     regmap_write(rt5514->i2c_regmap, 0x18002240, 0x0000000a);
0135     /* PLL3 source=RCOSC, fsi=rt_clk */
0136     regmap_write(rt5514->i2c_regmap, 0x18002100, 0x0000000b);
0137     /* Power on RCOSC, pll3 */
0138     regmap_write(rt5514->i2c_regmap, 0x18002004, 0x00808b81);
0139     /* DSP clk source = pll3, ENABLE DSP clk */
0140     regmap_write(rt5514->i2c_regmap, 0x18002f08, 0x00000005);
0141     /* Enable DSP clk auto switch */
0142     regmap_write(rt5514->i2c_regmap, 0x18001114, 0x00000001);
0143     /* Reduce DSP power */
0144     regmap_write(rt5514->i2c_regmap, 0x18001118, 0x00000001);
0145 }
0146 
0147 static bool rt5514_volatile_register(struct device *dev, unsigned int reg)
0148 {
0149     switch (reg) {
0150     case RT5514_VENDOR_ID1:
0151     case RT5514_VENDOR_ID2:
0152         return true;
0153 
0154     default:
0155         return false;
0156     }
0157 }
0158 
0159 static bool rt5514_readable_register(struct device *dev, unsigned int reg)
0160 {
0161     switch (reg) {
0162     case RT5514_RESET:
0163     case RT5514_PWR_ANA1:
0164     case RT5514_PWR_ANA2:
0165     case RT5514_I2S_CTRL1:
0166     case RT5514_I2S_CTRL2:
0167     case RT5514_VAD_CTRL6:
0168     case RT5514_EXT_VAD_CTRL:
0169     case RT5514_DIG_IO_CTRL:
0170     case RT5514_PAD_CTRL1:
0171     case RT5514_DMIC_DATA_CTRL:
0172     case RT5514_DIG_SOURCE_CTRL:
0173     case RT5514_SRC_CTRL:
0174     case RT5514_DOWNFILTER2_CTRL1:
0175     case RT5514_PLL_SOURCE_CTRL:
0176     case RT5514_CLK_CTRL1:
0177     case RT5514_CLK_CTRL2:
0178     case RT5514_PLL3_CALIB_CTRL1:
0179     case RT5514_PLL3_CALIB_CTRL5:
0180     case RT5514_DELAY_BUF_CTRL1:
0181     case RT5514_DELAY_BUF_CTRL3:
0182     case RT5514_ASRC_IN_CTRL1:
0183     case RT5514_DOWNFILTER0_CTRL1:
0184     case RT5514_DOWNFILTER0_CTRL2:
0185     case RT5514_DOWNFILTER0_CTRL3:
0186     case RT5514_DOWNFILTER1_CTRL1:
0187     case RT5514_DOWNFILTER1_CTRL2:
0188     case RT5514_DOWNFILTER1_CTRL3:
0189     case RT5514_ANA_CTRL_LDO10:
0190     case RT5514_ANA_CTRL_LDO18_16:
0191     case RT5514_ANA_CTRL_ADC12:
0192     case RT5514_ANA_CTRL_ADC21:
0193     case RT5514_ANA_CTRL_ADC22:
0194     case RT5514_ANA_CTRL_ADC23:
0195     case RT5514_ANA_CTRL_MICBST:
0196     case RT5514_ANA_CTRL_ADCFED:
0197     case RT5514_ANA_CTRL_INBUF:
0198     case RT5514_ANA_CTRL_VREF:
0199     case RT5514_ANA_CTRL_PLL3:
0200     case RT5514_ANA_CTRL_PLL1_1:
0201     case RT5514_ANA_CTRL_PLL1_2:
0202     case RT5514_DMIC_LP_CTRL:
0203     case RT5514_MISC_CTRL_DSP:
0204     case RT5514_DSP_CTRL1:
0205     case RT5514_DSP_CTRL3:
0206     case RT5514_DSP_CTRL4:
0207     case RT5514_VENDOR_ID1:
0208     case RT5514_VENDOR_ID2:
0209         return true;
0210 
0211     default:
0212         return false;
0213     }
0214 }
0215 
0216 static bool rt5514_i2c_readable_register(struct device *dev,
0217     unsigned int reg)
0218 {
0219     switch (reg) {
0220     case RT5514_DSP_MAPPING | RT5514_RESET:
0221     case RT5514_DSP_MAPPING | RT5514_PWR_ANA1:
0222     case RT5514_DSP_MAPPING | RT5514_PWR_ANA2:
0223     case RT5514_DSP_MAPPING | RT5514_I2S_CTRL1:
0224     case RT5514_DSP_MAPPING | RT5514_I2S_CTRL2:
0225     case RT5514_DSP_MAPPING | RT5514_VAD_CTRL6:
0226     case RT5514_DSP_MAPPING | RT5514_EXT_VAD_CTRL:
0227     case RT5514_DSP_MAPPING | RT5514_DIG_IO_CTRL:
0228     case RT5514_DSP_MAPPING | RT5514_PAD_CTRL1:
0229     case RT5514_DSP_MAPPING | RT5514_DMIC_DATA_CTRL:
0230     case RT5514_DSP_MAPPING | RT5514_DIG_SOURCE_CTRL:
0231     case RT5514_DSP_MAPPING | RT5514_SRC_CTRL:
0232     case RT5514_DSP_MAPPING | RT5514_DOWNFILTER2_CTRL1:
0233     case RT5514_DSP_MAPPING | RT5514_PLL_SOURCE_CTRL:
0234     case RT5514_DSP_MAPPING | RT5514_CLK_CTRL1:
0235     case RT5514_DSP_MAPPING | RT5514_CLK_CTRL2:
0236     case RT5514_DSP_MAPPING | RT5514_PLL3_CALIB_CTRL1:
0237     case RT5514_DSP_MAPPING | RT5514_PLL3_CALIB_CTRL5:
0238     case RT5514_DSP_MAPPING | RT5514_DELAY_BUF_CTRL1:
0239     case RT5514_DSP_MAPPING | RT5514_DELAY_BUF_CTRL3:
0240     case RT5514_DSP_MAPPING | RT5514_ASRC_IN_CTRL1:
0241     case RT5514_DSP_MAPPING | RT5514_DOWNFILTER0_CTRL1:
0242     case RT5514_DSP_MAPPING | RT5514_DOWNFILTER0_CTRL2:
0243     case RT5514_DSP_MAPPING | RT5514_DOWNFILTER0_CTRL3:
0244     case RT5514_DSP_MAPPING | RT5514_DOWNFILTER1_CTRL1:
0245     case RT5514_DSP_MAPPING | RT5514_DOWNFILTER1_CTRL2:
0246     case RT5514_DSP_MAPPING | RT5514_DOWNFILTER1_CTRL3:
0247     case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_LDO10:
0248     case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_LDO18_16:
0249     case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC12:
0250     case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC21:
0251     case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC22:
0252     case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC23:
0253     case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_MICBST:
0254     case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADCFED:
0255     case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_INBUF:
0256     case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_VREF:
0257     case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_PLL3:
0258     case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_PLL1_1:
0259     case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_PLL1_2:
0260     case RT5514_DSP_MAPPING | RT5514_DMIC_LP_CTRL:
0261     case RT5514_DSP_MAPPING | RT5514_MISC_CTRL_DSP:
0262     case RT5514_DSP_MAPPING | RT5514_DSP_CTRL1:
0263     case RT5514_DSP_MAPPING | RT5514_DSP_CTRL3:
0264     case RT5514_DSP_MAPPING | RT5514_DSP_CTRL4:
0265     case RT5514_DSP_MAPPING | RT5514_VENDOR_ID1:
0266     case RT5514_DSP_MAPPING | RT5514_VENDOR_ID2:
0267         return true;
0268 
0269     default:
0270         return false;
0271     }
0272 }
0273 
0274 /* {-3, 0, +3, +4.5, +7.5, +9.5, +12, +14, +17} dB */
0275 static const DECLARE_TLV_DB_RANGE(bst_tlv,
0276     0, 2, TLV_DB_SCALE_ITEM(-300, 300, 0),
0277     3, 3, TLV_DB_SCALE_ITEM(450, 0, 0),
0278     4, 4, TLV_DB_SCALE_ITEM(750, 0, 0),
0279     5, 5, TLV_DB_SCALE_ITEM(950, 0, 0),
0280     6, 6, TLV_DB_SCALE_ITEM(1200, 0, 0),
0281     7, 7, TLV_DB_SCALE_ITEM(1400, 0, 0),
0282     8, 8, TLV_DB_SCALE_ITEM(1700, 0, 0)
0283 );
0284 
0285 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
0286 
0287 static int rt5514_dsp_voice_wake_up_get(struct snd_kcontrol *kcontrol,
0288         struct snd_ctl_elem_value *ucontrol)
0289 {
0290     struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
0291     struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
0292 
0293     ucontrol->value.integer.value[0] = rt5514->dsp_enabled;
0294 
0295     return 0;
0296 }
0297 
0298 static int rt5514_calibration(struct rt5514_priv *rt5514, bool on)
0299 {
0300     if (on) {
0301         regmap_write(rt5514->regmap, RT5514_ANA_CTRL_PLL3, 0x0000000a);
0302         regmap_update_bits(rt5514->regmap, RT5514_PLL_SOURCE_CTRL, 0xf,
0303             0xa);
0304         regmap_update_bits(rt5514->regmap, RT5514_PWR_ANA1, 0x301,
0305             0x301);
0306         regmap_write(rt5514->regmap, RT5514_PLL3_CALIB_CTRL4,
0307             0x80000000 | rt5514->pll3_cal_value);
0308         regmap_write(rt5514->regmap, RT5514_PLL3_CALIB_CTRL1,
0309             0x8bb80800);
0310         regmap_update_bits(rt5514->regmap, RT5514_PLL3_CALIB_CTRL5,
0311             0xc0000000, 0x80000000);
0312         regmap_update_bits(rt5514->regmap, RT5514_PLL3_CALIB_CTRL5,
0313             0xc0000000, 0xc0000000);
0314     } else {
0315         regmap_update_bits(rt5514->regmap, RT5514_PLL3_CALIB_CTRL5,
0316             0xc0000000, 0x40000000);
0317         regmap_update_bits(rt5514->regmap, RT5514_PWR_ANA1, 0x301, 0);
0318         regmap_update_bits(rt5514->regmap, RT5514_PLL_SOURCE_CTRL, 0xf,
0319             0x4);
0320     }
0321 
0322     return 0;
0323 }
0324 
0325 static int rt5514_dsp_voice_wake_up_put(struct snd_kcontrol *kcontrol,
0326         struct snd_ctl_elem_value *ucontrol)
0327 {
0328     struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
0329     struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
0330     const struct firmware *fw = NULL;
0331     u8 buf[8];
0332 
0333     if (ucontrol->value.integer.value[0] == rt5514->dsp_enabled)
0334         return 0;
0335 
0336     if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
0337         rt5514->dsp_enabled = ucontrol->value.integer.value[0];
0338 
0339         if (rt5514->dsp_enabled) {
0340             if (rt5514->pdata.dsp_calib_clk_name &&
0341                 !IS_ERR(rt5514->dsp_calib_clk)) {
0342                 if (clk_set_rate(rt5514->dsp_calib_clk,
0343                     rt5514->pdata.dsp_calib_clk_rate))
0344                     dev_err(component->dev,
0345                         "Can't set rate for mclk");
0346 
0347                 if (clk_prepare_enable(rt5514->dsp_calib_clk))
0348                     dev_err(component->dev,
0349                         "Can't enable dsp_calib_clk");
0350 
0351                 rt5514_calibration(rt5514, true);
0352 
0353                 msleep(20);
0354 #if IS_ENABLED(CONFIG_SND_SOC_RT5514_SPI)
0355                 rt5514_spi_burst_read(RT5514_PLL3_CALIB_CTRL6 |
0356                     RT5514_DSP_MAPPING, buf, sizeof(buf));
0357 #else
0358                 dev_err(component->dev, "There is no SPI driver for"
0359                     " loading the firmware\n");
0360                 memset(buf, 0, sizeof(buf));
0361 #endif
0362                 rt5514->pll3_cal_value = buf[0] | buf[1] << 8 |
0363                     buf[2] << 16 | buf[3] << 24;
0364 
0365                 rt5514_calibration(rt5514, false);
0366                 clk_disable_unprepare(rt5514->dsp_calib_clk);
0367             }
0368 
0369             rt5514_enable_dsp_prepare(rt5514);
0370 
0371             request_firmware(&fw, RT5514_FIRMWARE1, component->dev);
0372             if (fw) {
0373 #if IS_ENABLED(CONFIG_SND_SOC_RT5514_SPI)
0374                 rt5514_spi_burst_write(0x4ff60000, fw->data,
0375                     ((fw->size/8)+1)*8);
0376 #else
0377                 dev_err(component->dev, "There is no SPI driver for"
0378                     " loading the firmware\n");
0379 #endif
0380                 release_firmware(fw);
0381                 fw = NULL;
0382             }
0383 
0384             request_firmware(&fw, RT5514_FIRMWARE2, component->dev);
0385             if (fw) {
0386 #if IS_ENABLED(CONFIG_SND_SOC_RT5514_SPI)
0387                 rt5514_spi_burst_write(0x4ffc0000, fw->data,
0388                     ((fw->size/8)+1)*8);
0389 #else
0390                 dev_err(component->dev, "There is no SPI driver for"
0391                     " loading the firmware\n");
0392 #endif
0393                 release_firmware(fw);
0394                 fw = NULL;
0395             }
0396 
0397             /* DSP run */
0398             regmap_write(rt5514->i2c_regmap, 0x18002f00,
0399                 0x00055148);
0400 
0401             if (rt5514->pdata.dsp_calib_clk_name &&
0402                 !IS_ERR(rt5514->dsp_calib_clk)) {
0403                 msleep(20);
0404 
0405                 regmap_write(rt5514->i2c_regmap, 0x1800211c,
0406                     rt5514->pll3_cal_value);
0407                 regmap_write(rt5514->i2c_regmap, 0x18002124,
0408                     0x00220012);
0409                 regmap_write(rt5514->i2c_regmap, 0x18002124,
0410                     0x80220042);
0411                 regmap_write(rt5514->i2c_regmap, 0x18002124,
0412                     0xe0220042);
0413             }
0414         } else {
0415             regmap_multi_reg_write(rt5514->i2c_regmap,
0416                 rt5514_i2c_patch, ARRAY_SIZE(rt5514_i2c_patch));
0417             regcache_mark_dirty(rt5514->regmap);
0418             regcache_sync(rt5514->regmap);
0419         }
0420     }
0421 
0422     return 1;
0423 }
0424 
0425 static const struct snd_kcontrol_new rt5514_snd_controls[] = {
0426     SOC_DOUBLE_TLV("MIC Boost Volume", RT5514_ANA_CTRL_MICBST,
0427         RT5514_SEL_BSTL_SFT, RT5514_SEL_BSTR_SFT, 8, 0, bst_tlv),
0428     SOC_DOUBLE_R_TLV("ADC1 Capture Volume", RT5514_DOWNFILTER0_CTRL1,
0429         RT5514_DOWNFILTER0_CTRL2, RT5514_AD_GAIN_SFT, 63, 0,
0430         adc_vol_tlv),
0431     SOC_DOUBLE_R_TLV("ADC2 Capture Volume", RT5514_DOWNFILTER1_CTRL1,
0432         RT5514_DOWNFILTER1_CTRL2, RT5514_AD_GAIN_SFT, 63, 0,
0433         adc_vol_tlv),
0434     SOC_SINGLE_EXT("DSP Voice Wake Up", SND_SOC_NOPM, 0, 1, 0,
0435         rt5514_dsp_voice_wake_up_get, rt5514_dsp_voice_wake_up_put),
0436 };
0437 
0438 /* ADC Mixer*/
0439 static const struct snd_kcontrol_new rt5514_sto1_adc_l_mix[] = {
0440     SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER0_CTRL1,
0441         RT5514_AD_DMIC_MIX_BIT, 1, 1),
0442     SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER0_CTRL1,
0443         RT5514_AD_AD_MIX_BIT, 1, 1),
0444 };
0445 
0446 static const struct snd_kcontrol_new rt5514_sto1_adc_r_mix[] = {
0447     SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER0_CTRL2,
0448         RT5514_AD_DMIC_MIX_BIT, 1, 1),
0449     SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER0_CTRL2,
0450         RT5514_AD_AD_MIX_BIT, 1, 1),
0451 };
0452 
0453 static const struct snd_kcontrol_new rt5514_sto2_adc_l_mix[] = {
0454     SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER1_CTRL1,
0455         RT5514_AD_DMIC_MIX_BIT, 1, 1),
0456     SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER1_CTRL1,
0457         RT5514_AD_AD_MIX_BIT, 1, 1),
0458 };
0459 
0460 static const struct snd_kcontrol_new rt5514_sto2_adc_r_mix[] = {
0461     SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER1_CTRL2,
0462         RT5514_AD_DMIC_MIX_BIT, 1, 1),
0463     SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER1_CTRL2,
0464         RT5514_AD_AD_MIX_BIT, 1, 1),
0465 };
0466 
0467 /* DMIC Source */
0468 static const char * const rt5514_dmic_src[] = {
0469     "DMIC1", "DMIC2"
0470 };
0471 
0472 static SOC_ENUM_SINGLE_DECL(
0473     rt5514_stereo1_dmic_enum, RT5514_DIG_SOURCE_CTRL,
0474     RT5514_AD0_DMIC_INPUT_SEL_SFT, rt5514_dmic_src);
0475 
0476 static const struct snd_kcontrol_new rt5514_sto1_dmic_mux =
0477     SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5514_stereo1_dmic_enum);
0478 
0479 static SOC_ENUM_SINGLE_DECL(
0480     rt5514_stereo2_dmic_enum, RT5514_DIG_SOURCE_CTRL,
0481     RT5514_AD1_DMIC_INPUT_SEL_SFT, rt5514_dmic_src);
0482 
0483 static const struct snd_kcontrol_new rt5514_sto2_dmic_mux =
0484     SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5514_stereo2_dmic_enum);
0485 
0486 /**
0487  * rt5514_calc_dmic_clk - Calculate the frequency divider parameter of dmic.
0488  *
0489  * @component: only used for dev_warn
0490  * @rate: base clock rate.
0491  *
0492  * Choose divider parameter that gives the highest possible DMIC frequency in
0493  * 1MHz - 3MHz range.
0494  */
0495 static int rt5514_calc_dmic_clk(struct snd_soc_component *component, int rate)
0496 {
0497     static const int div[] = {2, 3, 4, 8, 12, 16, 24, 32};
0498     int i;
0499 
0500     if (rate < 1000000 * div[0]) {
0501         pr_warn("Base clock rate %d is too low\n", rate);
0502         return -EINVAL;
0503     }
0504 
0505     for (i = 0; i < ARRAY_SIZE(div); i++) {
0506         /* find divider that gives DMIC frequency below 3.072MHz */
0507         if (3072000 * div[i] >= rate)
0508             return i;
0509     }
0510 
0511     dev_warn(component->dev, "Base clock rate %d is too high\n", rate);
0512     return -EINVAL;
0513 }
0514 
0515 static int rt5514_set_dmic_clk(struct snd_soc_dapm_widget *w,
0516     struct snd_kcontrol *kcontrol, int event)
0517 {
0518     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0519     struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
0520     int idx;
0521 
0522     idx = rt5514_calc_dmic_clk(component, rt5514->sysclk);
0523     if (idx < 0)
0524         dev_err(component->dev, "Failed to set DMIC clock\n");
0525     else
0526         regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL1,
0527             RT5514_CLK_DMIC_OUT_SEL_MASK,
0528             idx << RT5514_CLK_DMIC_OUT_SEL_SFT);
0529 
0530     if (rt5514->pdata.dmic_init_delay)
0531         msleep(rt5514->pdata.dmic_init_delay);
0532 
0533     return idx;
0534 }
0535 
0536 static int rt5514_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
0537              struct snd_soc_dapm_widget *sink)
0538 {
0539     struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
0540     struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
0541 
0542     if (rt5514->sysclk_src == RT5514_SCLK_S_PLL1)
0543         return 1;
0544     else
0545         return 0;
0546 }
0547 
0548 static int rt5514_i2s_use_asrc(struct snd_soc_dapm_widget *source,
0549     struct snd_soc_dapm_widget *sink)
0550 {
0551     struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
0552     struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
0553 
0554     return (rt5514->sysclk > rt5514->lrck * 384);
0555 }
0556 
0557 static const struct snd_soc_dapm_widget rt5514_dapm_widgets[] = {
0558     /* Input Lines */
0559     SND_SOC_DAPM_INPUT("DMIC1L"),
0560     SND_SOC_DAPM_INPUT("DMIC1R"),
0561     SND_SOC_DAPM_INPUT("DMIC2L"),
0562     SND_SOC_DAPM_INPUT("DMIC2R"),
0563 
0564     SND_SOC_DAPM_INPUT("AMICL"),
0565     SND_SOC_DAPM_INPUT("AMICR"),
0566 
0567     SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
0568     SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
0569 
0570     SND_SOC_DAPM_SUPPLY_S("DMIC CLK", 1, SND_SOC_NOPM, 0, 0,
0571         rt5514_set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
0572 
0573     SND_SOC_DAPM_SUPPLY("ADC CLK", RT5514_CLK_CTRL1,
0574         RT5514_CLK_AD_ANA1_EN_BIT, 0, NULL, 0),
0575 
0576     SND_SOC_DAPM_SUPPLY("LDO18 IN", RT5514_PWR_ANA1,
0577         RT5514_POW_LDO18_IN_BIT, 0, NULL, 0),
0578     SND_SOC_DAPM_SUPPLY("LDO18 ADC", RT5514_PWR_ANA1,
0579         RT5514_POW_LDO18_ADC_BIT, 0, NULL, 0),
0580     SND_SOC_DAPM_SUPPLY("LDO21", RT5514_PWR_ANA1, RT5514_POW_LDO21_BIT, 0,
0581         NULL, 0),
0582     SND_SOC_DAPM_SUPPLY("BG LDO18 IN", RT5514_PWR_ANA1,
0583         RT5514_POW_BG_LDO18_IN_BIT, 0, NULL, 0),
0584     SND_SOC_DAPM_SUPPLY("BG LDO21", RT5514_PWR_ANA1,
0585         RT5514_POW_BG_LDO21_BIT, 0, NULL, 0),
0586     SND_SOC_DAPM_SUPPLY("BG MBIAS", RT5514_PWR_ANA2,
0587         RT5514_POW_BG_MBIAS_BIT, 0, NULL, 0),
0588     SND_SOC_DAPM_SUPPLY("MBIAS", RT5514_PWR_ANA2, RT5514_POW_MBIAS_BIT, 0,
0589         NULL, 0),
0590     SND_SOC_DAPM_SUPPLY("VREF2", RT5514_PWR_ANA2, RT5514_POW_VREF2_BIT, 0,
0591         NULL, 0),
0592     SND_SOC_DAPM_SUPPLY("VREF1", RT5514_PWR_ANA2, RT5514_POW_VREF1_BIT, 0,
0593         NULL, 0),
0594     SND_SOC_DAPM_SUPPLY("ADC Power", SND_SOC_NOPM, 0, 0, NULL, 0),
0595 
0596 
0597     SND_SOC_DAPM_SUPPLY("LDO16L", RT5514_PWR_ANA2, RT5514_POWL_LDO16_BIT, 0,
0598         NULL, 0),
0599     SND_SOC_DAPM_SUPPLY("ADC1L", RT5514_PWR_ANA2, RT5514_POW_ADC1_L_BIT, 0,
0600         NULL, 0),
0601     SND_SOC_DAPM_SUPPLY("BSTL2", RT5514_PWR_ANA2, RT5514_POW2_BSTL_BIT, 0,
0602         NULL, 0),
0603     SND_SOC_DAPM_SUPPLY("BSTL", RT5514_PWR_ANA2, RT5514_POW_BSTL_BIT, 0,
0604         NULL, 0),
0605     SND_SOC_DAPM_SUPPLY("ADCFEDL", RT5514_PWR_ANA2, RT5514_POW_ADCFEDL_BIT,
0606         0, NULL, 0),
0607     SND_SOC_DAPM_SUPPLY("ADCL Power", SND_SOC_NOPM, 0, 0, NULL, 0),
0608 
0609     SND_SOC_DAPM_SUPPLY("LDO16R", RT5514_PWR_ANA2, RT5514_POWR_LDO16_BIT, 0,
0610         NULL, 0),
0611     SND_SOC_DAPM_SUPPLY("ADC1R", RT5514_PWR_ANA2, RT5514_POW_ADC1_R_BIT, 0,
0612         NULL, 0),
0613     SND_SOC_DAPM_SUPPLY("BSTR2", RT5514_PWR_ANA2, RT5514_POW2_BSTR_BIT, 0,
0614         NULL, 0),
0615     SND_SOC_DAPM_SUPPLY("BSTR", RT5514_PWR_ANA2, RT5514_POW_BSTR_BIT, 0,
0616         NULL, 0),
0617     SND_SOC_DAPM_SUPPLY("ADCFEDR", RT5514_PWR_ANA2, RT5514_POW_ADCFEDR_BIT,
0618         0, NULL, 0),
0619     SND_SOC_DAPM_SUPPLY("ADCR Power", SND_SOC_NOPM, 0, 0, NULL, 0),
0620 
0621     SND_SOC_DAPM_SUPPLY("PLL1 LDO ENABLE", RT5514_ANA_CTRL_PLL1_2,
0622         RT5514_EN_LDO_PLL1_BIT, 0, NULL, 0),
0623     SND_SOC_DAPM_SUPPLY("PLL1 LDO", RT5514_PWR_ANA2,
0624         RT5514_POW_PLL1_LDO_BIT, 0, NULL, 0),
0625     SND_SOC_DAPM_SUPPLY("PLL1", RT5514_PWR_ANA2, RT5514_POW_PLL1_BIT, 0,
0626         NULL, 0),
0627     SND_SOC_DAPM_SUPPLY_S("ASRC AD1", 1, RT5514_CLK_CTRL2,
0628         RT5514_CLK_AD0_ASRC_EN_BIT, 0, NULL, 0),
0629     SND_SOC_DAPM_SUPPLY_S("ASRC AD2", 1, RT5514_CLK_CTRL2,
0630         RT5514_CLK_AD1_ASRC_EN_BIT, 0, NULL, 0),
0631 
0632     /* ADC Mux */
0633     SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
0634                 &rt5514_sto1_dmic_mux),
0635     SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
0636                 &rt5514_sto2_dmic_mux),
0637 
0638     /* ADC Mixer */
0639     SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5514_CLK_CTRL1,
0640         RT5514_CLK_AD0_EN_BIT, 0, NULL, 0),
0641     SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5514_CLK_CTRL1,
0642         RT5514_CLK_AD1_EN_BIT, 0, NULL, 0),
0643 
0644     SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
0645         rt5514_sto1_adc_l_mix, ARRAY_SIZE(rt5514_sto1_adc_l_mix)),
0646     SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
0647         rt5514_sto1_adc_r_mix, ARRAY_SIZE(rt5514_sto1_adc_r_mix)),
0648     SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
0649         rt5514_sto2_adc_l_mix, ARRAY_SIZE(rt5514_sto2_adc_l_mix)),
0650     SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
0651         rt5514_sto2_adc_r_mix, ARRAY_SIZE(rt5514_sto2_adc_r_mix)),
0652 
0653     SND_SOC_DAPM_ADC("Stereo1 ADC MIXL", NULL, RT5514_DOWNFILTER0_CTRL1,
0654         RT5514_AD_AD_MUTE_BIT, 1),
0655     SND_SOC_DAPM_ADC("Stereo1 ADC MIXR", NULL, RT5514_DOWNFILTER0_CTRL2,
0656         RT5514_AD_AD_MUTE_BIT, 1),
0657     SND_SOC_DAPM_ADC("Stereo2 ADC MIXL", NULL, RT5514_DOWNFILTER1_CTRL1,
0658         RT5514_AD_AD_MUTE_BIT, 1),
0659     SND_SOC_DAPM_ADC("Stereo2 ADC MIXR", NULL, RT5514_DOWNFILTER1_CTRL2,
0660         RT5514_AD_AD_MUTE_BIT, 1),
0661 
0662     /* ADC PGA */
0663     SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
0664     SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
0665 
0666     /* Audio Interface */
0667     SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
0668 };
0669 
0670 static const struct snd_soc_dapm_route rt5514_dapm_routes[] = {
0671     { "DMIC1", NULL, "DMIC1L" },
0672     { "DMIC1", NULL, "DMIC1R" },
0673     { "DMIC2", NULL, "DMIC2L" },
0674     { "DMIC2", NULL, "DMIC2R" },
0675 
0676     { "DMIC1L", NULL, "DMIC CLK" },
0677     { "DMIC1R", NULL, "DMIC CLK" },
0678     { "DMIC2L", NULL, "DMIC CLK" },
0679     { "DMIC2R", NULL, "DMIC CLK" },
0680 
0681     { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
0682     { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
0683 
0684     { "Sto1 ADC MIXL", "DMIC Switch", "Stereo1 DMIC Mux" },
0685     { "Sto1 ADC MIXL", "ADC Switch", "AMICL" },
0686     { "Sto1 ADC MIXR", "DMIC Switch", "Stereo1 DMIC Mux" },
0687     { "Sto1 ADC MIXR", "ADC Switch", "AMICR" },
0688 
0689     { "ADC Power", NULL, "LDO18 IN" },
0690     { "ADC Power", NULL, "LDO18 ADC" },
0691     { "ADC Power", NULL, "LDO21" },
0692     { "ADC Power", NULL, "BG LDO18 IN" },
0693     { "ADC Power", NULL, "BG LDO21" },
0694     { "ADC Power", NULL, "BG MBIAS" },
0695     { "ADC Power", NULL, "MBIAS" },
0696     { "ADC Power", NULL, "VREF2" },
0697     { "ADC Power", NULL, "VREF1" },
0698 
0699     { "ADCL Power", NULL, "LDO16L" },
0700     { "ADCL Power", NULL, "ADC1L" },
0701     { "ADCL Power", NULL, "BSTL2" },
0702     { "ADCL Power", NULL, "BSTL" },
0703     { "ADCL Power", NULL, "ADCFEDL" },
0704 
0705     { "ADCR Power", NULL, "LDO16R" },
0706     { "ADCR Power", NULL, "ADC1R" },
0707     { "ADCR Power", NULL, "BSTR2" },
0708     { "ADCR Power", NULL, "BSTR" },
0709     { "ADCR Power", NULL, "ADCFEDR" },
0710 
0711     { "AMICL", NULL, "ADC CLK" },
0712     { "AMICL", NULL, "ADC Power" },
0713     { "AMICL", NULL, "ADCL Power" },
0714     { "AMICR", NULL, "ADC CLK" },
0715     { "AMICR", NULL, "ADC Power" },
0716     { "AMICR", NULL, "ADCR Power" },
0717 
0718     { "PLL1 LDO", NULL, "PLL1 LDO ENABLE" },
0719     { "PLL1", NULL, "PLL1 LDO" },
0720 
0721     { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
0722     { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
0723 
0724     { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
0725     { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
0726     { "Stereo1 ADC MIX", NULL, "adc stereo1 filter" },
0727     { "adc stereo1 filter", NULL, "PLL1", rt5514_is_sys_clk_from_pll },
0728     { "adc stereo1 filter", NULL, "ASRC AD1", rt5514_i2s_use_asrc },
0729 
0730     { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
0731     { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
0732 
0733     { "Sto2 ADC MIXL", "DMIC Switch", "Stereo2 DMIC Mux" },
0734     { "Sto2 ADC MIXL", "ADC Switch", "AMICL" },
0735     { "Sto2 ADC MIXR", "DMIC Switch", "Stereo2 DMIC Mux" },
0736     { "Sto2 ADC MIXR", "ADC Switch", "AMICR" },
0737 
0738     { "Stereo2 ADC MIXL", NULL, "Sto2 ADC MIXL" },
0739     { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
0740 
0741     { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
0742     { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
0743     { "Stereo2 ADC MIX", NULL, "adc stereo2 filter" },
0744     { "adc stereo2 filter", NULL, "PLL1", rt5514_is_sys_clk_from_pll },
0745     { "adc stereo2 filter", NULL, "ASRC AD2", rt5514_i2s_use_asrc },
0746 
0747     { "AIF1TX", NULL, "Stereo1 ADC MIX"},
0748     { "AIF1TX", NULL, "Stereo2 ADC MIX"},
0749 };
0750 
0751 static int rt5514_hw_params(struct snd_pcm_substream *substream,
0752     struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
0753 {
0754     struct snd_soc_component *component = dai->component;
0755     struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
0756     int pre_div, bclk_ms, frame_size;
0757     unsigned int val_len = 0;
0758 
0759     rt5514->lrck = params_rate(params);
0760     pre_div = rl6231_get_clk_info(rt5514->sysclk, rt5514->lrck);
0761     if (pre_div < 0) {
0762         dev_err(component->dev, "Unsupported clock setting\n");
0763         return -EINVAL;
0764     }
0765 
0766     frame_size = snd_soc_params_to_frame_size(params);
0767     if (frame_size < 0) {
0768         dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
0769         return -EINVAL;
0770     }
0771 
0772     bclk_ms = frame_size > 32;
0773     rt5514->bclk = rt5514->lrck * (32 << bclk_ms);
0774 
0775     dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
0776         rt5514->bclk, rt5514->lrck);
0777     dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
0778                 bclk_ms, pre_div, dai->id);
0779 
0780     switch (params_format(params)) {
0781     case SNDRV_PCM_FORMAT_S16_LE:
0782         break;
0783     case SNDRV_PCM_FORMAT_S20_3LE:
0784         val_len = RT5514_I2S_DL_20;
0785         break;
0786     case SNDRV_PCM_FORMAT_S24_LE:
0787         val_len = RT5514_I2S_DL_24;
0788         break;
0789     case SNDRV_PCM_FORMAT_S8:
0790         val_len = RT5514_I2S_DL_8;
0791         break;
0792     default:
0793         return -EINVAL;
0794     }
0795 
0796     regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL1, RT5514_I2S_DL_MASK,
0797         val_len);
0798     regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL1,
0799         RT5514_CLK_AD_ANA1_SEL_MASK,
0800         (pre_div + 1) << RT5514_CLK_AD_ANA1_SEL_SFT);
0801     regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL2,
0802         RT5514_CLK_SYS_DIV_OUT_MASK | RT5514_SEL_ADC_OSR_MASK,
0803         pre_div << RT5514_CLK_SYS_DIV_OUT_SFT |
0804         pre_div << RT5514_SEL_ADC_OSR_SFT);
0805 
0806     return 0;
0807 }
0808 
0809 static int rt5514_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
0810 {
0811     struct snd_soc_component *component = dai->component;
0812     struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
0813     unsigned int reg_val = 0;
0814 
0815     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0816     case SND_SOC_DAIFMT_NB_NF:
0817         break;
0818 
0819     case SND_SOC_DAIFMT_NB_IF:
0820         reg_val |= RT5514_I2S_LR_INV;
0821         break;
0822 
0823     case SND_SOC_DAIFMT_IB_NF:
0824         reg_val |= RT5514_I2S_BP_INV;
0825         break;
0826 
0827     case SND_SOC_DAIFMT_IB_IF:
0828         reg_val |= RT5514_I2S_BP_INV | RT5514_I2S_LR_INV;
0829         break;
0830 
0831     default:
0832         return -EINVAL;
0833     }
0834 
0835     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0836     case SND_SOC_DAIFMT_I2S:
0837         break;
0838 
0839     case SND_SOC_DAIFMT_LEFT_J:
0840         reg_val |= RT5514_I2S_DF_LEFT;
0841         break;
0842 
0843     case SND_SOC_DAIFMT_DSP_A:
0844         reg_val |= RT5514_I2S_DF_PCM_A;
0845         break;
0846 
0847     case SND_SOC_DAIFMT_DSP_B:
0848         reg_val |= RT5514_I2S_DF_PCM_B;
0849         break;
0850 
0851     default:
0852         return -EINVAL;
0853     }
0854 
0855     regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL1,
0856         RT5514_I2S_DF_MASK | RT5514_I2S_BP_MASK | RT5514_I2S_LR_MASK,
0857         reg_val);
0858 
0859     return 0;
0860 }
0861 
0862 static int rt5514_set_dai_sysclk(struct snd_soc_dai *dai,
0863         int clk_id, unsigned int freq, int dir)
0864 {
0865     struct snd_soc_component *component = dai->component;
0866     struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
0867     unsigned int reg_val = 0;
0868 
0869     if (freq == rt5514->sysclk && clk_id == rt5514->sysclk_src)
0870         return 0;
0871 
0872     switch (clk_id) {
0873     case RT5514_SCLK_S_MCLK:
0874         reg_val |= RT5514_CLK_SYS_PRE_SEL_MCLK;
0875         break;
0876 
0877     case RT5514_SCLK_S_PLL1:
0878         reg_val |= RT5514_CLK_SYS_PRE_SEL_PLL;
0879         break;
0880 
0881     default:
0882         dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
0883         return -EINVAL;
0884     }
0885 
0886     regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL2,
0887         RT5514_CLK_SYS_PRE_SEL_MASK, reg_val);
0888 
0889     rt5514->sysclk = freq;
0890     rt5514->sysclk_src = clk_id;
0891 
0892     dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
0893 
0894     return 0;
0895 }
0896 
0897 static int rt5514_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
0898             unsigned int freq_in, unsigned int freq_out)
0899 {
0900     struct snd_soc_component *component = dai->component;
0901     struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
0902     struct rl6231_pll_code pll_code;
0903     int ret;
0904 
0905     if (!freq_in || !freq_out) {
0906         dev_dbg(component->dev, "PLL disabled\n");
0907 
0908         rt5514->pll_in = 0;
0909         rt5514->pll_out = 0;
0910         regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL2,
0911             RT5514_CLK_SYS_PRE_SEL_MASK,
0912             RT5514_CLK_SYS_PRE_SEL_MCLK);
0913 
0914         return 0;
0915     }
0916 
0917     if (source == rt5514->pll_src && freq_in == rt5514->pll_in &&
0918         freq_out == rt5514->pll_out)
0919         return 0;
0920 
0921     switch (source) {
0922     case RT5514_PLL1_S_MCLK:
0923         regmap_update_bits(rt5514->regmap, RT5514_PLL_SOURCE_CTRL,
0924             RT5514_PLL_1_SEL_MASK, RT5514_PLL_1_SEL_MCLK);
0925         break;
0926 
0927     case RT5514_PLL1_S_BCLK:
0928         regmap_update_bits(rt5514->regmap, RT5514_PLL_SOURCE_CTRL,
0929             RT5514_PLL_1_SEL_MASK, RT5514_PLL_1_SEL_SCLK);
0930         break;
0931 
0932     default:
0933         dev_err(component->dev, "Unknown PLL source %d\n", source);
0934         return -EINVAL;
0935     }
0936 
0937     ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
0938     if (ret < 0) {
0939         dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
0940         return ret;
0941     }
0942 
0943     dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
0944         pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
0945         pll_code.n_code, pll_code.k_code);
0946 
0947     regmap_write(rt5514->regmap, RT5514_ANA_CTRL_PLL1_1,
0948         pll_code.k_code << RT5514_PLL_K_SFT |
0949         pll_code.n_code << RT5514_PLL_N_SFT |
0950         (pll_code.m_bp ? 0 : pll_code.m_code) << RT5514_PLL_M_SFT);
0951     regmap_update_bits(rt5514->regmap, RT5514_ANA_CTRL_PLL1_2,
0952         RT5514_PLL_M_BP, pll_code.m_bp << RT5514_PLL_M_BP_SFT);
0953 
0954     rt5514->pll_in = freq_in;
0955     rt5514->pll_out = freq_out;
0956     rt5514->pll_src = source;
0957 
0958     return 0;
0959 }
0960 
0961 static int rt5514_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
0962             unsigned int rx_mask, int slots, int slot_width)
0963 {
0964     struct snd_soc_component *component = dai->component;
0965     struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
0966     unsigned int val = 0, val2 = 0;
0967 
0968     if (rx_mask || tx_mask)
0969         val |= RT5514_TDM_MODE;
0970 
0971     switch (tx_mask) {
0972     case 0x3:
0973         val2 |= RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH2 |
0974             RT5514_TDM_DOCKING_START_SLOT0;
0975         break;
0976 
0977     case 0x30:
0978         val2 |= RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH2 |
0979             RT5514_TDM_DOCKING_START_SLOT4;
0980         break;
0981 
0982     case 0xf:
0983         val2 |= RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH4 |
0984             RT5514_TDM_DOCKING_START_SLOT0;
0985         break;
0986 
0987     case 0xf0:
0988         val2 |= RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH4 |
0989             RT5514_TDM_DOCKING_START_SLOT4;
0990         break;
0991 
0992     default:
0993         break;
0994     }
0995 
0996 
0997 
0998     switch (slots) {
0999     case 4:
1000         val |= RT5514_TDMSLOT_SEL_RX_4CH | RT5514_TDMSLOT_SEL_TX_4CH;
1001         break;
1002 
1003     case 6:
1004         val |= RT5514_TDMSLOT_SEL_RX_6CH | RT5514_TDMSLOT_SEL_TX_6CH;
1005         break;
1006 
1007     case 8:
1008         val |= RT5514_TDMSLOT_SEL_RX_8CH | RT5514_TDMSLOT_SEL_TX_8CH;
1009         break;
1010 
1011     case 2:
1012     default:
1013         break;
1014     }
1015 
1016     switch (slot_width) {
1017     case 20:
1018         val |= RT5514_CH_LEN_RX_20 | RT5514_CH_LEN_TX_20;
1019         break;
1020 
1021     case 24:
1022         val |= RT5514_CH_LEN_RX_24 | RT5514_CH_LEN_TX_24;
1023         break;
1024 
1025     case 25:
1026         val |= RT5514_TDM_MODE2;
1027         break;
1028 
1029     case 32:
1030         val |= RT5514_CH_LEN_RX_32 | RT5514_CH_LEN_TX_32;
1031         break;
1032 
1033     case 16:
1034     default:
1035         break;
1036     }
1037 
1038     regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL1, RT5514_TDM_MODE |
1039         RT5514_TDMSLOT_SEL_RX_MASK | RT5514_TDMSLOT_SEL_TX_MASK |
1040         RT5514_CH_LEN_RX_MASK | RT5514_CH_LEN_TX_MASK |
1041         RT5514_TDM_MODE2, val);
1042 
1043     regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL2,
1044         RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH_MASK |
1045         RT5514_TDM_DOCKING_START_MASK, val2);
1046 
1047     return 0;
1048 }
1049 
1050 static int rt5514_set_bias_level(struct snd_soc_component *component,
1051             enum snd_soc_bias_level level)
1052 {
1053     struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
1054     int ret;
1055 
1056     switch (level) {
1057     case SND_SOC_BIAS_PREPARE:
1058         if (IS_ERR(rt5514->mclk))
1059             break;
1060 
1061         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON) {
1062             clk_disable_unprepare(rt5514->mclk);
1063         } else {
1064             ret = clk_prepare_enable(rt5514->mclk);
1065             if (ret)
1066                 return ret;
1067         }
1068         break;
1069 
1070     case SND_SOC_BIAS_STANDBY:
1071         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1072             /*
1073              * If the DSP is enabled in start of recording, the DSP
1074              * should be disabled, and sync back to normal recording
1075              * settings to make sure recording properly.
1076              */
1077             if (rt5514->dsp_enabled) {
1078                 rt5514->dsp_enabled = 0;
1079                 regmap_multi_reg_write(rt5514->i2c_regmap,
1080                     rt5514_i2c_patch,
1081                     ARRAY_SIZE(rt5514_i2c_patch));
1082                 regcache_mark_dirty(rt5514->regmap);
1083                 regcache_sync(rt5514->regmap);
1084             }
1085         }
1086         break;
1087 
1088     default:
1089         break;
1090     }
1091 
1092     return 0;
1093 }
1094 
1095 static int rt5514_probe(struct snd_soc_component *component)
1096 {
1097     struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
1098     struct platform_device *pdev = container_of(component->dev,
1099                            struct platform_device, dev);
1100 
1101     rt5514->mclk = devm_clk_get(component->dev, "mclk");
1102     if (PTR_ERR(rt5514->mclk) == -EPROBE_DEFER)
1103         return -EPROBE_DEFER;
1104 
1105     if (rt5514->pdata.dsp_calib_clk_name) {
1106         rt5514->dsp_calib_clk = devm_clk_get(&pdev->dev,
1107                 rt5514->pdata.dsp_calib_clk_name);
1108         if (PTR_ERR(rt5514->dsp_calib_clk) == -EPROBE_DEFER)
1109             return -EPROBE_DEFER;
1110     }
1111 
1112     rt5514->component = component;
1113     rt5514->pll3_cal_value = 0x0078b000;
1114 
1115     return 0;
1116 }
1117 
1118 static int rt5514_i2c_read(void *context, unsigned int reg, unsigned int *val)
1119 {
1120     struct i2c_client *client = context;
1121     struct rt5514_priv *rt5514 = i2c_get_clientdata(client);
1122 
1123     regmap_read(rt5514->i2c_regmap, reg | RT5514_DSP_MAPPING, val);
1124 
1125     return 0;
1126 }
1127 
1128 static int rt5514_i2c_write(void *context, unsigned int reg, unsigned int val)
1129 {
1130     struct i2c_client *client = context;
1131     struct rt5514_priv *rt5514 = i2c_get_clientdata(client);
1132 
1133     regmap_write(rt5514->i2c_regmap, reg | RT5514_DSP_MAPPING, val);
1134 
1135     return 0;
1136 }
1137 
1138 #define RT5514_STEREO_RATES SNDRV_PCM_RATE_8000_192000
1139 #define RT5514_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1140             SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1141 
1142 static const struct snd_soc_dai_ops rt5514_aif_dai_ops = {
1143     .hw_params = rt5514_hw_params,
1144     .set_fmt = rt5514_set_dai_fmt,
1145     .set_sysclk = rt5514_set_dai_sysclk,
1146     .set_pll = rt5514_set_dai_pll,
1147     .set_tdm_slot = rt5514_set_tdm_slot,
1148 };
1149 
1150 static struct snd_soc_dai_driver rt5514_dai[] = {
1151     {
1152         .name = "rt5514-aif1",
1153         .id = 0,
1154         .capture = {
1155             .stream_name = "AIF1 Capture",
1156             .channels_min = 1,
1157             .channels_max = 4,
1158             .rates = RT5514_STEREO_RATES,
1159             .formats = RT5514_FORMATS,
1160         },
1161         .ops = &rt5514_aif_dai_ops,
1162     }
1163 };
1164 
1165 static const struct snd_soc_component_driver soc_component_dev_rt5514 = {
1166     .probe          = rt5514_probe,
1167     .set_bias_level     = rt5514_set_bias_level,
1168     .controls       = rt5514_snd_controls,
1169     .num_controls       = ARRAY_SIZE(rt5514_snd_controls),
1170     .dapm_widgets       = rt5514_dapm_widgets,
1171     .num_dapm_widgets   = ARRAY_SIZE(rt5514_dapm_widgets),
1172     .dapm_routes        = rt5514_dapm_routes,
1173     .num_dapm_routes    = ARRAY_SIZE(rt5514_dapm_routes),
1174     .use_pmdown_time    = 1,
1175     .endianness     = 1,
1176 };
1177 
1178 static const struct regmap_config rt5514_i2c_regmap = {
1179     .name = "i2c",
1180     .reg_bits = 32,
1181     .val_bits = 32,
1182 
1183     .readable_reg = rt5514_i2c_readable_register,
1184 
1185     .cache_type = REGCACHE_NONE,
1186 };
1187 
1188 static const struct regmap_config rt5514_regmap = {
1189     .reg_bits = 16,
1190     .val_bits = 32,
1191 
1192     .max_register = RT5514_VENDOR_ID2,
1193     .volatile_reg = rt5514_volatile_register,
1194     .readable_reg = rt5514_readable_register,
1195     .reg_read = rt5514_i2c_read,
1196     .reg_write = rt5514_i2c_write,
1197 
1198     .cache_type = REGCACHE_RBTREE,
1199     .reg_defaults = rt5514_reg,
1200     .num_reg_defaults = ARRAY_SIZE(rt5514_reg),
1201     .use_single_read = true,
1202     .use_single_write = true,
1203 };
1204 
1205 static const struct i2c_device_id rt5514_i2c_id[] = {
1206     { "rt5514", 0 },
1207     { }
1208 };
1209 MODULE_DEVICE_TABLE(i2c, rt5514_i2c_id);
1210 
1211 #if defined(CONFIG_OF)
1212 static const struct of_device_id rt5514_of_match[] = {
1213     { .compatible = "realtek,rt5514", },
1214     {},
1215 };
1216 MODULE_DEVICE_TABLE(of, rt5514_of_match);
1217 #endif
1218 
1219 #ifdef CONFIG_ACPI
1220 static const struct acpi_device_id rt5514_acpi_match[] = {
1221     { "10EC5514", 0},
1222     {},
1223 };
1224 MODULE_DEVICE_TABLE(acpi, rt5514_acpi_match);
1225 #endif
1226 
1227 static int rt5514_parse_dp(struct rt5514_priv *rt5514, struct device *dev)
1228 {
1229     device_property_read_u32(dev, "realtek,dmic-init-delay-ms",
1230         &rt5514->pdata.dmic_init_delay);
1231     device_property_read_string(dev, "realtek,dsp-calib-clk-name",
1232         &rt5514->pdata.dsp_calib_clk_name);
1233     device_property_read_u32(dev, "realtek,dsp-calib-clk-rate",
1234         &rt5514->pdata.dsp_calib_clk_rate);
1235 
1236     return 0;
1237 }
1238 
1239 static __maybe_unused int rt5514_i2c_resume(struct device *dev)
1240 {
1241     struct rt5514_priv *rt5514 = dev_get_drvdata(dev);
1242     unsigned int val;
1243 
1244     /*
1245      * Add a bogus read to avoid rt5514's confusion after s2r in case it
1246      * saw glitches on the i2c lines and thought the other side sent a
1247      * start bit.
1248      */
1249     regmap_read(rt5514->regmap, RT5514_VENDOR_ID2, &val);
1250 
1251     return 0;
1252 }
1253 
1254 static int rt5514_i2c_probe(struct i2c_client *i2c)
1255 {
1256     struct rt5514_platform_data *pdata = dev_get_platdata(&i2c->dev);
1257     struct rt5514_priv *rt5514;
1258     int ret;
1259     unsigned int val = ~0;
1260 
1261     rt5514 = devm_kzalloc(&i2c->dev, sizeof(struct rt5514_priv),
1262                 GFP_KERNEL);
1263     if (rt5514 == NULL)
1264         return -ENOMEM;
1265 
1266     i2c_set_clientdata(i2c, rt5514);
1267 
1268     if (pdata)
1269         rt5514->pdata = *pdata;
1270     else
1271         rt5514_parse_dp(rt5514, &i2c->dev);
1272 
1273     rt5514->i2c_regmap = devm_regmap_init_i2c(i2c, &rt5514_i2c_regmap);
1274     if (IS_ERR(rt5514->i2c_regmap)) {
1275         ret = PTR_ERR(rt5514->i2c_regmap);
1276         dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1277             ret);
1278         return ret;
1279     }
1280 
1281     rt5514->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5514_regmap);
1282     if (IS_ERR(rt5514->regmap)) {
1283         ret = PTR_ERR(rt5514->regmap);
1284         dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1285             ret);
1286         return ret;
1287     }
1288 
1289     /*
1290      * The rt5514 can get confused if the i2c lines glitch together, as
1291      * can happen at bootup as regulators are turned off and on.  If it's
1292      * in this glitched state the first i2c read will fail, so we'll give
1293      * it one change to retry.
1294      */
1295     ret = regmap_read(rt5514->regmap, RT5514_VENDOR_ID2, &val);
1296     if (ret || val != RT5514_DEVICE_ID)
1297         ret = regmap_read(rt5514->regmap, RT5514_VENDOR_ID2, &val);
1298     if (ret || val != RT5514_DEVICE_ID) {
1299         dev_err(&i2c->dev,
1300             "Device with ID register %x is not rt5514\n", val);
1301         return -ENODEV;
1302     }
1303 
1304     ret = regmap_multi_reg_write(rt5514->i2c_regmap, rt5514_i2c_patch,
1305                     ARRAY_SIZE(rt5514_i2c_patch));
1306     if (ret != 0)
1307         dev_warn(&i2c->dev, "Failed to apply i2c_regmap patch: %d\n",
1308             ret);
1309 
1310     ret = regmap_register_patch(rt5514->regmap, rt5514_patch,
1311                     ARRAY_SIZE(rt5514_patch));
1312     if (ret != 0)
1313         dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
1314 
1315     return devm_snd_soc_register_component(&i2c->dev,
1316             &soc_component_dev_rt5514,
1317             rt5514_dai, ARRAY_SIZE(rt5514_dai));
1318 }
1319 
1320 static const struct dev_pm_ops rt5514_i2_pm_ops = {
1321     SET_SYSTEM_SLEEP_PM_OPS(NULL, rt5514_i2c_resume)
1322 };
1323 
1324 static struct i2c_driver rt5514_i2c_driver = {
1325     .driver = {
1326         .name = "rt5514",
1327         .acpi_match_table = ACPI_PTR(rt5514_acpi_match),
1328         .of_match_table = of_match_ptr(rt5514_of_match),
1329         .pm = &rt5514_i2_pm_ops,
1330     },
1331     .probe_new = rt5514_i2c_probe,
1332     .id_table = rt5514_i2c_id,
1333 };
1334 module_i2c_driver(rt5514_i2c_driver);
1335 
1336 MODULE_DESCRIPTION("ASoC RT5514 driver");
1337 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
1338 MODULE_LICENSE("GPL v2");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!