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0009 #ifndef __RT5514_SPI_H__
0010 #define __RT5514_SPI_H__
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0013
0014
0015 #define RT5514_SPI_BUF_LEN 240
0016
0017 #define RT5514_BUFFER_VOICE_BASE 0x18000200
0018 #define RT5514_BUFFER_VOICE_LIMIT 0x18000204
0019 #define RT5514_BUFFER_VOICE_WP 0x1800020c
0020 #define RT5514_IRQ_CTRL 0x18002094
0021
0022 #define RT5514_IRQ_STATUS_BIT (0x1 << 5)
0023
0024
0025 enum {
0026 RT5514_SPI_CMD_16_READ = 0,
0027 RT5514_SPI_CMD_16_WRITE,
0028 RT5514_SPI_CMD_32_READ,
0029 RT5514_SPI_CMD_32_WRITE,
0030 RT5514_SPI_CMD_BURST_READ,
0031 RT5514_SPI_CMD_BURST_WRITE,
0032 };
0033
0034 int rt5514_spi_burst_read(unsigned int addr, u8 *rxbuf, size_t len);
0035 int rt5514_spi_burst_write(u32 addr, const u8 *txbuf, size_t len);
0036
0037 #endif