Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * rt286.c  --  RT286 ALSA SoC audio codec driver
0004  *
0005  * Copyright 2013 Realtek Semiconductor Corp.
0006  * Author: Bard Liao <bardliao@realtek.com>
0007  */
0008 
0009 #include <linux/module.h>
0010 #include <linux/moduleparam.h>
0011 #include <linux/init.h>
0012 #include <linux/delay.h>
0013 #include <linux/pm.h>
0014 #include <linux/i2c.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/spi/spi.h>
0017 #include <linux/dmi.h>
0018 #include <linux/acpi.h>
0019 #include <sound/core.h>
0020 #include <sound/pcm.h>
0021 #include <sound/pcm_params.h>
0022 #include <sound/soc.h>
0023 #include <sound/soc-dapm.h>
0024 #include <sound/initval.h>
0025 #include <sound/tlv.h>
0026 #include <sound/jack.h>
0027 #include <linux/workqueue.h>
0028 #include <sound/rt286.h>
0029 
0030 #include "rl6347a.h"
0031 #include "rt286.h"
0032 
0033 #define RT286_VENDOR_ID 0x10ec0286
0034 #define RT288_VENDOR_ID 0x10ec0288
0035 
0036 struct rt286_priv {
0037     struct reg_default *index_cache;
0038     int index_cache_size;
0039     struct regmap *regmap;
0040     struct snd_soc_component *component;
0041     struct rt286_platform_data pdata;
0042     struct i2c_client *i2c;
0043     struct snd_soc_jack *jack;
0044     struct delayed_work jack_detect_work;
0045     int sys_clk;
0046     int clk_id;
0047 };
0048 
0049 static const struct reg_default rt286_index_def[] = {
0050     { 0x01, 0xaaaa },
0051     { 0x02, 0x8aaa },
0052     { 0x03, 0x0002 },
0053     { 0x04, 0xaf01 },
0054     { 0x08, 0x000d },
0055     { 0x09, 0xd810 },
0056     { 0x0a, 0x0120 },
0057     { 0x0b, 0x0000 },
0058     { 0x0d, 0x2800 },
0059     { 0x0f, 0x0000 },
0060     { 0x19, 0x0a17 },
0061     { 0x20, 0x0020 },
0062     { 0x33, 0x0208 },
0063     { 0x49, 0x0004 },
0064     { 0x4f, 0x50e9 },
0065     { 0x50, 0x2000 },
0066     { 0x63, 0x2902 },
0067     { 0x67, 0x1111 },
0068     { 0x68, 0x1016 },
0069     { 0x69, 0x273f },
0070 };
0071 #define INDEX_CACHE_SIZE ARRAY_SIZE(rt286_index_def)
0072 
0073 static const struct reg_default rt286_reg[] = {
0074     { 0x00170500, 0x00000400 },
0075     { 0x00220000, 0x00000031 },
0076     { 0x00239000, 0x0000007f },
0077     { 0x0023a000, 0x0000007f },
0078     { 0x00270500, 0x00000400 },
0079     { 0x00370500, 0x00000400 },
0080     { 0x00870500, 0x00000400 },
0081     { 0x00920000, 0x00000031 },
0082     { 0x00935000, 0x000000c3 },
0083     { 0x00936000, 0x000000c3 },
0084     { 0x00970500, 0x00000400 },
0085     { 0x00b37000, 0x00000097 },
0086     { 0x00b37200, 0x00000097 },
0087     { 0x00b37300, 0x00000097 },
0088     { 0x00c37000, 0x00000000 },
0089     { 0x00c37100, 0x00000080 },
0090     { 0x01270500, 0x00000400 },
0091     { 0x01370500, 0x00000400 },
0092     { 0x01371f00, 0x411111f0 },
0093     { 0x01439000, 0x00000080 },
0094     { 0x0143a000, 0x00000080 },
0095     { 0x01470700, 0x00000000 },
0096     { 0x01470500, 0x00000400 },
0097     { 0x01470c00, 0x00000000 },
0098     { 0x01470100, 0x00000000 },
0099     { 0x01837000, 0x00000000 },
0100     { 0x01870500, 0x00000400 },
0101     { 0x02050000, 0x00000000 },
0102     { 0x02139000, 0x00000080 },
0103     { 0x0213a000, 0x00000080 },
0104     { 0x02170100, 0x00000000 },
0105     { 0x02170500, 0x00000400 },
0106     { 0x02170700, 0x00000000 },
0107     { 0x02270100, 0x00000000 },
0108     { 0x02370100, 0x00000000 },
0109     { 0x01870700, 0x00000020 },
0110     { 0x00830000, 0x000000c3 },
0111     { 0x00930000, 0x000000c3 },
0112     { 0x01270700, 0x00000000 },
0113 };
0114 
0115 static bool rt286_volatile_register(struct device *dev, unsigned int reg)
0116 {
0117     switch (reg) {
0118     case 0 ... 0xff:
0119     case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
0120     case RT286_GET_HP_SENSE:
0121     case RT286_GET_MIC1_SENSE:
0122     case RT286_PROC_COEF:
0123         return true;
0124     default:
0125         return false;
0126     }
0127 
0128 
0129 }
0130 
0131 static bool rt286_readable_register(struct device *dev, unsigned int reg)
0132 {
0133     switch (reg) {
0134     case 0 ... 0xff:
0135     case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
0136     case RT286_GET_HP_SENSE:
0137     case RT286_GET_MIC1_SENSE:
0138     case RT286_SET_AUDIO_POWER:
0139     case RT286_SET_HPO_POWER:
0140     case RT286_SET_SPK_POWER:
0141     case RT286_SET_DMIC1_POWER:
0142     case RT286_SPK_MUX:
0143     case RT286_HPO_MUX:
0144     case RT286_ADC0_MUX:
0145     case RT286_ADC1_MUX:
0146     case RT286_SET_MIC1:
0147     case RT286_SET_PIN_HPO:
0148     case RT286_SET_PIN_SPK:
0149     case RT286_SET_PIN_DMIC1:
0150     case RT286_SPK_EAPD:
0151     case RT286_SET_AMP_GAIN_HPO:
0152     case RT286_SET_DMIC2_DEFAULT:
0153     case RT286_DACL_GAIN:
0154     case RT286_DACR_GAIN:
0155     case RT286_ADCL_GAIN:
0156     case RT286_ADCR_GAIN:
0157     case RT286_MIC_GAIN:
0158     case RT286_SPOL_GAIN:
0159     case RT286_SPOR_GAIN:
0160     case RT286_HPOL_GAIN:
0161     case RT286_HPOR_GAIN:
0162     case RT286_F_DAC_SWITCH:
0163     case RT286_F_RECMIX_SWITCH:
0164     case RT286_REC_MIC_SWITCH:
0165     case RT286_REC_I2S_SWITCH:
0166     case RT286_REC_LINE_SWITCH:
0167     case RT286_REC_BEEP_SWITCH:
0168     case RT286_DAC_FORMAT:
0169     case RT286_ADC_FORMAT:
0170     case RT286_COEF_INDEX:
0171     case RT286_PROC_COEF:
0172     case RT286_SET_AMP_GAIN_ADC_IN1:
0173     case RT286_SET_AMP_GAIN_ADC_IN2:
0174     case RT286_SET_GPIO_MASK:
0175     case RT286_SET_GPIO_DIRECTION:
0176     case RT286_SET_GPIO_DATA:
0177     case RT286_SET_POWER(RT286_DAC_OUT1):
0178     case RT286_SET_POWER(RT286_DAC_OUT2):
0179     case RT286_SET_POWER(RT286_ADC_IN1):
0180     case RT286_SET_POWER(RT286_ADC_IN2):
0181     case RT286_SET_POWER(RT286_DMIC2):
0182     case RT286_SET_POWER(RT286_MIC1):
0183         return true;
0184     default:
0185         return false;
0186     }
0187 }
0188 
0189 #ifdef CONFIG_PM
0190 static void rt286_index_sync(struct snd_soc_component *component)
0191 {
0192     struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
0193     int i;
0194 
0195     for (i = 0; i < INDEX_CACHE_SIZE; i++) {
0196         snd_soc_component_write(component, rt286->index_cache[i].reg,
0197                   rt286->index_cache[i].def);
0198     }
0199 }
0200 #endif
0201 
0202 static int rt286_support_power_controls[] = {
0203     RT286_DAC_OUT1,
0204     RT286_DAC_OUT2,
0205     RT286_ADC_IN1,
0206     RT286_ADC_IN2,
0207     RT286_MIC1,
0208     RT286_DMIC1,
0209     RT286_DMIC2,
0210     RT286_SPK_OUT,
0211     RT286_HP_OUT,
0212 };
0213 #define RT286_POWER_REG_LEN ARRAY_SIZE(rt286_support_power_controls)
0214 
0215 static int rt286_jack_detect(struct rt286_priv *rt286, bool *hp, bool *mic)
0216 {
0217     struct snd_soc_dapm_context *dapm;
0218     unsigned int val, buf;
0219 
0220     *hp = false;
0221     *mic = false;
0222 
0223     if (!rt286->component)
0224         return -EINVAL;
0225 
0226     dapm = snd_soc_component_get_dapm(rt286->component);
0227 
0228     if (rt286->pdata.cbj_en) {
0229         regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
0230         *hp = buf & 0x80000000;
0231         if (*hp) {
0232             /* power on HV,VERF */
0233             regmap_update_bits(rt286->regmap,
0234                 RT286_DC_GAIN, 0x200, 0x200);
0235 
0236             snd_soc_dapm_force_enable_pin(dapm, "HV");
0237             snd_soc_dapm_force_enable_pin(dapm, "VREF");
0238             /* power LDO1 */
0239             snd_soc_dapm_force_enable_pin(dapm, "LDO1");
0240             snd_soc_dapm_sync(dapm);
0241 
0242             regmap_write(rt286->regmap, RT286_SET_MIC1, 0x24);
0243             msleep(50);
0244 
0245             regmap_update_bits(rt286->regmap,
0246                 RT286_CBJ_CTRL1, 0xfcc0, 0xd400);
0247             msleep(300);
0248             regmap_read(rt286->regmap, RT286_CBJ_CTRL2, &val);
0249 
0250             if (0x0070 == (val & 0x0070)) {
0251                 *mic = true;
0252             } else {
0253                 regmap_update_bits(rt286->regmap,
0254                     RT286_CBJ_CTRL1, 0xfcc0, 0xe400);
0255                 msleep(300);
0256                 regmap_read(rt286->regmap,
0257                     RT286_CBJ_CTRL2, &val);
0258                 if (0x0070 == (val & 0x0070)) {
0259                     *mic = true;
0260                 } else {
0261                     *mic = false;
0262                     regmap_update_bits(rt286->regmap,
0263                         RT286_CBJ_CTRL1,
0264                         0xfcc0, 0xc400);
0265                 }
0266             }
0267 
0268             regmap_update_bits(rt286->regmap,
0269                 RT286_DC_GAIN, 0x200, 0x0);
0270 
0271         } else {
0272             *mic = false;
0273             regmap_write(rt286->regmap, RT286_SET_MIC1, 0x20);
0274             regmap_update_bits(rt286->regmap,
0275                 RT286_CBJ_CTRL1, 0x0400, 0x0000);
0276         }
0277     } else {
0278         regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
0279         *hp = buf & 0x80000000;
0280         regmap_read(rt286->regmap, RT286_GET_MIC1_SENSE, &buf);
0281         *mic = buf & 0x80000000;
0282     }
0283 
0284     if (!*hp) {
0285         snd_soc_dapm_disable_pin(dapm, "HV");
0286         snd_soc_dapm_disable_pin(dapm, "VREF");
0287         snd_soc_dapm_disable_pin(dapm, "LDO1");
0288         snd_soc_dapm_sync(dapm);
0289     }
0290 
0291     return 0;
0292 }
0293 
0294 static void rt286_jack_detect_work(struct work_struct *work)
0295 {
0296     struct rt286_priv *rt286 =
0297         container_of(work, struct rt286_priv, jack_detect_work.work);
0298     int status = 0;
0299     bool hp = false;
0300     bool mic = false;
0301 
0302     rt286_jack_detect(rt286, &hp, &mic);
0303 
0304     if (hp)
0305         status |= SND_JACK_HEADPHONE;
0306 
0307     if (mic)
0308         status |= SND_JACK_MICROPHONE;
0309 
0310     snd_soc_jack_report(rt286->jack, status,
0311         SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
0312 }
0313 
0314 static int rt286_mic_detect(struct snd_soc_component *component,
0315                 struct snd_soc_jack *jack, void *data)
0316 {
0317     struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
0318     struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
0319 
0320     rt286->jack = jack;
0321 
0322     if (jack) {
0323         /* enable IRQ */
0324         if (rt286->jack->status & SND_JACK_HEADPHONE)
0325             snd_soc_dapm_force_enable_pin(dapm, "LDO1");
0326         regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x2, 0x2);
0327         /* Send an initial empty report */
0328         snd_soc_jack_report(rt286->jack, rt286->jack->status,
0329             SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
0330     } else {
0331         /* disable IRQ */
0332         regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x2, 0x0);
0333         snd_soc_dapm_disable_pin(dapm, "LDO1");
0334     }
0335     snd_soc_dapm_sync(dapm);
0336 
0337     return 0;
0338 }
0339 
0340 static int is_mclk_mode(struct snd_soc_dapm_widget *source,
0341              struct snd_soc_dapm_widget *sink)
0342 {
0343     struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
0344     struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
0345 
0346     if (rt286->clk_id == RT286_SCLK_S_MCLK)
0347         return 1;
0348     else
0349         return 0;
0350 }
0351 
0352 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0);
0353 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
0354 
0355 static const struct snd_kcontrol_new rt286_snd_controls[] = {
0356     SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT286_DACL_GAIN,
0357                 RT286_DACR_GAIN, 0, 0x7f, 0, out_vol_tlv),
0358     SOC_DOUBLE_R("ADC0 Capture Switch", RT286_ADCL_GAIN,
0359                 RT286_ADCR_GAIN, 7, 1, 1),
0360     SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT286_ADCL_GAIN,
0361                 RT286_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv),
0362     SOC_SINGLE_TLV("AMIC Volume", RT286_MIC_GAIN,
0363                 0, 0x3, 0, mic_vol_tlv),
0364     SOC_DOUBLE_R("Speaker Playback Switch", RT286_SPOL_GAIN,
0365                 RT286_SPOR_GAIN, RT286_MUTE_SFT, 1, 1),
0366 };
0367 
0368 /* Digital Mixer */
0369 static const struct snd_kcontrol_new rt286_front_mix[] = {
0370     SOC_DAPM_SINGLE("DAC Switch",  RT286_F_DAC_SWITCH,
0371             RT286_MUTE_SFT, 1, 1),
0372     SOC_DAPM_SINGLE("RECMIX Switch", RT286_F_RECMIX_SWITCH,
0373             RT286_MUTE_SFT, 1, 1),
0374 };
0375 
0376 /* Analog Input Mixer */
0377 static const struct snd_kcontrol_new rt286_rec_mix[] = {
0378     SOC_DAPM_SINGLE("Mic1 Switch", RT286_REC_MIC_SWITCH,
0379             RT286_MUTE_SFT, 1, 1),
0380     SOC_DAPM_SINGLE("I2S Switch", RT286_REC_I2S_SWITCH,
0381             RT286_MUTE_SFT, 1, 1),
0382     SOC_DAPM_SINGLE("Line1 Switch", RT286_REC_LINE_SWITCH,
0383             RT286_MUTE_SFT, 1, 1),
0384     SOC_DAPM_SINGLE("Beep Switch", RT286_REC_BEEP_SWITCH,
0385             RT286_MUTE_SFT, 1, 1),
0386 };
0387 
0388 static const struct snd_kcontrol_new spo_enable_control =
0389     SOC_DAPM_SINGLE("Switch", RT286_SET_PIN_SPK,
0390             RT286_SET_PIN_SFT, 1, 0);
0391 
0392 static const struct snd_kcontrol_new hpol_enable_control =
0393     SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOL_GAIN,
0394             RT286_MUTE_SFT, 1, 1);
0395 
0396 static const struct snd_kcontrol_new hpor_enable_control =
0397     SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOR_GAIN,
0398             RT286_MUTE_SFT, 1, 1);
0399 
0400 /* ADC0 source */
0401 static const char * const rt286_adc_src[] = {
0402     "Mic", "RECMIX", "Dmic"
0403 };
0404 
0405 static const int rt286_adc_values[] = {
0406     0, 4, 5,
0407 };
0408 
0409 static SOC_VALUE_ENUM_SINGLE_DECL(
0410     rt286_adc0_enum, RT286_ADC0_MUX, RT286_ADC_SEL_SFT,
0411     RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
0412 
0413 static const struct snd_kcontrol_new rt286_adc0_mux =
0414     SOC_DAPM_ENUM("ADC 0 source", rt286_adc0_enum);
0415 
0416 static SOC_VALUE_ENUM_SINGLE_DECL(
0417     rt286_adc1_enum, RT286_ADC1_MUX, RT286_ADC_SEL_SFT,
0418     RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
0419 
0420 static const struct snd_kcontrol_new rt286_adc1_mux =
0421     SOC_DAPM_ENUM("ADC 1 source", rt286_adc1_enum);
0422 
0423 static const char * const rt286_dac_src[] = {
0424     "Front", "Surround"
0425 };
0426 /* HP-OUT source */
0427 static SOC_ENUM_SINGLE_DECL(rt286_hpo_enum, RT286_HPO_MUX,
0428                 0, rt286_dac_src);
0429 
0430 static const struct snd_kcontrol_new rt286_hpo_mux =
0431 SOC_DAPM_ENUM("HPO source", rt286_hpo_enum);
0432 
0433 /* SPK-OUT source */
0434 static SOC_ENUM_SINGLE_DECL(rt286_spo_enum, RT286_SPK_MUX,
0435                 0, rt286_dac_src);
0436 
0437 static const struct snd_kcontrol_new rt286_spo_mux =
0438 SOC_DAPM_ENUM("SPO source", rt286_spo_enum);
0439 
0440 static int rt286_spk_event(struct snd_soc_dapm_widget *w,
0441                 struct snd_kcontrol *kcontrol, int event)
0442 {
0443     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0444 
0445     switch (event) {
0446     case SND_SOC_DAPM_POST_PMU:
0447         snd_soc_component_write(component,
0448             RT286_SPK_EAPD, RT286_SET_EAPD_HIGH);
0449         break;
0450     case SND_SOC_DAPM_PRE_PMD:
0451         snd_soc_component_write(component,
0452             RT286_SPK_EAPD, RT286_SET_EAPD_LOW);
0453         break;
0454 
0455     default:
0456         return 0;
0457     }
0458 
0459     return 0;
0460 }
0461 
0462 static int rt286_set_dmic1_event(struct snd_soc_dapm_widget *w,
0463                   struct snd_kcontrol *kcontrol, int event)
0464 {
0465     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0466 
0467     switch (event) {
0468     case SND_SOC_DAPM_POST_PMU:
0469         snd_soc_component_write(component, RT286_SET_PIN_DMIC1, 0x20);
0470         break;
0471     case SND_SOC_DAPM_PRE_PMD:
0472         snd_soc_component_write(component, RT286_SET_PIN_DMIC1, 0);
0473         break;
0474     default:
0475         return 0;
0476     }
0477 
0478     return 0;
0479 }
0480 
0481 static int rt286_ldo2_event(struct snd_soc_dapm_widget *w,
0482                  struct snd_kcontrol *kcontrol, int event)
0483 {
0484     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0485 
0486     switch (event) {
0487     case SND_SOC_DAPM_POST_PMU:
0488         snd_soc_component_update_bits(component, RT286_POWER_CTRL2, 0x38, 0x08);
0489         break;
0490     case SND_SOC_DAPM_PRE_PMD:
0491         snd_soc_component_update_bits(component, RT286_POWER_CTRL2, 0x38, 0x30);
0492         break;
0493     default:
0494         return 0;
0495     }
0496 
0497     return 0;
0498 }
0499 
0500 static int rt286_mic1_event(struct snd_soc_dapm_widget *w,
0501                  struct snd_kcontrol *kcontrol, int event)
0502 {
0503     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0504 
0505     switch (event) {
0506     case SND_SOC_DAPM_PRE_PMU:
0507         snd_soc_component_update_bits(component,
0508             RT286_A_BIAS_CTRL3, 0xc000, 0x8000);
0509         snd_soc_component_update_bits(component,
0510             RT286_A_BIAS_CTRL2, 0xc000, 0x8000);
0511         break;
0512     case SND_SOC_DAPM_POST_PMD:
0513         snd_soc_component_update_bits(component,
0514             RT286_A_BIAS_CTRL3, 0xc000, 0x0000);
0515         snd_soc_component_update_bits(component,
0516             RT286_A_BIAS_CTRL2, 0xc000, 0x0000);
0517         break;
0518     default:
0519         return 0;
0520     }
0521 
0522     return 0;
0523 }
0524 
0525 static const struct snd_soc_dapm_widget rt286_dapm_widgets[] = {
0526     SND_SOC_DAPM_SUPPLY_S("HV", 1, RT286_POWER_CTRL1,
0527         12, 1, NULL, 0),
0528     SND_SOC_DAPM_SUPPLY("VREF", RT286_POWER_CTRL1,
0529         0, 1, NULL, 0),
0530     SND_SOC_DAPM_SUPPLY_S("LDO1", 1, RT286_POWER_CTRL2,
0531         2, 0, NULL, 0),
0532     SND_SOC_DAPM_SUPPLY_S("LDO2", 2, RT286_POWER_CTRL1,
0533         13, 1, rt286_ldo2_event, SND_SOC_DAPM_PRE_PMD |
0534         SND_SOC_DAPM_POST_PMU),
0535     SND_SOC_DAPM_SUPPLY("MCLK MODE", RT286_PLL_CTRL1,
0536         5, 0, NULL, 0),
0537     SND_SOC_DAPM_SUPPLY("MIC1 Input Buffer", SND_SOC_NOPM,
0538         0, 0, rt286_mic1_event, SND_SOC_DAPM_PRE_PMU |
0539         SND_SOC_DAPM_POST_PMD),
0540 
0541     /* Input Lines */
0542     SND_SOC_DAPM_INPUT("DMIC1 Pin"),
0543     SND_SOC_DAPM_INPUT("DMIC2 Pin"),
0544     SND_SOC_DAPM_INPUT("MIC1"),
0545     SND_SOC_DAPM_INPUT("LINE1"),
0546     SND_SOC_DAPM_INPUT("Beep"),
0547 
0548     /* DMIC */
0549     SND_SOC_DAPM_PGA_E("DMIC1", RT286_SET_POWER(RT286_DMIC1), 0, 1,
0550         NULL, 0, rt286_set_dmic1_event,
0551         SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
0552     SND_SOC_DAPM_PGA("DMIC2", RT286_SET_POWER(RT286_DMIC2), 0, 1,
0553         NULL, 0),
0554     SND_SOC_DAPM_SUPPLY("DMIC Receiver", SND_SOC_NOPM,
0555         0, 0, NULL, 0),
0556 
0557     /* REC Mixer */
0558     SND_SOC_DAPM_MIXER("RECMIX", SND_SOC_NOPM, 0, 0,
0559         rt286_rec_mix, ARRAY_SIZE(rt286_rec_mix)),
0560 
0561     /* ADCs */
0562     SND_SOC_DAPM_ADC("ADC 0", NULL, SND_SOC_NOPM, 0, 0),
0563     SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0),
0564 
0565     /* ADC Mux */
0566     SND_SOC_DAPM_MUX("ADC 0 Mux", RT286_SET_POWER(RT286_ADC_IN1), 0, 1,
0567         &rt286_adc0_mux),
0568     SND_SOC_DAPM_MUX("ADC 1 Mux", RT286_SET_POWER(RT286_ADC_IN2), 0, 1,
0569         &rt286_adc1_mux),
0570 
0571     /* Audio Interface */
0572     SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
0573     SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
0574     SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
0575     SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
0576 
0577     /* Output Side */
0578     /* DACs */
0579     SND_SOC_DAPM_DAC("DAC 0", NULL, SND_SOC_NOPM, 0, 0),
0580     SND_SOC_DAPM_DAC("DAC 1", NULL, SND_SOC_NOPM, 0, 0),
0581 
0582     /* Output Mux */
0583     SND_SOC_DAPM_MUX("SPK Mux", SND_SOC_NOPM, 0, 0, &rt286_spo_mux),
0584     SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt286_hpo_mux),
0585 
0586     SND_SOC_DAPM_SUPPLY("HP Power", RT286_SET_PIN_HPO,
0587         RT286_SET_PIN_SFT, 0, NULL, 0),
0588 
0589     /* Output Mixer */
0590     SND_SOC_DAPM_MIXER("Front", RT286_SET_POWER(RT286_DAC_OUT1), 0, 1,
0591             rt286_front_mix, ARRAY_SIZE(rt286_front_mix)),
0592     SND_SOC_DAPM_PGA("Surround", RT286_SET_POWER(RT286_DAC_OUT2), 0, 1,
0593             NULL, 0),
0594 
0595     /* Output Pga */
0596     SND_SOC_DAPM_SWITCH_E("SPO", SND_SOC_NOPM, 0, 0,
0597         &spo_enable_control, rt286_spk_event,
0598         SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
0599     SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0,
0600         &hpol_enable_control),
0601     SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0,
0602         &hpor_enable_control),
0603 
0604     /* Output Lines */
0605     SND_SOC_DAPM_OUTPUT("SPOL"),
0606     SND_SOC_DAPM_OUTPUT("SPOR"),
0607     SND_SOC_DAPM_OUTPUT("HPO Pin"),
0608     SND_SOC_DAPM_OUTPUT("SPDIF"),
0609 };
0610 
0611 static const struct snd_soc_dapm_route rt286_dapm_routes[] = {
0612     {"ADC 0", NULL, "MCLK MODE", is_mclk_mode},
0613     {"ADC 1", NULL, "MCLK MODE", is_mclk_mode},
0614     {"Front", NULL, "MCLK MODE", is_mclk_mode},
0615     {"Surround", NULL, "MCLK MODE", is_mclk_mode},
0616 
0617     {"HP Power", NULL, "LDO1"},
0618     {"HP Power", NULL, "LDO2"},
0619 
0620     {"MIC1", NULL, "LDO1"},
0621     {"MIC1", NULL, "LDO2"},
0622     {"MIC1", NULL, "HV"},
0623     {"MIC1", NULL, "VREF"},
0624     {"MIC1", NULL, "MIC1 Input Buffer"},
0625 
0626     {"SPO", NULL, "LDO1"},
0627     {"SPO", NULL, "LDO2"},
0628     {"SPO", NULL, "HV"},
0629     {"SPO", NULL, "VREF"},
0630 
0631     {"DMIC1", NULL, "DMIC1 Pin"},
0632     {"DMIC2", NULL, "DMIC2 Pin"},
0633     {"DMIC1", NULL, "DMIC Receiver"},
0634     {"DMIC2", NULL, "DMIC Receiver"},
0635 
0636     {"RECMIX", "Beep Switch", "Beep"},
0637     {"RECMIX", "Line1 Switch", "LINE1"},
0638     {"RECMIX", "Mic1 Switch", "MIC1"},
0639 
0640     {"ADC 0 Mux", "Dmic", "DMIC1"},
0641     {"ADC 0 Mux", "RECMIX", "RECMIX"},
0642     {"ADC 0 Mux", "Mic", "MIC1"},
0643     {"ADC 1 Mux", "Dmic", "DMIC2"},
0644     {"ADC 1 Mux", "RECMIX", "RECMIX"},
0645     {"ADC 1 Mux", "Mic", "MIC1"},
0646 
0647     {"ADC 0", NULL, "ADC 0 Mux"},
0648     {"ADC 1", NULL, "ADC 1 Mux"},
0649 
0650     {"AIF1TX", NULL, "ADC 0"},
0651     {"AIF2TX", NULL, "ADC 1"},
0652 
0653     {"DAC 0", NULL, "AIF1RX"},
0654     {"DAC 1", NULL, "AIF2RX"},
0655 
0656     {"Front", "DAC Switch", "DAC 0"},
0657     {"Front", "RECMIX Switch", "RECMIX"},
0658 
0659     {"Surround", NULL, "DAC 1"},
0660 
0661     {"SPK Mux", "Front", "Front"},
0662     {"SPK Mux", "Surround", "Surround"},
0663 
0664     {"HPO Mux", "Front", "Front"},
0665     {"HPO Mux", "Surround", "Surround"},
0666 
0667     {"SPO", "Switch", "SPK Mux"},
0668     {"HPO L", "Switch", "HPO Mux"},
0669     {"HPO R", "Switch", "HPO Mux"},
0670     {"HPO L", NULL, "HP Power"},
0671     {"HPO R", NULL, "HP Power"},
0672 
0673     {"SPOL", NULL, "SPO"},
0674     {"SPOR", NULL, "SPO"},
0675     {"HPO Pin", NULL, "HPO L"},
0676     {"HPO Pin", NULL, "HPO R"},
0677 };
0678 
0679 static int rt286_hw_params(struct snd_pcm_substream *substream,
0680                 struct snd_pcm_hw_params *params,
0681                 struct snd_soc_dai *dai)
0682 {
0683     struct snd_soc_component *component = dai->component;
0684     struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
0685     unsigned int val = 0;
0686     int d_len_code;
0687 
0688     switch (params_rate(params)) {
0689     /* bit 14 0:48K 1:44.1K */
0690     case 44100:
0691         val |= 0x4000;
0692         break;
0693     case 48000:
0694         break;
0695     default:
0696         dev_err(component->dev, "Unsupported sample rate %d\n",
0697                     params_rate(params));
0698         return -EINVAL;
0699     }
0700     switch (rt286->sys_clk) {
0701     case 12288000:
0702     case 24576000:
0703         if (params_rate(params) != 48000) {
0704             dev_err(component->dev, "Sys_clk is not matched (%d %d)\n",
0705                     params_rate(params), rt286->sys_clk);
0706             return -EINVAL;
0707         }
0708         break;
0709     case 11289600:
0710     case 22579200:
0711         if (params_rate(params) != 44100) {
0712             dev_err(component->dev, "Sys_clk is not matched (%d %d)\n",
0713                     params_rate(params), rt286->sys_clk);
0714             return -EINVAL;
0715         }
0716         break;
0717     }
0718 
0719     if (params_channels(params) <= 16) {
0720         /* bit 3:0 Number of Channel */
0721         val |= (params_channels(params) - 1);
0722     } else {
0723         dev_err(component->dev, "Unsupported channels %d\n",
0724                     params_channels(params));
0725         return -EINVAL;
0726     }
0727 
0728     switch (params_width(params)) {
0729     /* bit 6:4 Bits per Sample */
0730     case 16:
0731         d_len_code = 0;
0732         val |= (0x1 << 4);
0733         break;
0734     case 32:
0735         d_len_code = 2;
0736         val |= (0x4 << 4);
0737         break;
0738     case 20:
0739         d_len_code = 1;
0740         val |= (0x2 << 4);
0741         break;
0742     case 24:
0743         d_len_code = 2;
0744         val |= (0x3 << 4);
0745         break;
0746     case 8:
0747         d_len_code = 3;
0748         break;
0749     default:
0750         return -EINVAL;
0751     }
0752 
0753     snd_soc_component_update_bits(component,
0754         RT286_I2S_CTRL1, 0x0018, d_len_code << 3);
0755     dev_dbg(component->dev, "format val = 0x%x\n", val);
0756 
0757     snd_soc_component_update_bits(component, RT286_DAC_FORMAT, 0x407f, val);
0758     snd_soc_component_update_bits(component, RT286_ADC_FORMAT, 0x407f, val);
0759 
0760     return 0;
0761 }
0762 
0763 static int rt286_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
0764 {
0765     struct snd_soc_component *component = dai->component;
0766 
0767     switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
0768     case SND_SOC_DAIFMT_CBM_CFM:
0769         snd_soc_component_update_bits(component,
0770             RT286_I2S_CTRL1, 0x800, 0x800);
0771         break;
0772     case SND_SOC_DAIFMT_CBS_CFS:
0773         snd_soc_component_update_bits(component,
0774             RT286_I2S_CTRL1, 0x800, 0x0);
0775         break;
0776     default:
0777         return -EINVAL;
0778     }
0779 
0780     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0781     case SND_SOC_DAIFMT_I2S:
0782         snd_soc_component_update_bits(component,
0783             RT286_I2S_CTRL1, 0x300, 0x0);
0784         break;
0785     case SND_SOC_DAIFMT_LEFT_J:
0786         snd_soc_component_update_bits(component,
0787             RT286_I2S_CTRL1, 0x300, 0x1 << 8);
0788         break;
0789     case SND_SOC_DAIFMT_DSP_A:
0790         snd_soc_component_update_bits(component,
0791             RT286_I2S_CTRL1, 0x300, 0x2 << 8);
0792         break;
0793     case SND_SOC_DAIFMT_DSP_B:
0794         snd_soc_component_update_bits(component,
0795             RT286_I2S_CTRL1, 0x300, 0x3 << 8);
0796         break;
0797     default:
0798         return -EINVAL;
0799     }
0800     /* bit 15 Stream Type 0:PCM 1:Non-PCM */
0801     snd_soc_component_update_bits(component, RT286_DAC_FORMAT, 0x8000, 0);
0802     snd_soc_component_update_bits(component, RT286_ADC_FORMAT, 0x8000, 0);
0803 
0804     return 0;
0805 }
0806 
0807 static int rt286_set_dai_sysclk(struct snd_soc_dai *dai,
0808                 int clk_id, unsigned int freq, int dir)
0809 {
0810     struct snd_soc_component *component = dai->component;
0811     struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
0812 
0813     dev_dbg(component->dev, "%s freq=%d\n", __func__, freq);
0814 
0815     if (RT286_SCLK_S_MCLK == clk_id) {
0816         snd_soc_component_update_bits(component,
0817             RT286_I2S_CTRL2, 0x0100, 0x0);
0818         snd_soc_component_update_bits(component,
0819             RT286_PLL_CTRL1, 0x20, 0x20);
0820     } else {
0821         snd_soc_component_update_bits(component,
0822             RT286_I2S_CTRL2, 0x0100, 0x0100);
0823         snd_soc_component_update_bits(component,
0824             RT286_PLL_CTRL, 0x4, 0x4);
0825         snd_soc_component_update_bits(component,
0826             RT286_PLL_CTRL1, 0x20, 0x0);
0827     }
0828 
0829     switch (freq) {
0830     case 19200000:
0831         if (RT286_SCLK_S_MCLK == clk_id) {
0832             dev_err(component->dev, "Should not use MCLK\n");
0833             return -EINVAL;
0834         }
0835         snd_soc_component_update_bits(component,
0836             RT286_I2S_CTRL2, 0x40, 0x40);
0837         break;
0838     case 24000000:
0839         if (RT286_SCLK_S_MCLK == clk_id) {
0840             dev_err(component->dev, "Should not use MCLK\n");
0841             return -EINVAL;
0842         }
0843         snd_soc_component_update_bits(component,
0844             RT286_I2S_CTRL2, 0x40, 0x0);
0845         break;
0846     case 12288000:
0847     case 11289600:
0848         snd_soc_component_update_bits(component,
0849             RT286_I2S_CTRL2, 0x8, 0x0);
0850         snd_soc_component_update_bits(component,
0851             RT286_CLK_DIV, 0xfc1e, 0x0004);
0852         break;
0853     case 24576000:
0854     case 22579200:
0855         snd_soc_component_update_bits(component,
0856             RT286_I2S_CTRL2, 0x8, 0x8);
0857         snd_soc_component_update_bits(component,
0858             RT286_CLK_DIV, 0xfc1e, 0x5406);
0859         break;
0860     default:
0861         dev_err(component->dev, "Unsupported system clock\n");
0862         return -EINVAL;
0863     }
0864 
0865     rt286->sys_clk = freq;
0866     rt286->clk_id = clk_id;
0867 
0868     return 0;
0869 }
0870 
0871 static int rt286_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
0872 {
0873     struct snd_soc_component *component = dai->component;
0874 
0875     dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio);
0876     if (50 == ratio)
0877         snd_soc_component_update_bits(component,
0878             RT286_I2S_CTRL1, 0x1000, 0x1000);
0879     else
0880         snd_soc_component_update_bits(component,
0881             RT286_I2S_CTRL1, 0x1000, 0x0);
0882 
0883 
0884     return 0;
0885 }
0886 
0887 static int rt286_set_bias_level(struct snd_soc_component *component,
0888                  enum snd_soc_bias_level level)
0889 {
0890     switch (level) {
0891     case SND_SOC_BIAS_PREPARE:
0892         if (SND_SOC_BIAS_STANDBY == snd_soc_component_get_bias_level(component)) {
0893             snd_soc_component_write(component,
0894                 RT286_SET_AUDIO_POWER, AC_PWRST_D0);
0895             snd_soc_component_update_bits(component,
0896                 RT286_DC_GAIN, 0x200, 0x200);
0897         }
0898         break;
0899 
0900     case SND_SOC_BIAS_ON:
0901         mdelay(10);
0902         snd_soc_component_update_bits(component,
0903             RT286_DC_GAIN, 0x200, 0x0);
0904 
0905         break;
0906 
0907     case SND_SOC_BIAS_STANDBY:
0908         snd_soc_component_write(component,
0909             RT286_SET_AUDIO_POWER, AC_PWRST_D3);
0910         break;
0911 
0912     default:
0913         break;
0914     }
0915 
0916     return 0;
0917 }
0918 
0919 static irqreturn_t rt286_irq(int irq, void *data)
0920 {
0921     struct rt286_priv *rt286 = data;
0922     bool hp = false;
0923     bool mic = false;
0924     int status = 0;
0925 
0926     rt286_jack_detect(rt286, &hp, &mic);
0927 
0928     /* Clear IRQ */
0929     regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x1, 0x1);
0930 
0931     if (hp)
0932         status |= SND_JACK_HEADPHONE;
0933 
0934     if (mic)
0935         status |= SND_JACK_MICROPHONE;
0936 
0937     snd_soc_jack_report(rt286->jack, status,
0938         SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
0939 
0940     pm_wakeup_event(&rt286->i2c->dev, 300);
0941 
0942     return IRQ_HANDLED;
0943 }
0944 
0945 static int rt286_probe(struct snd_soc_component *component)
0946 {
0947     struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
0948 
0949     rt286->component = component;
0950     INIT_DELAYED_WORK(&rt286->jack_detect_work, rt286_jack_detect_work);
0951 
0952     if (rt286->i2c->irq)
0953         schedule_delayed_work(&rt286->jack_detect_work,
0954                       msecs_to_jiffies(50));
0955     return 0;
0956 }
0957 
0958 static void rt286_remove(struct snd_soc_component *component)
0959 {
0960     struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
0961 
0962     cancel_delayed_work_sync(&rt286->jack_detect_work);
0963     rt286->component = NULL;
0964 }
0965 
0966 #ifdef CONFIG_PM
0967 static int rt286_suspend(struct snd_soc_component *component)
0968 {
0969     struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
0970 
0971     regcache_cache_only(rt286->regmap, true);
0972     regcache_mark_dirty(rt286->regmap);
0973 
0974     return 0;
0975 }
0976 
0977 static int rt286_resume(struct snd_soc_component *component)
0978 {
0979     struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
0980 
0981     regcache_cache_only(rt286->regmap, false);
0982     rt286_index_sync(component);
0983     regcache_sync(rt286->regmap);
0984 
0985     return 0;
0986 }
0987 #else
0988 #define rt286_suspend NULL
0989 #define rt286_resume NULL
0990 #endif
0991 
0992 #define RT286_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
0993 #define RT286_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
0994             SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
0995 
0996 static const struct snd_soc_dai_ops rt286_aif_dai_ops = {
0997     .hw_params = rt286_hw_params,
0998     .set_fmt = rt286_set_dai_fmt,
0999     .set_sysclk = rt286_set_dai_sysclk,
1000     .set_bclk_ratio = rt286_set_bclk_ratio,
1001 };
1002 
1003 static struct snd_soc_dai_driver rt286_dai[] = {
1004     {
1005         .name = "rt286-aif1",
1006         .id = RT286_AIF1,
1007         .playback = {
1008             .stream_name = "AIF1 Playback",
1009             .channels_min = 1,
1010             .channels_max = 2,
1011             .rates = RT286_STEREO_RATES,
1012             .formats = RT286_FORMATS,
1013         },
1014         .capture = {
1015             .stream_name = "AIF1 Capture",
1016             .channels_min = 1,
1017             .channels_max = 2,
1018             .rates = RT286_STEREO_RATES,
1019             .formats = RT286_FORMATS,
1020         },
1021         .ops = &rt286_aif_dai_ops,
1022         .symmetric_rate = 1,
1023     },
1024     {
1025         .name = "rt286-aif2",
1026         .id = RT286_AIF2,
1027         .playback = {
1028             .stream_name = "AIF2 Playback",
1029             .channels_min = 1,
1030             .channels_max = 2,
1031             .rates = RT286_STEREO_RATES,
1032             .formats = RT286_FORMATS,
1033         },
1034         .capture = {
1035             .stream_name = "AIF2 Capture",
1036             .channels_min = 1,
1037             .channels_max = 2,
1038             .rates = RT286_STEREO_RATES,
1039             .formats = RT286_FORMATS,
1040         },
1041         .ops = &rt286_aif_dai_ops,
1042         .symmetric_rate = 1,
1043     },
1044 
1045 };
1046 
1047 static const struct snd_soc_component_driver soc_component_dev_rt286 = {
1048     .probe          = rt286_probe,
1049     .remove         = rt286_remove,
1050     .suspend        = rt286_suspend,
1051     .resume         = rt286_resume,
1052     .set_bias_level     = rt286_set_bias_level,
1053     .set_jack       = rt286_mic_detect,
1054     .controls       = rt286_snd_controls,
1055     .num_controls       = ARRAY_SIZE(rt286_snd_controls),
1056     .dapm_widgets       = rt286_dapm_widgets,
1057     .num_dapm_widgets   = ARRAY_SIZE(rt286_dapm_widgets),
1058     .dapm_routes        = rt286_dapm_routes,
1059     .num_dapm_routes    = ARRAY_SIZE(rt286_dapm_routes),
1060     .use_pmdown_time    = 1,
1061     .endianness     = 1,
1062 };
1063 
1064 static const struct regmap_config rt286_regmap = {
1065     .reg_bits = 32,
1066     .val_bits = 32,
1067     .max_register = 0x02370100,
1068     .volatile_reg = rt286_volatile_register,
1069     .readable_reg = rt286_readable_register,
1070     .reg_write = rl6347a_hw_write,
1071     .reg_read = rl6347a_hw_read,
1072     .cache_type = REGCACHE_RBTREE,
1073     .reg_defaults = rt286_reg,
1074     .num_reg_defaults = ARRAY_SIZE(rt286_reg),
1075 };
1076 
1077 static const struct i2c_device_id rt286_i2c_id[] = {
1078     {"rt286", 0},
1079     {"rt288", 0},
1080     {}
1081 };
1082 MODULE_DEVICE_TABLE(i2c, rt286_i2c_id);
1083 
1084 #ifdef CONFIG_ACPI
1085 static const struct acpi_device_id rt286_acpi_match[] = {
1086     { "INT343A", 0 },
1087     {},
1088 };
1089 MODULE_DEVICE_TABLE(acpi, rt286_acpi_match);
1090 #endif
1091 
1092 static const struct dmi_system_id force_combo_jack_table[] = {
1093     {
1094         .ident = "Intel Wilson Beach",
1095         .matches = {
1096             DMI_MATCH(DMI_BOARD_NAME, "Wilson Beach SDS")
1097         }
1098     },
1099     {
1100         .ident = "Intel Skylake RVP",
1101         .matches = {
1102             DMI_MATCH(DMI_PRODUCT_NAME, "Skylake Client platform")
1103         }
1104     },
1105     {
1106         .ident = "Intel Kabylake RVP",
1107         .matches = {
1108             DMI_MATCH(DMI_PRODUCT_NAME, "Kabylake Client platform")
1109         }
1110     },
1111     {
1112         .ident = "Thinkpad Helix 2nd",
1113         .matches = {
1114             DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1115             DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad Helix 2nd")
1116         }
1117     },
1118 
1119     { }
1120 };
1121 
1122 static const struct dmi_system_id dmi_dell[] = {
1123     {
1124         .ident = "Dell",
1125         .matches = {
1126             DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1127         }
1128     },
1129     { }
1130 };
1131 
1132 static int rt286_i2c_probe(struct i2c_client *i2c)
1133 {
1134     struct rt286_platform_data *pdata = dev_get_platdata(&i2c->dev);
1135     struct rt286_priv *rt286;
1136     int i, ret, vendor_id;
1137 
1138     rt286 = devm_kzalloc(&i2c->dev, sizeof(*rt286),
1139                 GFP_KERNEL);
1140     if (NULL == rt286)
1141         return -ENOMEM;
1142 
1143     rt286->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt286_regmap);
1144     if (IS_ERR(rt286->regmap)) {
1145         ret = PTR_ERR(rt286->regmap);
1146         dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1147             ret);
1148         return ret;
1149     }
1150 
1151     ret = regmap_read(rt286->regmap,
1152         RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &vendor_id);
1153     if (ret != 0) {
1154         dev_err(&i2c->dev, "I2C error %d\n", ret);
1155         return ret;
1156     }
1157     if (vendor_id != RT286_VENDOR_ID && vendor_id != RT288_VENDOR_ID) {
1158         dev_err(&i2c->dev,
1159             "Device with ID register %#x is not rt286\n",
1160             vendor_id);
1161         return -ENODEV;
1162     }
1163 
1164     rt286->index_cache = devm_kmemdup(&i2c->dev, rt286_index_def,
1165                       sizeof(rt286_index_def), GFP_KERNEL);
1166     if (!rt286->index_cache)
1167         return -ENOMEM;
1168 
1169     rt286->index_cache_size = INDEX_CACHE_SIZE;
1170     rt286->i2c = i2c;
1171     i2c_set_clientdata(i2c, rt286);
1172 
1173     /* restore codec default */
1174     for (i = 0; i < INDEX_CACHE_SIZE; i++)
1175         regmap_write(rt286->regmap, rt286->index_cache[i].reg,
1176                 rt286->index_cache[i].def);
1177     for (i = 0; i < ARRAY_SIZE(rt286_reg); i++)
1178         regmap_write(rt286->regmap, rt286_reg[i].reg,
1179                 rt286_reg[i].def);
1180 
1181     if (pdata)
1182         rt286->pdata = *pdata;
1183 
1184     if ((vendor_id == RT288_VENDOR_ID && dmi_check_system(dmi_dell)) ||
1185         dmi_check_system(force_combo_jack_table))
1186         rt286->pdata.cbj_en = true;
1187 
1188     regmap_write(rt286->regmap, RT286_SET_AUDIO_POWER, AC_PWRST_D3);
1189 
1190     for (i = 0; i < RT286_POWER_REG_LEN; i++)
1191         regmap_write(rt286->regmap,
1192             RT286_SET_POWER(rt286_support_power_controls[i]),
1193             AC_PWRST_D1);
1194 
1195     if (!rt286->pdata.cbj_en) {
1196         regmap_write(rt286->regmap, RT286_CBJ_CTRL2, 0x0000);
1197         regmap_write(rt286->regmap, RT286_MIC1_DET_CTRL, 0x0816);
1198         regmap_update_bits(rt286->regmap,
1199                     RT286_CBJ_CTRL1, 0xf000, 0xb000);
1200     } else {
1201         regmap_update_bits(rt286->regmap,
1202                     RT286_CBJ_CTRL1, 0xf000, 0x5000);
1203     }
1204 
1205     mdelay(10);
1206 
1207     if (!rt286->pdata.gpio2_en)
1208         regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0x40);
1209     else
1210         regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0);
1211 
1212     mdelay(10);
1213 
1214     regmap_write(rt286->regmap, RT286_MISC_CTRL1, 0x0000);
1215     /* Power down LDO, VREF */
1216     regmap_update_bits(rt286->regmap, RT286_POWER_CTRL2, 0xc, 0x0);
1217     regmap_update_bits(rt286->regmap, RT286_POWER_CTRL1, 0x1001, 0x1001);
1218 
1219     /* Set depop parameter */
1220     regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL2, 0x403a, 0x401a);
1221     regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL3, 0xf777, 0x4737);
1222     regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL4, 0x00ff, 0x003f);
1223 
1224     if (vendor_id == RT288_VENDOR_ID && dmi_check_system(dmi_dell)) {
1225         regmap_update_bits(rt286->regmap,
1226             RT286_SET_GPIO_MASK, 0x40, 0x40);
1227         regmap_update_bits(rt286->regmap,
1228             RT286_SET_GPIO_DIRECTION, 0x40, 0x40);
1229         regmap_update_bits(rt286->regmap,
1230             RT286_SET_GPIO_DATA, 0x40, 0x40);
1231         regmap_update_bits(rt286->regmap,
1232             RT286_GPIO_CTRL, 0xc, 0x8);
1233     }
1234 
1235     if (rt286->i2c->irq) {
1236         ret = request_threaded_irq(rt286->i2c->irq, NULL, rt286_irq,
1237             IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt286", rt286);
1238         if (ret != 0) {
1239             dev_err(&i2c->dev,
1240                 "Failed to reguest IRQ: %d\n", ret);
1241             return ret;
1242         }
1243     }
1244 
1245     ret = devm_snd_soc_register_component(&i2c->dev,
1246                      &soc_component_dev_rt286,
1247                      rt286_dai, ARRAY_SIZE(rt286_dai));
1248 
1249     return ret;
1250 }
1251 
1252 static int rt286_i2c_remove(struct i2c_client *i2c)
1253 {
1254     struct rt286_priv *rt286 = i2c_get_clientdata(i2c);
1255 
1256     if (i2c->irq)
1257         free_irq(i2c->irq, rt286);
1258 
1259     return 0;
1260 }
1261 
1262 
1263 static struct i2c_driver rt286_i2c_driver = {
1264     .driver = {
1265            .name = "rt286",
1266            .acpi_match_table = ACPI_PTR(rt286_acpi_match),
1267            },
1268     .probe_new = rt286_i2c_probe,
1269     .remove = rt286_i2c_remove,
1270     .id_table = rt286_i2c_id,
1271 };
1272 
1273 module_i2c_driver(rt286_i2c_driver);
1274 
1275 MODULE_DESCRIPTION("ASoC RT286 driver");
1276 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
1277 MODULE_LICENSE("GPL");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!