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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * rt274.c  --  RT274 ALSA SoC audio codec driver
0004  *
0005  * Copyright 2017 Realtek Semiconductor Corp.
0006  * Author: Bard Liao <bardliao@realtek.com>
0007  */
0008 
0009 #include <linux/module.h>
0010 #include <linux/moduleparam.h>
0011 #include <linux/init.h>
0012 #include <linux/delay.h>
0013 #include <linux/pm.h>
0014 #include <linux/i2c.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/spi/spi.h>
0017 #include <linux/dmi.h>
0018 #include <linux/acpi.h>
0019 #include <sound/core.h>
0020 #include <sound/pcm.h>
0021 #include <sound/pcm_params.h>
0022 #include <sound/soc.h>
0023 #include <sound/soc-dapm.h>
0024 #include <sound/initval.h>
0025 #include <sound/tlv.h>
0026 #include <sound/jack.h>
0027 #include <linux/workqueue.h>
0028 
0029 #include "rl6347a.h"
0030 #include "rt274.h"
0031 
0032 #define RT274_VENDOR_ID 0x10ec0274
0033 
0034 struct rt274_priv {
0035     struct reg_default *index_cache;
0036     int index_cache_size;
0037     struct regmap *regmap;
0038     struct snd_soc_component *component;
0039     struct i2c_client *i2c;
0040     struct snd_soc_jack *jack;
0041     struct delayed_work jack_detect_work;
0042     int sys_clk;
0043     int clk_id;
0044     int fs;
0045     bool master;
0046 };
0047 
0048 static const struct reg_default rt274_index_def[] = {
0049     { 0x00, 0x1004 },
0050     { 0x01, 0xaaaa },
0051     { 0x02, 0x88aa },
0052     { 0x03, 0x0002 },
0053     { 0x04, 0xaa09 },
0054     { 0x05, 0x0700 },
0055     { 0x06, 0x6110 },
0056     { 0x07, 0x0200 },
0057     { 0x08, 0xa807 },
0058     { 0x09, 0x0021 },
0059     { 0x0a, 0x7770 },
0060     { 0x0b, 0x7770 },
0061     { 0x0c, 0x002b },
0062     { 0x0d, 0x2420 },
0063     { 0x0e, 0x65c0 },
0064     { 0x0f, 0x7770 },
0065     { 0x10, 0x0420 },
0066     { 0x11, 0x7418 },
0067     { 0x12, 0x6bd0 },
0068     { 0x13, 0x645f },
0069     { 0x14, 0x0400 },
0070     { 0x15, 0x8ccc },
0071     { 0x16, 0x4c50 },
0072     { 0x17, 0xff00 },
0073     { 0x18, 0x0003 },
0074     { 0x19, 0x2c11 },
0075     { 0x1a, 0x830b },
0076     { 0x1b, 0x4e4b },
0077     { 0x1c, 0x0000 },
0078     { 0x1d, 0x0000 },
0079     { 0x1e, 0x0000 },
0080     { 0x1f, 0x0000 },
0081     { 0x20, 0x51ff },
0082     { 0x21, 0x8000 },
0083     { 0x22, 0x8f00 },
0084     { 0x23, 0x88f4 },
0085     { 0x24, 0x0000 },
0086     { 0x25, 0x0000 },
0087     { 0x26, 0x0000 },
0088     { 0x27, 0x0000 },
0089     { 0x28, 0x0000 },
0090     { 0x29, 0x3000 },
0091     { 0x2a, 0x0000 },
0092     { 0x2b, 0x0000 },
0093     { 0x2c, 0x0f00 },
0094     { 0x2d, 0x100f },
0095     { 0x2e, 0x2902 },
0096     { 0x2f, 0xe280 },
0097     { 0x30, 0x1000 },
0098     { 0x31, 0x8400 },
0099     { 0x32, 0x5aaa },
0100     { 0x33, 0x8420 },
0101     { 0x34, 0xa20c },
0102     { 0x35, 0x096a },
0103     { 0x36, 0x5757 },
0104     { 0x37, 0xfe05 },
0105     { 0x38, 0x4901 },
0106     { 0x39, 0x110a },
0107     { 0x3a, 0x0010 },
0108     { 0x3b, 0x60d9 },
0109     { 0x3c, 0xf214 },
0110     { 0x3d, 0xc2ba },
0111     { 0x3e, 0xa928 },
0112     { 0x3f, 0x0000 },
0113     { 0x40, 0x9800 },
0114     { 0x41, 0x0000 },
0115     { 0x42, 0x2000 },
0116     { 0x43, 0x3d90 },
0117     { 0x44, 0x4900 },
0118     { 0x45, 0x5289 },
0119     { 0x46, 0x0004 },
0120     { 0x47, 0xa47a },
0121     { 0x48, 0xd049 },
0122     { 0x49, 0x0049 },
0123     { 0x4a, 0xa83b },
0124     { 0x4b, 0x0777 },
0125     { 0x4c, 0x065c },
0126     { 0x4d, 0x7fff },
0127     { 0x4e, 0x7fff },
0128     { 0x4f, 0x0000 },
0129     { 0x50, 0x0000 },
0130     { 0x51, 0x0000 },
0131     { 0x52, 0xbf5f },
0132     { 0x53, 0x3320 },
0133     { 0x54, 0xcc00 },
0134     { 0x55, 0x0000 },
0135     { 0x56, 0x3f00 },
0136     { 0x57, 0x0000 },
0137     { 0x58, 0x0000 },
0138     { 0x59, 0x0000 },
0139     { 0x5a, 0x1300 },
0140     { 0x5b, 0x005f },
0141     { 0x5c, 0x0000 },
0142     { 0x5d, 0x1001 },
0143     { 0x5e, 0x1000 },
0144     { 0x5f, 0x0000 },
0145     { 0x60, 0x5554 },
0146     { 0x61, 0xffc0 },
0147     { 0x62, 0xa000 },
0148     { 0x63, 0xd010 },
0149     { 0x64, 0x0000 },
0150     { 0x65, 0x3fb1 },
0151     { 0x66, 0x1881 },
0152     { 0x67, 0xc810 },
0153     { 0x68, 0x2000 },
0154     { 0x69, 0xfff0 },
0155     { 0x6a, 0x0300 },
0156     { 0x6b, 0x5060 },
0157     { 0x6c, 0x0000 },
0158     { 0x6d, 0x0000 },
0159     { 0x6e, 0x0c25 },
0160     { 0x6f, 0x0c0b },
0161     { 0x70, 0x8000 },
0162     { 0x71, 0x4008 },
0163     { 0x72, 0x0000 },
0164     { 0x73, 0x0800 },
0165     { 0x74, 0xa28f },
0166     { 0x75, 0xa050 },
0167     { 0x76, 0x7fe8 },
0168     { 0x77, 0xdb8c },
0169     { 0x78, 0x0000 },
0170     { 0x79, 0x0000 },
0171     { 0x7a, 0x2a96 },
0172     { 0x7b, 0x800f },
0173     { 0x7c, 0x0200 },
0174     { 0x7d, 0x1600 },
0175     { 0x7e, 0x0000 },
0176     { 0x7f, 0x0000 },
0177 };
0178 #define INDEX_CACHE_SIZE ARRAY_SIZE(rt274_index_def)
0179 
0180 static const struct reg_default rt274_reg[] = {
0181     { 0x00170500, 0x00000400 },
0182     { 0x00220000, 0x00000031 },
0183     { 0x00239000, 0x00000057 },
0184     { 0x0023a000, 0x00000057 },
0185     { 0x00270500, 0x00000400 },
0186     { 0x00370500, 0x00000400 },
0187     { 0x00870500, 0x00000400 },
0188     { 0x00920000, 0x00000031 },
0189     { 0x00935000, 0x00000097 },
0190     { 0x00936000, 0x00000097 },
0191     { 0x00970500, 0x00000400 },
0192     { 0x00b37000, 0x00000400 },
0193     { 0x00b37200, 0x00000400 },
0194     { 0x00b37300, 0x00000400 },
0195     { 0x00c37000, 0x00000400 },
0196     { 0x00c37100, 0x00000400 },
0197     { 0x01270500, 0x00000400 },
0198     { 0x01370500, 0x00000400 },
0199     { 0x01371f00, 0x411111f0 },
0200     { 0x01937000, 0x00000000 },
0201     { 0x01970500, 0x00000400 },
0202     { 0x02050000, 0x0000001b },
0203     { 0x02139000, 0x00000080 },
0204     { 0x0213a000, 0x00000080 },
0205     { 0x02170100, 0x00000001 },
0206     { 0x02170500, 0x00000400 },
0207     { 0x02170700, 0x00000000 },
0208     { 0x02270100, 0x00000000 },
0209     { 0x02370100, 0x00000000 },
0210     { 0x01970700, 0x00000020 },
0211     { 0x00830000, 0x00000097 },
0212     { 0x00930000, 0x00000097 },
0213     { 0x01270700, 0x00000000 },
0214 };
0215 
0216 static bool rt274_volatile_register(struct device *dev, unsigned int reg)
0217 {
0218     switch (reg) {
0219     case 0 ... 0xff:
0220     case RT274_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
0221     case RT274_GET_HP_SENSE:
0222     case RT274_GET_MIC_SENSE:
0223     case RT274_PROC_COEF:
0224     case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT274_MIC, 0):
0225     case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT274_HP_OUT, 0):
0226     case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_DAC_OUT0, 0):
0227     case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_DAC_OUT1, 0):
0228     case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_ADC_IN1, 0):
0229     case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_ADC_IN2, 0):
0230     case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DAC_OUT0, 0):
0231     case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DAC_OUT1, 0):
0232     case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_ADC_IN1, 0):
0233     case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_ADC_IN2, 0):
0234     case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DMIC1, 0):
0235     case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DMIC2, 0):
0236     case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_MIC, 0):
0237     case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_LINE1, 0):
0238     case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_LINE2, 0):
0239     case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_HP_OUT, 0):
0240     case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_HP_OUT, 0):
0241     case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_MIXER_IN1, 0):
0242     case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_MIXER_IN2, 0):
0243     case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_DMIC1, 0):
0244     case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_DMIC2, 0):
0245     case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_MIC, 0):
0246     case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_LINE1, 0):
0247     case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_LINE2, 0):
0248     case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_HP_OUT, 0):
0249     case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_HP_OUT, 0):
0250     case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_MIC, 0):
0251     case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_INLINE_CMD, 0):
0252         return true;
0253     default:
0254         return false;
0255     }
0256 
0257 
0258 }
0259 
0260 static bool rt274_readable_register(struct device *dev, unsigned int reg)
0261 {
0262     switch (reg) {
0263     case 0 ... 0xff:
0264     case RT274_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
0265     case RT274_GET_HP_SENSE:
0266     case RT274_GET_MIC_SENSE:
0267     case RT274_SET_AUDIO_POWER:
0268     case RT274_SET_HPO_POWER:
0269     case RT274_SET_DMIC1_POWER:
0270     case RT274_LOUT_MUX:
0271     case RT274_HPO_MUX:
0272     case RT274_ADC0_MUX:
0273     case RT274_ADC1_MUX:
0274     case RT274_SET_MIC:
0275     case RT274_SET_PIN_HPO:
0276     case RT274_SET_PIN_LOUT3:
0277     case RT274_SET_PIN_DMIC1:
0278     case RT274_SET_AMP_GAIN_HPO:
0279     case RT274_SET_DMIC2_DEFAULT:
0280     case RT274_DAC0L_GAIN:
0281     case RT274_DAC0R_GAIN:
0282     case RT274_DAC1L_GAIN:
0283     case RT274_DAC1R_GAIN:
0284     case RT274_ADCL_GAIN:
0285     case RT274_ADCR_GAIN:
0286     case RT274_MIC_GAIN:
0287     case RT274_HPOL_GAIN:
0288     case RT274_HPOR_GAIN:
0289     case RT274_LOUTL_GAIN:
0290     case RT274_LOUTR_GAIN:
0291     case RT274_DAC_FORMAT:
0292     case RT274_ADC_FORMAT:
0293     case RT274_COEF_INDEX:
0294     case RT274_PROC_COEF:
0295     case RT274_SET_AMP_GAIN_ADC_IN1:
0296     case RT274_SET_AMP_GAIN_ADC_IN2:
0297     case RT274_SET_POWER(RT274_DAC_OUT0):
0298     case RT274_SET_POWER(RT274_DAC_OUT1):
0299     case RT274_SET_POWER(RT274_ADC_IN1):
0300     case RT274_SET_POWER(RT274_ADC_IN2):
0301     case RT274_SET_POWER(RT274_DMIC2):
0302     case RT274_SET_POWER(RT274_MIC):
0303     case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT274_MIC, 0):
0304     case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT274_HP_OUT, 0):
0305     case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_DAC_OUT0, 0):
0306     case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_DAC_OUT1, 0):
0307     case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_ADC_IN1, 0):
0308     case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_ADC_IN2, 0):
0309     case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DAC_OUT0, 0):
0310     case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DAC_OUT1, 0):
0311     case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_ADC_IN1, 0):
0312     case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_ADC_IN2, 0):
0313     case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DMIC1, 0):
0314     case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DMIC2, 0):
0315     case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_MIC, 0):
0316     case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_LINE1, 0):
0317     case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_LINE2, 0):
0318     case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_HP_OUT, 0):
0319     case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_HP_OUT, 0):
0320     case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_MIXER_IN1, 0):
0321     case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_MIXER_IN2, 0):
0322     case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_DMIC1, 0):
0323     case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_DMIC2, 0):
0324     case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_MIC, 0):
0325     case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_LINE1, 0):
0326     case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_LINE2, 0):
0327     case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_HP_OUT, 0):
0328     case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_HP_OUT, 0):
0329     case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_MIC, 0):
0330     case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_INLINE_CMD, 0):
0331         return true;
0332     default:
0333         return false;
0334     }
0335 }
0336 
0337 #ifdef CONFIG_PM
0338 static void rt274_index_sync(struct snd_soc_component *component)
0339 {
0340     struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
0341     int i;
0342 
0343     for (i = 0; i < INDEX_CACHE_SIZE; i++) {
0344         snd_soc_component_write(component, rt274->index_cache[i].reg,
0345                   rt274->index_cache[i].def);
0346     }
0347 }
0348 #endif
0349 
0350 static int rt274_jack_detect(struct rt274_priv *rt274, bool *hp, bool *mic)
0351 {
0352     unsigned int buf;
0353     int ret;
0354 
0355     *hp = false;
0356     *mic = false;
0357 
0358     if (!rt274->component)
0359         return -EINVAL;
0360 
0361     ret = regmap_read(rt274->regmap, RT274_GET_HP_SENSE, &buf);
0362     if (ret)
0363         return ret;
0364 
0365     *hp = buf & 0x80000000;
0366     ret = regmap_read(rt274->regmap, RT274_GET_MIC_SENSE, &buf);
0367     if (ret)
0368         return ret;
0369 
0370     *mic = buf & 0x80000000;
0371 
0372     pr_debug("*hp = %d *mic = %d\n", *hp, *mic);
0373 
0374     return 0;
0375 }
0376 
0377 static void rt274_jack_detect_work(struct work_struct *work)
0378 {
0379     struct rt274_priv *rt274 =
0380         container_of(work, struct rt274_priv, jack_detect_work.work);
0381     int status = 0;
0382     bool hp = false;
0383     bool mic = false;
0384 
0385     if (rt274_jack_detect(rt274, &hp, &mic) < 0)
0386         return;
0387 
0388     if (hp)
0389         status |= SND_JACK_HEADPHONE;
0390 
0391     if (mic)
0392         status |= SND_JACK_MICROPHONE;
0393 
0394     snd_soc_jack_report(rt274->jack, status,
0395         SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
0396 }
0397 
0398 static irqreturn_t rt274_irq(int irq, void *data);
0399 
0400 static int rt274_mic_detect(struct snd_soc_component *component,
0401     struct snd_soc_jack *jack,  void *data)
0402 {
0403     struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
0404 
0405     rt274->jack = jack;
0406 
0407     if (jack == NULL) {
0408         /* Disable jack detection */
0409         regmap_update_bits(rt274->regmap, RT274_EAPD_GPIO_IRQ_CTRL,
0410                     RT274_IRQ_EN, RT274_IRQ_DIS);
0411 
0412         return 0;
0413     }
0414 
0415     regmap_update_bits(rt274->regmap, RT274_EAPD_GPIO_IRQ_CTRL,
0416                 RT274_IRQ_EN, RT274_IRQ_EN);
0417 
0418     /* Send an initial report */
0419     rt274_irq(0, rt274);
0420 
0421     return 0;
0422 }
0423 
0424 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0);
0425 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
0426 
0427 static const struct snd_kcontrol_new rt274_snd_controls[] = {
0428     SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT274_DAC0L_GAIN,
0429              RT274_DAC0R_GAIN, 0, 0x7f, 0, out_vol_tlv),
0430     SOC_DOUBLE_R_TLV("DAC1 Playback Volume", RT274_DAC1L_GAIN,
0431              RT274_DAC1R_GAIN, 0, 0x7f, 0, out_vol_tlv),
0432     SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT274_ADCL_GAIN,
0433                 RT274_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv),
0434     SOC_DOUBLE_R("ADC0 Capture Switch", RT274_ADCL_GAIN,
0435                 RT274_ADCR_GAIN, RT274_MUTE_SFT, 1, 1),
0436     SOC_SINGLE_TLV("AMIC Volume", RT274_MIC_GAIN,
0437                 0, 0x3, 0, mic_vol_tlv),
0438 };
0439 
0440 static const struct snd_kcontrol_new hpol_enable_control =
0441     SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT274_HPOL_GAIN,
0442             RT274_MUTE_SFT, 1, 1);
0443 
0444 static const struct snd_kcontrol_new hpor_enable_control =
0445     SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT274_HPOR_GAIN,
0446             RT274_MUTE_SFT, 1, 1);
0447 
0448 static const struct snd_kcontrol_new loutl_enable_control =
0449     SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT274_LOUTL_GAIN,
0450             RT274_MUTE_SFT, 1, 1);
0451 
0452 static const struct snd_kcontrol_new loutr_enable_control =
0453     SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT274_LOUTR_GAIN,
0454             RT274_MUTE_SFT, 1, 1);
0455 
0456 /* ADC0 source */
0457 static const char * const rt274_adc_src[] = {
0458     "Mic", "Line1", "Line2", "Dmic"
0459 };
0460 
0461 static SOC_ENUM_SINGLE_DECL(
0462     rt274_adc0_enum, RT274_ADC0_MUX, RT274_ADC_SEL_SFT,
0463     rt274_adc_src);
0464 
0465 static const struct snd_kcontrol_new rt274_adc0_mux =
0466     SOC_DAPM_ENUM("ADC 0 source", rt274_adc0_enum);
0467 
0468 static SOC_ENUM_SINGLE_DECL(
0469     rt274_adc1_enum, RT274_ADC1_MUX, RT274_ADC_SEL_SFT,
0470     rt274_adc_src);
0471 
0472 static const struct snd_kcontrol_new rt274_adc1_mux =
0473     SOC_DAPM_ENUM("ADC 1 source", rt274_adc1_enum);
0474 
0475 static const char * const rt274_dac_src[] = {
0476     "DAC OUT0", "DAC OUT1"
0477 };
0478 /* HP-OUT source */
0479 static SOC_ENUM_SINGLE_DECL(rt274_hpo_enum, RT274_HPO_MUX,
0480                 0, rt274_dac_src);
0481 
0482 static const struct snd_kcontrol_new rt274_hpo_mux =
0483 SOC_DAPM_ENUM("HPO source", rt274_hpo_enum);
0484 
0485 /* Line out source */
0486 static SOC_ENUM_SINGLE_DECL(rt274_lout_enum, RT274_LOUT_MUX,
0487                 0, rt274_dac_src);
0488 
0489 static const struct snd_kcontrol_new rt274_lout_mux =
0490 SOC_DAPM_ENUM("LOUT source", rt274_lout_enum);
0491 
0492 static const struct snd_soc_dapm_widget rt274_dapm_widgets[] = {
0493     /* Input Lines */
0494     SND_SOC_DAPM_INPUT("DMIC1 Pin"),
0495     SND_SOC_DAPM_INPUT("DMIC2 Pin"),
0496     SND_SOC_DAPM_INPUT("MIC"),
0497     SND_SOC_DAPM_INPUT("LINE1"),
0498     SND_SOC_DAPM_INPUT("LINE2"),
0499 
0500     /* DMIC */
0501     SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
0502     SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
0503 
0504     /* ADCs */
0505     SND_SOC_DAPM_ADC("ADC 0", NULL, RT274_SET_STREAMID_ADC1, 4, 0),
0506     SND_SOC_DAPM_ADC("ADC 1", NULL, RT274_SET_STREAMID_ADC2, 4, 0),
0507 
0508     /* ADC Mux */
0509     SND_SOC_DAPM_MUX("ADC 0 Mux", SND_SOC_NOPM, 0, 0,
0510         &rt274_adc0_mux),
0511     SND_SOC_DAPM_MUX("ADC 1 Mux", SND_SOC_NOPM, 0, 0,
0512         &rt274_adc1_mux),
0513 
0514     /* Audio Interface */
0515     SND_SOC_DAPM_AIF_IN("AIF1RXL", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
0516     SND_SOC_DAPM_AIF_IN("AIF1RXR", "AIF1 Playback", 1, SND_SOC_NOPM, 0, 0),
0517     SND_SOC_DAPM_AIF_OUT("AIF1TXL", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
0518     SND_SOC_DAPM_AIF_OUT("AIF1TXR", "AIF1 Capture", 1, SND_SOC_NOPM, 0, 0),
0519     SND_SOC_DAPM_AIF_IN("AIF2RXL", "AIF1 Playback", 2, SND_SOC_NOPM, 0, 0),
0520     SND_SOC_DAPM_AIF_IN("AIF2RXR", "AIF1 Playback", 3, SND_SOC_NOPM, 0, 0),
0521     SND_SOC_DAPM_AIF_OUT("AIF2TXL", "AIF1 Capture", 2, SND_SOC_NOPM, 0, 0),
0522     SND_SOC_DAPM_AIF_OUT("AIF2TXR", "AIF1 Capture", 3, SND_SOC_NOPM, 0, 0),
0523 
0524     /* Output Side */
0525     /* DACs */
0526     SND_SOC_DAPM_DAC("DAC 0", NULL, RT274_SET_STREAMID_DAC0, 4, 0),
0527     SND_SOC_DAPM_DAC("DAC 1", NULL, RT274_SET_STREAMID_DAC1, 4, 0),
0528 
0529     /* Output Mux */
0530     SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt274_hpo_mux),
0531     SND_SOC_DAPM_MUX("LOUT Mux", SND_SOC_NOPM, 0, 0, &rt274_lout_mux),
0532 
0533     SND_SOC_DAPM_SUPPLY("HP Power", RT274_SET_PIN_HPO,
0534         RT274_SET_PIN_SFT, 0, NULL, 0),
0535     SND_SOC_DAPM_SUPPLY("LOUT Power", RT274_SET_PIN_LOUT3,
0536         RT274_SET_PIN_SFT, 0, NULL, 0),
0537 
0538     /* Output Mixer */
0539     SND_SOC_DAPM_PGA("DAC OUT0", SND_SOC_NOPM, 0, 0,
0540             NULL, 0),
0541     SND_SOC_DAPM_PGA("DAC OUT1", SND_SOC_NOPM, 0, 0,
0542             NULL, 0),
0543 
0544     /* Output Pga */
0545     SND_SOC_DAPM_SWITCH("LOUT L", SND_SOC_NOPM, 0, 0,
0546         &loutl_enable_control),
0547     SND_SOC_DAPM_SWITCH("LOUT R", SND_SOC_NOPM, 0, 0,
0548         &loutr_enable_control),
0549     SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0,
0550         &hpol_enable_control),
0551     SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0,
0552         &hpor_enable_control),
0553 
0554     /* Output Lines */
0555     SND_SOC_DAPM_OUTPUT("HPO Pin"),
0556     SND_SOC_DAPM_OUTPUT("SPDIF"),
0557     SND_SOC_DAPM_OUTPUT("LINE3"),
0558 };
0559 
0560 static const struct snd_soc_dapm_route rt274_dapm_routes[] = {
0561     {"DMIC1", NULL, "DMIC1 Pin"},
0562     {"DMIC2", NULL, "DMIC2 Pin"},
0563 
0564     {"ADC 0 Mux", "Mic", "MIC"},
0565     {"ADC 0 Mux", "Dmic", "DMIC1"},
0566     {"ADC 0 Mux", "Line1", "LINE1"},
0567     {"ADC 0 Mux", "Line2", "LINE2"},
0568     {"ADC 1 Mux", "Mic", "MIC"},
0569     {"ADC 1 Mux", "Dmic", "DMIC2"},
0570     {"ADC 1 Mux", "Line1", "LINE1"},
0571     {"ADC 1 Mux", "Line2", "LINE2"},
0572 
0573     {"ADC 0", NULL, "ADC 0 Mux"},
0574     {"ADC 1", NULL, "ADC 1 Mux"},
0575 
0576     {"AIF1TXL", NULL, "ADC 0"},
0577     {"AIF1TXR", NULL, "ADC 0"},
0578     {"AIF2TXL", NULL, "ADC 1"},
0579     {"AIF2TXR", NULL, "ADC 1"},
0580 
0581     {"DAC 0", NULL, "AIF1RXL"},
0582     {"DAC 0", NULL, "AIF1RXR"},
0583     {"DAC 1", NULL, "AIF2RXL"},
0584     {"DAC 1", NULL, "AIF2RXR"},
0585 
0586     {"DAC OUT0", NULL, "DAC 0"},
0587 
0588     {"DAC OUT1", NULL, "DAC 1"},
0589 
0590     {"LOUT Mux", "DAC OUT0", "DAC OUT0"},
0591     {"LOUT Mux", "DAC OUT1", "DAC OUT1"},
0592 
0593     {"LOUT L", "Switch", "LOUT Mux"},
0594     {"LOUT R", "Switch", "LOUT Mux"},
0595     {"LOUT L", NULL, "LOUT Power"},
0596     {"LOUT R", NULL, "LOUT Power"},
0597 
0598     {"LINE3", NULL, "LOUT L"},
0599     {"LINE3", NULL, "LOUT R"},
0600 
0601     {"HPO Mux", "DAC OUT0", "DAC OUT0"},
0602     {"HPO Mux", "DAC OUT1", "DAC OUT1"},
0603 
0604     {"HPO L", "Switch", "HPO Mux"},
0605     {"HPO R", "Switch", "HPO Mux"},
0606     {"HPO L", NULL, "HP Power"},
0607     {"HPO R", NULL, "HP Power"},
0608 
0609     {"HPO Pin", NULL, "HPO L"},
0610     {"HPO Pin", NULL, "HPO R"},
0611 };
0612 
0613 static int rt274_hw_params(struct snd_pcm_substream *substream,
0614                 struct snd_pcm_hw_params *params,
0615                 struct snd_soc_dai *dai)
0616 {
0617     struct snd_soc_component *component = dai->component;
0618     struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
0619     unsigned int val = 0;
0620     int d_len_code = 0, c_len_code = 0;
0621 
0622     switch (params_rate(params)) {
0623     /* bit 14 0:48K 1:44.1K */
0624     case 44100:
0625     case 48000:
0626         break;
0627     default:
0628         dev_err(component->dev, "Unsupported sample rate %d\n",
0629                     params_rate(params));
0630         return -EINVAL;
0631     }
0632     switch (rt274->sys_clk) {
0633     case 12288000:
0634     case 24576000:
0635         if (params_rate(params) != 48000) {
0636             dev_err(component->dev, "Sys_clk is not matched (%d %d)\n",
0637                     params_rate(params), rt274->sys_clk);
0638             return -EINVAL;
0639         }
0640         break;
0641     case 11289600:
0642     case 22579200:
0643         if (params_rate(params) != 44100) {
0644             dev_err(component->dev, "Sys_clk is not matched (%d %d)\n",
0645                     params_rate(params), rt274->sys_clk);
0646             return -EINVAL;
0647         }
0648         break;
0649     }
0650 
0651     if (params_channels(params) <= 16) {
0652         /* bit 3:0 Number of Channel */
0653         val |= (params_channels(params) - 1);
0654     } else {
0655         dev_err(component->dev, "Unsupported channels %d\n",
0656                     params_channels(params));
0657         return -EINVAL;
0658     }
0659 
0660     switch (params_width(params)) {
0661     /* bit 6:4 Bits per Sample */
0662     case 16:
0663         d_len_code = 0;
0664         c_len_code = 0;
0665         val |= (0x1 << 4);
0666         break;
0667     case 32:
0668         d_len_code = 2;
0669         c_len_code = 3;
0670         val |= (0x4 << 4);
0671         break;
0672     case 20:
0673         d_len_code = 1;
0674         c_len_code = 1;
0675         val |= (0x2 << 4);
0676         break;
0677     case 24:
0678         d_len_code = 2;
0679         c_len_code = 2;
0680         val |= (0x3 << 4);
0681         break;
0682     case 8:
0683         d_len_code = 3;
0684         c_len_code = 0;
0685         break;
0686     default:
0687         return -EINVAL;
0688     }
0689 
0690     if (rt274->master)
0691         c_len_code = 0x3;
0692 
0693     snd_soc_component_update_bits(component,
0694         RT274_I2S_CTRL1, 0xc018, d_len_code << 3 | c_len_code << 14);
0695     dev_dbg(component->dev, "format val = 0x%x\n", val);
0696 
0697     snd_soc_component_update_bits(component, RT274_DAC_FORMAT, 0x407f, val);
0698     snd_soc_component_update_bits(component, RT274_ADC_FORMAT, 0x407f, val);
0699 
0700     return 0;
0701 }
0702 
0703 static int rt274_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
0704 {
0705     struct snd_soc_component *component = dai->component;
0706     struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
0707 
0708     switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
0709     case SND_SOC_DAIFMT_CBM_CFM:
0710         snd_soc_component_update_bits(component,
0711             RT274_I2S_CTRL1, RT274_I2S_MODE_MASK, RT274_I2S_MODE_M);
0712         rt274->master = true;
0713         break;
0714     case SND_SOC_DAIFMT_CBS_CFS:
0715         snd_soc_component_update_bits(component,
0716             RT274_I2S_CTRL1, RT274_I2S_MODE_MASK, RT274_I2S_MODE_S);
0717         rt274->master = false;
0718         break;
0719     default:
0720         return -EINVAL;
0721     }
0722 
0723     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0724     case SND_SOC_DAIFMT_I2S:
0725         snd_soc_component_update_bits(component, RT274_I2S_CTRL1,
0726                     RT274_I2S_FMT_MASK, RT274_I2S_FMT_I2S);
0727         break;
0728     case SND_SOC_DAIFMT_LEFT_J:
0729         snd_soc_component_update_bits(component, RT274_I2S_CTRL1,
0730                     RT274_I2S_FMT_MASK, RT274_I2S_FMT_LJ);
0731         break;
0732     case SND_SOC_DAIFMT_DSP_A:
0733         snd_soc_component_update_bits(component, RT274_I2S_CTRL1,
0734                     RT274_I2S_FMT_MASK, RT274_I2S_FMT_PCMA);
0735         break;
0736     case SND_SOC_DAIFMT_DSP_B:
0737         snd_soc_component_update_bits(component, RT274_I2S_CTRL1,
0738                     RT274_I2S_FMT_MASK, RT274_I2S_FMT_PCMB);
0739         break;
0740     default:
0741         return -EINVAL;
0742     }
0743     /* bit 15 Stream Type 0:PCM 1:Non-PCM */
0744     snd_soc_component_update_bits(component, RT274_DAC_FORMAT, 0x8000, 0);
0745     snd_soc_component_update_bits(component, RT274_ADC_FORMAT, 0x8000, 0);
0746 
0747     return 0;
0748 }
0749 
0750 static int rt274_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
0751             unsigned int freq_in, unsigned int freq_out)
0752 {
0753     struct snd_soc_component *component = dai->component;
0754     struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
0755 
0756     switch (source) {
0757     case RT274_PLL2_S_MCLK:
0758         snd_soc_component_update_bits(component, RT274_PLL2_CTRL,
0759                 RT274_PLL2_SRC_MASK, RT274_PLL2_SRC_MCLK);
0760         break;
0761     default:
0762         dev_warn(component->dev, "invalid pll source, use BCLK\n");
0763         fallthrough;
0764     case RT274_PLL2_S_BCLK:
0765         snd_soc_component_update_bits(component, RT274_PLL2_CTRL,
0766                 RT274_PLL2_SRC_MASK, RT274_PLL2_SRC_BCLK);
0767         break;
0768     }
0769 
0770     if (source == RT274_PLL2_S_BCLK) {
0771         snd_soc_component_update_bits(component, RT274_MCLK_CTRL,
0772                 (0x3 << 12), (0x3 << 12));
0773         switch (rt274->fs) {
0774         case 50:
0775             snd_soc_component_write(component, 0x7a, 0xaab6);
0776             snd_soc_component_write(component, 0x7b, 0x0301);
0777             snd_soc_component_write(component, 0x7c, 0x04fe);
0778             break;
0779         case 64:
0780             snd_soc_component_write(component, 0x7a, 0xaa96);
0781             snd_soc_component_write(component, 0x7b, 0x8003);
0782             snd_soc_component_write(component, 0x7c, 0x081e);
0783             break;
0784         case 128:
0785             snd_soc_component_write(component, 0x7a, 0xaa96);
0786             snd_soc_component_write(component, 0x7b, 0x8003);
0787             snd_soc_component_write(component, 0x7c, 0x080e);
0788             break;
0789         default:
0790             dev_warn(component->dev, "invalid freq_in, assume 4.8M\n");
0791             fallthrough;
0792         case 100:
0793             snd_soc_component_write(component, 0x7a, 0xaab6);
0794             snd_soc_component_write(component, 0x7b, 0x0301);
0795             snd_soc_component_write(component, 0x7c, 0x047e);
0796             break;
0797         }
0798     }
0799 
0800     return 0;
0801 }
0802 
0803 static int rt274_set_dai_sysclk(struct snd_soc_dai *dai,
0804                 int clk_id, unsigned int freq, int dir)
0805 {
0806     struct snd_soc_component *component = dai->component;
0807     struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
0808     unsigned int clk_src, mclk_en;
0809 
0810     dev_dbg(component->dev, "%s freq=%d\n", __func__, freq);
0811 
0812     switch (clk_id) {
0813     case RT274_SCLK_S_MCLK:
0814         mclk_en = RT274_MCLK_MODE_EN;
0815         clk_src = RT274_CLK_SRC_MCLK;
0816         break;
0817     case RT274_SCLK_S_PLL1:
0818         mclk_en = RT274_MCLK_MODE_DIS;
0819         clk_src = RT274_CLK_SRC_MCLK;
0820         break;
0821     case RT274_SCLK_S_PLL2:
0822         mclk_en = RT274_MCLK_MODE_EN;
0823         clk_src = RT274_CLK_SRC_PLL2;
0824         break;
0825     default:
0826         mclk_en = RT274_MCLK_MODE_DIS;
0827         clk_src = RT274_CLK_SRC_MCLK;
0828         dev_warn(component->dev, "invalid sysclk source, use PLL1\n");
0829         break;
0830     }
0831     snd_soc_component_update_bits(component, RT274_MCLK_CTRL,
0832             RT274_MCLK_MODE_MASK, mclk_en);
0833     snd_soc_component_update_bits(component, RT274_CLK_CTRL,
0834             RT274_CLK_SRC_MASK, clk_src);
0835 
0836     switch (freq) {
0837     case 19200000:
0838         if (clk_id == RT274_SCLK_S_MCLK) {
0839             dev_err(component->dev, "Should not use MCLK\n");
0840             return -EINVAL;
0841         }
0842         snd_soc_component_update_bits(component,
0843             RT274_I2S_CTRL2, 0x40, 0x40);
0844         break;
0845     case 24000000:
0846         if (clk_id == RT274_SCLK_S_MCLK) {
0847             dev_err(component->dev, "Should not use MCLK\n");
0848             return -EINVAL;
0849         }
0850         snd_soc_component_update_bits(component,
0851             RT274_I2S_CTRL2, 0x40, 0x0);
0852         break;
0853     case 12288000:
0854     case 11289600:
0855         snd_soc_component_update_bits(component,
0856             RT274_MCLK_CTRL, 0x1fcf, 0x0008);
0857         break;
0858     case 24576000:
0859     case 22579200:
0860         snd_soc_component_update_bits(component,
0861             RT274_MCLK_CTRL, 0x1fcf, 0x1543);
0862         break;
0863     default:
0864         dev_err(component->dev, "Unsupported system clock\n");
0865         return -EINVAL;
0866     }
0867 
0868     rt274->sys_clk = freq;
0869     rt274->clk_id = clk_id;
0870 
0871     return 0;
0872 }
0873 
0874 static int rt274_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
0875 {
0876     struct snd_soc_component *component = dai->component;
0877     struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
0878 
0879     dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio);
0880     rt274->fs = ratio;
0881     if ((ratio / 50) == 0)
0882         snd_soc_component_update_bits(component,
0883             RT274_I2S_CTRL1, 0x1000, 0x1000);
0884     else
0885         snd_soc_component_update_bits(component,
0886             RT274_I2S_CTRL1, 0x1000, 0x0);
0887 
0888 
0889     return 0;
0890 }
0891 
0892 static int rt274_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
0893             unsigned int rx_mask, int slots, int slot_width)
0894 
0895 {
0896     struct snd_soc_component *component = dai->component;
0897 
0898     if (rx_mask || tx_mask) {
0899         snd_soc_component_update_bits(component,
0900             RT274_I2S_CTRL1, RT274_TDM_EN, RT274_TDM_EN);
0901     } else {
0902         snd_soc_component_update_bits(component,
0903             RT274_I2S_CTRL1, RT274_TDM_EN, RT274_TDM_DIS);
0904         return 0;
0905     }
0906 
0907     switch (slots) {
0908     case 4:
0909         snd_soc_component_update_bits(component,
0910             RT274_I2S_CTRL1, RT274_TDM_CH_NUM, RT274_TDM_4CH);
0911         break;
0912     case 2:
0913         snd_soc_component_update_bits(component,
0914             RT274_I2S_CTRL1, RT274_TDM_CH_NUM, RT274_TDM_2CH);
0915         break;
0916     default:
0917         dev_err(component->dev,
0918             "Support 2 or 4 slots TDM only\n");
0919         return -EINVAL;
0920     }
0921 
0922     return 0;
0923 }
0924 
0925 static int rt274_set_bias_level(struct snd_soc_component *component,
0926                  enum snd_soc_bias_level level)
0927 {
0928     switch (level) {
0929     case SND_SOC_BIAS_PREPARE:
0930         if (SND_SOC_BIAS_STANDBY ==
0931             snd_soc_component_get_bias_level(component)) {
0932             snd_soc_component_write(component,
0933                 RT274_SET_AUDIO_POWER, AC_PWRST_D0);
0934         }
0935         break;
0936 
0937     case SND_SOC_BIAS_STANDBY:
0938         snd_soc_component_write(component,
0939             RT274_SET_AUDIO_POWER, AC_PWRST_D3);
0940         break;
0941 
0942     default:
0943         break;
0944     }
0945 
0946     return 0;
0947 }
0948 
0949 static irqreturn_t rt274_irq(int irq, void *data)
0950 {
0951     struct rt274_priv *rt274 = data;
0952     bool hp = false;
0953     bool mic = false;
0954     int ret, status = 0;
0955 
0956     /* Clear IRQ */
0957     regmap_update_bits(rt274->regmap, RT274_EAPD_GPIO_IRQ_CTRL,
0958                 RT274_IRQ_CLR, RT274_IRQ_CLR);
0959 
0960     ret = rt274_jack_detect(rt274, &hp, &mic);
0961 
0962     if (ret == 0) {
0963         if (hp)
0964             status |= SND_JACK_HEADPHONE;
0965 
0966         if (mic)
0967             status |= SND_JACK_MICROPHONE;
0968 
0969         snd_soc_jack_report(rt274->jack, status,
0970             SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
0971 
0972         pm_wakeup_event(&rt274->i2c->dev, 300);
0973     }
0974 
0975     return IRQ_HANDLED;
0976 }
0977 
0978 static int rt274_probe(struct snd_soc_component *component)
0979 {
0980     struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
0981 
0982     rt274->component = component;
0983     INIT_DELAYED_WORK(&rt274->jack_detect_work, rt274_jack_detect_work);
0984 
0985     if (rt274->i2c->irq)
0986         schedule_delayed_work(&rt274->jack_detect_work,
0987                       msecs_to_jiffies(1250));
0988     return 0;
0989 }
0990 
0991 static void rt274_remove(struct snd_soc_component *component)
0992 {
0993     struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
0994 
0995     cancel_delayed_work_sync(&rt274->jack_detect_work);
0996     rt274->component = NULL;
0997 }
0998 
0999 #ifdef CONFIG_PM
1000 static int rt274_suspend(struct snd_soc_component *component)
1001 {
1002     struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
1003 
1004     regcache_cache_only(rt274->regmap, true);
1005     regcache_mark_dirty(rt274->regmap);
1006 
1007     return 0;
1008 }
1009 
1010 static int rt274_resume(struct snd_soc_component *component)
1011 {
1012     struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
1013 
1014     regcache_cache_only(rt274->regmap, false);
1015     rt274_index_sync(component);
1016     regcache_sync(rt274->regmap);
1017 
1018     return 0;
1019 }
1020 #else
1021 #define rt274_suspend NULL
1022 #define rt274_resume NULL
1023 #endif
1024 
1025 #define RT274_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
1026 #define RT274_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1027             SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1028 
1029 static const struct snd_soc_dai_ops rt274_aif_dai_ops = {
1030     .hw_params = rt274_hw_params,
1031     .set_fmt = rt274_set_dai_fmt,
1032     .set_sysclk = rt274_set_dai_sysclk,
1033     .set_pll = rt274_set_dai_pll,
1034     .set_bclk_ratio = rt274_set_bclk_ratio,
1035     .set_tdm_slot = rt274_set_tdm_slot,
1036 };
1037 
1038 static struct snd_soc_dai_driver rt274_dai[] = {
1039     {
1040         .name = "rt274-aif1",
1041         .id = RT274_AIF1,
1042         .playback = {
1043             .stream_name = "AIF1 Playback",
1044             .channels_min = 1,
1045             .channels_max = 2,
1046             .rates = RT274_STEREO_RATES,
1047             .formats = RT274_FORMATS,
1048         },
1049         .capture = {
1050             .stream_name = "AIF1 Capture",
1051             .channels_min = 1,
1052             .channels_max = 2,
1053             .rates = RT274_STEREO_RATES,
1054             .formats = RT274_FORMATS,
1055         },
1056         .ops = &rt274_aif_dai_ops,
1057         .symmetric_rate = 1,
1058     },
1059 };
1060 
1061 static const struct snd_soc_component_driver soc_component_dev_rt274 = {
1062     .probe          = rt274_probe,
1063     .remove         = rt274_remove,
1064     .suspend        = rt274_suspend,
1065     .resume         = rt274_resume,
1066     .set_bias_level     = rt274_set_bias_level,
1067     .set_jack       = rt274_mic_detect,
1068     .controls       = rt274_snd_controls,
1069     .num_controls       = ARRAY_SIZE(rt274_snd_controls),
1070     .dapm_widgets       = rt274_dapm_widgets,
1071     .num_dapm_widgets   = ARRAY_SIZE(rt274_dapm_widgets),
1072     .dapm_routes        = rt274_dapm_routes,
1073     .num_dapm_routes    = ARRAY_SIZE(rt274_dapm_routes),
1074     .use_pmdown_time    = 1,
1075     .endianness     = 1,
1076 };
1077 
1078 static const struct regmap_config rt274_regmap = {
1079     .reg_bits = 32,
1080     .val_bits = 32,
1081     .max_register = 0x05bfffff,
1082     .volatile_reg = rt274_volatile_register,
1083     .readable_reg = rt274_readable_register,
1084     .reg_write = rl6347a_hw_write,
1085     .reg_read = rl6347a_hw_read,
1086     .cache_type = REGCACHE_RBTREE,
1087     .reg_defaults = rt274_reg,
1088     .num_reg_defaults = ARRAY_SIZE(rt274_reg),
1089 };
1090 
1091 #ifdef CONFIG_OF
1092 static const struct of_device_id rt274_of_match[] = {
1093     {.compatible = "realtek,rt274"},
1094     {},
1095 };
1096 MODULE_DEVICE_TABLE(of, rt274_of_match);
1097 #endif
1098 
1099 static const struct i2c_device_id rt274_i2c_id[] = {
1100     {"rt274", 0},
1101     {}
1102 };
1103 MODULE_DEVICE_TABLE(i2c, rt274_i2c_id);
1104 
1105 #ifdef CONFIG_ACPI
1106 static const struct acpi_device_id rt274_acpi_match[] = {
1107     { "10EC0274", 0 },
1108     { "INT34C2", 0 },
1109     {},
1110 };
1111 MODULE_DEVICE_TABLE(acpi, rt274_acpi_match);
1112 #endif
1113 
1114 static int rt274_i2c_probe(struct i2c_client *i2c)
1115 {
1116     struct rt274_priv *rt274;
1117 
1118     int ret;
1119     unsigned int val;
1120 
1121     rt274 = devm_kzalloc(&i2c->dev, sizeof(*rt274),
1122                 GFP_KERNEL);
1123     if (rt274 == NULL)
1124         return -ENOMEM;
1125 
1126     rt274->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt274_regmap);
1127     if (IS_ERR(rt274->regmap)) {
1128         ret = PTR_ERR(rt274->regmap);
1129         dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1130             ret);
1131         return ret;
1132     }
1133 
1134     ret = regmap_read(rt274->regmap,
1135         RT274_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &val);
1136     if (ret)
1137         return ret;
1138 
1139     if (val != RT274_VENDOR_ID) {
1140         dev_err(&i2c->dev,
1141             "Device with ID register %#x is not rt274\n", val);
1142         return -ENODEV;
1143     }
1144 
1145     rt274->index_cache = devm_kmemdup(&i2c->dev, rt274_index_def,
1146                       sizeof(rt274_index_def), GFP_KERNEL);
1147     if (!rt274->index_cache)
1148         return -ENOMEM;
1149 
1150     rt274->index_cache_size = INDEX_CACHE_SIZE;
1151     rt274->i2c = i2c;
1152     i2c_set_clientdata(i2c, rt274);
1153 
1154     /* reset codec */
1155     regmap_write(rt274->regmap, RT274_RESET, 0);
1156     regmap_update_bits(rt274->regmap, 0x1a, 0x4000, 0x4000);
1157 
1158     /* Set Pad PDB is floating */
1159     regmap_update_bits(rt274->regmap, RT274_PAD_CTRL12, 0x3, 0x0);
1160     regmap_write(rt274->regmap, RT274_COEF5b_INDEX, 0x01);
1161     regmap_write(rt274->regmap, RT274_COEF5b_COEF, 0x8540);
1162     regmap_update_bits(rt274->regmap, 0x6f, 0x0100, 0x0100);
1163     /* Combo jack auto detect */
1164     regmap_write(rt274->regmap, 0x4a, 0x201b);
1165     /* Aux mode off */
1166     regmap_update_bits(rt274->regmap, 0x6f, 0x3000, 0x2000);
1167     /* HP DC Calibration */
1168     regmap_update_bits(rt274->regmap, 0x6f, 0xf, 0x0);
1169     /* Set NID=58h.Index 00h [15]= 1b; */
1170     regmap_write(rt274->regmap, RT274_COEF58_INDEX, 0x00);
1171     regmap_write(rt274->regmap, RT274_COEF58_COEF, 0xb888);
1172     msleep(500);
1173     regmap_update_bits(rt274->regmap, 0x6f, 0xf, 0xb);
1174     regmap_write(rt274->regmap, RT274_COEF58_INDEX, 0x00);
1175     regmap_write(rt274->regmap, RT274_COEF58_COEF, 0x3888);
1176     /* Set pin widget */
1177     regmap_write(rt274->regmap, RT274_SET_PIN_HPO, 0x40);
1178     regmap_write(rt274->regmap, RT274_SET_PIN_LOUT3, 0x40);
1179     regmap_write(rt274->regmap, RT274_SET_MIC, 0x20);
1180     regmap_write(rt274->regmap, RT274_SET_PIN_DMIC1, 0x20);
1181 
1182     regmap_update_bits(rt274->regmap, RT274_I2S_CTRL2, 0xc004, 0x4004);
1183     regmap_update_bits(rt274->regmap, RT274_EAPD_GPIO_IRQ_CTRL,
1184                 RT274_GPI2_SEL_MASK, RT274_GPI2_SEL_DMIC_CLK);
1185 
1186     /* jack detection */
1187     regmap_write(rt274->regmap, RT274_UNSOLICITED_HP_OUT, 0x81);
1188     regmap_write(rt274->regmap, RT274_UNSOLICITED_MIC, 0x82);
1189 
1190     if (rt274->i2c->irq) {
1191         ret = request_threaded_irq(rt274->i2c->irq, NULL, rt274_irq,
1192             IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt274", rt274);
1193         if (ret != 0) {
1194             dev_err(&i2c->dev,
1195                 "Failed to reguest IRQ: %d\n", ret);
1196             return ret;
1197         }
1198     }
1199 
1200     ret = devm_snd_soc_register_component(&i2c->dev,
1201                      &soc_component_dev_rt274,
1202                      rt274_dai, ARRAY_SIZE(rt274_dai));
1203 
1204     return ret;
1205 }
1206 
1207 static int rt274_i2c_remove(struct i2c_client *i2c)
1208 {
1209     struct rt274_priv *rt274 = i2c_get_clientdata(i2c);
1210 
1211     if (i2c->irq)
1212         free_irq(i2c->irq, rt274);
1213 
1214     return 0;
1215 }
1216 
1217 
1218 static struct i2c_driver rt274_i2c_driver = {
1219     .driver = {
1220            .name = "rt274",
1221            .acpi_match_table = ACPI_PTR(rt274_acpi_match),
1222 #ifdef CONFIG_OF
1223            .of_match_table = of_match_ptr(rt274_of_match),
1224 #endif
1225            },
1226     .probe_new = rt274_i2c_probe,
1227     .remove = rt274_i2c_remove,
1228     .id_table = rt274_i2c_id,
1229 };
1230 
1231 module_i2c_driver(rt274_i2c_driver);
1232 
1233 MODULE_DESCRIPTION("ASoC RT274 driver");
1234 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
1235 MODULE_LICENSE("GPL v2");
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