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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 //
0003 // rt1316-sdw.c -- rt1316 SDCA ALSA SoC amplifier audio driver
0004 //
0005 // Copyright(c) 2021 Realtek Semiconductor Corp.
0006 //
0007 //
0008 #include <linux/delay.h>
0009 #include <linux/device.h>
0010 #include <linux/pm_runtime.h>
0011 #include <linux/mod_devicetable.h>
0012 #include <linux/module.h>
0013 #include <linux/regmap.h>
0014 #include <sound/core.h>
0015 #include <sound/pcm.h>
0016 #include <sound/pcm_params.h>
0017 #include <sound/soc-dapm.h>
0018 #include <sound/initval.h>
0019 #include "rt1316-sdw.h"
0020 
0021 static const struct reg_default rt1316_reg_defaults[] = {
0022     { 0x3004, 0x00 },
0023     { 0x3005, 0x00 },
0024     { 0x3206, 0x00 },
0025     { 0xc001, 0x00 },
0026     { 0xc002, 0x00 },
0027     { 0xc003, 0x00 },
0028     { 0xc004, 0x00 },
0029     { 0xc005, 0x00 },
0030     { 0xc006, 0x00 },
0031     { 0xc007, 0x00 },
0032     { 0xc008, 0x00 },
0033     { 0xc009, 0x00 },
0034     { 0xc00a, 0x00 },
0035     { 0xc00b, 0x00 },
0036     { 0xc00c, 0x00 },
0037     { 0xc00d, 0x00 },
0038     { 0xc00e, 0x00 },
0039     { 0xc00f, 0x00 },
0040     { 0xc010, 0xa5 },
0041     { 0xc011, 0x00 },
0042     { 0xc012, 0xff },
0043     { 0xc013, 0xff },
0044     { 0xc014, 0x40 },
0045     { 0xc015, 0x00 },
0046     { 0xc016, 0x00 },
0047     { 0xc017, 0x00 },
0048     { 0xc605, 0x30 },
0049     { 0xc700, 0x0a },
0050     { 0xc701, 0xaa },
0051     { 0xc702, 0x1a },
0052     { 0xc703, 0x0a },
0053     { 0xc710, 0x80 },
0054     { 0xc711, 0x00 },
0055     { 0xc712, 0x3e },
0056     { 0xc713, 0x80 },
0057     { 0xc714, 0x80 },
0058     { 0xc715, 0x06 },
0059     { 0xd101, 0x00 },
0060     { 0xd102, 0x30 },
0061     { 0xd103, 0x00 },
0062     { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_UDMPU21, RT1316_SDCA_CTL_UDMPU_CLUSTER, 0), 0x00 },
0063     { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_L), 0x01 },
0064     { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_R), 0x01 },
0065     { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_XU24, RT1316_SDCA_CTL_BYPASS, 0), 0x01 },
0066     { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23, RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
0067     { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22, RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
0068     { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24, RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
0069 };
0070 
0071 static const struct reg_sequence rt1316_blind_write[] = {
0072     { 0xc710, 0x17 },
0073     { 0xc711, 0x80 },
0074     { 0xc712, 0x26 },
0075     { 0xc713, 0x06 },
0076     { 0xc714, 0x80 },
0077     { 0xc715, 0x06 },
0078     { 0xc702, 0x0a },
0079     { 0xc703, 0x0a },
0080     { 0xc001, 0x45 },
0081     { 0xc003, 0x00 },
0082     { 0xc004, 0x11 },
0083     { 0xc005, 0x00 },
0084     { 0xc006, 0x00 },
0085     { 0xc106, 0x00 },
0086     { 0xc007, 0x11 },
0087     { 0xc008, 0x11 },
0088     { 0xc009, 0x00 },
0089 
0090     { 0x2f0a, 0x00 },
0091     { 0xd101, 0xf0 },
0092     { 0xd103, 0x9b },
0093     { 0x2f36, 0x8e },
0094     { 0x3206, 0x80 },
0095     { 0x3211, 0x0b },
0096     { 0x3216, 0x06 },
0097     { 0xc614, 0x20 },
0098     { 0xc615, 0x0a },
0099     { 0xc616, 0x02 },
0100     { 0xc617, 0x00 },
0101     { 0xc60b, 0x10 },
0102     { 0xc60e, 0x05 },
0103     { 0xc102, 0x00 },
0104     { 0xc090, 0xb0 },
0105     { 0xc00f, 0x01 },
0106     { 0xc09c, 0x7b },
0107 
0108     { 0xc602, 0x07 },
0109     { 0xc603, 0x07 },
0110     { 0xc0a3, 0x71 },
0111     { 0xc00b, 0x30 },
0112     { 0xc093, 0x80 },
0113     { 0xc09d, 0x80 },
0114     { 0xc0b0, 0x77 },
0115     { 0xc010, 0xa5 },
0116     { 0xc050, 0x83 },
0117     { 0x2f55, 0x03 },
0118     { 0x3217, 0xb5 },
0119     { 0x3202, 0x02 },
0120 
0121     { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_XU24, RT1316_SDCA_CTL_BYPASS, 0), 0x00 },
0122 
0123     /* for IV sense */
0124     { 0x2232, 0x80 },
0125     { 0xc0b0, 0x77 },
0126     { 0xc011, 0x00 },
0127     { 0xc020, 0x00 },
0128     { 0xc023, 0x00 },
0129     { 0x3101, 0x00 },
0130     { 0x3004, 0xa0 },
0131     { 0x3005, 0xb1 },
0132     { 0xc007, 0x11 },
0133     { 0xc008, 0x11 },
0134     { 0xc009, 0x00 },
0135     { 0xc022, 0xd6 },
0136     { 0xc025, 0xd6 },
0137 
0138     { 0xd001, 0x03 },
0139     { 0xd002, 0xbf },
0140     { 0xd003, 0x03 },
0141     { 0xd004, 0xbf },
0142 };
0143 
0144 static bool rt1316_readable_register(struct device *dev, unsigned int reg)
0145 {
0146     switch (reg) {
0147     case 0x2f0a:
0148     case 0x2f36:
0149     case 0x3203 ... 0x320e:
0150     case 0xc000 ... 0xc7b4:
0151     case 0xcf00 ... 0xcf03:
0152     case 0xd101 ... 0xd103:
0153     case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_UDMPU21, RT1316_SDCA_CTL_UDMPU_CLUSTER, 0):
0154     case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_L):
0155     case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_R):
0156     case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23, RT1316_SDCA_CTL_REQ_POWER_STATE, 0):
0157     case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE27, RT1316_SDCA_CTL_REQ_POWER_STATE, 0):
0158     case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22, RT1316_SDCA_CTL_REQ_POWER_STATE, 0):
0159     case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24, RT1316_SDCA_CTL_REQ_POWER_STATE, 0):
0160         return true;
0161     default:
0162         return false;
0163     }
0164 }
0165 
0166 static bool rt1316_volatile_register(struct device *dev, unsigned int reg)
0167 {
0168     switch (reg) {
0169     case 0xc000:
0170     case 0xc093:
0171     case 0xc09d:
0172     case 0xc0a3:
0173     case 0xc201:
0174     case 0xc427 ... 0xc428:
0175     case 0xd102:
0176         return true;
0177     default:
0178         return false;
0179     }
0180 }
0181 
0182 static const struct regmap_config rt1316_sdw_regmap = {
0183     .reg_bits = 32,
0184     .val_bits = 8,
0185     .readable_reg = rt1316_readable_register,
0186     .volatile_reg = rt1316_volatile_register,
0187     .max_register = 0x4108ffff,
0188     .reg_defaults = rt1316_reg_defaults,
0189     .num_reg_defaults = ARRAY_SIZE(rt1316_reg_defaults),
0190     .cache_type = REGCACHE_RBTREE,
0191     .use_single_read = true,
0192     .use_single_write = true,
0193 };
0194 
0195 static int rt1316_read_prop(struct sdw_slave *slave)
0196 {
0197     struct sdw_slave_prop *prop = &slave->prop;
0198     int nval;
0199     int i, j;
0200     u32 bit;
0201     unsigned long addr;
0202     struct sdw_dpn_prop *dpn;
0203 
0204     prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
0205     prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
0206     prop->is_sdca = true;
0207 
0208     prop->paging_support = true;
0209 
0210     /* first we need to allocate memory for set bits in port lists */
0211     prop->source_ports = 0x04; /* BITMAP: 00000100 */
0212     prop->sink_ports = 0x2; /* BITMAP:  00000010 */
0213 
0214     nval = hweight32(prop->source_ports);
0215     prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
0216         sizeof(*prop->src_dpn_prop), GFP_KERNEL);
0217     if (!prop->src_dpn_prop)
0218         return -ENOMEM;
0219 
0220     i = 0;
0221     dpn = prop->src_dpn_prop;
0222     addr = prop->source_ports;
0223     for_each_set_bit(bit, &addr, 32) {
0224         dpn[i].num = bit;
0225         dpn[i].type = SDW_DPN_FULL;
0226         dpn[i].simple_ch_prep_sm = true;
0227         dpn[i].ch_prep_timeout = 10;
0228         i++;
0229     }
0230 
0231     /* do this again for sink now */
0232     nval = hweight32(prop->sink_ports);
0233     prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
0234         sizeof(*prop->sink_dpn_prop), GFP_KERNEL);
0235     if (!prop->sink_dpn_prop)
0236         return -ENOMEM;
0237 
0238     j = 0;
0239     dpn = prop->sink_dpn_prop;
0240     addr = prop->sink_ports;
0241     for_each_set_bit(bit, &addr, 32) {
0242         dpn[j].num = bit;
0243         dpn[j].type = SDW_DPN_FULL;
0244         dpn[j].simple_ch_prep_sm = true;
0245         dpn[j].ch_prep_timeout = 10;
0246         j++;
0247     }
0248 
0249     /* set the timeout values */
0250     prop->clk_stop_timeout = 20;
0251 
0252     dev_dbg(&slave->dev, "%s\n", __func__);
0253 
0254     return 0;
0255 }
0256 
0257 static int rt1316_io_init(struct device *dev, struct sdw_slave *slave)
0258 {
0259     struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(dev);
0260 
0261     if (rt1316->hw_init)
0262         return 0;
0263 
0264     if (rt1316->first_hw_init) {
0265         regcache_cache_only(rt1316->regmap, false);
0266         regcache_cache_bypass(rt1316->regmap, true);
0267     } else {
0268         /*
0269          * PM runtime is only enabled when a Slave reports as Attached
0270          */
0271 
0272         /* set autosuspend parameters */
0273         pm_runtime_set_autosuspend_delay(&slave->dev, 3000);
0274         pm_runtime_use_autosuspend(&slave->dev);
0275 
0276         /* update count of parent 'active' children */
0277         pm_runtime_set_active(&slave->dev);
0278 
0279         /* make sure the device does not suspend immediately */
0280         pm_runtime_mark_last_busy(&slave->dev);
0281 
0282         pm_runtime_enable(&slave->dev);
0283     }
0284 
0285     pm_runtime_get_noresume(&slave->dev);
0286 
0287     /* sw reset */
0288     regmap_write(rt1316->regmap, 0xc000, 0x02);
0289 
0290     /* initial settings - blind write */
0291     regmap_multi_reg_write(rt1316->regmap, rt1316_blind_write,
0292         ARRAY_SIZE(rt1316_blind_write));
0293 
0294     if (rt1316->first_hw_init) {
0295         regcache_cache_bypass(rt1316->regmap, false);
0296         regcache_mark_dirty(rt1316->regmap);
0297     } else
0298         rt1316->first_hw_init = true;
0299 
0300     /* Mark Slave initialization complete */
0301     rt1316->hw_init = true;
0302 
0303     pm_runtime_mark_last_busy(&slave->dev);
0304     pm_runtime_put_autosuspend(&slave->dev);
0305 
0306     dev_dbg(&slave->dev, "%s hw_init complete\n", __func__);
0307     return 0;
0308 }
0309 
0310 static int rt1316_update_status(struct sdw_slave *slave,
0311                     enum sdw_slave_status status)
0312 {
0313     struct  rt1316_sdw_priv *rt1316 = dev_get_drvdata(&slave->dev);
0314 
0315     /* Update the status */
0316     rt1316->status = status;
0317 
0318     if (status == SDW_SLAVE_UNATTACHED)
0319         rt1316->hw_init = false;
0320 
0321     /*
0322      * Perform initialization only if slave status is present and
0323      * hw_init flag is false
0324      */
0325     if (rt1316->hw_init || rt1316->status != SDW_SLAVE_ATTACHED)
0326         return 0;
0327 
0328     /* perform I/O transfers required for Slave initialization */
0329     return rt1316_io_init(&slave->dev, slave);
0330 }
0331 
0332 static int rt1316_classd_event(struct snd_soc_dapm_widget *w,
0333     struct snd_kcontrol *kcontrol, int event)
0334 {
0335     struct snd_soc_component *component =
0336         snd_soc_dapm_to_component(w->dapm);
0337     struct rt1316_sdw_priv *rt1316 = snd_soc_component_get_drvdata(component);
0338     unsigned char ps0 = 0x0, ps3 = 0x3;
0339 
0340     switch (event) {
0341     case SND_SOC_DAPM_POST_PMU:
0342         regmap_write(rt1316->regmap,
0343             SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23,
0344                 RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
0345                 ps0);
0346         regmap_write(rt1316->regmap,
0347             SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE27,
0348                 RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
0349                 ps0);
0350         regmap_write(rt1316->regmap,
0351             SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22,
0352                 RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
0353                 ps0);
0354         break;
0355     case SND_SOC_DAPM_PRE_PMD:
0356         regmap_write(rt1316->regmap,
0357             SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23,
0358                 RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
0359                 ps3);
0360         regmap_write(rt1316->regmap,
0361             SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE27,
0362                 RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
0363                 ps3);
0364         regmap_write(rt1316->regmap,
0365             SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22,
0366                 RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
0367                 ps3);
0368         break;
0369 
0370     default:
0371         break;
0372     }
0373 
0374     return 0;
0375 }
0376 
0377 static int rt1316_pde24_event(struct snd_soc_dapm_widget *w,
0378     struct snd_kcontrol *kcontrol, int event)
0379 {
0380     struct snd_soc_component *component =
0381         snd_soc_dapm_to_component(w->dapm);
0382     struct rt1316_sdw_priv *rt1316 = snd_soc_component_get_drvdata(component);
0383     unsigned char ps0 = 0x0, ps3 = 0x3;
0384 
0385     switch (event) {
0386     case SND_SOC_DAPM_POST_PMU:
0387         regmap_write(rt1316->regmap,
0388             SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24,
0389                 RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
0390                 ps0);
0391         break;
0392     case SND_SOC_DAPM_PRE_PMD:
0393         regmap_write(rt1316->regmap,
0394             SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24,
0395                 RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
0396                 ps3);
0397         break;
0398     }
0399     return 0;
0400 }
0401 
0402 static const char * const rt1316_rx_data_ch_select[] = {
0403     "L,R",
0404     "L,L",
0405     "L,R",
0406     "L,L+R",
0407     "R,L",
0408     "R,R",
0409     "R,L+R",
0410     "L+R,L",
0411     "L+R,R",
0412     "L+R,L+R",
0413 };
0414 
0415 static SOC_ENUM_SINGLE_DECL(rt1316_rx_data_ch_enum,
0416     SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_UDMPU21, RT1316_SDCA_CTL_UDMPU_CLUSTER, 0), 0,
0417     rt1316_rx_data_ch_select);
0418 
0419 static const struct snd_kcontrol_new rt1316_snd_controls[] = {
0420 
0421     /* I2S Data Channel Selection */
0422     SOC_ENUM("RX Channel Select", rt1316_rx_data_ch_enum),
0423 
0424     /* XU24 Bypass Control */
0425     SOC_SINGLE("XU24 Bypass Switch",
0426         SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_XU24, RT1316_SDCA_CTL_BYPASS, 0), 0, 1, 0),
0427 
0428     /* Left/Right IV tag */
0429     SOC_SINGLE("Left V Tag Select", 0x3004, 0, 7, 0),
0430     SOC_SINGLE("Left I Tag Select", 0x3004, 4, 7, 0),
0431     SOC_SINGLE("Right V Tag Select", 0x3005, 0, 7, 0),
0432     SOC_SINGLE("Right I Tag Select", 0x3005, 4, 7, 0),
0433 
0434     /* IV mixer Control */
0435     SOC_DOUBLE("Isense Mixer Switch", 0xc605, 2, 0, 1, 1),
0436     SOC_DOUBLE("Vsense Mixer Switch", 0xc605, 3, 1, 1, 1),
0437 };
0438 
0439 static const struct snd_kcontrol_new rt1316_sto_dac =
0440     SOC_DAPM_DOUBLE_R("Switch",
0441         SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_L),
0442         SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_R),
0443         0, 1, 1);
0444 
0445 static const struct snd_soc_dapm_widget rt1316_dapm_widgets[] = {
0446     /* Audio Interface */
0447     SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0),
0448     SND_SOC_DAPM_AIF_OUT("DP2TX", "DP2 Capture", 0, SND_SOC_NOPM, 0, 0),
0449 
0450     /* Digital Interface */
0451     SND_SOC_DAPM_SWITCH("DAC", SND_SOC_NOPM, 0, 0, &rt1316_sto_dac),
0452 
0453     /* Output Lines */
0454     SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0,
0455         rt1316_classd_event,
0456         SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
0457     SND_SOC_DAPM_OUTPUT("SPOL"),
0458     SND_SOC_DAPM_OUTPUT("SPOR"),
0459 
0460     SND_SOC_DAPM_SUPPLY("PDE 24", SND_SOC_NOPM, 0, 0,
0461         rt1316_pde24_event,
0462         SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
0463     SND_SOC_DAPM_PGA("I Sense", SND_SOC_NOPM, 0, 0, NULL, 0),
0464     SND_SOC_DAPM_PGA("V Sense", SND_SOC_NOPM, 0, 0, NULL, 0),
0465     SND_SOC_DAPM_SIGGEN("I Gen"),
0466     SND_SOC_DAPM_SIGGEN("V Gen"),
0467 };
0468 
0469 static const struct snd_soc_dapm_route rt1316_dapm_routes[] = {
0470     { "DAC", "Switch", "DP1RX" },
0471     { "CLASS D", NULL, "DAC" },
0472     { "SPOL", NULL, "CLASS D" },
0473     { "SPOR", NULL, "CLASS D" },
0474 
0475     { "I Sense", NULL, "I Gen" },
0476     { "V Sense", NULL, "V Gen" },
0477     { "I Sense", NULL, "PDE 24" },
0478     { "V Sense", NULL, "PDE 24" },
0479     { "DP2TX", NULL, "I Sense" },
0480     { "DP2TX", NULL, "V Sense" },
0481 };
0482 
0483 static int rt1316_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
0484                 int direction)
0485 {
0486     struct sdw_stream_data *stream;
0487 
0488     if (!sdw_stream)
0489         return 0;
0490 
0491     stream = kzalloc(sizeof(*stream), GFP_KERNEL);
0492     if (!stream)
0493         return -ENOMEM;
0494 
0495     stream->sdw_stream = sdw_stream;
0496 
0497     /* Use tx_mask or rx_mask to configure stream tag and set dma_data */
0498     if (direction == SNDRV_PCM_STREAM_PLAYBACK)
0499         dai->playback_dma_data = stream;
0500     else
0501         dai->capture_dma_data = stream;
0502 
0503     return 0;
0504 }
0505 
0506 static void rt1316_sdw_shutdown(struct snd_pcm_substream *substream,
0507                 struct snd_soc_dai *dai)
0508 {
0509     struct sdw_stream_data *stream;
0510 
0511     stream = snd_soc_dai_get_dma_data(dai, substream);
0512     snd_soc_dai_set_dma_data(dai, substream, NULL);
0513     kfree(stream);
0514 }
0515 
0516 static int rt1316_sdw_hw_params(struct snd_pcm_substream *substream,
0517     struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
0518 {
0519     struct snd_soc_component *component = dai->component;
0520     struct rt1316_sdw_priv *rt1316 =
0521         snd_soc_component_get_drvdata(component);
0522     struct sdw_stream_config stream_config;
0523     struct sdw_port_config port_config;
0524     enum sdw_data_direction direction;
0525     struct sdw_stream_data *stream;
0526     int retval, port, num_channels, ch_mask;
0527 
0528     dev_dbg(dai->dev, "%s %s", __func__, dai->name);
0529     stream = snd_soc_dai_get_dma_data(dai, substream);
0530 
0531     if (!stream)
0532         return -EINVAL;
0533 
0534     if (!rt1316->sdw_slave)
0535         return -EINVAL;
0536 
0537     /* SoundWire specific configuration */
0538     /* port 1 for playback */
0539     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0540         direction = SDW_DATA_DIR_RX;
0541         port = 1;
0542     } else {
0543         direction = SDW_DATA_DIR_TX;
0544         port = 2;
0545     }
0546 
0547     num_channels = params_channels(params);
0548     ch_mask = (1 << num_channels) - 1;
0549 
0550     stream_config.frame_rate = params_rate(params);
0551     stream_config.ch_count = num_channels;
0552     stream_config.bps = snd_pcm_format_width(params_format(params));
0553     stream_config.direction = direction;
0554 
0555     port_config.ch_mask = ch_mask;
0556     port_config.num = port;
0557 
0558     retval = sdw_stream_add_slave(rt1316->sdw_slave, &stream_config,
0559                 &port_config, 1, stream->sdw_stream);
0560     if (retval) {
0561         dev_err(dai->dev, "Unable to configure port\n");
0562         return retval;
0563     }
0564 
0565     return 0;
0566 }
0567 
0568 static int rt1316_sdw_pcm_hw_free(struct snd_pcm_substream *substream,
0569                 struct snd_soc_dai *dai)
0570 {
0571     struct snd_soc_component *component = dai->component;
0572     struct rt1316_sdw_priv *rt1316 =
0573         snd_soc_component_get_drvdata(component);
0574     struct sdw_stream_data *stream =
0575         snd_soc_dai_get_dma_data(dai, substream);
0576 
0577     if (!rt1316->sdw_slave)
0578         return -EINVAL;
0579 
0580     sdw_stream_remove_slave(rt1316->sdw_slave, stream->sdw_stream);
0581     return 0;
0582 }
0583 
0584 /*
0585  * slave_ops: callbacks for get_clock_stop_mode, clock_stop and
0586  * port_prep are not defined for now
0587  */
0588 static struct sdw_slave_ops rt1316_slave_ops = {
0589     .read_prop = rt1316_read_prop,
0590     .update_status = rt1316_update_status,
0591 };
0592 
0593 static int rt1316_sdw_component_probe(struct snd_soc_component *component)
0594 {
0595     int ret;
0596 
0597     ret = pm_runtime_resume(component->dev);
0598     if (ret < 0 && ret != -EACCES)
0599         return ret;
0600 
0601     return 0;
0602 }
0603 
0604 static const struct snd_soc_component_driver soc_component_sdw_rt1316 = {
0605     .probe = rt1316_sdw_component_probe,
0606     .controls = rt1316_snd_controls,
0607     .num_controls = ARRAY_SIZE(rt1316_snd_controls),
0608     .dapm_widgets = rt1316_dapm_widgets,
0609     .num_dapm_widgets = ARRAY_SIZE(rt1316_dapm_widgets),
0610     .dapm_routes = rt1316_dapm_routes,
0611     .num_dapm_routes = ARRAY_SIZE(rt1316_dapm_routes),
0612     .endianness = 1,
0613 };
0614 
0615 static const struct snd_soc_dai_ops rt1316_aif_dai_ops = {
0616     .hw_params = rt1316_sdw_hw_params,
0617     .hw_free    = rt1316_sdw_pcm_hw_free,
0618     .set_stream = rt1316_set_sdw_stream,
0619     .shutdown   = rt1316_sdw_shutdown,
0620 };
0621 
0622 #define RT1316_STEREO_RATES SNDRV_PCM_RATE_48000
0623 #define RT1316_FORMATS (SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \
0624             SNDRV_PCM_FMTBIT_S24_LE)
0625 
0626 static struct snd_soc_dai_driver rt1316_sdw_dai[] = {
0627     {
0628         .name = "rt1316-aif",
0629         .playback = {
0630             .stream_name = "DP1 Playback",
0631             .channels_min = 1,
0632             .channels_max = 2,
0633             .rates = RT1316_STEREO_RATES,
0634             .formats = RT1316_FORMATS,
0635         },
0636         .capture = {
0637             .stream_name = "DP2 Capture",
0638             .channels_min = 1,
0639             .channels_max = 2,
0640             .rates = RT1316_STEREO_RATES,
0641             .formats = RT1316_FORMATS,
0642         },
0643         .ops = &rt1316_aif_dai_ops,
0644     },
0645 };
0646 
0647 static int rt1316_sdw_init(struct device *dev, struct regmap *regmap,
0648                 struct sdw_slave *slave)
0649 {
0650     struct rt1316_sdw_priv *rt1316;
0651     int ret;
0652 
0653     rt1316 = devm_kzalloc(dev, sizeof(*rt1316), GFP_KERNEL);
0654     if (!rt1316)
0655         return -ENOMEM;
0656 
0657     dev_set_drvdata(dev, rt1316);
0658     rt1316->sdw_slave = slave;
0659     rt1316->regmap = regmap;
0660 
0661     /*
0662      * Mark hw_init to false
0663      * HW init will be performed when device reports present
0664      */
0665     rt1316->hw_init = false;
0666     rt1316->first_hw_init = false;
0667 
0668     ret =  devm_snd_soc_register_component(dev,
0669                 &soc_component_sdw_rt1316,
0670                 rt1316_sdw_dai,
0671                 ARRAY_SIZE(rt1316_sdw_dai));
0672 
0673     dev_dbg(&slave->dev, "%s\n", __func__);
0674 
0675     return ret;
0676 }
0677 
0678 static int rt1316_sdw_probe(struct sdw_slave *slave,
0679                 const struct sdw_device_id *id)
0680 {
0681     struct regmap *regmap;
0682 
0683     /* Regmap Initialization */
0684     regmap = devm_regmap_init_sdw(slave, &rt1316_sdw_regmap);
0685     if (IS_ERR(regmap))
0686         return PTR_ERR(regmap);
0687 
0688     return rt1316_sdw_init(&slave->dev, regmap, slave);
0689 }
0690 
0691 static int rt1316_sdw_remove(struct sdw_slave *slave)
0692 {
0693     struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(&slave->dev);
0694 
0695     if (rt1316->first_hw_init)
0696         pm_runtime_disable(&slave->dev);
0697 
0698     return 0;
0699 }
0700 
0701 static const struct sdw_device_id rt1316_id[] = {
0702     SDW_SLAVE_ENTRY_EXT(0x025d, 0x1316, 0x3, 0x1, 0),
0703     {},
0704 };
0705 MODULE_DEVICE_TABLE(sdw, rt1316_id);
0706 
0707 static int __maybe_unused rt1316_dev_suspend(struct device *dev)
0708 {
0709     struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(dev);
0710 
0711     if (!rt1316->hw_init)
0712         return 0;
0713 
0714     regcache_cache_only(rt1316->regmap, true);
0715 
0716     return 0;
0717 }
0718 
0719 #define RT1316_PROBE_TIMEOUT 5000
0720 
0721 static int __maybe_unused rt1316_dev_resume(struct device *dev)
0722 {
0723     struct sdw_slave *slave = dev_to_sdw_dev(dev);
0724     struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(dev);
0725     unsigned long time;
0726 
0727     if (!rt1316->first_hw_init)
0728         return 0;
0729 
0730     if (!slave->unattach_request)
0731         goto regmap_sync;
0732 
0733     time = wait_for_completion_timeout(&slave->initialization_complete,
0734                 msecs_to_jiffies(RT1316_PROBE_TIMEOUT));
0735     if (!time) {
0736         dev_err(&slave->dev, "Initialization not complete, timed out\n");
0737         return -ETIMEDOUT;
0738     }
0739 
0740 regmap_sync:
0741     slave->unattach_request = 0;
0742     regcache_cache_only(rt1316->regmap, false);
0743     regcache_sync(rt1316->regmap);
0744 
0745     return 0;
0746 }
0747 
0748 static const struct dev_pm_ops rt1316_pm = {
0749     SET_SYSTEM_SLEEP_PM_OPS(rt1316_dev_suspend, rt1316_dev_resume)
0750     SET_RUNTIME_PM_OPS(rt1316_dev_suspend, rt1316_dev_resume, NULL)
0751 };
0752 
0753 static struct sdw_driver rt1316_sdw_driver = {
0754     .driver = {
0755         .name = "rt1316-sdca",
0756         .owner = THIS_MODULE,
0757         .pm = &rt1316_pm,
0758     },
0759     .probe = rt1316_sdw_probe,
0760     .remove = rt1316_sdw_remove,
0761     .ops = &rt1316_slave_ops,
0762     .id_table = rt1316_id,
0763 };
0764 module_sdw_driver(rt1316_sdw_driver);
0765 
0766 MODULE_DESCRIPTION("ASoC RT1316 driver SDCA SDW");
0767 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>");
0768 MODULE_LICENSE("GPL");
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