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0009 #include <linux/module.h>
0010 #include <linux/moduleparam.h>
0011 #include <linux/init.h>
0012 #include <linux/delay.h>
0013 #include <linux/pm.h>
0014 #include <linux/gpio.h>
0015 #include <linux/i2c.h>
0016 #include <linux/regmap.h>
0017 #include <linux/of_gpio.h>
0018 #include <linux/acpi.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/firmware.h>
0021 #include <sound/core.h>
0022 #include <sound/pcm.h>
0023 #include <sound/pcm_params.h>
0024 #include <sound/soc.h>
0025 #include <sound/soc-dapm.h>
0026 #include <sound/initval.h>
0027 #include <sound/tlv.h>
0028
0029 #include "rl6231.h"
0030 #include "rt1308.h"
0031
0032 static const struct reg_sequence init_list[] = {
0033
0034 { RT1308_I2C_I2S_SDW_SET, 0x01014005 },
0035 { RT1308_CLASS_D_SET_2, 0x227f5501 },
0036 { RT1308_PADS_1, 0x50150505 },
0037 { RT1308_VREF, 0x18100000 },
0038 { RT1308_IV_SENSE, 0x87010000 },
0039 { RT1308_DUMMY_REG, 0x00000200 },
0040 { RT1308_SIL_DET, 0xe1c30000 },
0041 { RT1308_DC_CAL_2, 0x00ffff00 },
0042 { RT1308_CLK_DET, 0x01000000 },
0043 { RT1308_POWER_STATUS, 0x08800000 },
0044 { RT1308_DAC_SET, 0xafaf0700 },
0045
0046 };
0047 #define RT1308_INIT_REG_LEN ARRAY_SIZE(init_list)
0048
0049 struct rt1308_priv {
0050 struct snd_soc_component *component;
0051 struct regmap *regmap;
0052
0053 int sysclk;
0054 int sysclk_src;
0055 int lrck;
0056 int bclk;
0057 int master;
0058
0059 int pll_src;
0060 int pll_in;
0061 int pll_out;
0062 };
0063
0064 static const struct reg_default rt1308_reg[] = {
0065
0066 { 0x01, 0x1f3f5f00 },
0067 { 0x02, 0x07000000 },
0068 { 0x03, 0x80003e00 },
0069 { 0x04, 0x80800600 },
0070 { 0x05, 0x0aaa1a0a },
0071 { 0x06, 0x52000000 },
0072 { 0x07, 0x00000000 },
0073 { 0x08, 0x00600000 },
0074 { 0x09, 0xe1030000 },
0075 { 0x0a, 0x00000000 },
0076 { 0x0b, 0x30000000 },
0077 { 0x0c, 0x7fff7000 },
0078 { 0x10, 0xffff0700 },
0079 { 0x11, 0x0a000000 },
0080 { 0x12, 0x60040000 },
0081 { 0x13, 0x00000000 },
0082 { 0x14, 0x0f300000 },
0083 { 0x15, 0x00000022 },
0084 { 0x16, 0x02000000 },
0085 { 0x17, 0x01004045 },
0086 { 0x18, 0x00000000 },
0087 { 0x19, 0x00000000 },
0088 { 0x1a, 0x80000000 },
0089 { 0x1b, 0x10325476 },
0090 { 0x1c, 0x1d1d0000 },
0091 { 0x20, 0xd2101300 },
0092 { 0x21, 0xf3ffff00 },
0093 { 0x22, 0x00000000 },
0094 { 0x23, 0x00000000 },
0095 { 0x24, 0x00000000 },
0096 { 0x25, 0x00000000 },
0097 { 0x26, 0x00000000 },
0098 { 0x27, 0x00000000 },
0099 { 0x28, 0x00000000 },
0100 { 0x29, 0x00000000 },
0101 { 0x2a, 0x00000000 },
0102 { 0x2b, 0x00000000 },
0103 { 0x2c, 0x00000000 },
0104 { 0x2d, 0x00000000 },
0105 { 0x2e, 0x00000000 },
0106 { 0x2f, 0x00000000 },
0107 { 0x30, 0x01000000 },
0108 { 0x31, 0x20025501 },
0109 { 0x32, 0x00000000 },
0110 { 0x33, 0x105a0000 },
0111 { 0x34, 0x10100000 },
0112 { 0x35, 0x2aaa52aa },
0113 { 0x36, 0x00c00000 },
0114 { 0x37, 0x20046100 },
0115 { 0x50, 0x10022f00 },
0116 { 0x51, 0x003c0000 },
0117 { 0x54, 0x04000000 },
0118 { 0x55, 0x01000000 },
0119 { 0x56, 0x02000000 },
0120 { 0x57, 0x02000000 },
0121 { 0x58, 0x02000000 },
0122 { 0x59, 0x02000000 },
0123 { 0x5b, 0x02000000 },
0124 { 0x5c, 0x00000000 },
0125 { 0x5d, 0x00000000 },
0126 { 0x5e, 0x00000000 },
0127 { 0x5f, 0x00000000 },
0128 { 0x60, 0x02000000 },
0129 { 0x61, 0x00000000 },
0130 { 0x62, 0x00000000 },
0131 { 0x63, 0x00000000 },
0132 { 0x64, 0x00000000 },
0133 { 0x65, 0x02000000 },
0134 { 0x66, 0x00000000 },
0135 { 0x67, 0x00000000 },
0136 { 0x68, 0x00000000 },
0137 { 0x69, 0x00000000 },
0138 { 0x6a, 0x02000000 },
0139 { 0x6c, 0x00000000 },
0140 { 0x6d, 0x00000000 },
0141 { 0x6e, 0x00000000 },
0142 { 0x70, 0x10EC1308 },
0143 { 0x71, 0x00000000 },
0144 { 0x72, 0x00000000 },
0145 { 0x73, 0x00000000 },
0146 { 0x74, 0x00000000 },
0147 { 0x75, 0x00000000 },
0148 { 0x76, 0x00000000 },
0149 { 0x77, 0x00000000 },
0150 { 0x78, 0x00000000 },
0151 { 0x79, 0x00000000 },
0152 { 0x7a, 0x00000000 },
0153 { 0x7b, 0x00000000 },
0154 { 0x7c, 0x00000000 },
0155 { 0x7d, 0x00000000 },
0156 { 0x7e, 0x00000000 },
0157 { 0x7f, 0x00020f00 },
0158 { 0x80, 0x00000000 },
0159 { 0x81, 0x00000000 },
0160 { 0x82, 0x00000000 },
0161 { 0x83, 0x00000000 },
0162 { 0x84, 0x00000000 },
0163 { 0x85, 0x00000000 },
0164 { 0x86, 0x00000000 },
0165 { 0x87, 0x00000000 },
0166 { 0x88, 0x00000000 },
0167 { 0x89, 0x00000000 },
0168 { 0x8a, 0x00000000 },
0169 { 0x8b, 0x00000000 },
0170 { 0x8c, 0x00000000 },
0171 { 0x8d, 0x00000000 },
0172 { 0x8e, 0x00000000 },
0173 { 0x90, 0x50250905 },
0174 { 0x91, 0x15050000 },
0175 { 0xa0, 0x00000000 },
0176 { 0xa1, 0x00000000 },
0177 { 0xa2, 0x00000000 },
0178 { 0xa3, 0x00000000 },
0179 { 0xa4, 0x00000000 },
0180 { 0xb0, 0x00000000 },
0181 { 0xb1, 0x00000000 },
0182 { 0xb2, 0x00000000 },
0183 { 0xb3, 0x00000000 },
0184 { 0xb4, 0x00000000 },
0185 { 0xb5, 0x00000000 },
0186 { 0xb6, 0x00000000 },
0187 { 0xb7, 0x00000000 },
0188 { 0xb8, 0x00000000 },
0189 { 0xb9, 0x00000000 },
0190 { 0xba, 0x00000000 },
0191 { 0xbb, 0x00000000 },
0192 { 0xc0, 0x01000000 },
0193 { 0xc1, 0x00000000 },
0194 { 0xf0, 0x00000000 },
0195 };
0196
0197 static int rt1308_reg_init(struct snd_soc_component *component)
0198 {
0199 struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
0200
0201 return regmap_multi_reg_write(rt1308->regmap, init_list,
0202 RT1308_INIT_REG_LEN);
0203 }
0204
0205 static bool rt1308_volatile_register(struct device *dev, unsigned int reg)
0206 {
0207 switch (reg) {
0208 case RT1308_RESET:
0209 case RT1308_RESET_N:
0210 case RT1308_CLK_2:
0211 case RT1308_SIL_DET:
0212 case RT1308_CLK_DET:
0213 case RT1308_DC_DET:
0214 case RT1308_DAC_SET:
0215 case RT1308_DAC_BUF:
0216 case RT1308_SDW_REG_RDATA:
0217 case RT1308_DC_CAL_1:
0218 case RT1308_PVDD_OFFSET_CTL:
0219 case RT1308_CAL_OFFSET_DAC_PBTL:
0220 case RT1308_CAL_OFFSET_DAC_L:
0221 case RT1308_CAL_OFFSET_DAC_R:
0222 case RT1308_CAL_OFFSET_PWM_L:
0223 case RT1308_CAL_OFFSET_PWM_R:
0224 case RT1308_CAL_PWM_VOS_ADC_L:
0225 case RT1308_CAL_PWM_VOS_ADC_R:
0226 case RT1308_MBIAS:
0227 case RT1308_POWER_STATUS:
0228 case RT1308_POWER_INT:
0229 case RT1308_SINE_TONE_GEN_2:
0230 case RT1308_BQ_SET:
0231 case RT1308_BQ_PARA_UPDATE:
0232 case RT1308_VEN_DEV_ID:
0233 case RT1308_VERSION_ID:
0234 case RT1308_EFUSE_1:
0235 case RT1308_EFUSE_READ_PVDD_L:
0236 case RT1308_EFUSE_READ_PVDD_R:
0237 case RT1308_EFUSE_READ_PVDD_PTBL:
0238 case RT1308_EFUSE_READ_DEV:
0239 case RT1308_EFUSE_READ_R0:
0240 case RT1308_EFUSE_READ_ADC_L:
0241 case RT1308_EFUSE_READ_ADC_R:
0242 case RT1308_EFUSE_READ_ADC_PBTL:
0243 case RT1308_EFUSE_RESERVE:
0244 case RT1308_EFUSE_DATA_0_MSB:
0245 case RT1308_EFUSE_DATA_0_LSB:
0246 case RT1308_EFUSE_DATA_1_MSB:
0247 case RT1308_EFUSE_DATA_1_LSB:
0248 case RT1308_EFUSE_DATA_2_MSB:
0249 case RT1308_EFUSE_DATA_2_LSB:
0250 case RT1308_EFUSE_DATA_3_MSB:
0251 case RT1308_EFUSE_DATA_3_LSB:
0252 case RT1308_EFUSE_STATUS_1:
0253 case RT1308_EFUSE_STATUS_2:
0254 case RT1308_DUMMY_REG:
0255 return true;
0256 default:
0257 return false;
0258 }
0259 }
0260
0261 static bool rt1308_readable_register(struct device *dev, unsigned int reg)
0262 {
0263 switch (reg) {
0264 case RT1308_RESET:
0265 case RT1308_RESET_N:
0266 case RT1308_CLK_GATING ... RT1308_DC_DET_THRES:
0267 case RT1308_DAC_SET ... RT1308_AD_FILTER_SET:
0268 case RT1308_DC_CAL_1 ... RT1308_POWER_INT:
0269 case RT1308_SINE_TONE_GEN_1:
0270 case RT1308_SINE_TONE_GEN_2:
0271 case RT1308_BQ_SET:
0272 case RT1308_BQ_PARA_UPDATE:
0273 case RT1308_BQ_PRE_VOL_L ... RT1308_BQ_POST_VOL_R:
0274 case RT1308_BQ1_L_H0 ... RT1308_BQ2_R_A2:
0275 case RT1308_VEN_DEV_ID:
0276 case RT1308_VERSION_ID:
0277 case RT1308_SPK_BOUND:
0278 case RT1308_BQ1_EQ_L_1 ... RT1308_BQ2_EQ_R_3:
0279 case RT1308_EFUSE_1 ... RT1308_EFUSE_RESERVE:
0280 case RT1308_PADS_1:
0281 case RT1308_PADS_2:
0282 case RT1308_TEST_MODE:
0283 case RT1308_TEST_1:
0284 case RT1308_TEST_2:
0285 case RT1308_TEST_3:
0286 case RT1308_TEST_4:
0287 case RT1308_EFUSE_DATA_0_MSB ... RT1308_EFUSE_STATUS_2:
0288 case RT1308_TCON_1:
0289 case RT1308_TCON_2:
0290 case RT1308_DUMMY_REG:
0291 case RT1308_MAX_REG:
0292 return true;
0293 default:
0294 return false;
0295 }
0296 }
0297
0298 static int rt1308_classd_event(struct snd_soc_dapm_widget *w,
0299 struct snd_kcontrol *kcontrol, int event)
0300 {
0301 struct snd_soc_component *component =
0302 snd_soc_dapm_to_component(w->dapm);
0303
0304 switch (event) {
0305 case SND_SOC_DAPM_POST_PMU:
0306 msleep(30);
0307 snd_soc_component_update_bits(component, RT1308_POWER_STATUS,
0308 RT1308_POW_PDB_REG_BIT | RT1308_POW_PDB_MN_BIT,
0309 RT1308_POW_PDB_REG_BIT | RT1308_POW_PDB_MN_BIT);
0310 msleep(40);
0311 break;
0312 case SND_SOC_DAPM_PRE_PMD:
0313 snd_soc_component_update_bits(component, RT1308_POWER_STATUS,
0314 RT1308_POW_PDB_REG_BIT | RT1308_POW_PDB_MN_BIT, 0);
0315 usleep_range(150000, 200000);
0316 break;
0317
0318 default:
0319 break;
0320 }
0321
0322 return 0;
0323 }
0324
0325 static const char * const rt1308_rx_data_ch_select[] = {
0326 "LR",
0327 "LL",
0328 "RL",
0329 "RR",
0330 };
0331
0332 static SOC_ENUM_SINGLE_DECL(rt1308_rx_data_ch_enum, RT1308_DATA_PATH, 24,
0333 rt1308_rx_data_ch_select);
0334
0335 static const struct snd_kcontrol_new rt1308_snd_controls[] = {
0336
0337
0338 SOC_ENUM("RX Channel Select", rt1308_rx_data_ch_enum),
0339 };
0340
0341 static const struct snd_kcontrol_new rt1308_sto_dac_l =
0342 SOC_DAPM_SINGLE("Switch", RT1308_DAC_SET,
0343 RT1308_DVOL_MUTE_L_EN_SFT, 1, 1);
0344
0345 static const struct snd_kcontrol_new rt1308_sto_dac_r =
0346 SOC_DAPM_SINGLE("Switch", RT1308_DAC_SET,
0347 RT1308_DVOL_MUTE_R_EN_SFT, 1, 1);
0348
0349 static const struct snd_soc_dapm_widget rt1308_dapm_widgets[] = {
0350
0351 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
0352
0353
0354 SND_SOC_DAPM_SUPPLY("MBIAS20U", RT1308_POWER,
0355 RT1308_POW_MBIAS20U_BIT, 0, NULL, 0),
0356 SND_SOC_DAPM_SUPPLY("ALDO", RT1308_POWER,
0357 RT1308_POW_ALDO_BIT, 0, NULL, 0),
0358 SND_SOC_DAPM_SUPPLY("DBG", RT1308_POWER,
0359 RT1308_POW_DBG_BIT, 0, NULL, 0),
0360 SND_SOC_DAPM_SUPPLY("DACL", RT1308_POWER,
0361 RT1308_POW_DACL_BIT, 0, NULL, 0),
0362 SND_SOC_DAPM_SUPPLY("CLK25M", RT1308_POWER,
0363 RT1308_POW_CLK25M_BIT, 0, NULL, 0),
0364 SND_SOC_DAPM_SUPPLY("ADC_R", RT1308_POWER,
0365 RT1308_POW_ADC_R_BIT, 0, NULL, 0),
0366 SND_SOC_DAPM_SUPPLY("ADC_L", RT1308_POWER,
0367 RT1308_POW_ADC_L_BIT, 0, NULL, 0),
0368 SND_SOC_DAPM_SUPPLY("DLDO", RT1308_POWER,
0369 RT1308_POW_DLDO_BIT, 0, NULL, 0),
0370 SND_SOC_DAPM_SUPPLY("VREF", RT1308_POWER,
0371 RT1308_POW_VREF_BIT, 0, NULL, 0),
0372 SND_SOC_DAPM_SUPPLY("MIXER_R", RT1308_POWER,
0373 RT1308_POW_MIXER_R_BIT, 0, NULL, 0),
0374 SND_SOC_DAPM_SUPPLY("MIXER_L", RT1308_POWER,
0375 RT1308_POW_MIXER_L_BIT, 0, NULL, 0),
0376 SND_SOC_DAPM_SUPPLY("MBIAS4U", RT1308_POWER,
0377 RT1308_POW_MBIAS4U_BIT, 0, NULL, 0),
0378 SND_SOC_DAPM_SUPPLY("PLL2_LDO", RT1308_POWER,
0379 RT1308_POW_PLL2_LDO_EN_BIT, 0, NULL, 0),
0380 SND_SOC_DAPM_SUPPLY("PLL2B", RT1308_POWER,
0381 RT1308_POW_PLL2B_EN_BIT, 0, NULL, 0),
0382 SND_SOC_DAPM_SUPPLY("PLL2F", RT1308_POWER,
0383 RT1308_POW_PLL2F_EN_BIT, 0, NULL, 0),
0384 SND_SOC_DAPM_SUPPLY("PLL2F2", RT1308_POWER,
0385 RT1308_POW_PLL2F2_EN_BIT, 0, NULL, 0),
0386 SND_SOC_DAPM_SUPPLY("PLL2B2", RT1308_POWER,
0387 RT1308_POW_PLL2B2_EN_BIT, 0, NULL, 0),
0388
0389
0390 SND_SOC_DAPM_SUPPLY("DAC Power", RT1308_POWER,
0391 RT1308_POW_DAC1_BIT, 0, NULL, 0),
0392 SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
0393 SND_SOC_DAPM_SWITCH("DAC L", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_l),
0394 SND_SOC_DAPM_SWITCH("DAC R", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_r),
0395
0396
0397 SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0,
0398 rt1308_classd_event,
0399 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
0400 SND_SOC_DAPM_OUTPUT("SPOL"),
0401 SND_SOC_DAPM_OUTPUT("SPOR"),
0402 };
0403
0404 static const struct snd_soc_dapm_route rt1308_dapm_routes[] = {
0405
0406 { "DAC", NULL, "AIF1RX" },
0407
0408 { "DAC", NULL, "MBIAS20U" },
0409 { "DAC", NULL, "ALDO" },
0410 { "DAC", NULL, "DBG" },
0411 { "DAC", NULL, "DACL" },
0412 { "DAC", NULL, "CLK25M" },
0413 { "DAC", NULL, "ADC_R" },
0414 { "DAC", NULL, "ADC_L" },
0415 { "DAC", NULL, "DLDO" },
0416 { "DAC", NULL, "VREF" },
0417 { "DAC", NULL, "MIXER_R" },
0418 { "DAC", NULL, "MIXER_L" },
0419 { "DAC", NULL, "MBIAS4U" },
0420 { "DAC", NULL, "PLL2_LDO" },
0421 { "DAC", NULL, "PLL2B" },
0422 { "DAC", NULL, "PLL2F" },
0423 { "DAC", NULL, "PLL2F2" },
0424 { "DAC", NULL, "PLL2B2" },
0425
0426 { "DAC L", "Switch", "DAC" },
0427 { "DAC R", "Switch", "DAC" },
0428 { "DAC L", NULL, "DAC Power" },
0429 { "DAC R", NULL, "DAC Power" },
0430
0431 { "CLASS D", NULL, "DAC L" },
0432 { "CLASS D", NULL, "DAC R" },
0433 { "SPOL", NULL, "CLASS D" },
0434 { "SPOR", NULL, "CLASS D" },
0435 };
0436
0437 static int rt1308_get_clk_info(int sclk, int rate)
0438 {
0439 int i;
0440 static const int pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
0441
0442 if (sclk <= 0 || rate <= 0)
0443 return -EINVAL;
0444
0445 rate = rate << 8;
0446 for (i = 0; i < ARRAY_SIZE(pd); i++)
0447 if (sclk == rate * pd[i])
0448 return i;
0449
0450 return -EINVAL;
0451 }
0452
0453 static int rt1308_hw_params(struct snd_pcm_substream *substream,
0454 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
0455 {
0456 struct snd_soc_component *component = dai->component;
0457 struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
0458 unsigned int val_len = 0, val_clk, mask_clk;
0459 int pre_div, bclk_ms, frame_size;
0460
0461 rt1308->lrck = params_rate(params);
0462 pre_div = rt1308_get_clk_info(rt1308->sysclk, rt1308->lrck);
0463 if (pre_div < 0) {
0464 dev_err(component->dev,
0465 "Unsupported clock setting %d\n", rt1308->lrck);
0466 return -EINVAL;
0467 }
0468
0469 frame_size = snd_soc_params_to_frame_size(params);
0470 if (frame_size < 0) {
0471 dev_err(component->dev, "Unsupported frame size: %d\n",
0472 frame_size);
0473 return -EINVAL;
0474 }
0475
0476 bclk_ms = frame_size > 32;
0477 rt1308->bclk = rt1308->lrck * (32 << bclk_ms);
0478
0479 dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
0480 bclk_ms, pre_div, dai->id);
0481
0482 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
0483 rt1308->lrck, pre_div, dai->id);
0484
0485 switch (params_width(params)) {
0486 case 16:
0487 val_len |= RT1308_I2S_DL_SEL_16B;
0488 break;
0489 case 20:
0490 val_len |= RT1308_I2S_DL_SEL_20B;
0491 break;
0492 case 24:
0493 val_len |= RT1308_I2S_DL_SEL_24B;
0494 break;
0495 case 8:
0496 val_len |= RT1308_I2S_DL_SEL_8B;
0497 break;
0498 default:
0499 return -EINVAL;
0500 }
0501
0502 switch (dai->id) {
0503 case RT1308_AIF1:
0504 mask_clk = RT1308_DIV_FS_SYS_MASK;
0505 val_clk = pre_div << RT1308_DIV_FS_SYS_SFT;
0506 snd_soc_component_update_bits(component,
0507 RT1308_I2S_SET_2, RT1308_I2S_DL_SEL_MASK,
0508 val_len);
0509 break;
0510 default:
0511 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
0512 return -EINVAL;
0513 }
0514
0515 snd_soc_component_update_bits(component, RT1308_CLK_1,
0516 mask_clk, val_clk);
0517
0518 return 0;
0519 }
0520
0521 static int rt1308_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
0522 {
0523 struct snd_soc_component *component = dai->component;
0524 struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
0525 unsigned int reg_val = 0, reg1_val = 0;
0526
0527 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
0528 case SND_SOC_DAIFMT_CBS_CFS:
0529 rt1308->master = 0;
0530 break;
0531 default:
0532 return -EINVAL;
0533 }
0534
0535 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0536 case SND_SOC_DAIFMT_I2S:
0537 break;
0538 case SND_SOC_DAIFMT_LEFT_J:
0539 reg_val |= RT1308_I2S_DF_SEL_LEFT;
0540 break;
0541 case SND_SOC_DAIFMT_DSP_A:
0542 reg_val |= RT1308_I2S_DF_SEL_PCM_A;
0543 break;
0544 case SND_SOC_DAIFMT_DSP_B:
0545 reg_val |= RT1308_I2S_DF_SEL_PCM_B;
0546 break;
0547 default:
0548 return -EINVAL;
0549 }
0550
0551 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0552 case SND_SOC_DAIFMT_NB_NF:
0553 break;
0554 case SND_SOC_DAIFMT_IB_NF:
0555 reg1_val |= RT1308_I2S_BCLK_INV;
0556 break;
0557 default:
0558 return -EINVAL;
0559 }
0560
0561 switch (dai->id) {
0562 case RT1308_AIF1:
0563 snd_soc_component_update_bits(component,
0564 RT1308_I2S_SET_1, RT1308_I2S_DF_SEL_MASK,
0565 reg_val);
0566 snd_soc_component_update_bits(component,
0567 RT1308_I2S_SET_2, RT1308_I2S_BCLK_MASK,
0568 reg1_val);
0569 break;
0570 default:
0571 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
0572 return -EINVAL;
0573 }
0574 return 0;
0575 }
0576
0577 static int rt1308_set_component_sysclk(struct snd_soc_component *component,
0578 int clk_id, int source, unsigned int freq, int dir)
0579 {
0580 struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
0581 unsigned int reg_val = 0;
0582
0583 if (freq == rt1308->sysclk && clk_id == rt1308->sysclk_src)
0584 return 0;
0585
0586 switch (clk_id) {
0587 case RT1308_FS_SYS_S_MCLK:
0588 reg_val |= RT1308_SEL_FS_SYS_SRC_MCLK;
0589 snd_soc_component_update_bits(component,
0590 RT1308_CLK_DET, RT1308_MCLK_DET_EN_MASK,
0591 RT1308_MCLK_DET_EN);
0592 break;
0593 case RT1308_FS_SYS_S_BCLK:
0594 reg_val |= RT1308_SEL_FS_SYS_SRC_BCLK;
0595 break;
0596 case RT1308_FS_SYS_S_PLL:
0597 reg_val |= RT1308_SEL_FS_SYS_SRC_PLL;
0598 break;
0599 case RT1308_FS_SYS_S_RCCLK:
0600 reg_val |= RT1308_SEL_FS_SYS_SRC_RCCLK;
0601 break;
0602 default:
0603 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
0604 return -EINVAL;
0605 }
0606 snd_soc_component_update_bits(component, RT1308_CLK_1,
0607 RT1308_SEL_FS_SYS_MASK, reg_val);
0608 rt1308->sysclk = freq;
0609 rt1308->sysclk_src = clk_id;
0610
0611 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
0612 freq, clk_id);
0613
0614 return 0;
0615 }
0616
0617 static int rt1308_set_component_pll(struct snd_soc_component *component,
0618 int pll_id, int source, unsigned int freq_in,
0619 unsigned int freq_out)
0620 {
0621 struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
0622 struct rl6231_pll_code pll_code;
0623 int ret;
0624
0625 if (source == rt1308->pll_src && freq_in == rt1308->pll_in &&
0626 freq_out == rt1308->pll_out)
0627 return 0;
0628
0629 if (!freq_in || !freq_out) {
0630 dev_dbg(component->dev, "PLL disabled\n");
0631
0632 rt1308->pll_in = 0;
0633 rt1308->pll_out = 0;
0634 snd_soc_component_update_bits(component,
0635 RT1308_CLK_1, RT1308_SEL_FS_SYS_MASK,
0636 RT1308_SEL_FS_SYS_SRC_MCLK);
0637 return 0;
0638 }
0639
0640 switch (source) {
0641 case RT1308_PLL_S_MCLK:
0642 snd_soc_component_update_bits(component,
0643 RT1308_CLK_2, RT1308_SEL_PLL_SRC_MASK,
0644 RT1308_SEL_PLL_SRC_MCLK);
0645 snd_soc_component_update_bits(component,
0646 RT1308_CLK_DET, RT1308_MCLK_DET_EN_MASK,
0647 RT1308_MCLK_DET_EN);
0648 break;
0649 case RT1308_PLL_S_BCLK:
0650 snd_soc_component_update_bits(component,
0651 RT1308_CLK_2, RT1308_SEL_PLL_SRC_MASK,
0652 RT1308_SEL_PLL_SRC_BCLK);
0653 break;
0654 case RT1308_PLL_S_RCCLK:
0655 snd_soc_component_update_bits(component,
0656 RT1308_CLK_2, RT1308_SEL_PLL_SRC_MASK,
0657 RT1308_SEL_PLL_SRC_RCCLK);
0658 freq_in = 25000000;
0659 break;
0660 default:
0661 dev_err(component->dev, "Unknown PLL Source %d\n", source);
0662 return -EINVAL;
0663 }
0664
0665 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
0666 if (ret < 0) {
0667 dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
0668 return ret;
0669 }
0670
0671 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
0672 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
0673 pll_code.n_code, pll_code.k_code);
0674
0675 snd_soc_component_write(component, RT1308_PLL_1,
0676 (pll_code.k_code << RT1308_PLL1_K_SFT) |
0677 (pll_code.m_bp << RT1308_PLL1_M_BYPASS_SFT) |
0678 ((pll_code.m_bp ? 0 : pll_code.m_code) << RT1308_PLL1_M_SFT) |
0679 (pll_code.n_code << RT1308_PLL1_N_SFT));
0680
0681 rt1308->pll_in = freq_in;
0682 rt1308->pll_out = freq_out;
0683 rt1308->pll_src = source;
0684
0685 return 0;
0686 }
0687
0688 static int rt1308_probe(struct snd_soc_component *component)
0689 {
0690 struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
0691
0692 rt1308->component = component;
0693
0694 return rt1308_reg_init(component);
0695 }
0696
0697 static void rt1308_remove(struct snd_soc_component *component)
0698 {
0699 struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
0700
0701 regmap_write(rt1308->regmap, RT1308_RESET, 0);
0702 }
0703
0704 #ifdef CONFIG_PM
0705 static int rt1308_suspend(struct snd_soc_component *component)
0706 {
0707 struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
0708
0709 regcache_cache_only(rt1308->regmap, true);
0710 regcache_mark_dirty(rt1308->regmap);
0711
0712 return 0;
0713 }
0714
0715 static int rt1308_resume(struct snd_soc_component *component)
0716 {
0717 struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
0718
0719 regcache_cache_only(rt1308->regmap, false);
0720 regcache_sync(rt1308->regmap);
0721
0722 return 0;
0723 }
0724 #else
0725 #define rt1308_suspend NULL
0726 #define rt1308_resume NULL
0727 #endif
0728
0729 #define RT1308_STEREO_RATES SNDRV_PCM_RATE_48000
0730 #define RT1308_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
0731 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \
0732 SNDRV_PCM_FMTBIT_S24_LE)
0733
0734 static const struct snd_soc_dai_ops rt1308_aif_dai_ops = {
0735 .hw_params = rt1308_hw_params,
0736 .set_fmt = rt1308_set_dai_fmt,
0737 };
0738
0739 static struct snd_soc_dai_driver rt1308_dai[] = {
0740 {
0741 .name = "rt1308-aif",
0742 .playback = {
0743 .stream_name = "AIF1 Playback",
0744 .channels_min = 1,
0745 .channels_max = 2,
0746 .rates = RT1308_STEREO_RATES,
0747 .formats = RT1308_FORMATS,
0748 },
0749 .ops = &rt1308_aif_dai_ops,
0750 },
0751 };
0752
0753 static const struct snd_soc_component_driver soc_component_dev_rt1308 = {
0754 .probe = rt1308_probe,
0755 .remove = rt1308_remove,
0756 .suspend = rt1308_suspend,
0757 .resume = rt1308_resume,
0758 .controls = rt1308_snd_controls,
0759 .num_controls = ARRAY_SIZE(rt1308_snd_controls),
0760 .dapm_widgets = rt1308_dapm_widgets,
0761 .num_dapm_widgets = ARRAY_SIZE(rt1308_dapm_widgets),
0762 .dapm_routes = rt1308_dapm_routes,
0763 .num_dapm_routes = ARRAY_SIZE(rt1308_dapm_routes),
0764 .set_sysclk = rt1308_set_component_sysclk,
0765 .set_pll = rt1308_set_component_pll,
0766 .use_pmdown_time = 1,
0767 .endianness = 1,
0768 };
0769
0770 static const struct regmap_config rt1308_regmap = {
0771 .reg_bits = 8,
0772 .val_bits = 32,
0773 .max_register = RT1308_MAX_REG,
0774 .volatile_reg = rt1308_volatile_register,
0775 .readable_reg = rt1308_readable_register,
0776 .cache_type = REGCACHE_RBTREE,
0777 .reg_defaults = rt1308_reg,
0778 .num_reg_defaults = ARRAY_SIZE(rt1308_reg),
0779 .use_single_read = true,
0780 .use_single_write = true,
0781 };
0782
0783 #ifdef CONFIG_OF
0784 static const struct of_device_id rt1308_of_match[] = {
0785 { .compatible = "realtek,rt1308", },
0786 { },
0787 };
0788 MODULE_DEVICE_TABLE(of, rt1308_of_match);
0789 #endif
0790
0791 #ifdef CONFIG_ACPI
0792 static const struct acpi_device_id rt1308_acpi_match[] = {
0793 { "10EC1308", 0, },
0794 { },
0795 };
0796 MODULE_DEVICE_TABLE(acpi, rt1308_acpi_match);
0797 #endif
0798
0799 static const struct i2c_device_id rt1308_i2c_id[] = {
0800 { "rt1308", 0 },
0801 { }
0802 };
0803 MODULE_DEVICE_TABLE(i2c, rt1308_i2c_id);
0804
0805 static void rt1308_efuse(struct rt1308_priv *rt1308)
0806 {
0807 regmap_write(rt1308->regmap, RT1308_RESET, 0);
0808
0809 regmap_write(rt1308->regmap, RT1308_POWER_STATUS, 0x01800000);
0810 msleep(100);
0811 regmap_write(rt1308->regmap, RT1308_EFUSE_1, 0x44fe0f00);
0812 msleep(20);
0813 regmap_write(rt1308->regmap, RT1308_PVDD_OFFSET_CTL, 0x10000000);
0814 }
0815
0816 static int rt1308_i2c_probe(struct i2c_client *i2c)
0817 {
0818 struct rt1308_priv *rt1308;
0819 int ret;
0820 unsigned int val;
0821
0822 rt1308 = devm_kzalloc(&i2c->dev, sizeof(struct rt1308_priv),
0823 GFP_KERNEL);
0824 if (rt1308 == NULL)
0825 return -ENOMEM;
0826
0827 i2c_set_clientdata(i2c, rt1308);
0828
0829 rt1308->regmap = devm_regmap_init_i2c(i2c, &rt1308_regmap);
0830 if (IS_ERR(rt1308->regmap)) {
0831 ret = PTR_ERR(rt1308->regmap);
0832 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
0833 ret);
0834 return ret;
0835 }
0836
0837 regmap_read(rt1308->regmap, RT1308_VEN_DEV_ID, &val);
0838
0839 if ((val & 0xFFFFFF00) != RT1308_DEVICE_ID_NUM) {
0840 dev_err(&i2c->dev,
0841 "Device with ID register %x is not rt1308\n", val);
0842 return -ENODEV;
0843 }
0844
0845 rt1308_efuse(rt1308);
0846
0847 return devm_snd_soc_register_component(&i2c->dev,
0848 &soc_component_dev_rt1308,
0849 rt1308_dai, ARRAY_SIZE(rt1308_dai));
0850 }
0851
0852 static void rt1308_i2c_shutdown(struct i2c_client *client)
0853 {
0854 struct rt1308_priv *rt1308 = i2c_get_clientdata(client);
0855
0856 regmap_write(rt1308->regmap, RT1308_RESET, 0);
0857 }
0858
0859 static struct i2c_driver rt1308_i2c_driver = {
0860 .driver = {
0861 .name = "rt1308",
0862 .of_match_table = of_match_ptr(rt1308_of_match),
0863 .acpi_match_table = ACPI_PTR(rt1308_acpi_match),
0864 },
0865 .probe_new = rt1308_i2c_probe,
0866 .shutdown = rt1308_i2c_shutdown,
0867 .id_table = rt1308_i2c_id,
0868 };
0869 module_i2c_driver(rt1308_i2c_driver);
0870
0871 MODULE_DESCRIPTION("ASoC RT1308 amplifier driver");
0872 MODULE_AUTHOR("Derek Fang <derek.fang@realtek.com>");
0873 MODULE_LICENSE("GPL v2");
