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0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // rt1308-sdw.c -- rt1308 ALSA SoC audio driver
0004 //
0005 // Copyright(c) 2019 Realtek Semiconductor Corp.
0006 //
0007 //
0008 #include <linux/delay.h>
0009 #include <linux/device.h>
0010 #include <linux/pm_runtime.h>
0011 #include <linux/mod_devicetable.h>
0012 #include <linux/soundwire/sdw.h>
0013 #include <linux/soundwire/sdw_type.h>
0014 #include <linux/soundwire/sdw_registers.h>
0015 #include <linux/module.h>
0016 #include <linux/regmap.h>
0017 #include <sound/core.h>
0018 #include <sound/pcm.h>
0019 #include <sound/pcm_params.h>
0020 #include <sound/soc.h>
0021 #include <sound/soc-dapm.h>
0022 #include <sound/initval.h>
0023 
0024 #include "rt1308.h"
0025 #include "rt1308-sdw.h"
0026 
0027 static bool rt1308_readable_register(struct device *dev, unsigned int reg)
0028 {
0029     switch (reg) {
0030     case 0x00e0:
0031     case 0x00f0:
0032     case 0x2f01 ... 0x2f07:
0033     case 0x3000 ... 0x3001:
0034     case 0x3004 ... 0x3005:
0035     case 0x3008:
0036     case 0x300a:
0037     case 0xc000 ... 0xcff3:
0038         return true;
0039     default:
0040         return false;
0041     }
0042 }
0043 
0044 static bool rt1308_volatile_register(struct device *dev, unsigned int reg)
0045 {
0046     switch (reg) {
0047     case 0x2f01 ... 0x2f07:
0048     case 0x3000 ... 0x3001:
0049     case 0x3004 ... 0x3005:
0050     case 0x3008:
0051     case 0x300a:
0052     case 0xc000:
0053     case 0xc860 ... 0xc863:
0054     case 0xc870 ... 0xc873:
0055         return true;
0056     default:
0057         return false;
0058     }
0059 }
0060 
0061 static const struct regmap_config rt1308_sdw_regmap = {
0062     .reg_bits = 32,
0063     .val_bits = 8,
0064     .readable_reg = rt1308_readable_register,
0065     .volatile_reg = rt1308_volatile_register,
0066     .max_register = 0xcfff,
0067     .reg_defaults = rt1308_reg_defaults,
0068     .num_reg_defaults = ARRAY_SIZE(rt1308_reg_defaults),
0069     .cache_type = REGCACHE_RBTREE,
0070     .use_single_read = true,
0071     .use_single_write = true,
0072 };
0073 
0074 /* Bus clock frequency */
0075 #define RT1308_CLK_FREQ_9600000HZ 9600000
0076 #define RT1308_CLK_FREQ_12000000HZ 12000000
0077 #define RT1308_CLK_FREQ_6000000HZ 6000000
0078 #define RT1308_CLK_FREQ_4800000HZ 4800000
0079 #define RT1308_CLK_FREQ_2400000HZ 2400000
0080 #define RT1308_CLK_FREQ_12288000HZ 12288000
0081 
0082 static int rt1308_clock_config(struct device *dev)
0083 {
0084     struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev);
0085     unsigned int clk_freq, value;
0086 
0087     clk_freq = (rt1308->params.curr_dr_freq >> 1);
0088 
0089     switch (clk_freq) {
0090     case RT1308_CLK_FREQ_12000000HZ:
0091         value = 0x0;
0092         break;
0093     case RT1308_CLK_FREQ_6000000HZ:
0094         value = 0x1;
0095         break;
0096     case RT1308_CLK_FREQ_9600000HZ:
0097         value = 0x2;
0098         break;
0099     case RT1308_CLK_FREQ_4800000HZ:
0100         value = 0x3;
0101         break;
0102     case RT1308_CLK_FREQ_2400000HZ:
0103         value = 0x4;
0104         break;
0105     case RT1308_CLK_FREQ_12288000HZ:
0106         value = 0x5;
0107         break;
0108     default:
0109         return -EINVAL;
0110     }
0111 
0112     regmap_write(rt1308->regmap, 0xe0, value);
0113     regmap_write(rt1308->regmap, 0xf0, value);
0114 
0115     dev_dbg(dev, "%s complete, clk_freq=%d\n", __func__, clk_freq);
0116 
0117     return 0;
0118 }
0119 
0120 static int rt1308_read_prop(struct sdw_slave *slave)
0121 {
0122     struct sdw_slave_prop *prop = &slave->prop;
0123     int nval, i;
0124     u32 bit;
0125     unsigned long addr;
0126     struct sdw_dpn_prop *dpn;
0127 
0128     prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
0129     prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
0130 
0131     prop->paging_support = true;
0132 
0133     /* first we need to allocate memory for set bits in port lists */
0134     prop->source_ports = 0x00; /* BITMAP: 00010100 (not enable yet) */
0135     prop->sink_ports = 0x2; /* BITMAP:  00000010 */
0136 
0137     /* for sink */
0138     nval = hweight32(prop->sink_ports);
0139     prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
0140                         sizeof(*prop->sink_dpn_prop),
0141                         GFP_KERNEL);
0142     if (!prop->sink_dpn_prop)
0143         return -ENOMEM;
0144 
0145     i = 0;
0146     dpn = prop->sink_dpn_prop;
0147     addr = prop->sink_ports;
0148     for_each_set_bit(bit, &addr, 32) {
0149         dpn[i].num = bit;
0150         dpn[i].type = SDW_DPN_FULL;
0151         dpn[i].simple_ch_prep_sm = true;
0152         dpn[i].ch_prep_timeout = 10;
0153         i++;
0154     }
0155 
0156     /* set the timeout values */
0157     prop->clk_stop_timeout = 20;
0158 
0159     dev_dbg(&slave->dev, "%s\n", __func__);
0160 
0161     return 0;
0162 }
0163 
0164 static void rt1308_apply_calib_params(struct rt1308_sdw_priv *rt1308)
0165 {
0166     unsigned int efuse_m_btl_l, efuse_m_btl_r, tmp;
0167     unsigned int efuse_c_btl_l, efuse_c_btl_r;
0168 
0169     /* read efuse to apply calibration parameters */
0170     regmap_write(rt1308->regmap, 0xc7f0, 0x04);
0171     regmap_write(rt1308->regmap, 0xc7f1, 0xfe);
0172     msleep(100);
0173     regmap_write(rt1308->regmap, 0xc7f0, 0x44);
0174     msleep(20);
0175     regmap_write(rt1308->regmap, 0xc240, 0x10);
0176 
0177     regmap_read(rt1308->regmap, 0xc861, &tmp);
0178     efuse_m_btl_l = tmp;
0179     regmap_read(rt1308->regmap, 0xc860, &tmp);
0180     efuse_m_btl_l = efuse_m_btl_l | (tmp << 8);
0181     regmap_read(rt1308->regmap, 0xc863, &tmp);
0182     efuse_c_btl_l = tmp;
0183     regmap_read(rt1308->regmap, 0xc862, &tmp);
0184     efuse_c_btl_l = efuse_c_btl_l | (tmp << 8);
0185     regmap_read(rt1308->regmap, 0xc871, &tmp);
0186     efuse_m_btl_r = tmp;
0187     regmap_read(rt1308->regmap, 0xc870, &tmp);
0188     efuse_m_btl_r = efuse_m_btl_r | (tmp << 8);
0189     regmap_read(rt1308->regmap, 0xc873, &tmp);
0190     efuse_c_btl_r = tmp;
0191     regmap_read(rt1308->regmap, 0xc872, &tmp);
0192     efuse_c_btl_r = efuse_c_btl_r | (tmp << 8);
0193     dev_dbg(&rt1308->sdw_slave->dev, "%s m_btl_l=0x%x, m_btl_r=0x%x\n", __func__,
0194         efuse_m_btl_l, efuse_m_btl_r);
0195     dev_dbg(&rt1308->sdw_slave->dev, "%s c_btl_l=0x%x, c_btl_r=0x%x\n", __func__,
0196         efuse_c_btl_l, efuse_c_btl_r);
0197 }
0198 
0199 static int rt1308_io_init(struct device *dev, struct sdw_slave *slave)
0200 {
0201     struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev);
0202     int ret = 0;
0203 
0204     if (rt1308->hw_init)
0205         return 0;
0206 
0207     if (rt1308->first_hw_init) {
0208         regcache_cache_only(rt1308->regmap, false);
0209         regcache_cache_bypass(rt1308->regmap, true);
0210     }
0211 
0212     /*
0213      * PM runtime is only enabled when a Slave reports as Attached
0214      */
0215     if (!rt1308->first_hw_init) {
0216         /* set autosuspend parameters */
0217         pm_runtime_set_autosuspend_delay(&slave->dev, 3000);
0218         pm_runtime_use_autosuspend(&slave->dev);
0219 
0220         /* update count of parent 'active' children */
0221         pm_runtime_set_active(&slave->dev);
0222 
0223         /* make sure the device does not suspend immediately */
0224         pm_runtime_mark_last_busy(&slave->dev);
0225 
0226         pm_runtime_enable(&slave->dev);
0227     }
0228 
0229     pm_runtime_get_noresume(&slave->dev);
0230 
0231     /* sw reset */
0232     regmap_write(rt1308->regmap, RT1308_SDW_RESET, 0);
0233 
0234     /* initial settings */
0235     regmap_write(rt1308->regmap, 0xc103, 0xc0);
0236     regmap_write(rt1308->regmap, 0xc030, 0x17);
0237     regmap_write(rt1308->regmap, 0xc031, 0x81);
0238     regmap_write(rt1308->regmap, 0xc032, 0x26);
0239     regmap_write(rt1308->regmap, 0xc040, 0x80);
0240     regmap_write(rt1308->regmap, 0xc041, 0x80);
0241     regmap_write(rt1308->regmap, 0xc042, 0x06);
0242     regmap_write(rt1308->regmap, 0xc052, 0x0a);
0243     regmap_write(rt1308->regmap, 0xc080, 0x0a);
0244     regmap_write(rt1308->regmap, 0xc060, 0x02);
0245     regmap_write(rt1308->regmap, 0xc061, 0x75);
0246     regmap_write(rt1308->regmap, 0xc062, 0x05);
0247     regmap_write(rt1308->regmap, 0xc171, 0x07);
0248     regmap_write(rt1308->regmap, 0xc173, 0x0d);
0249     regmap_write(rt1308->regmap, 0xc311, 0x7f);
0250     regmap_write(rt1308->regmap, 0xc900, 0x90);
0251     regmap_write(rt1308->regmap, 0xc1a0, 0x84);
0252     regmap_write(rt1308->regmap, 0xc1a1, 0x01);
0253     regmap_write(rt1308->regmap, 0xc360, 0x78);
0254     regmap_write(rt1308->regmap, 0xc361, 0x87);
0255     regmap_write(rt1308->regmap, 0xc0a1, 0x71);
0256     regmap_write(rt1308->regmap, 0xc210, 0x00);
0257     regmap_write(rt1308->regmap, 0xc070, 0x00);
0258     regmap_write(rt1308->regmap, 0xc100, 0xd7);
0259     regmap_write(rt1308->regmap, 0xc101, 0xd7);
0260     regmap_write(rt1308->regmap, 0xc300, 0x09);
0261 
0262     if (rt1308->first_hw_init) {
0263         regcache_cache_bypass(rt1308->regmap, false);
0264         regcache_mark_dirty(rt1308->regmap);
0265     } else
0266         rt1308->first_hw_init = true;
0267 
0268     /* Mark Slave initialization complete */
0269     rt1308->hw_init = true;
0270 
0271     pm_runtime_mark_last_busy(&slave->dev);
0272     pm_runtime_put_autosuspend(&slave->dev);
0273 
0274     dev_dbg(&slave->dev, "%s hw_init complete\n", __func__);
0275 
0276     return ret;
0277 }
0278 
0279 static int rt1308_update_status(struct sdw_slave *slave,
0280                     enum sdw_slave_status status)
0281 {
0282     struct  rt1308_sdw_priv *rt1308 = dev_get_drvdata(&slave->dev);
0283 
0284     /* Update the status */
0285     rt1308->status = status;
0286 
0287     if (status == SDW_SLAVE_UNATTACHED)
0288         rt1308->hw_init = false;
0289 
0290     /*
0291      * Perform initialization only if slave status is present and
0292      * hw_init flag is false
0293      */
0294     if (rt1308->hw_init || rt1308->status != SDW_SLAVE_ATTACHED)
0295         return 0;
0296 
0297     /* perform I/O transfers required for Slave initialization */
0298     return rt1308_io_init(&slave->dev, slave);
0299 }
0300 
0301 static int rt1308_bus_config(struct sdw_slave *slave,
0302                 struct sdw_bus_params *params)
0303 {
0304     struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(&slave->dev);
0305     int ret;
0306 
0307     memcpy(&rt1308->params, params, sizeof(*params));
0308 
0309     ret = rt1308_clock_config(&slave->dev);
0310     if (ret < 0)
0311         dev_err(&slave->dev, "Invalid clk config");
0312 
0313     return ret;
0314 }
0315 
0316 static int rt1308_interrupt_callback(struct sdw_slave *slave,
0317                     struct sdw_slave_intr_status *status)
0318 {
0319     dev_dbg(&slave->dev,
0320         "%s control_port_stat=%x", __func__, status->control_port);
0321 
0322     return 0;
0323 }
0324 
0325 static int rt1308_classd_event(struct snd_soc_dapm_widget *w,
0326     struct snd_kcontrol *kcontrol, int event)
0327 {
0328     struct snd_soc_component *component =
0329         snd_soc_dapm_to_component(w->dapm);
0330     struct rt1308_sdw_priv *rt1308 =
0331         snd_soc_component_get_drvdata(component);
0332 
0333     switch (event) {
0334     case SND_SOC_DAPM_POST_PMU:
0335         msleep(30);
0336         snd_soc_component_update_bits(component,
0337             RT1308_SDW_OFFSET | (RT1308_POWER_STATUS << 4),
0338             0x3,    0x3);
0339         msleep(40);
0340         rt1308_apply_calib_params(rt1308);
0341         break;
0342     case SND_SOC_DAPM_PRE_PMD:
0343         snd_soc_component_update_bits(component,
0344             RT1308_SDW_OFFSET | (RT1308_POWER_STATUS << 4),
0345             0x3, 0);
0346         usleep_range(150000, 200000);
0347         break;
0348 
0349     default:
0350         break;
0351     }
0352 
0353     return 0;
0354 }
0355 
0356 static const char * const rt1308_rx_data_ch_select[] = {
0357     "LR",
0358     "LL",
0359     "RL",
0360     "RR",
0361 };
0362 
0363 static SOC_ENUM_SINGLE_DECL(rt1308_rx_data_ch_enum,
0364     RT1308_SDW_OFFSET | (RT1308_DATA_PATH << 4), 0,
0365     rt1308_rx_data_ch_select);
0366 
0367 static const struct snd_kcontrol_new rt1308_snd_controls[] = {
0368 
0369     /* I2S Data Channel Selection */
0370     SOC_ENUM("RX Channel Select", rt1308_rx_data_ch_enum),
0371 };
0372 
0373 static const struct snd_kcontrol_new rt1308_sto_dac_l =
0374     SOC_DAPM_SINGLE_AUTODISABLE("Switch",
0375         RT1308_SDW_OFFSET_BYTE3 | (RT1308_DAC_SET << 4),
0376         RT1308_DVOL_MUTE_L_EN_SFT, 1, 1);
0377 
0378 static const struct snd_kcontrol_new rt1308_sto_dac_r =
0379     SOC_DAPM_SINGLE_AUTODISABLE("Switch",
0380         RT1308_SDW_OFFSET_BYTE3 | (RT1308_DAC_SET << 4),
0381         RT1308_DVOL_MUTE_R_EN_SFT, 1, 1);
0382 
0383 static const struct snd_soc_dapm_widget rt1308_dapm_widgets[] = {
0384     /* Audio Interface */
0385     SND_SOC_DAPM_AIF_IN("AIF1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0),
0386 
0387     /* Supply Widgets */
0388     SND_SOC_DAPM_SUPPLY("MBIAS20U",
0389         RT1308_SDW_OFFSET | (RT1308_POWER << 4),    7, 0, NULL, 0),
0390     SND_SOC_DAPM_SUPPLY("ALDO",
0391         RT1308_SDW_OFFSET | (RT1308_POWER << 4),    6, 0, NULL, 0),
0392     SND_SOC_DAPM_SUPPLY("DBG",
0393         RT1308_SDW_OFFSET | (RT1308_POWER << 4),    5, 0, NULL, 0),
0394     SND_SOC_DAPM_SUPPLY("DACL",
0395         RT1308_SDW_OFFSET | (RT1308_POWER << 4),    4, 0, NULL, 0),
0396     SND_SOC_DAPM_SUPPLY("CLK25M",
0397         RT1308_SDW_OFFSET | (RT1308_POWER << 4),    2, 0, NULL, 0),
0398     SND_SOC_DAPM_SUPPLY("ADC_R",
0399         RT1308_SDW_OFFSET | (RT1308_POWER << 4),    1, 0, NULL, 0),
0400     SND_SOC_DAPM_SUPPLY("ADC_L",
0401         RT1308_SDW_OFFSET | (RT1308_POWER << 4),    0, 0, NULL, 0),
0402     SND_SOC_DAPM_SUPPLY("DAC Power",
0403         RT1308_SDW_OFFSET | (RT1308_POWER << 4),    3, 0, NULL, 0),
0404 
0405     SND_SOC_DAPM_SUPPLY("DLDO",
0406         RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4),  5, 0, NULL, 0),
0407     SND_SOC_DAPM_SUPPLY("VREF",
0408         RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4),  4, 0, NULL, 0),
0409     SND_SOC_DAPM_SUPPLY("MIXER_R",
0410         RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4),  2, 0, NULL, 0),
0411     SND_SOC_DAPM_SUPPLY("MIXER_L",
0412         RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4),  1, 0, NULL, 0),
0413     SND_SOC_DAPM_SUPPLY("MBIAS4U",
0414         RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4),  0, 0, NULL, 0),
0415 
0416     SND_SOC_DAPM_SUPPLY("PLL2_LDO",
0417         RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 4, 0, NULL, 0),
0418     SND_SOC_DAPM_SUPPLY("PLL2B",
0419         RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 3, 0, NULL, 0),
0420     SND_SOC_DAPM_SUPPLY("PLL2F",
0421         RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 2, 0, NULL, 0),
0422     SND_SOC_DAPM_SUPPLY("PLL2F2",
0423         RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 1, 0, NULL, 0),
0424     SND_SOC_DAPM_SUPPLY("PLL2B2",
0425         RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 0, 0, NULL, 0),
0426 
0427     /* Digital Interface */
0428     SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
0429     SND_SOC_DAPM_SWITCH("DAC L", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_l),
0430     SND_SOC_DAPM_SWITCH("DAC R", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_r),
0431 
0432     /* Output Lines */
0433     SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0,
0434         rt1308_classd_event,
0435         SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
0436     SND_SOC_DAPM_OUTPUT("SPOL"),
0437     SND_SOC_DAPM_OUTPUT("SPOR"),
0438 };
0439 
0440 static const struct snd_soc_dapm_route rt1308_dapm_routes[] = {
0441 
0442     { "DAC", NULL, "AIF1RX" },
0443 
0444     { "DAC", NULL, "MBIAS20U" },
0445     { "DAC", NULL, "ALDO" },
0446     { "DAC", NULL, "DBG" },
0447     { "DAC", NULL, "DACL" },
0448     { "DAC", NULL, "CLK25M" },
0449     { "DAC", NULL, "ADC_R" },
0450     { "DAC", NULL, "ADC_L" },
0451     { "DAC", NULL, "DLDO" },
0452     { "DAC", NULL, "VREF" },
0453     { "DAC", NULL, "MIXER_R" },
0454     { "DAC", NULL, "MIXER_L" },
0455     { "DAC", NULL, "MBIAS4U" },
0456     { "DAC", NULL, "PLL2_LDO" },
0457     { "DAC", NULL, "PLL2B" },
0458     { "DAC", NULL, "PLL2F" },
0459     { "DAC", NULL, "PLL2F2" },
0460     { "DAC", NULL, "PLL2B2" },
0461 
0462     { "DAC L", "Switch", "DAC" },
0463     { "DAC R", "Switch", "DAC" },
0464     { "DAC L", NULL, "DAC Power" },
0465     { "DAC R", NULL, "DAC Power" },
0466 
0467     { "CLASS D", NULL, "DAC L" },
0468     { "CLASS D", NULL, "DAC R" },
0469     { "SPOL", NULL, "CLASS D" },
0470     { "SPOR", NULL, "CLASS D" },
0471 };
0472 
0473 static int rt1308_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
0474                 int direction)
0475 {
0476     struct sdw_stream_data *stream;
0477 
0478     if (!sdw_stream)
0479         return 0;
0480 
0481     stream = kzalloc(sizeof(*stream), GFP_KERNEL);
0482     if (!stream)
0483         return -ENOMEM;
0484 
0485     stream->sdw_stream = sdw_stream;
0486 
0487     /* Use tx_mask or rx_mask to configure stream tag and set dma_data */
0488     if (direction == SNDRV_PCM_STREAM_PLAYBACK)
0489         dai->playback_dma_data = stream;
0490     else
0491         dai->capture_dma_data = stream;
0492 
0493     return 0;
0494 }
0495 
0496 static void rt1308_sdw_shutdown(struct snd_pcm_substream *substream,
0497                 struct snd_soc_dai *dai)
0498 {
0499     struct sdw_stream_data *stream;
0500 
0501     stream = snd_soc_dai_get_dma_data(dai, substream);
0502     snd_soc_dai_set_dma_data(dai, substream, NULL);
0503     kfree(stream);
0504 }
0505 
0506 static int rt1308_sdw_set_tdm_slot(struct snd_soc_dai *dai,
0507                    unsigned int tx_mask,
0508                    unsigned int rx_mask,
0509                    int slots, int slot_width)
0510 {
0511     struct snd_soc_component *component = dai->component;
0512     struct rt1308_sdw_priv *rt1308 =
0513         snd_soc_component_get_drvdata(component);
0514 
0515     if (tx_mask)
0516         return -EINVAL;
0517 
0518     if (slots > 2)
0519         return -EINVAL;
0520 
0521     rt1308->rx_mask = rx_mask;
0522     rt1308->slots = slots;
0523     /* slot_width is not used since it's irrelevant for SoundWire */
0524 
0525     return 0;
0526 }
0527 
0528 static int rt1308_sdw_hw_params(struct snd_pcm_substream *substream,
0529     struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
0530 {
0531     struct snd_soc_component *component = dai->component;
0532     struct rt1308_sdw_priv *rt1308 =
0533         snd_soc_component_get_drvdata(component);
0534     struct sdw_stream_config stream_config;
0535     struct sdw_port_config port_config;
0536     enum sdw_data_direction direction;
0537     struct sdw_stream_data *stream;
0538     int retval, port, num_channels, ch_mask;
0539 
0540     dev_dbg(dai->dev, "%s %s", __func__, dai->name);
0541     stream = snd_soc_dai_get_dma_data(dai, substream);
0542 
0543     if (!stream)
0544         return -EINVAL;
0545 
0546     if (!rt1308->sdw_slave)
0547         return -EINVAL;
0548 
0549     /* SoundWire specific configuration */
0550     /* port 1 for playback */
0551     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0552         direction = SDW_DATA_DIR_RX;
0553         port = 1;
0554     } else {
0555         return -EINVAL;
0556     }
0557 
0558     if (rt1308->slots) {
0559         num_channels = rt1308->slots;
0560         ch_mask = rt1308->rx_mask;
0561     } else {
0562         num_channels = params_channels(params);
0563         ch_mask = (1 << num_channels) - 1;
0564     }
0565 
0566     stream_config.frame_rate = params_rate(params);
0567     stream_config.ch_count = num_channels;
0568     stream_config.bps = snd_pcm_format_width(params_format(params));
0569     stream_config.direction = direction;
0570 
0571     port_config.ch_mask = ch_mask;
0572     port_config.num = port;
0573 
0574     retval = sdw_stream_add_slave(rt1308->sdw_slave, &stream_config,
0575                 &port_config, 1, stream->sdw_stream);
0576     if (retval) {
0577         dev_err(dai->dev, "Unable to configure port\n");
0578         return retval;
0579     }
0580 
0581     return retval;
0582 }
0583 
0584 static int rt1308_sdw_pcm_hw_free(struct snd_pcm_substream *substream,
0585                 struct snd_soc_dai *dai)
0586 {
0587     struct snd_soc_component *component = dai->component;
0588     struct rt1308_sdw_priv *rt1308 =
0589         snd_soc_component_get_drvdata(component);
0590     struct sdw_stream_data *stream =
0591         snd_soc_dai_get_dma_data(dai, substream);
0592 
0593     if (!rt1308->sdw_slave)
0594         return -EINVAL;
0595 
0596     sdw_stream_remove_slave(rt1308->sdw_slave, stream->sdw_stream);
0597     return 0;
0598 }
0599 
0600 /*
0601  * slave_ops: callbacks for get_clock_stop_mode, clock_stop and
0602  * port_prep are not defined for now
0603  */
0604 static const struct sdw_slave_ops rt1308_slave_ops = {
0605     .read_prop = rt1308_read_prop,
0606     .interrupt_callback = rt1308_interrupt_callback,
0607     .update_status = rt1308_update_status,
0608     .bus_config = rt1308_bus_config,
0609 };
0610 
0611 static int rt1308_sdw_component_probe(struct snd_soc_component *component)
0612 {
0613     int ret;
0614 
0615     ret = pm_runtime_resume(component->dev);
0616     if (ret < 0 && ret != -EACCES)
0617         return ret;
0618 
0619     return 0;
0620 }
0621 
0622 static const struct snd_soc_component_driver soc_component_sdw_rt1308 = {
0623     .probe = rt1308_sdw_component_probe,
0624     .controls = rt1308_snd_controls,
0625     .num_controls = ARRAY_SIZE(rt1308_snd_controls),
0626     .dapm_widgets = rt1308_dapm_widgets,
0627     .num_dapm_widgets = ARRAY_SIZE(rt1308_dapm_widgets),
0628     .dapm_routes = rt1308_dapm_routes,
0629     .num_dapm_routes = ARRAY_SIZE(rt1308_dapm_routes),
0630     .endianness = 1,
0631 };
0632 
0633 static const struct snd_soc_dai_ops rt1308_aif_dai_ops = {
0634     .hw_params = rt1308_sdw_hw_params,
0635     .hw_free    = rt1308_sdw_pcm_hw_free,
0636     .set_stream = rt1308_set_sdw_stream,
0637     .shutdown   = rt1308_sdw_shutdown,
0638     .set_tdm_slot   = rt1308_sdw_set_tdm_slot,
0639 };
0640 
0641 #define RT1308_STEREO_RATES SNDRV_PCM_RATE_48000
0642 #define RT1308_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
0643             SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \
0644             SNDRV_PCM_FMTBIT_S24_LE)
0645 
0646 static struct snd_soc_dai_driver rt1308_sdw_dai[] = {
0647     {
0648         .name = "rt1308-aif",
0649         .playback = {
0650             .stream_name = "DP1 Playback",
0651             .channels_min = 1,
0652             .channels_max = 2,
0653             .rates = RT1308_STEREO_RATES,
0654             .formats = RT1308_FORMATS,
0655         },
0656         .ops = &rt1308_aif_dai_ops,
0657     },
0658 };
0659 
0660 static int rt1308_sdw_init(struct device *dev, struct regmap *regmap,
0661                 struct sdw_slave *slave)
0662 {
0663     struct rt1308_sdw_priv *rt1308;
0664     int ret;
0665 
0666     rt1308 = devm_kzalloc(dev, sizeof(*rt1308), GFP_KERNEL);
0667     if (!rt1308)
0668         return -ENOMEM;
0669 
0670     dev_set_drvdata(dev, rt1308);
0671     rt1308->sdw_slave = slave;
0672     rt1308->regmap = regmap;
0673 
0674     /*
0675      * Mark hw_init to false
0676      * HW init will be performed when device reports present
0677      */
0678     rt1308->hw_init = false;
0679     rt1308->first_hw_init = false;
0680 
0681     ret =  devm_snd_soc_register_component(dev,
0682                 &soc_component_sdw_rt1308,
0683                 rt1308_sdw_dai,
0684                 ARRAY_SIZE(rt1308_sdw_dai));
0685 
0686     dev_dbg(&slave->dev, "%s\n", __func__);
0687 
0688     return ret;
0689 }
0690 
0691 static int rt1308_sdw_probe(struct sdw_slave *slave,
0692                 const struct sdw_device_id *id)
0693 {
0694     struct regmap *regmap;
0695 
0696     /* Regmap Initialization */
0697     regmap = devm_regmap_init_sdw(slave, &rt1308_sdw_regmap);
0698     if (IS_ERR(regmap))
0699         return PTR_ERR(regmap);
0700 
0701     rt1308_sdw_init(&slave->dev, regmap, slave);
0702 
0703     return 0;
0704 }
0705 
0706 static int rt1308_sdw_remove(struct sdw_slave *slave)
0707 {
0708     struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(&slave->dev);
0709 
0710     if (rt1308->first_hw_init)
0711         pm_runtime_disable(&slave->dev);
0712 
0713     return 0;
0714 }
0715 
0716 static const struct sdw_device_id rt1308_id[] = {
0717     SDW_SLAVE_ENTRY_EXT(0x025d, 0x1308, 0x2, 0, 0),
0718     {},
0719 };
0720 MODULE_DEVICE_TABLE(sdw, rt1308_id);
0721 
0722 static int __maybe_unused rt1308_dev_suspend(struct device *dev)
0723 {
0724     struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev);
0725 
0726     if (!rt1308->hw_init)
0727         return 0;
0728 
0729     regcache_cache_only(rt1308->regmap, true);
0730 
0731     return 0;
0732 }
0733 
0734 #define RT1308_PROBE_TIMEOUT 5000
0735 
0736 static int __maybe_unused rt1308_dev_resume(struct device *dev)
0737 {
0738     struct sdw_slave *slave = dev_to_sdw_dev(dev);
0739     struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev);
0740     unsigned long time;
0741 
0742     if (!rt1308->first_hw_init)
0743         return 0;
0744 
0745     if (!slave->unattach_request)
0746         goto regmap_sync;
0747 
0748     time = wait_for_completion_timeout(&slave->initialization_complete,
0749                 msecs_to_jiffies(RT1308_PROBE_TIMEOUT));
0750     if (!time) {
0751         dev_err(&slave->dev, "Initialization not complete, timed out\n");
0752         return -ETIMEDOUT;
0753     }
0754 
0755 regmap_sync:
0756     slave->unattach_request = 0;
0757     regcache_cache_only(rt1308->regmap, false);
0758     regcache_sync_region(rt1308->regmap, 0xc000, 0xcfff);
0759 
0760     return 0;
0761 }
0762 
0763 static const struct dev_pm_ops rt1308_pm = {
0764     SET_SYSTEM_SLEEP_PM_OPS(rt1308_dev_suspend, rt1308_dev_resume)
0765     SET_RUNTIME_PM_OPS(rt1308_dev_suspend, rt1308_dev_resume, NULL)
0766 };
0767 
0768 static struct sdw_driver rt1308_sdw_driver = {
0769     .driver = {
0770         .name = "rt1308",
0771         .owner = THIS_MODULE,
0772         .pm = &rt1308_pm,
0773     },
0774     .probe = rt1308_sdw_probe,
0775     .remove = rt1308_sdw_remove,
0776     .ops = &rt1308_slave_ops,
0777     .id_table = rt1308_id,
0778 };
0779 module_sdw_driver(rt1308_sdw_driver);
0780 
0781 MODULE_DESCRIPTION("ASoC RT1308 driver SDW");
0782 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>");
0783 MODULE_LICENSE("GPL v2");
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