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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * rt1305.c  --  RT1305 ALSA SoC amplifier component driver
0004  *
0005  * Copyright 2018 Realtek Semiconductor Corp.
0006  * Author: Shuming Fan <shumingf@realtek.com>
0007  */
0008 
0009 #include <linux/module.h>
0010 #include <linux/moduleparam.h>
0011 #include <linux/init.h>
0012 #include <linux/delay.h>
0013 #include <linux/pm.h>
0014 #include <linux/acpi.h>
0015 #include <linux/gpio.h>
0016 #include <linux/i2c.h>
0017 #include <linux/regmap.h>
0018 #include <linux/of_gpio.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/firmware.h>
0021 #include <sound/core.h>
0022 #include <sound/pcm.h>
0023 #include <sound/pcm_params.h>
0024 #include <sound/soc.h>
0025 #include <sound/soc-dapm.h>
0026 #include <sound/initval.h>
0027 #include <sound/tlv.h>
0028 
0029 #include "rl6231.h"
0030 #include "rt1305.h"
0031 
0032 
0033 #define RT1305_PR_RANGE_BASE (0xff + 1)
0034 #define RT1305_PR_SPACING 0x100
0035 
0036 #define RT1305_PR_BASE (RT1305_PR_RANGE_BASE + (0 * RT1305_PR_SPACING))
0037 
0038 
0039 static const struct regmap_range_cfg rt1305_ranges[] = {
0040     {
0041         .name = "PR",
0042         .range_min = RT1305_PR_BASE,
0043         .range_max = RT1305_PR_BASE + 0xff,
0044         .selector_reg = RT1305_PRIV_INDEX,
0045         .selector_mask = 0xff,
0046         .selector_shift = 0x0,
0047         .window_start = RT1305_PRIV_DATA,
0048         .window_len = 0x1,
0049     },
0050 };
0051 
0052 
0053 static const struct reg_sequence init_list[] = {
0054 
0055     { RT1305_PR_BASE + 0xcf, 0x5548 },
0056     { RT1305_PR_BASE + 0x5d, 0x0442 },
0057     { RT1305_PR_BASE + 0xc1, 0x0320 },
0058 
0059     { RT1305_POWER_STATUS, 0x0000 },
0060 
0061     { RT1305_SPK_TEMP_PROTECTION_1, 0xd6de },
0062     { RT1305_SPK_TEMP_PROTECTION_2, 0x0707 },
0063     { RT1305_SPK_TEMP_PROTECTION_3, 0x4090 },
0064 
0065     { RT1305_DAC_SET_1, 0xdfdf },   /* 4 ohm 2W  */
0066     { RT1305_ADC_SET_3, 0x0219 },
0067     { RT1305_ADC_SET_1, 0x170f },   /* 0.2 ohm RSense*/
0068 
0069 };
0070 #define RT1305_INIT_REG_LEN ARRAY_SIZE(init_list)
0071 
0072 struct rt1305_priv {
0073     struct snd_soc_component *component;
0074     struct regmap *regmap;
0075 
0076     int sysclk;
0077     int sysclk_src;
0078     int lrck;
0079     int bclk;
0080     int master;
0081 
0082     int pll_src;
0083     int pll_in;
0084     int pll_out;
0085 };
0086 
0087 static const struct reg_default rt1305_reg[] = {
0088 
0089     { 0x04, 0x0400 },
0090     { 0x05, 0x0880 },
0091     { 0x06, 0x0000 },
0092     { 0x07, 0x3100 },
0093     { 0x08, 0x8000 },
0094     { 0x09, 0x0000 },
0095     { 0x0a, 0x087e },
0096     { 0x0b, 0x0020 },
0097     { 0x0c, 0x0802 },
0098     { 0x0d, 0x0020 },
0099     { 0x10, 0x1d1d },
0100     { 0x11, 0x1d1d },
0101     { 0x12, 0xffff },
0102     { 0x14, 0x000c },
0103     { 0x16, 0x1717 },
0104     { 0x17, 0x4000 },
0105     { 0x18, 0x0019 },
0106     { 0x20, 0x0000 },
0107     { 0x22, 0x0000 },
0108     { 0x24, 0x0000 },
0109     { 0x26, 0x0000 },
0110     { 0x28, 0x0000 },
0111     { 0x2a, 0x4000 },
0112     { 0x2b, 0x3000 },
0113     { 0x2d, 0x6000 },
0114     { 0x2e, 0x0000 },
0115     { 0x2f, 0x8000 },
0116     { 0x32, 0x0000 },
0117     { 0x39, 0x0001 },
0118     { 0x3a, 0x0000 },
0119     { 0x3b, 0x1020 },
0120     { 0x3c, 0x0000 },
0121     { 0x3d, 0x0000 },
0122     { 0x3e, 0x4c00 },
0123     { 0x3f, 0x3000 },
0124     { 0x40, 0x000c },
0125     { 0x42, 0x0400 },
0126     { 0x46, 0xc22c },
0127     { 0x47, 0x0000 },
0128     { 0x4b, 0x0000 },
0129     { 0x4c, 0x0300 },
0130     { 0x4f, 0xf000 },
0131     { 0x50, 0xc200 },
0132     { 0x51, 0x1f1f },
0133     { 0x52, 0x01f0 },
0134     { 0x53, 0x407f },
0135     { 0x54, 0xffff },
0136     { 0x58, 0x4005 },
0137     { 0x5e, 0x0000 },
0138     { 0x5f, 0x0000 },
0139     { 0x60, 0xee13 },
0140     { 0x62, 0x0000 },
0141     { 0x63, 0x5f5f },
0142     { 0x64, 0x0040 },
0143     { 0x65, 0x4000 },
0144     { 0x66, 0x4004 },
0145     { 0x67, 0x0306 },
0146     { 0x68, 0x8c04 },
0147     { 0x69, 0xe021 },
0148     { 0x6a, 0x0000 },
0149     { 0x6c, 0xaaaa },
0150     { 0x70, 0x0333 },
0151     { 0x71, 0x3330 },
0152     { 0x72, 0x3333 },
0153     { 0x73, 0x3300 },
0154     { 0x74, 0x0000 },
0155     { 0x75, 0x0000 },
0156     { 0x76, 0x0000 },
0157     { 0x7a, 0x0003 },
0158     { 0x7c, 0x10ec },
0159     { 0x7e, 0x6251 },
0160     { 0x80, 0x0800 },
0161     { 0x81, 0x4000 },
0162     { 0x82, 0x0000 },
0163     { 0x90, 0x7a01 },
0164     { 0x91, 0x8431 },
0165     { 0x92, 0x0180 },
0166     { 0x93, 0x0000 },
0167     { 0x94, 0x0000 },
0168     { 0x95, 0x0000 },
0169     { 0x96, 0x0000 },
0170     { 0x97, 0x0000 },
0171     { 0x98, 0x0000 },
0172     { 0x99, 0x0000 },
0173     { 0x9a, 0x0000 },
0174     { 0x9b, 0x0000 },
0175     { 0x9c, 0x0000 },
0176     { 0x9d, 0x0000 },
0177     { 0x9e, 0x0000 },
0178     { 0x9f, 0x0000 },
0179     { 0xa0, 0x0000 },
0180     { 0xb0, 0x8200 },
0181     { 0xb1, 0x00ff },
0182     { 0xb2, 0x0008 },
0183     { 0xc0, 0x0200 },
0184     { 0xc1, 0x0000 },
0185     { 0xc2, 0x0000 },
0186     { 0xc3, 0x0000 },
0187     { 0xc4, 0x0000 },
0188     { 0xc5, 0x0000 },
0189     { 0xc6, 0x0000 },
0190     { 0xc7, 0x0000 },
0191     { 0xc8, 0x0000 },
0192     { 0xc9, 0x0000 },
0193     { 0xca, 0x0200 },
0194     { 0xcb, 0x0000 },
0195     { 0xcc, 0x0000 },
0196     { 0xcd, 0x0000 },
0197     { 0xce, 0x0000 },
0198     { 0xcf, 0x0000 },
0199     { 0xd0, 0x0000 },
0200     { 0xd1, 0x0000 },
0201     { 0xd2, 0x0000 },
0202     { 0xd3, 0x0000 },
0203     { 0xd4, 0x0200 },
0204     { 0xd5, 0x0000 },
0205     { 0xd6, 0x0000 },
0206     { 0xd7, 0x0000 },
0207     { 0xd8, 0x0000 },
0208     { 0xd9, 0x0000 },
0209     { 0xda, 0x0000 },
0210     { 0xdb, 0x0000 },
0211     { 0xdc, 0x0000 },
0212     { 0xdd, 0x0000 },
0213     { 0xde, 0x0200 },
0214     { 0xdf, 0x0000 },
0215     { 0xe0, 0x0000 },
0216     { 0xe1, 0x0000 },
0217     { 0xe2, 0x0000 },
0218     { 0xe3, 0x0000 },
0219     { 0xe4, 0x0000 },
0220     { 0xe5, 0x0000 },
0221     { 0xe6, 0x0000 },
0222     { 0xe7, 0x0000 },
0223     { 0xe8, 0x0200 },
0224     { 0xe9, 0x0000 },
0225     { 0xea, 0x0000 },
0226     { 0xeb, 0x0000 },
0227     { 0xec, 0x0000 },
0228     { 0xed, 0x0000 },
0229     { 0xee, 0x0000 },
0230     { 0xef, 0x0000 },
0231     { 0xf0, 0x0000 },
0232     { 0xf1, 0x0000 },
0233     { 0xf2, 0x0200 },
0234     { 0xf3, 0x0000 },
0235     { 0xf4, 0x0000 },
0236     { 0xf5, 0x0000 },
0237     { 0xf6, 0x0000 },
0238     { 0xf7, 0x0000 },
0239     { 0xf8, 0x0000 },
0240     { 0xf9, 0x0000 },
0241     { 0xfa, 0x0000 },
0242     { 0xfb, 0x0000 },
0243 };
0244 
0245 static int rt1305_reg_init(struct snd_soc_component *component)
0246 {
0247     struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
0248 
0249     regmap_multi_reg_write(rt1305->regmap, init_list, RT1305_INIT_REG_LEN);
0250     return 0;
0251 }
0252 
0253 static bool rt1305_volatile_register(struct device *dev, unsigned int reg)
0254 {
0255     int i;
0256 
0257     for (i = 0; i < ARRAY_SIZE(rt1305_ranges); i++) {
0258         if (reg >= rt1305_ranges[i].range_min &&
0259             reg <= rt1305_ranges[i].range_max) {
0260             return true;
0261         }
0262     }
0263 
0264     switch (reg) {
0265     case RT1305_RESET:
0266     case RT1305_SPDIF_IN_SET_1:
0267     case RT1305_SPDIF_IN_SET_2:
0268     case RT1305_SPDIF_IN_SET_3:
0269     case RT1305_POWER_CTRL_2:
0270     case RT1305_CLOCK_DETECT:
0271     case RT1305_BIQUAD_SET_1:
0272     case RT1305_BIQUAD_SET_2:
0273     case RT1305_EQ_SET_2:
0274     case RT1305_SPK_TEMP_PROTECTION_0:
0275     case RT1305_SPK_TEMP_PROTECTION_2:
0276     case RT1305_SPK_DC_DETECT_1:
0277     case RT1305_SILENCE_DETECT:
0278     case RT1305_VERSION_ID:
0279     case RT1305_VENDOR_ID:
0280     case RT1305_DEVICE_ID:
0281     case RT1305_EFUSE_1:
0282     case RT1305_EFUSE_3:
0283     case RT1305_DC_CALIB_1:
0284     case RT1305_DC_CALIB_3:
0285     case RT1305_DAC_OFFSET_1:
0286     case RT1305_DAC_OFFSET_2:
0287     case RT1305_DAC_OFFSET_3:
0288     case RT1305_DAC_OFFSET_4:
0289     case RT1305_DAC_OFFSET_5:
0290     case RT1305_DAC_OFFSET_6:
0291     case RT1305_DAC_OFFSET_7:
0292     case RT1305_DAC_OFFSET_8:
0293     case RT1305_DAC_OFFSET_9:
0294     case RT1305_DAC_OFFSET_10:
0295     case RT1305_DAC_OFFSET_11:
0296     case RT1305_TRIM_1:
0297     case RT1305_TRIM_2:
0298         return true;
0299 
0300     default:
0301         return false;
0302     }
0303 }
0304 
0305 static bool rt1305_readable_register(struct device *dev, unsigned int reg)
0306 {
0307     int i;
0308 
0309     for (i = 0; i < ARRAY_SIZE(rt1305_ranges); i++) {
0310         if (reg >= rt1305_ranges[i].range_min &&
0311             reg <= rt1305_ranges[i].range_max) {
0312             return true;
0313         }
0314     }
0315 
0316     switch (reg) {
0317     case RT1305_RESET:
0318     case RT1305_CLK_1 ... RT1305_CAL_EFUSE_CLOCK:
0319     case RT1305_PLL0_1 ... RT1305_PLL1_2:
0320     case RT1305_MIXER_CTRL_1:
0321     case RT1305_MIXER_CTRL_2:
0322     case RT1305_DAC_SET_1:
0323     case RT1305_DAC_SET_2:
0324     case RT1305_ADC_SET_1:
0325     case RT1305_ADC_SET_2:
0326     case RT1305_ADC_SET_3:
0327     case RT1305_PATH_SET:
0328     case RT1305_SPDIF_IN_SET_1:
0329     case RT1305_SPDIF_IN_SET_2:
0330     case RT1305_SPDIF_IN_SET_3:
0331     case RT1305_SPDIF_OUT_SET_1:
0332     case RT1305_SPDIF_OUT_SET_2:
0333     case RT1305_SPDIF_OUT_SET_3:
0334     case RT1305_I2S_SET_1:
0335     case RT1305_I2S_SET_2:
0336     case RT1305_PBTL_MONO_MODE_SRC:
0337     case RT1305_MANUALLY_I2C_DEVICE:
0338     case RT1305_POWER_STATUS:
0339     case RT1305_POWER_CTRL_1:
0340     case RT1305_POWER_CTRL_2:
0341     case RT1305_POWER_CTRL_3:
0342     case RT1305_POWER_CTRL_4:
0343     case RT1305_POWER_CTRL_5:
0344     case RT1305_CLOCK_DETECT:
0345     case RT1305_BIQUAD_SET_1:
0346     case RT1305_BIQUAD_SET_2:
0347     case RT1305_ADJUSTED_HPF_1:
0348     case RT1305_ADJUSTED_HPF_2:
0349     case RT1305_EQ_SET_1:
0350     case RT1305_EQ_SET_2:
0351     case RT1305_SPK_TEMP_PROTECTION_0:
0352     case RT1305_SPK_TEMP_PROTECTION_1:
0353     case RT1305_SPK_TEMP_PROTECTION_2:
0354     case RT1305_SPK_TEMP_PROTECTION_3:
0355     case RT1305_SPK_DC_DETECT_1:
0356     case RT1305_SPK_DC_DETECT_2:
0357     case RT1305_LOUDNESS:
0358     case RT1305_THERMAL_FOLD_BACK_1:
0359     case RT1305_THERMAL_FOLD_BACK_2:
0360     case RT1305_SILENCE_DETECT ... RT1305_SPK_EXCURSION_LIMITER_7:
0361     case RT1305_VERSION_ID:
0362     case RT1305_VENDOR_ID:
0363     case RT1305_DEVICE_ID:
0364     case RT1305_EFUSE_1:
0365     case RT1305_EFUSE_2:
0366     case RT1305_EFUSE_3:
0367     case RT1305_DC_CALIB_1:
0368     case RT1305_DC_CALIB_2:
0369     case RT1305_DC_CALIB_3:
0370     case RT1305_DAC_OFFSET_1 ... RT1305_DAC_OFFSET_14:
0371     case RT1305_TRIM_1:
0372     case RT1305_TRIM_2:
0373     case RT1305_TUNE_INTERNAL_OSC:
0374     case RT1305_BIQUAD1_H0_L_28_16 ... RT1305_BIQUAD3_A2_R_15_0:
0375         return true;
0376     default:
0377         return false;
0378     }
0379 }
0380 
0381 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9435, 37, 0);
0382 
0383 static const char * const rt1305_rx_data_ch_select[] = {
0384     "LR",
0385     "RL",
0386     "Copy L",
0387     "Copy R",
0388 };
0389 
0390 static SOC_ENUM_SINGLE_DECL(rt1305_rx_data_ch_enum, RT1305_I2S_SET_2, 2,
0391     rt1305_rx_data_ch_select);
0392 
0393 static void rt1305_reset(struct regmap *regmap)
0394 {
0395     regmap_write(regmap, RT1305_RESET, 0);
0396 }
0397 
0398 static const struct snd_kcontrol_new rt1305_snd_controls[] = {
0399     SOC_DOUBLE_TLV("DAC Playback Volume", RT1305_DAC_SET_1,
0400             8, 0, 0xff, 0, dac_vol_tlv),
0401 
0402     /* I2S Data Channel Selection */
0403     SOC_ENUM("RX Channel Select", rt1305_rx_data_ch_enum),
0404 };
0405 
0406 static int rt1305_is_rc_clk_from_pll(struct snd_soc_dapm_widget *source,
0407              struct snd_soc_dapm_widget *sink)
0408 {
0409     struct snd_soc_component *component =
0410         snd_soc_dapm_to_component(source->dapm);
0411     struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
0412     unsigned int val;
0413 
0414     val = snd_soc_component_read(component, RT1305_CLK_1);
0415 
0416     if (rt1305->sysclk_src == RT1305_FS_SYS_PRE_S_PLL1 &&
0417         (val & RT1305_SEL_PLL_SRC_2_RCCLK))
0418         return 1;
0419     else
0420         return 0;
0421 }
0422 
0423 static int rt1305_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
0424              struct snd_soc_dapm_widget *sink)
0425 {
0426     struct snd_soc_component *component =
0427         snd_soc_dapm_to_component(source->dapm);
0428     struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
0429 
0430     if (rt1305->sysclk_src == RT1305_FS_SYS_PRE_S_PLL1)
0431         return 1;
0432     else
0433         return 0;
0434 }
0435 
0436 static int rt1305_classd_event(struct snd_soc_dapm_widget *w,
0437     struct snd_kcontrol *kcontrol, int event)
0438 {
0439     struct snd_soc_component *component =
0440         snd_soc_dapm_to_component(w->dapm);
0441 
0442     switch (event) {
0443     case SND_SOC_DAPM_POST_PMU:
0444         snd_soc_component_update_bits(component, RT1305_POWER_CTRL_1,
0445             RT1305_POW_PDB_JD_MASK, RT1305_POW_PDB_JD);
0446         break;
0447     case SND_SOC_DAPM_PRE_PMD:
0448         snd_soc_component_update_bits(component, RT1305_POWER_CTRL_1,
0449             RT1305_POW_PDB_JD_MASK, 0);
0450         usleep_range(150000, 200000);
0451         break;
0452 
0453     default:
0454         return 0;
0455     }
0456 
0457     return 0;
0458 }
0459 
0460 static const struct snd_kcontrol_new rt1305_sto_dac_l =
0461     SOC_DAPM_SINGLE("Switch", RT1305_DAC_SET_2,
0462         RT1305_DVOL_MUTE_L_EN_SFT, 1, 1);
0463 
0464 static const struct snd_kcontrol_new rt1305_sto_dac_r =
0465     SOC_DAPM_SINGLE("Switch", RT1305_DAC_SET_2,
0466         RT1305_DVOL_MUTE_R_EN_SFT, 1, 1);
0467 
0468 static const struct snd_soc_dapm_widget rt1305_dapm_widgets[] = {
0469     SND_SOC_DAPM_SUPPLY("PLL0", RT1305_POWER_CTRL_1,
0470         RT1305_POW_PLL0_EN_BIT, 0, NULL, 0),
0471     SND_SOC_DAPM_SUPPLY("PLL1", RT1305_POWER_CTRL_1,
0472         RT1305_POW_PLL1_EN_BIT, 0, NULL, 0),
0473     SND_SOC_DAPM_SUPPLY("MBIAS", RT1305_POWER_CTRL_1,
0474         RT1305_POW_MBIAS_LV_BIT, 0, NULL, 0),
0475     SND_SOC_DAPM_SUPPLY("BG MBIAS", RT1305_POWER_CTRL_1,
0476         RT1305_POW_BG_MBIAS_LV_BIT, 0, NULL, 0),
0477     SND_SOC_DAPM_SUPPLY("LDO2", RT1305_POWER_CTRL_1,
0478         RT1305_POW_LDO2_BIT, 0, NULL, 0),
0479     SND_SOC_DAPM_SUPPLY("BG2", RT1305_POWER_CTRL_1,
0480         RT1305_POW_BG2_BIT, 0, NULL, 0),
0481     SND_SOC_DAPM_SUPPLY("LDO2 IB2", RT1305_POWER_CTRL_1,
0482         RT1305_POW_LDO2_IB2_BIT, 0, NULL, 0),
0483     SND_SOC_DAPM_SUPPLY("VREF", RT1305_POWER_CTRL_1,
0484         RT1305_POW_VREF_BIT, 0, NULL, 0),
0485     SND_SOC_DAPM_SUPPLY("VREF1", RT1305_POWER_CTRL_1,
0486         RT1305_POW_VREF1_BIT, 0, NULL, 0),
0487     SND_SOC_DAPM_SUPPLY("VREF2", RT1305_POWER_CTRL_1,
0488         RT1305_POW_VREF2_BIT, 0, NULL, 0),
0489 
0490 
0491     SND_SOC_DAPM_SUPPLY("DISC VREF", RT1305_POWER_CTRL_2,
0492         RT1305_POW_DISC_VREF_BIT, 0, NULL, 0),
0493     SND_SOC_DAPM_SUPPLY("FASTB VREF", RT1305_POWER_CTRL_2,
0494         RT1305_POW_FASTB_VREF_BIT, 0, NULL, 0),
0495     SND_SOC_DAPM_SUPPLY("ULTRA FAST VREF", RT1305_POWER_CTRL_2,
0496         RT1305_POW_ULTRA_FAST_VREF_BIT, 0, NULL, 0),
0497     SND_SOC_DAPM_SUPPLY("CHOP DAC", RT1305_POWER_CTRL_2,
0498         RT1305_POW_CKXEN_DAC_BIT, 0, NULL, 0),
0499     SND_SOC_DAPM_SUPPLY("CKGEN DAC", RT1305_POWER_CTRL_2,
0500         RT1305_POW_EN_CKGEN_DAC_BIT, 0, NULL, 0),
0501     SND_SOC_DAPM_SUPPLY("CLAMP", RT1305_POWER_CTRL_2,
0502         RT1305_POW_CLAMP_BIT, 0, NULL, 0),
0503     SND_SOC_DAPM_SUPPLY("BUFL", RT1305_POWER_CTRL_2,
0504         RT1305_POW_BUFL_BIT, 0, NULL, 0),
0505     SND_SOC_DAPM_SUPPLY("BUFR", RT1305_POWER_CTRL_2,
0506         RT1305_POW_BUFR_BIT, 0, NULL, 0),
0507     SND_SOC_DAPM_SUPPLY("CKGEN ADC", RT1305_POWER_CTRL_2,
0508         RT1305_POW_EN_CKGEN_ADC_BIT, 0, NULL, 0),
0509     SND_SOC_DAPM_SUPPLY("ADC3 L", RT1305_POWER_CTRL_2,
0510         RT1305_POW_ADC3_L_BIT, 0, NULL, 0),
0511     SND_SOC_DAPM_SUPPLY("ADC3 R", RT1305_POWER_CTRL_2,
0512         RT1305_POW_ADC3_R_BIT, 0, NULL, 0),
0513     SND_SOC_DAPM_SUPPLY("TRIOSC", RT1305_POWER_CTRL_2,
0514         RT1305_POW_TRIOSC_BIT, 0, NULL, 0),
0515     SND_SOC_DAPM_SUPPLY("AVDD1", RT1305_POWER_CTRL_2,
0516         RT1305_POR_AVDD1_BIT, 0, NULL, 0),
0517     SND_SOC_DAPM_SUPPLY("AVDD2", RT1305_POWER_CTRL_2,
0518         RT1305_POR_AVDD2_BIT, 0, NULL, 0),
0519 
0520 
0521     SND_SOC_DAPM_SUPPLY("VSENSE R", RT1305_POWER_CTRL_3,
0522         RT1305_POW_VSENSE_RCH_BIT, 0, NULL, 0),
0523     SND_SOC_DAPM_SUPPLY("VSENSE L", RT1305_POWER_CTRL_3,
0524         RT1305_POW_VSENSE_LCH_BIT, 0, NULL, 0),
0525     SND_SOC_DAPM_SUPPLY("ISENSE R", RT1305_POWER_CTRL_3,
0526         RT1305_POW_ISENSE_RCH_BIT, 0, NULL, 0),
0527     SND_SOC_DAPM_SUPPLY("ISENSE L", RT1305_POWER_CTRL_3,
0528         RT1305_POW_ISENSE_LCH_BIT, 0, NULL, 0),
0529     SND_SOC_DAPM_SUPPLY("POR AVDD1", RT1305_POWER_CTRL_3,
0530         RT1305_POW_POR_AVDD1_BIT, 0, NULL, 0),
0531     SND_SOC_DAPM_SUPPLY("POR AVDD2", RT1305_POWER_CTRL_3,
0532         RT1305_POW_POR_AVDD2_BIT, 0, NULL, 0),
0533     SND_SOC_DAPM_SUPPLY("VCM 6172", RT1305_POWER_CTRL_3,
0534         RT1305_EN_VCM_6172_BIT, 0, NULL, 0),
0535 
0536 
0537     /* Audio Interface */
0538     SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
0539 
0540     /* Digital Interface */
0541     SND_SOC_DAPM_SUPPLY("DAC L Power", RT1305_POWER_CTRL_2,
0542         RT1305_POW_DAC1_L_BIT, 0, NULL, 0),
0543     SND_SOC_DAPM_SUPPLY("DAC R Power", RT1305_POWER_CTRL_2,
0544         RT1305_POW_DAC1_R_BIT, 0, NULL, 0),
0545     SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
0546     SND_SOC_DAPM_SWITCH("DAC L", SND_SOC_NOPM, 0, 0, &rt1305_sto_dac_l),
0547     SND_SOC_DAPM_SWITCH("DAC R", SND_SOC_NOPM, 0, 0, &rt1305_sto_dac_r),
0548 
0549     /* Output Lines */
0550     SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0,
0551         rt1305_classd_event,
0552         SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
0553     SND_SOC_DAPM_OUTPUT("SPOL"),
0554     SND_SOC_DAPM_OUTPUT("SPOR"),
0555 };
0556 
0557 static const struct snd_soc_dapm_route rt1305_dapm_routes[] = {
0558 
0559     { "DAC", NULL, "AIF1RX" },
0560 
0561     { "DAC", NULL, "PLL0", rt1305_is_rc_clk_from_pll },
0562     { "DAC", NULL, "PLL1", rt1305_is_sys_clk_from_pll },
0563 
0564     { "DAC", NULL, "MBIAS" },
0565     { "DAC", NULL, "BG MBIAS" },
0566     { "DAC", NULL, "LDO2" },
0567     { "DAC", NULL, "BG2" },
0568     { "DAC", NULL, "LDO2 IB2" },
0569     { "DAC", NULL, "VREF" },
0570     { "DAC", NULL, "VREF1" },
0571     { "DAC", NULL, "VREF2" },
0572 
0573     { "DAC", NULL, "DISC VREF" },
0574     { "DAC", NULL, "FASTB VREF" },
0575     { "DAC", NULL, "ULTRA FAST VREF" },
0576     { "DAC", NULL, "CHOP DAC" },
0577     { "DAC", NULL, "CKGEN DAC" },
0578     { "DAC", NULL, "CLAMP" },
0579     { "DAC", NULL, "CKGEN ADC" },
0580     { "DAC", NULL, "TRIOSC" },
0581     { "DAC", NULL, "AVDD1" },
0582     { "DAC", NULL, "AVDD2" },
0583 
0584     { "DAC", NULL, "POR AVDD1" },
0585     { "DAC", NULL, "POR AVDD2" },
0586     { "DAC", NULL, "VCM 6172" },
0587 
0588     { "DAC L", "Switch", "DAC" },
0589     { "DAC R", "Switch", "DAC" },
0590 
0591     { "DAC R", NULL, "VSENSE R" },
0592     { "DAC L", NULL, "VSENSE L" },
0593     { "DAC R", NULL, "ISENSE R" },
0594     { "DAC L", NULL, "ISENSE L" },
0595     { "DAC L", NULL, "ADC3 L" },
0596     { "DAC R", NULL, "ADC3 R" },
0597     { "DAC L", NULL, "BUFL" },
0598     { "DAC R", NULL, "BUFR" },
0599     { "DAC L", NULL, "DAC L Power" },
0600     { "DAC R", NULL, "DAC R Power" },
0601 
0602     { "CLASS D", NULL, "DAC L" },
0603     { "CLASS D", NULL, "DAC R" },
0604 
0605     { "SPOL", NULL, "CLASS D" },
0606     { "SPOR", NULL, "CLASS D" },
0607 };
0608 
0609 static int rt1305_get_clk_info(int sclk, int rate)
0610 {
0611     int i;
0612     static const int pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
0613 
0614     if (sclk <= 0 || rate <= 0)
0615         return -EINVAL;
0616 
0617     rate = rate << 8;
0618     for (i = 0; i < ARRAY_SIZE(pd); i++)
0619         if (sclk == rate * pd[i])
0620             return i;
0621 
0622     return -EINVAL;
0623 }
0624 
0625 static int rt1305_hw_params(struct snd_pcm_substream *substream,
0626     struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
0627 {
0628     struct snd_soc_component *component = dai->component;
0629     struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
0630     unsigned int val_len = 0, val_clk, mask_clk;
0631     int pre_div, bclk_ms, frame_size;
0632 
0633     rt1305->lrck = params_rate(params);
0634     pre_div = rt1305_get_clk_info(rt1305->sysclk, rt1305->lrck);
0635     if (pre_div < 0) {
0636         dev_warn(component->dev, "Force using PLL ");
0637         snd_soc_dai_set_pll(dai, 0, RT1305_PLL1_S_BCLK,
0638             rt1305->lrck * 64, rt1305->lrck * 256);
0639         snd_soc_dai_set_sysclk(dai, RT1305_FS_SYS_PRE_S_PLL1,
0640             rt1305->lrck * 256, SND_SOC_CLOCK_IN);
0641         pre_div = 0;
0642     }
0643     frame_size = snd_soc_params_to_frame_size(params);
0644     if (frame_size < 0) {
0645         dev_err(component->dev, "Unsupported frame size: %d\n",
0646             frame_size);
0647         return -EINVAL;
0648     }
0649 
0650     bclk_ms = frame_size > 32;
0651     rt1305->bclk = rt1305->lrck * (32 << bclk_ms);
0652 
0653     dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
0654                 bclk_ms, pre_div, dai->id);
0655 
0656     dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
0657                 rt1305->lrck, pre_div, dai->id);
0658 
0659     switch (params_width(params)) {
0660     case 16:
0661         val_len |= RT1305_I2S_DL_SEL_16B;
0662         break;
0663     case 20:
0664         val_len |= RT1305_I2S_DL_SEL_20B;
0665         break;
0666     case 24:
0667         val_len |= RT1305_I2S_DL_SEL_24B;
0668         break;
0669     case 8:
0670         val_len |= RT1305_I2S_DL_SEL_8B;
0671         break;
0672     default:
0673         return -EINVAL;
0674     }
0675 
0676     switch (dai->id) {
0677     case RT1305_AIF1:
0678         mask_clk = RT1305_DIV_FS_SYS_MASK;
0679         val_clk = pre_div << RT1305_DIV_FS_SYS_SFT;
0680         snd_soc_component_update_bits(component, RT1305_I2S_SET_2,
0681             RT1305_I2S_DL_SEL_MASK,
0682             val_len);
0683         break;
0684     default:
0685         dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
0686         return -EINVAL;
0687     }
0688 
0689     snd_soc_component_update_bits(component, RT1305_CLK_2,
0690         mask_clk, val_clk);
0691 
0692     return 0;
0693 }
0694 
0695 static int rt1305_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
0696 {
0697     struct snd_soc_component *component = dai->component;
0698     struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
0699     unsigned int reg_val = 0, reg1_val = 0;
0700 
0701     switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
0702     case SND_SOC_DAIFMT_CBM_CFM:
0703         reg_val |= RT1305_SEL_I2S_OUT_MODE_M;
0704         rt1305->master = 1;
0705         break;
0706     case SND_SOC_DAIFMT_CBS_CFS:
0707         reg_val |= RT1305_SEL_I2S_OUT_MODE_S;
0708         rt1305->master = 0;
0709         break;
0710     default:
0711         return -EINVAL;
0712     }
0713 
0714     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0715     case SND_SOC_DAIFMT_NB_NF:
0716         break;
0717     case SND_SOC_DAIFMT_IB_NF:
0718         reg1_val |= RT1305_I2S_BCLK_INV;
0719         break;
0720     default:
0721         return -EINVAL;
0722     }
0723 
0724     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0725     case SND_SOC_DAIFMT_I2S:
0726         break;
0727     case SND_SOC_DAIFMT_LEFT_J:
0728         reg1_val |= RT1305_I2S_DF_SEL_LEFT;
0729         break;
0730     case SND_SOC_DAIFMT_DSP_A:
0731         reg1_val |= RT1305_I2S_DF_SEL_PCM_A;
0732         break;
0733     case SND_SOC_DAIFMT_DSP_B:
0734         reg1_val |= RT1305_I2S_DF_SEL_PCM_B;
0735         break;
0736     default:
0737         return -EINVAL;
0738     }
0739 
0740     switch (dai->id) {
0741     case RT1305_AIF1:
0742         snd_soc_component_update_bits(component, RT1305_I2S_SET_1,
0743             RT1305_SEL_I2S_OUT_MODE_MASK, reg_val);
0744         snd_soc_component_update_bits(component, RT1305_I2S_SET_2,
0745             RT1305_I2S_DF_SEL_MASK | RT1305_I2S_BCLK_MASK,
0746             reg1_val);
0747         break;
0748     default:
0749         dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
0750         return -EINVAL;
0751     }
0752     return 0;
0753 }
0754 
0755 static int rt1305_set_component_sysclk(struct snd_soc_component *component,
0756         int clk_id, int source, unsigned int freq, int dir)
0757 {
0758     struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
0759     unsigned int reg_val = 0;
0760 
0761     if (freq == rt1305->sysclk && clk_id == rt1305->sysclk_src)
0762         return 0;
0763 
0764     switch (clk_id) {
0765     case RT1305_FS_SYS_PRE_S_MCLK:
0766         reg_val |= RT1305_SEL_FS_SYS_PRE_MCLK;
0767         snd_soc_component_update_bits(component,
0768             RT1305_CLOCK_DETECT, RT1305_SEL_CLK_DET_SRC_MASK,
0769             RT1305_SEL_CLK_DET_SRC_MCLK);
0770         break;
0771     case RT1305_FS_SYS_PRE_S_PLL1:
0772         reg_val |= RT1305_SEL_FS_SYS_PRE_PLL;
0773         break;
0774     case RT1305_FS_SYS_PRE_S_RCCLK:
0775         reg_val |= RT1305_SEL_FS_SYS_PRE_RCCLK;
0776         break;
0777     default:
0778         dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
0779         return -EINVAL;
0780     }
0781     snd_soc_component_update_bits(component, RT1305_CLK_1,
0782         RT1305_SEL_FS_SYS_PRE_MASK, reg_val);
0783     rt1305->sysclk = freq;
0784     rt1305->sysclk_src = clk_id;
0785 
0786     dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
0787         freq, clk_id);
0788 
0789     return 0;
0790 }
0791 
0792 static int rt1305_set_component_pll(struct snd_soc_component *component,
0793         int pll_id, int source, unsigned int freq_in,
0794         unsigned int freq_out)
0795 {
0796     struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
0797     struct rl6231_pll_code pll_code;
0798     int ret;
0799 
0800     if (source == rt1305->pll_src && freq_in == rt1305->pll_in &&
0801         freq_out == rt1305->pll_out)
0802         return 0;
0803 
0804     if (!freq_in || !freq_out) {
0805         dev_dbg(component->dev, "PLL disabled\n");
0806 
0807         rt1305->pll_in = 0;
0808         rt1305->pll_out = 0;
0809         snd_soc_component_update_bits(component, RT1305_CLK_1,
0810             RT1305_SEL_FS_SYS_PRE_MASK | RT1305_SEL_PLL_SRC_1_MASK,
0811             RT1305_SEL_FS_SYS_PRE_PLL | RT1305_SEL_PLL_SRC_1_BCLK);
0812         return 0;
0813     }
0814 
0815     switch (source) {
0816     case RT1305_PLL2_S_MCLK:
0817         snd_soc_component_update_bits(component, RT1305_CLK_1,
0818             RT1305_SEL_PLL_SRC_2_MASK | RT1305_SEL_PLL_SRC_1_MASK |
0819             RT1305_DIV_PLL_SRC_2_MASK,
0820             RT1305_SEL_PLL_SRC_2_MCLK | RT1305_SEL_PLL_SRC_1_PLL2);
0821         snd_soc_component_update_bits(component,
0822             RT1305_CLOCK_DETECT, RT1305_SEL_CLK_DET_SRC_MASK,
0823             RT1305_SEL_CLK_DET_SRC_MCLK);
0824         break;
0825     case RT1305_PLL1_S_BCLK:
0826         snd_soc_component_update_bits(component,
0827             RT1305_CLK_1, RT1305_SEL_PLL_SRC_1_MASK,
0828             RT1305_SEL_PLL_SRC_1_BCLK);
0829         break;
0830     case RT1305_PLL2_S_RCCLK:
0831         snd_soc_component_update_bits(component, RT1305_CLK_1,
0832             RT1305_SEL_PLL_SRC_2_MASK | RT1305_SEL_PLL_SRC_1_MASK |
0833             RT1305_DIV_PLL_SRC_2_MASK,
0834             RT1305_SEL_PLL_SRC_2_RCCLK | RT1305_SEL_PLL_SRC_1_PLL2);
0835         freq_in = 98304000;
0836         break;
0837     default:
0838         dev_err(component->dev, "Unknown PLL Source %d\n", source);
0839         return -EINVAL;
0840     }
0841 
0842     ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
0843     if (ret < 0) {
0844         dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
0845         return ret;
0846     }
0847 
0848     dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
0849         pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
0850         pll_code.n_code, pll_code.k_code);
0851 
0852     snd_soc_component_write(component, RT1305_PLL1_1,
0853         ((pll_code.m_bp ? 0 : pll_code.m_code) << RT1305_PLL_1_M_SFT) |
0854         (pll_code.m_bp << RT1305_PLL_1_M_BYPASS_SFT) |
0855         pll_code.n_code);
0856     snd_soc_component_write(component, RT1305_PLL1_2,
0857         pll_code.k_code);
0858 
0859     rt1305->pll_in = freq_in;
0860     rt1305->pll_out = freq_out;
0861     rt1305->pll_src = source;
0862 
0863     return 0;
0864 }
0865 
0866 static int rt1305_probe(struct snd_soc_component *component)
0867 {
0868     struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
0869 
0870     rt1305->component = component;
0871 
0872     /* initial settings */
0873     rt1305_reg_init(component);
0874 
0875     return 0;
0876 }
0877 
0878 static void rt1305_remove(struct snd_soc_component *component)
0879 {
0880     struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
0881 
0882     rt1305_reset(rt1305->regmap);
0883 }
0884 
0885 #ifdef CONFIG_PM
0886 static int rt1305_suspend(struct snd_soc_component *component)
0887 {
0888     struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
0889 
0890     regcache_cache_only(rt1305->regmap, true);
0891     regcache_mark_dirty(rt1305->regmap);
0892 
0893     return 0;
0894 }
0895 
0896 static int rt1305_resume(struct snd_soc_component *component)
0897 {
0898     struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
0899 
0900     regcache_cache_only(rt1305->regmap, false);
0901     regcache_sync(rt1305->regmap);
0902 
0903     return 0;
0904 }
0905 #else
0906 #define rt1305_suspend NULL
0907 #define rt1305_resume NULL
0908 #endif
0909 
0910 #define RT1305_STEREO_RATES SNDRV_PCM_RATE_8000_192000
0911 #define RT1305_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
0912             SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \
0913             SNDRV_PCM_FMTBIT_S24_LE)
0914 
0915 static const struct snd_soc_dai_ops rt1305_aif_dai_ops = {
0916     .hw_params = rt1305_hw_params,
0917     .set_fmt = rt1305_set_dai_fmt,
0918 };
0919 
0920 static struct snd_soc_dai_driver rt1305_dai[] = {
0921     {
0922         .name = "rt1305-aif",
0923         .playback = {
0924             .stream_name = "AIF1 Playback",
0925             .channels_min = 1,
0926             .channels_max = 2,
0927             .rates = RT1305_STEREO_RATES,
0928             .formats = RT1305_FORMATS,
0929         },
0930         .ops = &rt1305_aif_dai_ops,
0931     },
0932 };
0933 
0934 static const struct snd_soc_component_driver soc_component_dev_rt1305 = {
0935     .probe = rt1305_probe,
0936     .remove = rt1305_remove,
0937     .suspend = rt1305_suspend,
0938     .resume = rt1305_resume,
0939     .controls = rt1305_snd_controls,
0940     .num_controls = ARRAY_SIZE(rt1305_snd_controls),
0941     .dapm_widgets = rt1305_dapm_widgets,
0942     .num_dapm_widgets = ARRAY_SIZE(rt1305_dapm_widgets),
0943     .dapm_routes = rt1305_dapm_routes,
0944     .num_dapm_routes = ARRAY_SIZE(rt1305_dapm_routes),
0945     .set_sysclk = rt1305_set_component_sysclk,
0946     .set_pll = rt1305_set_component_pll,
0947     .use_pmdown_time    = 1,
0948     .endianness     = 1,
0949 };
0950 
0951 static const struct regmap_config rt1305_regmap = {
0952     .reg_bits = 8,
0953     .val_bits = 16,
0954     .max_register = RT1305_MAX_REG + 1 + (ARRAY_SIZE(rt1305_ranges) *
0955                            RT1305_PR_SPACING),
0956     .volatile_reg = rt1305_volatile_register,
0957     .readable_reg = rt1305_readable_register,
0958     .cache_type = REGCACHE_RBTREE,
0959     .reg_defaults = rt1305_reg,
0960     .num_reg_defaults = ARRAY_SIZE(rt1305_reg),
0961     .ranges = rt1305_ranges,
0962     .num_ranges = ARRAY_SIZE(rt1305_ranges),
0963     .use_single_read = true,
0964     .use_single_write = true,
0965 };
0966 
0967 #if defined(CONFIG_OF)
0968 static const struct of_device_id rt1305_of_match[] = {
0969     { .compatible = "realtek,rt1305", },
0970     { .compatible = "realtek,rt1306", },
0971     {},
0972 };
0973 MODULE_DEVICE_TABLE(of, rt1305_of_match);
0974 #endif
0975 
0976 #ifdef CONFIG_ACPI
0977 static const struct acpi_device_id rt1305_acpi_match[] = {
0978     {"10EC1305", 0,},
0979     {"10EC1306", 0,},
0980     {},
0981 };
0982 MODULE_DEVICE_TABLE(acpi, rt1305_acpi_match);
0983 #endif
0984 
0985 static const struct i2c_device_id rt1305_i2c_id[] = {
0986     { "rt1305", 0 },
0987     { "rt1306", 0 },
0988     { }
0989 };
0990 MODULE_DEVICE_TABLE(i2c, rt1305_i2c_id);
0991 
0992 static void rt1305_calibrate(struct rt1305_priv *rt1305)
0993 {
0994     unsigned int valmsb, vallsb, offsetl, offsetr;
0995     unsigned int rh, rl, rhl, r0ohm;
0996     u64 r0l, r0r;
0997 
0998     regcache_cache_bypass(rt1305->regmap, true);
0999 
1000     rt1305_reset(rt1305->regmap);
1001     regmap_write(rt1305->regmap, RT1305_ADC_SET_3, 0x0219);
1002     regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xcf, 0x5548);
1003     regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc1, 0x0320);
1004     regmap_write(rt1305->regmap, RT1305_CLOCK_DETECT, 0x1000);
1005     regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0600);
1006     regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xffd0);
1007     regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0080);
1008     regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880);
1009     regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0dfe);
1010 
1011     /* Sin Gen */
1012     regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x0442);
1013 
1014     regmap_write(rt1305->regmap, RT1305_CAL_EFUSE_CLOCK, 0xb000);
1015     regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc3, 0xd4a0);
1016     regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xcc, 0x00cc);
1017     regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc1, 0x0320);
1018     regmap_write(rt1305->regmap, RT1305_POWER_STATUS, 0x0000);
1019     regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0xffff);
1020     regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfc20);
1021     regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x06, 0x00c0);
1022     regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfca0);
1023     regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfce0);
1024     regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfcf0);
1025 
1026     /* EFUSE read */
1027     regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0080);
1028     regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880);
1029     regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880);
1030     regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfce0);
1031     regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfca0);
1032     regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfc20);
1033     regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x06, 0x0000);
1034     regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0000);
1035 
1036     regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_5, &valmsb);
1037     regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_6, &vallsb);
1038     offsetl = valmsb << 16 | vallsb;
1039     regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_7, &valmsb);
1040     regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_8, &vallsb);
1041     offsetr = valmsb << 16 | vallsb;
1042     pr_info("DC offsetl=0x%x, offsetr=0x%x\n", offsetl, offsetr);
1043 
1044     /* R0 calibration */
1045     regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x9542);
1046     regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfcf0);
1047     regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0xffff);
1048     regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x1dfe);
1049     regmap_write(rt1305->regmap, RT1305_SILENCE_DETECT, 0x0e13);
1050     regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0650);
1051 
1052     regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x50, 0x0064);
1053     regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x51, 0x0770);
1054     regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x52, 0xc30c);
1055     regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0x8200);
1056     regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xfb00);
1057     regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xff80);
1058     msleep(2000);
1059     regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x55, &rh);
1060     regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x56, &rl);
1061     rhl = (rh << 16) | rl;
1062     r0ohm = (rhl*10) / 33554432;
1063 
1064     pr_debug("Left_rhl = 0x%x rh=0x%x rl=0x%x\n", rhl, rh, rl);
1065     pr_info("Left channel %d.%dohm\n", (r0ohm/10), (r0ohm%10));
1066 
1067     r0l = 562949953421312ULL;
1068     if (rhl != 0)
1069         do_div(r0l, rhl);
1070     pr_debug("Left_r0 = 0x%llx\n", r0l);
1071 
1072     regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0x9200);
1073     regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xfb00);
1074     regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xff80);
1075     msleep(2000);
1076     regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x55, &rh);
1077     regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x56, &rl);
1078     rhl = (rh << 16) | rl;
1079     r0ohm = (rhl*10) / 33554432;
1080 
1081     pr_debug("Right_rhl = 0x%x rh=0x%x rl=0x%x\n", rhl, rh, rl);
1082     pr_info("Right channel %d.%dohm\n", (r0ohm/10), (r0ohm%10));
1083 
1084     r0r = 562949953421312ULL;
1085     if (rhl != 0)
1086         do_div(r0r, rhl);
1087     pr_debug("Right_r0 = 0x%llx\n", r0r);
1088 
1089     regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0xc2ec);
1090 
1091     if ((r0l > R0_UPPER) && (r0l < R0_LOWER) &&
1092         (r0r > R0_UPPER) && (r0r < R0_LOWER)) {
1093         regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x4e,
1094             (r0l >> 16) & 0xffff);
1095         regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x4f,
1096             r0l & 0xffff);
1097         regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xfe,
1098             ((r0r >> 16) & 0xffff) | 0xf800);
1099         regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xfd,
1100             r0r & 0xffff);
1101     } else {
1102         pr_err("R0 calibration failed\n");
1103     }
1104 
1105     /* restore some registers */
1106     regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0dfe);
1107     usleep_range(200000, 400000);
1108     regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x0442);
1109     regmap_write(rt1305->regmap, RT1305_CLOCK_DETECT, 0x3000);
1110     regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0400);
1111     regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0000);
1112     regmap_write(rt1305->regmap, RT1305_CAL_EFUSE_CLOCK, 0x8000);
1113     regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0x1020);
1114     regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0x0000);
1115 
1116     regcache_cache_bypass(rt1305->regmap, false);
1117 }
1118 
1119 static int rt1305_i2c_probe(struct i2c_client *i2c)
1120 {
1121     struct rt1305_priv *rt1305;
1122     int ret;
1123     unsigned int val;
1124 
1125     rt1305 = devm_kzalloc(&i2c->dev, sizeof(struct rt1305_priv),
1126                 GFP_KERNEL);
1127     if (rt1305 == NULL)
1128         return -ENOMEM;
1129 
1130     i2c_set_clientdata(i2c, rt1305);
1131 
1132     rt1305->regmap = devm_regmap_init_i2c(i2c, &rt1305_regmap);
1133     if (IS_ERR(rt1305->regmap)) {
1134         ret = PTR_ERR(rt1305->regmap);
1135         dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1136             ret);
1137         return ret;
1138     }
1139 
1140     regmap_read(rt1305->regmap, RT1305_DEVICE_ID, &val);
1141     if (val != RT1305_DEVICE_ID_NUM) {
1142         dev_err(&i2c->dev,
1143             "Device with ID register %x is not rt1305\n", val);
1144         return -ENODEV;
1145     }
1146 
1147     rt1305_reset(rt1305->regmap);
1148     rt1305_calibrate(rt1305);
1149 
1150     return devm_snd_soc_register_component(&i2c->dev,
1151             &soc_component_dev_rt1305,
1152             rt1305_dai, ARRAY_SIZE(rt1305_dai));
1153 }
1154 
1155 static void rt1305_i2c_shutdown(struct i2c_client *client)
1156 {
1157     struct rt1305_priv *rt1305 = i2c_get_clientdata(client);
1158 
1159     rt1305_reset(rt1305->regmap);
1160 }
1161 
1162 
1163 static struct i2c_driver rt1305_i2c_driver = {
1164     .driver = {
1165         .name = "rt1305",
1166 #if defined(CONFIG_OF)
1167         .of_match_table = rt1305_of_match,
1168 #endif
1169 #if defined(CONFIG_ACPI)
1170         .acpi_match_table = ACPI_PTR(rt1305_acpi_match)
1171 #endif
1172     },
1173     .probe_new = rt1305_i2c_probe,
1174     .shutdown = rt1305_i2c_shutdown,
1175     .id_table = rt1305_i2c_id,
1176 };
1177 module_i2c_driver(rt1305_i2c_driver);
1178 
1179 MODULE_DESCRIPTION("ASoC RT1305 amplifier driver");
1180 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>");
1181 MODULE_LICENSE("GPL v2");
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