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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 //
0003 // rt1019.c  --  RT1019 ALSA SoC audio amplifier driver
0004 // Author: Jack Yu <jack.yu@realtek.com>
0005 //
0006 // Copyright(c) 2021 Realtek Semiconductor Corp.
0007 //
0008 //
0009 
0010 #include <linux/acpi.h>
0011 #include <linux/fs.h>
0012 #include <linux/module.h>
0013 #include <linux/moduleparam.h>
0014 #include <linux/init.h>
0015 #include <linux/delay.h>
0016 #include <linux/pm.h>
0017 #include <linux/regmap.h>
0018 #include <linux/i2c.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/firmware.h>
0021 #include <linux/gpio.h>
0022 #include <sound/core.h>
0023 #include <sound/pcm.h>
0024 #include <sound/pcm_params.h>
0025 #include <sound/soc.h>
0026 #include <sound/soc-dapm.h>
0027 #include <sound/initval.h>
0028 #include <sound/tlv.h>
0029 
0030 #include "rl6231.h"
0031 #include "rt1019.h"
0032 
0033 static const struct reg_default rt1019_reg[] = {
0034     { 0x0000, 0x00 },
0035     { 0x0011, 0x04 },
0036     { 0x0013, 0x00 },
0037     { 0x0019, 0x30 },
0038     { 0x001b, 0x01 },
0039     { 0x005c, 0x00 },
0040     { 0x005e, 0x10 },
0041     { 0x005f, 0xec },
0042     { 0x0061, 0x10 },
0043     { 0x0062, 0x19 },
0044     { 0x0066, 0x08 },
0045     { 0x0100, 0x80 },
0046     { 0x0100, 0x51 },
0047     { 0x0102, 0x23 },
0048     { 0x0311, 0x00 },
0049     { 0x0312, 0x3e },
0050     { 0x0313, 0x86 },
0051     { 0x0400, 0x03 },
0052     { 0x0401, 0x02 },
0053     { 0x0402, 0x01 },
0054     { 0x0504, 0xff },
0055     { 0x0505, 0x24 },
0056     { 0x0b00, 0x50 },
0057     { 0x0b01, 0xc3 },
0058 };
0059 
0060 static bool rt1019_volatile_register(struct device *dev, unsigned int reg)
0061 {
0062     switch (reg) {
0063     case RT1019_PWR_STRP_2:
0064     case RT1019_VER_ID:
0065     case RT1019_VEND_ID_1:
0066     case RT1019_VEND_ID_2:
0067     case RT1019_DEV_ID_1:
0068     case RT1019_DEV_ID_2:
0069         return true;
0070 
0071     default:
0072         return false;
0073     }
0074 }
0075 
0076 static bool rt1019_readable_register(struct device *dev, unsigned int reg)
0077 {
0078     switch (reg) {
0079     case RT1019_RESET:
0080     case RT1019_IDS_CTRL:
0081     case RT1019_ASEL_CTRL:
0082     case RT1019_PWR_STRP_2:
0083     case RT1019_BEEP_TONE:
0084     case RT1019_VER_ID:
0085     case RT1019_VEND_ID_1:
0086     case RT1019_VEND_ID_2:
0087     case RT1019_DEV_ID_1:
0088     case RT1019_DEV_ID_2:
0089     case RT1019_SDB_CTRL:
0090     case RT1019_CLK_TREE_1:
0091     case RT1019_CLK_TREE_2:
0092     case RT1019_CLK_TREE_3:
0093     case RT1019_PLL_1:
0094     case RT1019_PLL_2:
0095     case RT1019_PLL_3:
0096     case RT1019_TDM_1:
0097     case RT1019_TDM_2:
0098     case RT1019_TDM_3:
0099     case RT1019_DMIX_MONO_1:
0100     case RT1019_DMIX_MONO_2:
0101     case RT1019_BEEP_1:
0102     case RT1019_BEEP_2:
0103         return true;
0104     default:
0105         return false;
0106     }
0107 }
0108 
0109 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9525, 75, 0);
0110 
0111 static const char * const rt1019_din_source_select[] = {
0112     "Left",
0113     "Right",
0114     "Left + Right average",
0115 };
0116 
0117 static SOC_ENUM_SINGLE_DECL(rt1019_mono_lr_sel, RT1019_IDS_CTRL, 0,
0118     rt1019_din_source_select);
0119 
0120 static const struct snd_kcontrol_new rt1019_snd_controls[] = {
0121     SOC_SINGLE_TLV("DAC Playback Volume", RT1019_DMIX_MONO_1, 0,
0122         127, 0, dac_vol_tlv),
0123     SOC_ENUM("Mono LR Select", rt1019_mono_lr_sel),
0124 };
0125 
0126 static int r1019_dac_event(struct snd_soc_dapm_widget *w,
0127     struct snd_kcontrol *kcontrol, int event)
0128 {
0129     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0130 
0131     switch (event) {
0132     case SND_SOC_DAPM_PRE_PMU:
0133         snd_soc_component_write(component, RT1019_SDB_CTRL, 0xb);
0134         break;
0135     case SND_SOC_DAPM_POST_PMD:
0136         snd_soc_component_write(component, RT1019_SDB_CTRL, 0xa);
0137         break;
0138     default:
0139         break;
0140     }
0141 
0142     return 0;
0143 }
0144 
0145 static const struct snd_soc_dapm_widget rt1019_dapm_widgets[] = {
0146     SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
0147     SND_SOC_DAPM_DAC_E("DAC", NULL, SND_SOC_NOPM, 0, 0,
0148         r1019_dac_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0149     SND_SOC_DAPM_OUTPUT("SPO"),
0150 };
0151 
0152 static const struct snd_soc_dapm_route rt1019_dapm_routes[] = {
0153     { "DAC", NULL, "AIFRX" },
0154     { "SPO", NULL, "DAC" },
0155 };
0156 
0157 static int rt1019_hw_params(struct snd_pcm_substream *substream,
0158     struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
0159 {
0160     struct snd_soc_component *component = dai->component;
0161     struct rt1019_priv *rt1019 = snd_soc_component_get_drvdata(component);
0162     int pre_div, bclk_ms, frame_size;
0163     unsigned int val_len = 0, sys_div_da_filter = 0;
0164     unsigned int sys_dac_osr = 0, sys_fifo_clk = 0;
0165     unsigned int sys_clk_cal = 0, sys_asrc_in = 0;
0166 
0167     rt1019->lrck = params_rate(params);
0168     pre_div = rl6231_get_clk_info(rt1019->sysclk, rt1019->lrck);
0169     if (pre_div < 0) {
0170         dev_err(component->dev, "Unsupported clock setting\n");
0171         return -EINVAL;
0172     }
0173 
0174     frame_size = snd_soc_params_to_frame_size(params);
0175     if (frame_size < 0) {
0176         dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
0177         return -EINVAL;
0178     }
0179 
0180     bclk_ms = frame_size > 32;
0181     rt1019->bclk = rt1019->lrck * (32 << bclk_ms);
0182 
0183     dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
0184         rt1019->bclk, rt1019->lrck);
0185     dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
0186                 bclk_ms, pre_div, dai->id);
0187 
0188     switch (pre_div) {
0189     case 0:
0190         sys_div_da_filter = RT1019_SYS_DIV_DA_FIL_DIV1;
0191         sys_dac_osr = RT1019_SYS_DA_OSR_DIV1;
0192         sys_asrc_in = RT1019_ASRC_256FS_DIV1;
0193         sys_fifo_clk = RT1019_SEL_FIFO_DIV1;
0194         sys_clk_cal = RT1019_SEL_CLK_CAL_DIV1;
0195         break;
0196     case 1:
0197         sys_div_da_filter = RT1019_SYS_DIV_DA_FIL_DIV2;
0198         sys_dac_osr = RT1019_SYS_DA_OSR_DIV2;
0199         sys_asrc_in = RT1019_ASRC_256FS_DIV2;
0200         sys_fifo_clk = RT1019_SEL_FIFO_DIV2;
0201         sys_clk_cal = RT1019_SEL_CLK_CAL_DIV2;
0202         break;
0203     case 3:
0204         sys_div_da_filter = RT1019_SYS_DIV_DA_FIL_DIV4;
0205         sys_dac_osr = RT1019_SYS_DA_OSR_DIV4;
0206         sys_asrc_in = RT1019_ASRC_256FS_DIV4;
0207         sys_fifo_clk = RT1019_SEL_FIFO_DIV4;
0208         sys_clk_cal = RT1019_SEL_CLK_CAL_DIV4;
0209         break;
0210     default:
0211         return -EINVAL;
0212     }
0213 
0214     switch (params_width(params)) {
0215     case 16:
0216         break;
0217     case 20:
0218         val_len = RT1019_I2S_DL_20;
0219         break;
0220     case 24:
0221         val_len = RT1019_I2S_DL_24;
0222         break;
0223     case 32:
0224         val_len = RT1019_I2S_DL_32;
0225         break;
0226     case 8:
0227         val_len = RT1019_I2S_DL_8;
0228         break;
0229     default:
0230         return -EINVAL;
0231     }
0232 
0233     snd_soc_component_update_bits(component, RT1019_TDM_2, RT1019_I2S_DL_MASK,
0234             val_len);
0235     snd_soc_component_update_bits(component, RT1019_CLK_TREE_1,
0236             RT1019_SEL_FIFO_MASK, sys_fifo_clk);
0237     snd_soc_component_update_bits(component, RT1019_CLK_TREE_2,
0238             RT1019_SYS_DIV_DA_FIL_MASK | RT1019_SYS_DA_OSR_MASK |
0239             RT1019_ASRC_256FS_MASK, sys_div_da_filter | sys_dac_osr |
0240             sys_asrc_in);
0241     snd_soc_component_update_bits(component, RT1019_CLK_TREE_3,
0242             RT1019_SEL_CLK_CAL_MASK, sys_clk_cal);
0243 
0244     return 0;
0245 }
0246 
0247 static int rt1019_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
0248 {
0249     struct snd_soc_component *component = dai->component;
0250     unsigned int reg_val = 0, reg_val2 = 0;
0251 
0252     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0253     case SND_SOC_DAIFMT_NB_NF:
0254         break;
0255     case SND_SOC_DAIFMT_IB_NF:
0256         reg_val2 |= RT1019_TDM_BCLK_INV;
0257         break;
0258     default:
0259         return -EINVAL;
0260     }
0261 
0262     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0263     case SND_SOC_DAIFMT_I2S:
0264         break;
0265 
0266     case SND_SOC_DAIFMT_LEFT_J:
0267         reg_val |= RT1019_I2S_DF_LEFT;
0268         break;
0269 
0270     case SND_SOC_DAIFMT_DSP_A:
0271         reg_val |= RT1019_I2S_DF_PCM_A_R;
0272         break;
0273 
0274     case SND_SOC_DAIFMT_DSP_B:
0275         reg_val |= RT1019_I2S_DF_PCM_B_R;
0276         break;
0277 
0278     default:
0279         return -EINVAL;
0280     }
0281 
0282     snd_soc_component_update_bits(component, RT1019_TDM_2,
0283         RT1019_I2S_DF_MASK, reg_val);
0284     snd_soc_component_update_bits(component, RT1019_TDM_1,
0285         RT1019_TDM_BCLK_MASK, reg_val2);
0286 
0287     return 0;
0288 }
0289 
0290 static int rt1019_set_dai_sysclk(struct snd_soc_dai *dai,
0291         int clk_id, unsigned int freq, int dir)
0292 {
0293     struct snd_soc_component *component = dai->component;
0294     struct rt1019_priv *rt1019 = snd_soc_component_get_drvdata(component);
0295     unsigned int reg_val = 0;
0296 
0297     if (freq == rt1019->sysclk && clk_id == rt1019->sysclk_src)
0298         return 0;
0299 
0300     switch (clk_id) {
0301     case RT1019_SCLK_S_BCLK:
0302         reg_val |= RT1019_CLK_SYS_PRE_SEL_BCLK;
0303         break;
0304 
0305     case RT1019_SCLK_S_PLL:
0306         reg_val |= RT1019_CLK_SYS_PRE_SEL_PLL;
0307         break;
0308 
0309     default:
0310         dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
0311         return -EINVAL;
0312     }
0313 
0314     rt1019->sysclk = freq;
0315     rt1019->sysclk_src = clk_id;
0316 
0317     dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
0318 
0319     snd_soc_component_update_bits(component, RT1019_CLK_TREE_1,
0320         RT1019_CLK_SYS_PRE_SEL_MASK, reg_val);
0321 
0322     return 0;
0323 }
0324 
0325 static int rt1019_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
0326             unsigned int freq_in, unsigned int freq_out)
0327 {
0328     struct snd_soc_component *component = dai->component;
0329     struct rt1019_priv *rt1019 = snd_soc_component_get_drvdata(component);
0330     struct rl6231_pll_code pll_code;
0331     int ret;
0332 
0333     if (!freq_in || !freq_out) {
0334         dev_dbg(component->dev, "PLL disabled\n");
0335         rt1019->pll_in = 0;
0336         rt1019->pll_out = 0;
0337         return 0;
0338     }
0339 
0340     if (source == rt1019->pll_src && freq_in == rt1019->pll_in &&
0341         freq_out == rt1019->pll_out)
0342         return 0;
0343 
0344     switch (source) {
0345     case RT1019_PLL_S_BCLK:
0346         snd_soc_component_update_bits(component, RT1019_CLK_TREE_1,
0347             RT1019_PLL_SRC_MASK, RT1019_PLL_SRC_SEL_BCLK);
0348         break;
0349 
0350     case RT1019_PLL_S_RC25M:
0351         snd_soc_component_update_bits(component, RT1019_CLK_TREE_1,
0352             RT1019_PLL_SRC_MASK, RT1019_PLL_SRC_SEL_RC);
0353         break;
0354 
0355     default:
0356         dev_err(component->dev, "Unknown PLL source %d\n", source);
0357         return -EINVAL;
0358     }
0359 
0360     ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
0361     if (ret < 0) {
0362         dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
0363         return ret;
0364     }
0365 
0366     dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
0367         pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
0368         pll_code.n_code, pll_code.k_code);
0369 
0370     snd_soc_component_update_bits(component, RT1019_PWR_STRP_2,
0371         RT1019_AUTO_BITS_SEL_MASK | RT1019_AUTO_CLK_SEL_MASK,
0372         RT1019_AUTO_BITS_SEL_MANU | RT1019_AUTO_CLK_SEL_MANU);
0373     snd_soc_component_update_bits(component, RT1019_PLL_1,
0374         RT1019_PLL_M_MASK | RT1019_PLL_M_BP_MASK | RT1019_PLL_Q_8_8_MASK,
0375         ((pll_code.m_bp ? 0 : pll_code.m_code) << RT1019_PLL_M_SFT) |
0376         (pll_code.m_bp << RT1019_PLL_M_BP_SFT) |
0377         ((pll_code.n_code >> 8) & RT1019_PLL_Q_8_8_MASK));
0378     snd_soc_component_update_bits(component, RT1019_PLL_2,
0379         RT1019_PLL_Q_7_0_MASK, pll_code.n_code & RT1019_PLL_Q_7_0_MASK);
0380     snd_soc_component_update_bits(component, RT1019_PLL_3,
0381         RT1019_PLL_K_MASK, pll_code.k_code);
0382 
0383     rt1019->pll_in = freq_in;
0384     rt1019->pll_out = freq_out;
0385     rt1019->pll_src = source;
0386 
0387     return 0;
0388 }
0389 
0390 static int rt1019_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
0391             unsigned int rx_mask, int slots, int slot_width)
0392 {
0393     struct snd_soc_component *component = dai->component;
0394     unsigned int val = 0, rx_slotnum;
0395     int ret = 0, first_bit;
0396 
0397     switch (slots) {
0398     case 4:
0399         val |= RT1019_I2S_TX_4CH;
0400         break;
0401     case 6:
0402         val |= RT1019_I2S_TX_6CH;
0403         break;
0404     case 8:
0405         val |= RT1019_I2S_TX_8CH;
0406         break;
0407     case 2:
0408         break;
0409     default:
0410         return -EINVAL;
0411     }
0412 
0413     switch (slot_width) {
0414     case 20:
0415         val |= RT1019_I2S_DL_20;
0416         break;
0417     case 24:
0418         val |= RT1019_I2S_DL_24;
0419         break;
0420     case 32:
0421         val |= RT1019_I2S_DL_32;
0422         break;
0423     case 8:
0424         val |= RT1019_I2S_DL_8;
0425         break;
0426     case 16:
0427         break;
0428     default:
0429         return -EINVAL;
0430     }
0431 
0432     /* Rx slot configuration */
0433     rx_slotnum = hweight_long(rx_mask);
0434     if (rx_slotnum != 1) {
0435         ret = -EINVAL;
0436         dev_err(component->dev, "too many rx slots or zero slot\n");
0437         goto _set_tdm_err_;
0438     }
0439     /* This is an assumption that the system sends stereo audio to the
0440      * amplifier typically. And the stereo audio is placed in slot 0/2/4/6
0441      * as the starting slot. The users could select the channel from
0442      * L/R/L+R by "Mono LR Select" control.
0443      */
0444     first_bit = __ffs(rx_mask);
0445     switch (first_bit) {
0446     case 0:
0447     case 2:
0448     case 4:
0449     case 6:
0450         snd_soc_component_update_bits(component,
0451             RT1019_TDM_3,
0452             RT1019_TDM_I2S_TX_L_DAC1_1_MASK |
0453             RT1019_TDM_I2S_TX_R_DAC1_1_MASK,
0454             (first_bit << RT1019_TDM_I2S_TX_L_DAC1_1_SFT) |
0455             ((first_bit + 1) << RT1019_TDM_I2S_TX_R_DAC1_1_SFT));
0456         break;
0457     case 1:
0458     case 3:
0459     case 5:
0460     case 7:
0461         snd_soc_component_update_bits(component,
0462             RT1019_TDM_3,
0463             RT1019_TDM_I2S_TX_L_DAC1_1_MASK |
0464             RT1019_TDM_I2S_TX_R_DAC1_1_MASK,
0465             ((first_bit - 1) << RT1019_TDM_I2S_TX_L_DAC1_1_SFT) |
0466             (first_bit << RT1019_TDM_I2S_TX_R_DAC1_1_SFT));
0467         break;
0468     default:
0469         ret = -EINVAL;
0470         goto _set_tdm_err_;
0471     }
0472 
0473     snd_soc_component_update_bits(component, RT1019_TDM_2,
0474         RT1019_I2S_CH_TX_MASK | RT1019_I2S_DF_MASK, val);
0475 
0476 _set_tdm_err_:
0477     return ret;
0478 }
0479 
0480 static int rt1019_probe(struct snd_soc_component *component)
0481 {
0482     struct rt1019_priv *rt1019 = snd_soc_component_get_drvdata(component);
0483 
0484     rt1019->component = component;
0485     snd_soc_component_write(component, RT1019_SDB_CTRL, 0xa);
0486 
0487     return 0;
0488 }
0489 
0490 #define RT1019_STEREO_RATES SNDRV_PCM_RATE_8000_192000
0491 #define RT1019_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
0492             SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
0493 
0494 static const struct snd_soc_dai_ops rt1019_aif_dai_ops = {
0495     .hw_params = rt1019_hw_params,
0496     .set_fmt = rt1019_set_dai_fmt,
0497     .set_sysclk = rt1019_set_dai_sysclk,
0498     .set_pll = rt1019_set_dai_pll,
0499     .set_tdm_slot = rt1019_set_tdm_slot,
0500 };
0501 
0502 static struct snd_soc_dai_driver rt1019_dai[] = {
0503     {
0504         .name = "rt1019-aif",
0505         .id = 0,
0506         .playback = {
0507             .stream_name = "AIF Playback",
0508             .channels_min = 1,
0509             .channels_max = 2,
0510             .rates = RT1019_STEREO_RATES,
0511             .formats = RT1019_FORMATS,
0512         },
0513         .ops = &rt1019_aif_dai_ops,
0514     }
0515 };
0516 
0517 static const struct snd_soc_component_driver soc_component_dev_rt1019 = {
0518     .probe          = rt1019_probe,
0519     .controls       = rt1019_snd_controls,
0520     .num_controls       = ARRAY_SIZE(rt1019_snd_controls),
0521     .dapm_widgets       = rt1019_dapm_widgets,
0522     .num_dapm_widgets   = ARRAY_SIZE(rt1019_dapm_widgets),
0523     .dapm_routes        = rt1019_dapm_routes,
0524     .num_dapm_routes    = ARRAY_SIZE(rt1019_dapm_routes),
0525     .endianness     = 1,
0526 };
0527 
0528 static const struct regmap_config rt1019_regmap = {
0529     .reg_bits = 16,
0530     .val_bits = 8,
0531     .use_single_read = true,
0532     .use_single_write = true,
0533     .max_register = RT1019_BEEP_2,
0534     .volatile_reg = rt1019_volatile_register,
0535     .readable_reg = rt1019_readable_register,
0536     .cache_type = REGCACHE_RBTREE,
0537     .reg_defaults = rt1019_reg,
0538     .num_reg_defaults = ARRAY_SIZE(rt1019_reg),
0539 };
0540 
0541 static const struct i2c_device_id rt1019_i2c_id[] = {
0542     { "rt1019", 0 },
0543     { }
0544 };
0545 MODULE_DEVICE_TABLE(i2c, rt1019_i2c_id);
0546 
0547 static const struct of_device_id rt1019_of_match[] = {
0548     { .compatible = "realtek,rt1019", },
0549     {},
0550 };
0551 MODULE_DEVICE_TABLE(of, rt1019_of_match);
0552 
0553 #ifdef CONFIG_ACPI
0554 static const struct acpi_device_id rt1019_acpi_match[] = {
0555     { "10EC1019", 0},
0556     { },
0557 };
0558 MODULE_DEVICE_TABLE(acpi, rt1019_acpi_match);
0559 #endif
0560 
0561 static int rt1019_i2c_probe(struct i2c_client *i2c)
0562 {
0563     struct rt1019_priv *rt1019;
0564     int ret;
0565     unsigned int val, val2, dev_id;
0566 
0567     rt1019 = devm_kzalloc(&i2c->dev, sizeof(struct rt1019_priv),
0568                 GFP_KERNEL);
0569     if (!rt1019)
0570         return -ENOMEM;
0571 
0572     i2c_set_clientdata(i2c, rt1019);
0573 
0574     rt1019->regmap = devm_regmap_init_i2c(i2c, &rt1019_regmap);
0575     if (IS_ERR(rt1019->regmap)) {
0576         ret = PTR_ERR(rt1019->regmap);
0577         dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
0578             ret);
0579         return ret;
0580     }
0581 
0582     regmap_read(rt1019->regmap, RT1019_DEV_ID_1, &val);
0583     regmap_read(rt1019->regmap, RT1019_DEV_ID_2, &val2);
0584     dev_id = val << 8 | val2;
0585     if (dev_id != RT1019_DEVICE_ID_VAL && dev_id != RT1019_DEVICE_ID_VAL2) {
0586         dev_err(&i2c->dev,
0587             "Device with ID register 0x%x is not rt1019\n", dev_id);
0588         return -ENODEV;
0589     }
0590 
0591     return devm_snd_soc_register_component(&i2c->dev,
0592         &soc_component_dev_rt1019, rt1019_dai, ARRAY_SIZE(rt1019_dai));
0593 }
0594 
0595 static struct i2c_driver rt1019_i2c_driver = {
0596     .driver = {
0597         .name = "rt1019",
0598         .of_match_table = of_match_ptr(rt1019_of_match),
0599         .acpi_match_table = ACPI_PTR(rt1019_acpi_match),
0600     },
0601     .probe_new = rt1019_i2c_probe,
0602     .id_table = rt1019_i2c_id,
0603 };
0604 module_i2c_driver(rt1019_i2c_driver);
0605 
0606 MODULE_DESCRIPTION("ASoC RT1019 driver");
0607 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
0608 MODULE_LICENSE("GPL v2");
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