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0009 #include <linux/fs.h>
0010 #include <linux/module.h>
0011 #include <linux/moduleparam.h>
0012 #include <linux/init.h>
0013 #include <linux/delay.h>
0014 #include <linux/pm.h>
0015 #include <linux/regmap.h>
0016 #include <linux/i2c.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/firmware.h>
0019 #include <linux/gpio.h>
0020 #include <sound/core.h>
0021 #include <sound/pcm.h>
0022 #include <sound/pcm_params.h>
0023 #include <sound/soc.h>
0024 #include <sound/soc-dapm.h>
0025 #include <sound/initval.h>
0026 #include <sound/tlv.h>
0027
0028 #include "rl6231.h"
0029 #include "rt1016.h"
0030
0031 static const struct reg_sequence rt1016_patch[] = {
0032 {RT1016_VOL_CTRL_3, 0x8900},
0033 {RT1016_ANA_CTRL_1, 0xa002},
0034 {RT1016_ANA_CTRL_2, 0x0002},
0035 {RT1016_CLOCK_4, 0x6700},
0036 {RT1016_CLASSD_3, 0xdc55},
0037 {RT1016_CLASSD_4, 0x376a},
0038 {RT1016_CLASSD_5, 0x009f},
0039 };
0040
0041 static const struct reg_default rt1016_reg[] = {
0042 {0x00, 0x0000},
0043 {0x01, 0x5400},
0044 {0x02, 0x5506},
0045 {0x03, 0xf800},
0046 {0x04, 0x0000},
0047 {0x05, 0xbfbf},
0048 {0x06, 0x8900},
0049 {0x07, 0xa002},
0050 {0x08, 0x0000},
0051 {0x09, 0x0000},
0052 {0x0a, 0x0000},
0053 {0x0c, 0x0000},
0054 {0x0d, 0x0000},
0055 {0x0e, 0x10ec},
0056 {0x0f, 0x6595},
0057 {0x11, 0x0002},
0058 {0x1c, 0x0000},
0059 {0x1d, 0x0000},
0060 {0x1e, 0x0000},
0061 {0x1f, 0xf000},
0062 {0x20, 0x0000},
0063 {0x21, 0x6000},
0064 {0x22, 0x0000},
0065 {0x23, 0x6700},
0066 {0x24, 0x0000},
0067 {0x25, 0x0000},
0068 {0x26, 0x0000},
0069 {0x40, 0x0018},
0070 {0x60, 0x00a5},
0071 {0x80, 0x0010},
0072 {0x81, 0x0009},
0073 {0x82, 0x0000},
0074 {0x83, 0x0000},
0075 {0xa0, 0x0700},
0076 {0xc0, 0x0080},
0077 {0xc1, 0x02a0},
0078 {0xc2, 0x1400},
0079 {0xc3, 0x0a4a},
0080 {0xc4, 0x552a},
0081 {0xc5, 0x087e},
0082 {0xc6, 0x0020},
0083 {0xc7, 0xa833},
0084 {0xc8, 0x0433},
0085 {0xc9, 0x8040},
0086 {0xca, 0xdc55},
0087 {0xcb, 0x376a},
0088 {0xcc, 0x009f},
0089 {0xcf, 0x0020},
0090 };
0091
0092 static bool rt1016_volatile_register(struct device *dev, unsigned int reg)
0093 {
0094 switch (reg) {
0095 case RT1016_ANA_FLAG:
0096 case RT1016_VERSION2_ID:
0097 case RT1016_VERSION1_ID:
0098 case RT1016_VENDER_ID:
0099 case RT1016_DEVICE_ID:
0100 case RT1016_TEST_SIGNAL:
0101 case RT1016_SC_CTRL_1:
0102 return true;
0103
0104 default:
0105 return false;
0106 }
0107 }
0108
0109 static bool rt1016_readable_register(struct device *dev, unsigned int reg)
0110 {
0111 switch (reg) {
0112 case RT1016_RESET:
0113 case RT1016_PADS_CTRL_1:
0114 case RT1016_PADS_CTRL_2:
0115 case RT1016_I2C_CTRL:
0116 case RT1016_VOL_CTRL_1:
0117 case RT1016_VOL_CTRL_2:
0118 case RT1016_VOL_CTRL_3:
0119 case RT1016_ANA_CTRL_1:
0120 case RT1016_MUX_SEL:
0121 case RT1016_RX_I2S_CTRL:
0122 case RT1016_ANA_FLAG:
0123 case RT1016_VERSION2_ID:
0124 case RT1016_VERSION1_ID:
0125 case RT1016_VENDER_ID:
0126 case RT1016_DEVICE_ID:
0127 case RT1016_ANA_CTRL_2:
0128 case RT1016_TEST_SIGNAL:
0129 case RT1016_TEST_CTRL_1:
0130 case RT1016_TEST_CTRL_2:
0131 case RT1016_TEST_CTRL_3:
0132 case RT1016_CLOCK_1:
0133 case RT1016_CLOCK_2:
0134 case RT1016_CLOCK_3:
0135 case RT1016_CLOCK_4:
0136 case RT1016_CLOCK_5:
0137 case RT1016_CLOCK_6:
0138 case RT1016_CLOCK_7:
0139 case RT1016_I2S_CTRL:
0140 case RT1016_DAC_CTRL_1:
0141 case RT1016_SC_CTRL_1:
0142 case RT1016_SC_CTRL_2:
0143 case RT1016_SC_CTRL_3:
0144 case RT1016_SC_CTRL_4:
0145 case RT1016_SIL_DET:
0146 case RT1016_SYS_CLK:
0147 case RT1016_BIAS_CUR:
0148 case RT1016_DAC_CTRL_2:
0149 case RT1016_LDO_CTRL:
0150 case RT1016_CLASSD_1:
0151 case RT1016_PLL1:
0152 case RT1016_PLL2:
0153 case RT1016_PLL3:
0154 case RT1016_CLASSD_2:
0155 case RT1016_CLASSD_OUT:
0156 case RT1016_CLASSD_3:
0157 case RT1016_CLASSD_4:
0158 case RT1016_CLASSD_5:
0159 case RT1016_PWR_CTRL:
0160 return true;
0161
0162 default:
0163 return false;
0164 }
0165 }
0166
0167 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9550, 50, 0);
0168
0169 static const struct snd_kcontrol_new rt1016_snd_controls[] = {
0170 SOC_DOUBLE_TLV("DAC Playback Volume", RT1016_VOL_CTRL_2,
0171 RT1016_L_VOL_SFT, RT1016_R_VOL_SFT, 191, 0, dac_vol_tlv),
0172 SOC_DOUBLE("DAC Playback Switch", RT1016_VOL_CTRL_1,
0173 RT1016_DA_MUTE_L_SFT, RT1016_DA_MUTE_R_SFT, 1, 1),
0174 };
0175
0176 static int rt1016_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
0177 struct snd_soc_dapm_widget *sink)
0178 {
0179 struct snd_soc_component *component =
0180 snd_soc_dapm_to_component(source->dapm);
0181 struct rt1016_priv *rt1016 = snd_soc_component_get_drvdata(component);
0182
0183 if (rt1016->sysclk_src == RT1016_SCLK_S_PLL)
0184 return 1;
0185 else
0186 return 0;
0187 }
0188
0189
0190 static const char * const rt1016_data_select[] = {
0191 "L/R", "R/L", "L/L", "R/R"
0192 };
0193
0194 static SOC_ENUM_SINGLE_DECL(rt1016_if_data_swap_enum,
0195 RT1016_I2S_CTRL, RT1016_I2S_DATA_SWAP_SFT, rt1016_data_select);
0196
0197 static const struct snd_kcontrol_new rt1016_if_data_swap_mux =
0198 SOC_DAPM_ENUM("Data Swap Mux", rt1016_if_data_swap_enum);
0199
0200 static const struct snd_soc_dapm_widget rt1016_dapm_widgets[] = {
0201 SND_SOC_DAPM_MUX("Data Swap Mux", SND_SOC_NOPM, 0, 0,
0202 &rt1016_if_data_swap_mux),
0203
0204 SND_SOC_DAPM_SUPPLY("DAC Filter", RT1016_CLOCK_3,
0205 RT1016_PWR_DAC_FILTER_BIT, 0, NULL, 0),
0206 SND_SOC_DAPM_SUPPLY("DAMOD", RT1016_CLOCK_3, RT1016_PWR_DACMOD_BIT, 0,
0207 NULL, 0),
0208 SND_SOC_DAPM_SUPPLY("FIFO", RT1016_CLOCK_3, RT1016_PWR_CLK_FIFO_BIT, 0,
0209 NULL, 0),
0210 SND_SOC_DAPM_SUPPLY("Pure DC", RT1016_CLOCK_3,
0211 RT1016_PWR_CLK_PUREDC_BIT, 0, NULL, 0),
0212 SND_SOC_DAPM_SUPPLY("CLK Silence Det", RT1016_CLOCK_3,
0213 RT1016_PWR_SIL_DET_BIT, 0, NULL, 0),
0214 SND_SOC_DAPM_SUPPLY("RC 25M", RT1016_CLOCK_3, RT1016_PWR_RC_25M_BIT, 0,
0215 NULL, 0),
0216 SND_SOC_DAPM_SUPPLY("PLL1", RT1016_CLOCK_3, RT1016_PWR_PLL1_BIT, 0,
0217 NULL, 0),
0218 SND_SOC_DAPM_SUPPLY("ANA CTRL", RT1016_CLOCK_3, RT1016_PWR_ANA_CTRL_BIT,
0219 0, NULL, 0),
0220 SND_SOC_DAPM_SUPPLY("CLK SYS", RT1016_CLOCK_3, RT1016_PWR_CLK_SYS_BIT,
0221 0, NULL, 0),
0222
0223 SND_SOC_DAPM_SUPPLY("LRCK Det", RT1016_CLOCK_4, RT1016_PWR_LRCK_DET_BIT,
0224 0, NULL, 0),
0225 SND_SOC_DAPM_SUPPLY("BCLK Det", RT1016_CLOCK_4, RT1016_PWR_BCLK_DET_BIT,
0226 0, NULL, 0),
0227
0228 SND_SOC_DAPM_SUPPLY("CKGEN DAC", RT1016_DAC_CTRL_2,
0229 RT1016_CKGEN_DAC_BIT, 0, NULL, 0),
0230 SND_SOC_DAPM_SUPPLY("VCM SLOW", RT1016_CLASSD_1, RT1016_VCM_SLOW_BIT, 0,
0231 NULL, 0),
0232 SND_SOC_DAPM_SUPPLY("Silence Det", RT1016_SIL_DET,
0233 RT1016_SIL_DET_EN_BIT, 0, NULL, 0),
0234 SND_SOC_DAPM_SUPPLY("PLL2", RT1016_PLL2, RT1016_PLL2_EN_BIT, 0, NULL,
0235 0),
0236
0237 SND_SOC_DAPM_SUPPLY_S("BG1 BG2", 1, RT1016_PWR_CTRL,
0238 RT1016_PWR_BG_1_2_BIT, 0, NULL, 0),
0239 SND_SOC_DAPM_SUPPLY_S("MBIAS BG", 1, RT1016_PWR_CTRL,
0240 RT1016_PWR_MBIAS_BG_BIT, 0, NULL, 0),
0241 SND_SOC_DAPM_SUPPLY_S("PLL", 1, RT1016_PWR_CTRL, RT1016_PWR_PLL_BIT, 0,
0242 NULL, 0),
0243 SND_SOC_DAPM_SUPPLY_S("BASIC", 1, RT1016_PWR_CTRL, RT1016_PWR_BASIC_BIT,
0244 0, NULL, 0),
0245 SND_SOC_DAPM_SUPPLY_S("CLASS D", 1, RT1016_PWR_CTRL,
0246 RT1016_PWR_CLSD_BIT, 0, NULL, 0),
0247 SND_SOC_DAPM_SUPPLY_S("25M", 1, RT1016_PWR_CTRL, RT1016_PWR_25M_BIT, 0,
0248 NULL, 0),
0249 SND_SOC_DAPM_SUPPLY_S("DACL", 1, RT1016_PWR_CTRL, RT1016_PWR_DACL_BIT,
0250 0, NULL, 0),
0251 SND_SOC_DAPM_SUPPLY_S("DACR", 1, RT1016_PWR_CTRL, RT1016_PWR_DACR_BIT,
0252 0, NULL, 0),
0253 SND_SOC_DAPM_SUPPLY_S("LDO2", 1, RT1016_PWR_CTRL, RT1016_PWR_LDO2_BIT,
0254 0, NULL, 0),
0255 SND_SOC_DAPM_SUPPLY_S("VREF", 1, RT1016_PWR_CTRL, RT1016_PWR_VREF_BIT,
0256 0, NULL, 0),
0257 SND_SOC_DAPM_SUPPLY_S("MBIAS", 1, RT1016_PWR_CTRL, RT1016_PWR_MBIAS_BIT,
0258 0, NULL, 0),
0259
0260 SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
0261 SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
0262
0263 SND_SOC_DAPM_OUTPUT("SPO"),
0264 };
0265
0266 static const struct snd_soc_dapm_route rt1016_dapm_routes[] = {
0267 { "Data Swap Mux", "L/R", "AIFRX" },
0268 { "Data Swap Mux", "R/L", "AIFRX" },
0269 { "Data Swap Mux", "L/L", "AIFRX" },
0270 { "Data Swap Mux", "R/R", "AIFRX" },
0271
0272 { "DAC", NULL, "DAC Filter" },
0273 { "DAC", NULL, "DAMOD" },
0274 { "DAC", NULL, "FIFO" },
0275 { "DAC", NULL, "Pure DC" },
0276 { "DAC", NULL, "Silence Det" },
0277 { "DAC", NULL, "ANA CTRL" },
0278 { "DAC", NULL, "CLK SYS" },
0279 { "DAC", NULL, "LRCK Det" },
0280 { "DAC", NULL, "BCLK Det" },
0281 { "DAC", NULL, "CKGEN DAC" },
0282 { "DAC", NULL, "VCM SLOW" },
0283
0284 { "PLL", NULL, "PLL1" },
0285 { "PLL", NULL, "PLL2" },
0286 { "25M", NULL, "RC 25M" },
0287 { "Silence Det", NULL, "CLK Silence Det" },
0288
0289 { "DAC", NULL, "Data Swap Mux" },
0290 { "DAC", NULL, "BG1 BG2" },
0291 { "DAC", NULL, "MBIAS BG" },
0292 { "DAC", NULL, "PLL", rt1016_is_sys_clk_from_pll},
0293 { "DAC", NULL, "BASIC" },
0294 { "DAC", NULL, "CLASS D" },
0295 { "DAC", NULL, "25M" },
0296 { "DAC", NULL, "DACL" },
0297 { "DAC", NULL, "DACR" },
0298 { "DAC", NULL, "LDO2" },
0299 { "DAC", NULL, "VREF" },
0300 { "DAC", NULL, "MBIAS" },
0301
0302 { "SPO", NULL, "DAC" },
0303 };
0304
0305 static int rt1016_hw_params(struct snd_pcm_substream *substream,
0306 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
0307 {
0308 struct snd_soc_component *component = dai->component;
0309 struct rt1016_priv *rt1016 = snd_soc_component_get_drvdata(component);
0310 int pre_div, bclk_ms, frame_size;
0311 unsigned int val_len = 0;
0312
0313 rt1016->lrck = params_rate(params);
0314 pre_div = rl6231_get_clk_info(rt1016->sysclk, rt1016->lrck);
0315 if (pre_div < 0) {
0316 dev_err(component->dev, "Unsupported clock rate\n");
0317 return -EINVAL;
0318 }
0319
0320 frame_size = snd_soc_params_to_frame_size(params);
0321 if (frame_size < 0) {
0322 dev_err(component->dev, "Unsupported frame size: %d\n",
0323 frame_size);
0324 return -EINVAL;
0325 }
0326
0327 bclk_ms = frame_size > 32;
0328 rt1016->bclk = rt1016->lrck * (32 << bclk_ms);
0329
0330 if (bclk_ms && rt1016->master)
0331 snd_soc_component_update_bits(component, RT1016_I2S_CTRL,
0332 RT1016_I2S_BCLK_MS_MASK, RT1016_I2S_BCLK_MS_64);
0333
0334 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
0335 rt1016->lrck, pre_div, dai->id);
0336
0337 switch (params_width(params)) {
0338 case 16:
0339 val_len = RT1016_I2S_DL_16;
0340 break;
0341 case 20:
0342 val_len = RT1016_I2S_DL_20;
0343 break;
0344 case 24:
0345 val_len = RT1016_I2S_DL_24;
0346 break;
0347 case 32:
0348 val_len = RT1016_I2S_DL_32;
0349 break;
0350 default:
0351 return -EINVAL;
0352 }
0353
0354 snd_soc_component_update_bits(component, RT1016_I2S_CTRL,
0355 RT1016_I2S_DL_MASK, val_len);
0356 snd_soc_component_update_bits(component, RT1016_CLOCK_2,
0357 RT1016_FS_PD_MASK | RT1016_OSR_PD_MASK,
0358 ((pre_div + 3) << RT1016_FS_PD_SFT) |
0359 (pre_div << RT1016_OSR_PD_SFT));
0360
0361 return 0;
0362 }
0363
0364 static int rt1016_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
0365 {
0366 struct snd_soc_component *component = dai->component;
0367 struct rt1016_priv *rt1016 = snd_soc_component_get_drvdata(component);
0368 unsigned int reg_val = 0;
0369
0370 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
0371 case SND_SOC_DAIFMT_CBM_CFM:
0372 reg_val |= RT1016_I2S_MS_M;
0373 rt1016->master = 1;
0374 break;
0375 case SND_SOC_DAIFMT_CBS_CFS:
0376 reg_val |= RT1016_I2S_MS_S;
0377 break;
0378 default:
0379 return -EINVAL;
0380 }
0381
0382 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0383 case SND_SOC_DAIFMT_NB_NF:
0384 break;
0385 case SND_SOC_DAIFMT_IB_NF:
0386 reg_val |= RT1016_I2S_BCLK_POL_INV;
0387 break;
0388 default:
0389 return -EINVAL;
0390 }
0391
0392 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0393 case SND_SOC_DAIFMT_I2S:
0394 break;
0395
0396 case SND_SOC_DAIFMT_LEFT_J:
0397 reg_val |= RT1016_I2S_DF_LEFT;
0398 break;
0399
0400 case SND_SOC_DAIFMT_DSP_A:
0401 reg_val |= RT1016_I2S_DF_PCM_A;
0402 break;
0403
0404 case SND_SOC_DAIFMT_DSP_B:
0405 reg_val |= RT1016_I2S_DF_PCM_B;
0406 break;
0407
0408 default:
0409 return -EINVAL;
0410 }
0411
0412 snd_soc_component_update_bits(component, RT1016_I2S_CTRL,
0413 RT1016_I2S_MS_MASK | RT1016_I2S_BCLK_POL_MASK |
0414 RT1016_I2S_DF_MASK, reg_val);
0415
0416 return 0;
0417 }
0418
0419 static int rt1016_set_component_sysclk(struct snd_soc_component *component,
0420 int clk_id, int source, unsigned int freq, int dir)
0421 {
0422 struct rt1016_priv *rt1016 = snd_soc_component_get_drvdata(component);
0423 unsigned int reg_val = 0;
0424
0425 if (freq == rt1016->sysclk && clk_id == rt1016->sysclk_src)
0426 return 0;
0427
0428 switch (clk_id) {
0429 case RT1016_SCLK_S_MCLK:
0430 reg_val |= RT1016_CLK_SYS_SEL_MCLK;
0431 break;
0432
0433 case RT1016_SCLK_S_PLL:
0434 reg_val |= RT1016_CLK_SYS_SEL_PLL;
0435 break;
0436
0437 default:
0438 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
0439 return -EINVAL;
0440 }
0441
0442 rt1016->sysclk = freq;
0443 rt1016->sysclk_src = clk_id;
0444
0445 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
0446 freq, clk_id);
0447
0448 snd_soc_component_update_bits(component, RT1016_CLOCK_1,
0449 RT1016_CLK_SYS_SEL_MASK, reg_val);
0450
0451 return 0;
0452 }
0453
0454 static int rt1016_set_component_pll(struct snd_soc_component *component,
0455 int pll_id, int source, unsigned int freq_in,
0456 unsigned int freq_out)
0457 {
0458 struct rt1016_priv *rt1016 = snd_soc_component_get_drvdata(component);
0459 struct rl6231_pll_code pll_code;
0460 int ret;
0461
0462 if (!freq_in || !freq_out) {
0463 dev_dbg(component->dev, "PLL disabled\n");
0464
0465 rt1016->pll_in = 0;
0466 rt1016->pll_out = 0;
0467
0468 return 0;
0469 }
0470
0471 if (source == rt1016->pll_src && freq_in == rt1016->pll_in &&
0472 freq_out == rt1016->pll_out)
0473 return 0;
0474
0475 switch (source) {
0476 case RT1016_PLL_S_MCLK:
0477 snd_soc_component_update_bits(component, RT1016_CLOCK_1,
0478 RT1016_PLL_SEL_MASK, RT1016_PLL_SEL_MCLK);
0479 break;
0480
0481 case RT1016_PLL_S_BCLK:
0482 snd_soc_component_update_bits(component, RT1016_CLOCK_1,
0483 RT1016_PLL_SEL_MASK, RT1016_PLL_SEL_BCLK);
0484 break;
0485
0486 default:
0487 dev_err(component->dev, "Unknown PLL Source %d\n", source);
0488 return -EINVAL;
0489 }
0490
0491 ret = rl6231_pll_calc(freq_in, freq_out * 4, &pll_code);
0492 if (ret < 0) {
0493 dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
0494 return ret;
0495 }
0496
0497 dev_dbg(component->dev, "mbypass=%d m=%d n=%d kbypass=%d k=%d\n",
0498 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
0499 pll_code.n_code, pll_code.k_bp,
0500 (pll_code.k_bp ? 0 : pll_code.k_code));
0501
0502 snd_soc_component_write(component, RT1016_PLL1,
0503 ((pll_code.m_bp ? 0 : pll_code.m_code) << RT1016_PLL_M_SFT) |
0504 (pll_code.m_bp << RT1016_PLL_M_BP_SFT) |
0505 pll_code.n_code);
0506 snd_soc_component_write(component, RT1016_PLL2,
0507 (pll_code.k_bp << RT1016_PLL_K_BP_SFT) |
0508 (pll_code.k_bp ? 0 : pll_code.k_code));
0509
0510 rt1016->pll_in = freq_in;
0511 rt1016->pll_out = freq_out;
0512 rt1016->pll_src = source;
0513
0514 return 0;
0515 }
0516
0517 static int rt1016_probe(struct snd_soc_component *component)
0518 {
0519 struct rt1016_priv *rt1016 =
0520 snd_soc_component_get_drvdata(component);
0521
0522 rt1016->component = component;
0523
0524 return 0;
0525 }
0526
0527 static void rt1016_remove(struct snd_soc_component *component)
0528 {
0529 struct rt1016_priv *rt1016 = snd_soc_component_get_drvdata(component);
0530
0531 regmap_write(rt1016->regmap, RT1016_RESET, 0);
0532 }
0533
0534 #define RT1016_STEREO_RATES SNDRV_PCM_RATE_8000_48000
0535 #define RT1016_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
0536 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
0537
0538 static const struct snd_soc_dai_ops rt1016_aif_dai_ops = {
0539 .hw_params = rt1016_hw_params,
0540 .set_fmt = rt1016_set_dai_fmt,
0541 };
0542
0543 static struct snd_soc_dai_driver rt1016_dai[] = {
0544 {
0545 .name = "rt1016-aif",
0546 .id = 0,
0547 .playback = {
0548 .stream_name = "AIF Playback",
0549 .channels_min = 1,
0550 .channels_max = 2,
0551 .rates = RT1016_STEREO_RATES,
0552 .formats = RT1016_FORMATS,
0553 },
0554 .ops = &rt1016_aif_dai_ops,
0555 }
0556 };
0557
0558 #ifdef CONFIG_PM
0559 static int rt1016_suspend(struct snd_soc_component *component)
0560 {
0561 struct rt1016_priv *rt1016 = snd_soc_component_get_drvdata(component);
0562
0563 regcache_cache_only(rt1016->regmap, true);
0564 regcache_mark_dirty(rt1016->regmap);
0565
0566 return 0;
0567 }
0568
0569 static int rt1016_resume(struct snd_soc_component *component)
0570 {
0571 struct rt1016_priv *rt1016 = snd_soc_component_get_drvdata(component);
0572
0573 regcache_cache_only(rt1016->regmap, false);
0574 regcache_sync(rt1016->regmap);
0575
0576 return 0;
0577 }
0578 #else
0579 #define rt1016_suspend NULL
0580 #define rt1016_resume NULL
0581 #endif
0582
0583 static const struct snd_soc_component_driver soc_component_dev_rt1016 = {
0584 .probe = rt1016_probe,
0585 .remove = rt1016_remove,
0586 .suspend = rt1016_suspend,
0587 .resume = rt1016_resume,
0588 .controls = rt1016_snd_controls,
0589 .num_controls = ARRAY_SIZE(rt1016_snd_controls),
0590 .dapm_widgets = rt1016_dapm_widgets,
0591 .num_dapm_widgets = ARRAY_SIZE(rt1016_dapm_widgets),
0592 .dapm_routes = rt1016_dapm_routes,
0593 .num_dapm_routes = ARRAY_SIZE(rt1016_dapm_routes),
0594 .set_sysclk = rt1016_set_component_sysclk,
0595 .set_pll = rt1016_set_component_pll,
0596 .use_pmdown_time = 1,
0597 .endianness = 1,
0598 };
0599
0600 static const struct regmap_config rt1016_regmap = {
0601 .reg_bits = 8,
0602 .val_bits = 16,
0603 .max_register = RT1016_PWR_CTRL,
0604 .volatile_reg = rt1016_volatile_register,
0605 .readable_reg = rt1016_readable_register,
0606 .cache_type = REGCACHE_RBTREE,
0607 .reg_defaults = rt1016_reg,
0608 .num_reg_defaults = ARRAY_SIZE(rt1016_reg),
0609 };
0610
0611 static const struct i2c_device_id rt1016_i2c_id[] = {
0612 { "rt1016", 0 },
0613 { }
0614 };
0615 MODULE_DEVICE_TABLE(i2c, rt1016_i2c_id);
0616
0617 #if defined(CONFIG_OF)
0618 static const struct of_device_id rt1016_of_match[] = {
0619 { .compatible = "realtek,rt1016", },
0620 {},
0621 };
0622 MODULE_DEVICE_TABLE(of, rt1016_of_match);
0623 #endif
0624
0625 #ifdef CONFIG_ACPI
0626 static const struct acpi_device_id rt1016_acpi_match[] = {
0627 {"10EC1016", 0,},
0628 {},
0629 };
0630 MODULE_DEVICE_TABLE(acpi, rt1016_acpi_match);
0631 #endif
0632
0633 static int rt1016_i2c_probe(struct i2c_client *i2c)
0634 {
0635 struct rt1016_priv *rt1016;
0636 int ret;
0637 unsigned int val;
0638
0639 rt1016 = devm_kzalloc(&i2c->dev, sizeof(struct rt1016_priv),
0640 GFP_KERNEL);
0641 if (rt1016 == NULL)
0642 return -ENOMEM;
0643
0644 i2c_set_clientdata(i2c, rt1016);
0645
0646 rt1016->regmap = devm_regmap_init_i2c(i2c, &rt1016_regmap);
0647 if (IS_ERR(rt1016->regmap)) {
0648 ret = PTR_ERR(rt1016->regmap);
0649 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
0650 ret);
0651 return ret;
0652 }
0653
0654 regmap_read(rt1016->regmap, RT1016_DEVICE_ID, &val);
0655 if (val != RT1016_DEVICE_ID_VAL) {
0656 dev_err(&i2c->dev,
0657 "Device with ID register %x is not rt1016\n", val);
0658 return -ENODEV;
0659 }
0660
0661 regmap_write(rt1016->regmap, RT1016_RESET, 0);
0662
0663 ret = regmap_register_patch(rt1016->regmap, rt1016_patch,
0664 ARRAY_SIZE(rt1016_patch));
0665 if (ret != 0)
0666 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
0667
0668 return devm_snd_soc_register_component(&i2c->dev,
0669 &soc_component_dev_rt1016,
0670 rt1016_dai, ARRAY_SIZE(rt1016_dai));
0671 }
0672
0673 static void rt1016_i2c_shutdown(struct i2c_client *client)
0674 {
0675 struct rt1016_priv *rt1016 = i2c_get_clientdata(client);
0676
0677 regmap_write(rt1016->regmap, RT1016_RESET, 0);
0678 }
0679
0680 static struct i2c_driver rt1016_i2c_driver = {
0681 .driver = {
0682 .name = "rt1016",
0683 .of_match_table = of_match_ptr(rt1016_of_match),
0684 .acpi_match_table = ACPI_PTR(rt1016_acpi_match),
0685 },
0686 .probe_new = rt1016_i2c_probe,
0687 .shutdown = rt1016_i2c_shutdown,
0688 .id_table = rt1016_i2c_id,
0689 };
0690 module_i2c_driver(rt1016_i2c_driver);
0691
0692 MODULE_DESCRIPTION("ASoC RT1016 driver");
0693 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
0694 MODULE_LICENSE("GPL v2");
