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0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // rt1015.c  --  RT1015 ALSA SoC audio amplifier driver
0004 //
0005 // Copyright 2019 Realtek Semiconductor Corp.
0006 //
0007 // Author: Jack Yu <jack.yu@realtek.com>
0008 //
0009 //
0010 
0011 #include <linux/acpi.h>
0012 #include <linux/delay.h>
0013 #include <linux/firmware.h>
0014 #include <linux/fs.h>
0015 #include <linux/gpio.h>
0016 #include <linux/i2c.h>
0017 #include <linux/init.h>
0018 #include <linux/module.h>
0019 #include <linux/moduleparam.h>
0020 #include <linux/platform_device.h>
0021 #include <linux/pm.h>
0022 #include <linux/regmap.h>
0023 #include <sound/core.h>
0024 #include <sound/initval.h>
0025 #include <sound/pcm.h>
0026 #include <sound/pcm_params.h>
0027 #include <sound/rt1015.h>
0028 #include <sound/soc-dapm.h>
0029 #include <sound/soc.h>
0030 #include <sound/tlv.h>
0031 
0032 #include "rl6231.h"
0033 #include "rt1015.h"
0034 
0035 static const struct rt1015_platform_data i2s_default_platform_data = {
0036     .power_up_delay_ms = 50,
0037 };
0038 
0039 static const struct reg_default rt1015_reg[] = {
0040     { 0x0000, 0x0000 },
0041     { 0x0004, 0xa000 },
0042     { 0x0006, 0x0003 },
0043     { 0x000a, 0x081e },
0044     { 0x000c, 0x0006 },
0045     { 0x000e, 0x0000 },
0046     { 0x0010, 0x0000 },
0047     { 0x0012, 0x0000 },
0048     { 0x0014, 0x0000 },
0049     { 0x0016, 0x0000 },
0050     { 0x0018, 0x0000 },
0051     { 0x0020, 0x8000 },
0052     { 0x0022, 0x8043 },
0053     { 0x0076, 0x0000 },
0054     { 0x0078, 0x0000 },
0055     { 0x007a, 0x0002 },
0056     { 0x007c, 0x10ec },
0057     { 0x007d, 0x1015 },
0058     { 0x00f0, 0x5000 },
0059     { 0x00f2, 0x004c },
0060     { 0x00f3, 0xecfe },
0061     { 0x00f4, 0x0000 },
0062     { 0x00f6, 0x0400 },
0063     { 0x0100, 0x0028 },
0064     { 0x0102, 0xff02 },
0065     { 0x0104, 0xa213 },
0066     { 0x0106, 0x200c },
0067     { 0x010c, 0x0000 },
0068     { 0x010e, 0x0058 },
0069     { 0x0111, 0x0200 },
0070     { 0x0112, 0x0400 },
0071     { 0x0114, 0x0022 },
0072     { 0x0116, 0x0000 },
0073     { 0x0118, 0x0000 },
0074     { 0x011a, 0x0123 },
0075     { 0x011c, 0x4567 },
0076     { 0x0300, 0x203d },
0077     { 0x0302, 0x001e },
0078     { 0x0311, 0x0000 },
0079     { 0x0313, 0x6014 },
0080     { 0x0314, 0x00a2 },
0081     { 0x031a, 0x00a0 },
0082     { 0x031c, 0x001f },
0083     { 0x031d, 0xffff },
0084     { 0x031e, 0x0000 },
0085     { 0x031f, 0x0000 },
0086     { 0x0320, 0x0000 },
0087     { 0x0321, 0x0000 },
0088     { 0x0322, 0xd7df },
0089     { 0x0328, 0x10b2 },
0090     { 0x0329, 0x0175 },
0091     { 0x032a, 0x36ad },
0092     { 0x032b, 0x7e55 },
0093     { 0x032c, 0x0520 },
0094     { 0x032d, 0xaa00 },
0095     { 0x032e, 0x570e },
0096     { 0x0330, 0xe180 },
0097     { 0x0332, 0x0034 },
0098     { 0x0334, 0x0001 },
0099     { 0x0336, 0x0010 },
0100     { 0x0338, 0x0000 },
0101     { 0x04fa, 0x0030 },
0102     { 0x04fc, 0x35c8 },
0103     { 0x04fe, 0x0800 },
0104     { 0x0500, 0x0400 },
0105     { 0x0502, 0x1000 },
0106     { 0x0504, 0x0000 },
0107     { 0x0506, 0x04ff },
0108     { 0x0508, 0x0010 },
0109     { 0x050a, 0x001a },
0110     { 0x0519, 0x1c68 },
0111     { 0x051a, 0x0ccc },
0112     { 0x051b, 0x0666 },
0113     { 0x051d, 0x0000 },
0114     { 0x051f, 0x0000 },
0115     { 0x0536, 0x061c },
0116     { 0x0538, 0x0000 },
0117     { 0x053a, 0x0000 },
0118     { 0x053c, 0x0000 },
0119     { 0x053d, 0x0000 },
0120     { 0x053e, 0x0000 },
0121     { 0x053f, 0x0000 },
0122     { 0x0540, 0x0000 },
0123     { 0x0541, 0x0000 },
0124     { 0x0542, 0x0000 },
0125     { 0x0543, 0x0000 },
0126     { 0x0544, 0x0000 },
0127     { 0x0568, 0x0000 },
0128     { 0x056a, 0x0000 },
0129     { 0x1000, 0x0040 },
0130     { 0x1002, 0x5405 },
0131     { 0x1006, 0x5515 },
0132     { 0x1007, 0x05f7 },
0133     { 0x1009, 0x0b0a },
0134     { 0x100a, 0x00ef },
0135     { 0x100d, 0x0003 },
0136     { 0x1010, 0xa433 },
0137     { 0x1020, 0x0000 },
0138     { 0x1200, 0x5a01 },
0139     { 0x1202, 0x6524 },
0140     { 0x1204, 0x1f00 },
0141     { 0x1206, 0x0000 },
0142     { 0x1208, 0x0000 },
0143     { 0x120a, 0x0000 },
0144     { 0x120c, 0x0000 },
0145     { 0x120e, 0x0000 },
0146     { 0x1210, 0x0000 },
0147     { 0x1212, 0x0000 },
0148     { 0x1300, 0x10a1 },
0149     { 0x1302, 0x12ff },
0150     { 0x1304, 0x0400 },
0151     { 0x1305, 0x0844 },
0152     { 0x1306, 0x4611 },
0153     { 0x1308, 0x555e },
0154     { 0x130a, 0x0000 },
0155     { 0x130c, 0x2000 },
0156     { 0x130e, 0x0100 },
0157     { 0x130f, 0x0001 },
0158     { 0x1310, 0x0000 },
0159     { 0x1312, 0x0000 },
0160     { 0x1314, 0x0000 },
0161     { 0x1316, 0x0000 },
0162     { 0x1318, 0x0000 },
0163     { 0x131a, 0x0000 },
0164     { 0x1322, 0x0029 },
0165     { 0x1323, 0x4a52 },
0166     { 0x1324, 0x002c },
0167     { 0x1325, 0x0b02 },
0168     { 0x1326, 0x002d },
0169     { 0x1327, 0x6b5a },
0170     { 0x1328, 0x002e },
0171     { 0x1329, 0xcbb2 },
0172     { 0x132a, 0x0030 },
0173     { 0x132b, 0x2c0b },
0174     { 0x1330, 0x0031 },
0175     { 0x1331, 0x8c63 },
0176     { 0x1332, 0x0032 },
0177     { 0x1333, 0xecbb },
0178     { 0x1334, 0x0034 },
0179     { 0x1335, 0x4d13 },
0180     { 0x1336, 0x0037 },
0181     { 0x1337, 0x0dc3 },
0182     { 0x1338, 0x003d },
0183     { 0x1339, 0xef7b },
0184     { 0x133a, 0x0044 },
0185     { 0x133b, 0xd134 },
0186     { 0x133c, 0x0047 },
0187     { 0x133d, 0x91e4 },
0188     { 0x133e, 0x004d },
0189     { 0x133f, 0xc370 },
0190     { 0x1340, 0x0053 },
0191     { 0x1341, 0xf4fd },
0192     { 0x1342, 0x0060 },
0193     { 0x1343, 0x5816 },
0194     { 0x1344, 0x006c },
0195     { 0x1345, 0xbb2e },
0196     { 0x1346, 0x0072 },
0197     { 0x1347, 0xecbb },
0198     { 0x1348, 0x0076 },
0199     { 0x1349, 0x5d97 },
0200 };
0201 
0202 static bool rt1015_volatile_register(struct device *dev, unsigned int reg)
0203 {
0204     switch (reg) {
0205     case RT1015_RESET:
0206     case RT1015_CLK_DET:
0207     case RT1015_SIL_DET:
0208     case RT1015_VER_ID:
0209     case RT1015_VENDOR_ID:
0210     case RT1015_DEVICE_ID:
0211     case RT1015_PRO_ALT:
0212     case RT1015_MAN_I2C:
0213     case RT1015_DAC3:
0214     case RT1015_VBAT_TEST_OUT1:
0215     case RT1015_VBAT_TEST_OUT2:
0216     case RT1015_VBAT_PROT_ATT:
0217     case RT1015_VBAT_DET_CODE:
0218     case RT1015_SMART_BST_CTRL1:
0219     case RT1015_SPK_DC_DETECT1:
0220     case RT1015_SPK_DC_DETECT4:
0221     case RT1015_SPK_DC_DETECT5:
0222     case RT1015_DC_CALIB_CLSD1:
0223     case RT1015_DC_CALIB_CLSD5:
0224     case RT1015_DC_CALIB_CLSD6:
0225     case RT1015_DC_CALIB_CLSD7:
0226     case RT1015_DC_CALIB_CLSD8:
0227     case RT1015_S_BST_TIMING_INTER1:
0228     case RT1015_OSCK_STA:
0229     case RT1015_MONO_DYNA_CTRL1:
0230     case RT1015_MONO_DYNA_CTRL5:
0231         return true;
0232 
0233     default:
0234         return false;
0235     }
0236 }
0237 
0238 static bool rt1015_readable_register(struct device *dev, unsigned int reg)
0239 {
0240     switch (reg) {
0241     case RT1015_RESET:
0242     case RT1015_CLK2:
0243     case RT1015_CLK3:
0244     case RT1015_PLL1:
0245     case RT1015_PLL2:
0246     case RT1015_DUM_RW1:
0247     case RT1015_DUM_RW2:
0248     case RT1015_DUM_RW3:
0249     case RT1015_DUM_RW4:
0250     case RT1015_DUM_RW5:
0251     case RT1015_DUM_RW6:
0252     case RT1015_CLK_DET:
0253     case RT1015_SIL_DET:
0254     case RT1015_CUSTOMER_ID:
0255     case RT1015_PCODE_FWVER:
0256     case RT1015_VER_ID:
0257     case RT1015_VENDOR_ID:
0258     case RT1015_DEVICE_ID:
0259     case RT1015_PAD_DRV1:
0260     case RT1015_PAD_DRV2:
0261     case RT1015_GAT_BOOST:
0262     case RT1015_PRO_ALT:
0263     case RT1015_OSCK_STA:
0264     case RT1015_MAN_I2C:
0265     case RT1015_DAC1:
0266     case RT1015_DAC2:
0267     case RT1015_DAC3:
0268     case RT1015_ADC1:
0269     case RT1015_ADC2:
0270     case RT1015_TDM_MASTER:
0271     case RT1015_TDM_TCON:
0272     case RT1015_TDM1_1:
0273     case RT1015_TDM1_2:
0274     case RT1015_TDM1_3:
0275     case RT1015_TDM1_4:
0276     case RT1015_TDM1_5:
0277     case RT1015_MIXER1:
0278     case RT1015_MIXER2:
0279     case RT1015_ANA_PROTECT1:
0280     case RT1015_ANA_CTRL_SEQ1:
0281     case RT1015_ANA_CTRL_SEQ2:
0282     case RT1015_VBAT_DET_DEB:
0283     case RT1015_VBAT_VOLT_DET1:
0284     case RT1015_VBAT_VOLT_DET2:
0285     case RT1015_VBAT_TEST_OUT1:
0286     case RT1015_VBAT_TEST_OUT2:
0287     case RT1015_VBAT_PROT_ATT:
0288     case RT1015_VBAT_DET_CODE:
0289     case RT1015_PWR1:
0290     case RT1015_PWR4:
0291     case RT1015_PWR5:
0292     case RT1015_PWR6:
0293     case RT1015_PWR7:
0294     case RT1015_PWR8:
0295     case RT1015_PWR9:
0296     case RT1015_CLASSD_SEQ:
0297     case RT1015_SMART_BST_CTRL1:
0298     case RT1015_SMART_BST_CTRL2:
0299     case RT1015_ANA_CTRL1:
0300     case RT1015_ANA_CTRL2:
0301     case RT1015_PWR_STATE_CTRL:
0302     case RT1015_MONO_DYNA_CTRL:
0303     case RT1015_MONO_DYNA_CTRL1:
0304     case RT1015_MONO_DYNA_CTRL2:
0305     case RT1015_MONO_DYNA_CTRL3:
0306     case RT1015_MONO_DYNA_CTRL4:
0307     case RT1015_MONO_DYNA_CTRL5:
0308     case RT1015_SPK_VOL:
0309     case RT1015_SHORT_DETTOP1:
0310     case RT1015_SHORT_DETTOP2:
0311     case RT1015_SPK_DC_DETECT1:
0312     case RT1015_SPK_DC_DETECT2:
0313     case RT1015_SPK_DC_DETECT3:
0314     case RT1015_SPK_DC_DETECT4:
0315     case RT1015_SPK_DC_DETECT5:
0316     case RT1015_BAT_RPO_STEP1:
0317     case RT1015_BAT_RPO_STEP2:
0318     case RT1015_BAT_RPO_STEP3:
0319     case RT1015_BAT_RPO_STEP4:
0320     case RT1015_BAT_RPO_STEP5:
0321     case RT1015_BAT_RPO_STEP6:
0322     case RT1015_BAT_RPO_STEP7:
0323     case RT1015_BAT_RPO_STEP8:
0324     case RT1015_BAT_RPO_STEP9:
0325     case RT1015_BAT_RPO_STEP10:
0326     case RT1015_BAT_RPO_STEP11:
0327     case RT1015_BAT_RPO_STEP12:
0328     case RT1015_SPREAD_SPEC1:
0329     case RT1015_SPREAD_SPEC2:
0330     case RT1015_PAD_STATUS:
0331     case RT1015_PADS_PULLING_CTRL1:
0332     case RT1015_PADS_DRIVING:
0333     case RT1015_SYS_RST1:
0334     case RT1015_SYS_RST2:
0335     case RT1015_SYS_GATING1:
0336     case RT1015_TEST_MODE1:
0337     case RT1015_TEST_MODE2:
0338     case RT1015_TIMING_CTRL1:
0339     case RT1015_PLL_INT:
0340     case RT1015_TEST_OUT1:
0341     case RT1015_DC_CALIB_CLSD1:
0342     case RT1015_DC_CALIB_CLSD2:
0343     case RT1015_DC_CALIB_CLSD3:
0344     case RT1015_DC_CALIB_CLSD4:
0345     case RT1015_DC_CALIB_CLSD5:
0346     case RT1015_DC_CALIB_CLSD6:
0347     case RT1015_DC_CALIB_CLSD7:
0348     case RT1015_DC_CALIB_CLSD8:
0349     case RT1015_DC_CALIB_CLSD9:
0350     case RT1015_DC_CALIB_CLSD10:
0351     case RT1015_CLSD_INTERNAL1:
0352     case RT1015_CLSD_INTERNAL2:
0353     case RT1015_CLSD_INTERNAL3:
0354     case RT1015_CLSD_INTERNAL4:
0355     case RT1015_CLSD_INTERNAL5:
0356     case RT1015_CLSD_INTERNAL6:
0357     case RT1015_CLSD_INTERNAL7:
0358     case RT1015_CLSD_INTERNAL8:
0359     case RT1015_CLSD_INTERNAL9:
0360     case RT1015_CLSD_OCP_CTRL:
0361     case RT1015_VREF_LV:
0362     case RT1015_MBIAS1:
0363     case RT1015_MBIAS2:
0364     case RT1015_MBIAS3:
0365     case RT1015_MBIAS4:
0366     case RT1015_VREF_LV1:
0367     case RT1015_S_BST_TIMING_INTER1:
0368     case RT1015_S_BST_TIMING_INTER2:
0369     case RT1015_S_BST_TIMING_INTER3:
0370     case RT1015_S_BST_TIMING_INTER4:
0371     case RT1015_S_BST_TIMING_INTER5:
0372     case RT1015_S_BST_TIMING_INTER6:
0373     case RT1015_S_BST_TIMING_INTER7:
0374     case RT1015_S_BST_TIMING_INTER8:
0375     case RT1015_S_BST_TIMING_INTER9:
0376     case RT1015_S_BST_TIMING_INTER10:
0377     case RT1015_S_BST_TIMING_INTER11:
0378     case RT1015_S_BST_TIMING_INTER12:
0379     case RT1015_S_BST_TIMING_INTER13:
0380     case RT1015_S_BST_TIMING_INTER14:
0381     case RT1015_S_BST_TIMING_INTER15:
0382     case RT1015_S_BST_TIMING_INTER16:
0383     case RT1015_S_BST_TIMING_INTER17:
0384     case RT1015_S_BST_TIMING_INTER18:
0385     case RT1015_S_BST_TIMING_INTER19:
0386     case RT1015_S_BST_TIMING_INTER20:
0387     case RT1015_S_BST_TIMING_INTER21:
0388     case RT1015_S_BST_TIMING_INTER22:
0389     case RT1015_S_BST_TIMING_INTER23:
0390     case RT1015_S_BST_TIMING_INTER24:
0391     case RT1015_S_BST_TIMING_INTER25:
0392     case RT1015_S_BST_TIMING_INTER26:
0393     case RT1015_S_BST_TIMING_INTER27:
0394     case RT1015_S_BST_TIMING_INTER28:
0395     case RT1015_S_BST_TIMING_INTER29:
0396     case RT1015_S_BST_TIMING_INTER30:
0397     case RT1015_S_BST_TIMING_INTER31:
0398     case RT1015_S_BST_TIMING_INTER32:
0399     case RT1015_S_BST_TIMING_INTER33:
0400     case RT1015_S_BST_TIMING_INTER34:
0401     case RT1015_S_BST_TIMING_INTER35:
0402     case RT1015_S_BST_TIMING_INTER36:
0403         return true;
0404 
0405     default:
0406         return false;
0407     }
0408 }
0409 
0410 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9525, 75, 0);
0411 
0412 static const char * const rt1015_din_source_select[] = {
0413     "Left",
0414     "Right",
0415     "Left + Right average",
0416 };
0417 
0418 static SOC_ENUM_SINGLE_DECL(rt1015_mono_lr_sel, RT1015_PAD_DRV2, 4,
0419     rt1015_din_source_select);
0420 
0421 static const char * const rt1015_boost_mode[] = {
0422     "Bypass", "Adaptive", "Fixed Adaptive"
0423 };
0424 
0425 static SOC_ENUM_SINGLE_DECL(rt1015_boost_mode_enum, 0, 0,
0426     rt1015_boost_mode);
0427 
0428 static int rt1015_boost_mode_get(struct snd_kcontrol *kcontrol,
0429         struct snd_ctl_elem_value *ucontrol)
0430 {
0431     struct snd_soc_component *component =
0432         snd_soc_kcontrol_component(kcontrol);
0433     struct rt1015_priv *rt1015 =
0434         snd_soc_component_get_drvdata(component);
0435 
0436     ucontrol->value.integer.value[0] = rt1015->boost_mode;
0437 
0438     return 0;
0439 }
0440 
0441 static int rt1015_boost_mode_put(struct snd_kcontrol *kcontrol,
0442         struct snd_ctl_elem_value *ucontrol)
0443 {
0444     struct snd_soc_component *component =
0445         snd_soc_kcontrol_component(kcontrol);
0446     struct rt1015_priv *rt1015 =
0447         snd_soc_component_get_drvdata(component);
0448     int boost_mode = ucontrol->value.integer.value[0];
0449 
0450     switch (boost_mode) {
0451     case BYPASS:
0452         snd_soc_component_update_bits(component,
0453             RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK |
0454             RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK,
0455             RT1015_ABST_REG_MODE | RT1015_ABST_FIX_TGT_DIS |
0456             RT1015_BYPASS_SWRREG_BYPASS);
0457         break;
0458     case ADAPTIVE:
0459         snd_soc_component_update_bits(component,
0460             RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK |
0461             RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK,
0462             RT1015_ABST_AUTO_MODE | RT1015_ABST_FIX_TGT_DIS |
0463             RT1015_BYPASS_SWRREG_PASS);
0464         break;
0465     case FIXED_ADAPTIVE:
0466         snd_soc_component_update_bits(component,
0467             RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK |
0468             RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK,
0469             RT1015_ABST_AUTO_MODE | RT1015_ABST_FIX_TGT_EN |
0470             RT1015_BYPASS_SWRREG_PASS);
0471         break;
0472     default:
0473         dev_err(component->dev, "Unknown boost control.\n");
0474         return -EINVAL;
0475     }
0476 
0477     rt1015->boost_mode = boost_mode;
0478 
0479     return 0;
0480 }
0481 
0482 static int rt1015_bypass_boost_get(struct snd_kcontrol *kcontrol,
0483         struct snd_ctl_elem_value *ucontrol)
0484 {
0485     struct snd_soc_component *component =
0486         snd_soc_kcontrol_component(kcontrol);
0487     struct rt1015_priv *rt1015 =
0488         snd_soc_component_get_drvdata(component);
0489 
0490     ucontrol->value.integer.value[0] = rt1015->bypass_boost;
0491 
0492     return 0;
0493 }
0494 
0495 static void rt1015_calibrate(struct rt1015_priv *rt1015)
0496 {
0497     struct snd_soc_component *component = rt1015->component;
0498     struct regmap *regmap = rt1015->regmap;
0499 
0500     snd_soc_dapm_mutex_lock(&component->dapm);
0501     regcache_cache_bypass(regmap, true);
0502 
0503     regmap_write(regmap, RT1015_CLK_DET, 0x0000);
0504     regmap_write(regmap, RT1015_PWR4, 0x00B2);
0505     regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x0009);
0506     msleep(100);
0507     regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x000A);
0508     msleep(100);
0509     regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x000C);
0510     msleep(100);
0511     regmap_write(regmap, RT1015_CLSD_INTERNAL8, 0x2028);
0512     regmap_write(regmap, RT1015_CLSD_INTERNAL9, 0x0140);
0513     regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x000D);
0514     msleep(300);
0515     regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x0008);
0516     regmap_write(regmap, RT1015_SYS_RST1, 0x05F5);
0517     regmap_write(regmap, RT1015_CLK_DET, 0x8000);
0518 
0519     regcache_cache_bypass(regmap, false);
0520     regcache_mark_dirty(regmap);
0521     regcache_sync(regmap);
0522     snd_soc_dapm_mutex_unlock(&component->dapm);
0523 }
0524 
0525 static int rt1015_bypass_boost_put(struct snd_kcontrol *kcontrol,
0526         struct snd_ctl_elem_value *ucontrol)
0527 {
0528     struct snd_soc_component *component =
0529         snd_soc_kcontrol_component(kcontrol);
0530     struct rt1015_priv *rt1015 =
0531         snd_soc_component_get_drvdata(component);
0532 
0533     if (rt1015->dac_is_used) {
0534         dev_err(component->dev, "DAC is being used!\n");
0535         return -EBUSY;
0536     }
0537 
0538     rt1015->bypass_boost = ucontrol->value.integer.value[0];
0539     if (rt1015->bypass_boost == RT1015_Bypass_Boost &&
0540             !rt1015->cali_done) {
0541         rt1015_calibrate(rt1015);
0542         rt1015->cali_done = 1;
0543 
0544         regmap_write(rt1015->regmap, RT1015_MONO_DYNA_CTRL, 0x0010);
0545     }
0546 
0547     return 0;
0548 }
0549 
0550 static const struct snd_kcontrol_new rt1015_snd_controls[] = {
0551     SOC_SINGLE_TLV("DAC Playback Volume", RT1015_DAC1, RT1015_DAC_VOL_SFT,
0552         127, 0, dac_vol_tlv),
0553     SOC_DOUBLE("DAC Playback Switch", RT1015_DAC3,
0554         RT1015_DA_MUTE_SFT, RT1015_DVOL_MUTE_FLAG_SFT, 1, 1),
0555     SOC_ENUM_EXT("Boost Mode", rt1015_boost_mode_enum,
0556         rt1015_boost_mode_get, rt1015_boost_mode_put),
0557     SOC_ENUM("Mono LR Select", rt1015_mono_lr_sel),
0558     SOC_SINGLE_EXT("Bypass Boost", SND_SOC_NOPM, 0, 1, 0,
0559         rt1015_bypass_boost_get, rt1015_bypass_boost_put),
0560 };
0561 
0562 static int rt1015_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
0563              struct snd_soc_dapm_widget *sink)
0564 {
0565     struct snd_soc_component *component =
0566         snd_soc_dapm_to_component(source->dapm);
0567     struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
0568 
0569     if (rt1015->sysclk_src == RT1015_SCLK_S_PLL)
0570         return 1;
0571     else
0572         return 0;
0573 }
0574 
0575 static int r1015_dac_event(struct snd_soc_dapm_widget *w,
0576     struct snd_kcontrol *kcontrol, int event)
0577 {
0578     struct snd_soc_component *component =
0579         snd_soc_dapm_to_component(w->dapm);
0580     struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
0581 
0582     switch (event) {
0583     case SND_SOC_DAPM_PRE_PMU:
0584         rt1015->dac_is_used = 1;
0585         if (rt1015->bypass_boost == RT1015_Enable_Boost) {
0586             snd_soc_component_write(component,
0587                 RT1015_SYS_RST1, 0x05f7);
0588             snd_soc_component_write(component,
0589                 RT1015_SYS_RST2, 0x0b0a);
0590             snd_soc_component_write(component,
0591                 RT1015_GAT_BOOST, 0xacfe);
0592             snd_soc_component_write(component,
0593                 RT1015_PWR9, 0xaa00);
0594             snd_soc_component_write(component,
0595                 RT1015_GAT_BOOST, 0xecfe);
0596         } else {
0597             snd_soc_component_write(component,
0598                 0x032d, 0xaa60);
0599             snd_soc_component_write(component,
0600                 RT1015_SYS_RST1, 0x05f7);
0601             snd_soc_component_write(component,
0602                 RT1015_SYS_RST2, 0x0b0a);
0603             snd_soc_component_write(component,
0604                 RT1015_PWR_STATE_CTRL, 0x008e);
0605         }
0606         break;
0607 
0608     case SND_SOC_DAPM_POST_PMD:
0609         if (rt1015->bypass_boost == RT1015_Enable_Boost) {
0610             snd_soc_component_write(component,
0611                 RT1015_PWR9, 0xa800);
0612             snd_soc_component_write(component,
0613                 RT1015_SYS_RST1, 0x05f5);
0614             snd_soc_component_write(component,
0615                 RT1015_SYS_RST2, 0x0b9a);
0616         } else {
0617             snd_soc_component_write(component,
0618                 0x032d, 0xaa60);
0619             snd_soc_component_write(component,
0620                 RT1015_PWR_STATE_CTRL, 0x0088);
0621             snd_soc_component_write(component,
0622                 RT1015_SYS_RST1, 0x05f5);
0623             snd_soc_component_write(component,
0624                 RT1015_SYS_RST2, 0x0b9a);
0625         }
0626         rt1015->dac_is_used = 0;
0627         break;
0628 
0629     default:
0630         break;
0631     }
0632     return 0;
0633 }
0634 
0635 static int rt1015_amp_drv_event(struct snd_soc_dapm_widget *w,
0636     struct snd_kcontrol *kcontrol, int event)
0637 {
0638     struct snd_soc_component *component =
0639         snd_soc_dapm_to_component(w->dapm);
0640     struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
0641     unsigned int ret, ret2;
0642 
0643     switch (event) {
0644     case SND_SOC_DAPM_PRE_PMU:
0645         ret = snd_soc_component_read(component, RT1015_CLK_DET);
0646         ret2 = snd_soc_component_read(component, RT1015_SPK_DC_DETECT1);
0647         if (!((ret >> 15) & 0x1)) {
0648             snd_soc_component_update_bits(component, RT1015_CLK_DET,
0649                 RT1015_EN_BCLK_DET_MASK, RT1015_EN_BCLK_DET);
0650             dev_dbg(component->dev, "BCLK Detection Enabled.\n");
0651         }
0652         if (!((ret2 >> 12) & 0x1)) {
0653             snd_soc_component_update_bits(component, RT1015_SPK_DC_DETECT1,
0654                 RT1015_EN_CLA_D_DC_DET_MASK, RT1015_EN_CLA_D_DC_DET);
0655             dev_dbg(component->dev, "Class-D DC Detection Enabled.\n");
0656         }
0657         break;
0658     case SND_SOC_DAPM_POST_PMU:
0659         msleep(rt1015->pdata.power_up_delay_ms);
0660         break;
0661     default:
0662         break;
0663     }
0664     return 0;
0665 }
0666 
0667 static const struct snd_soc_dapm_widget rt1015_dapm_widgets[] = {
0668     SND_SOC_DAPM_SUPPLY("PLL", RT1015_PWR1, RT1015_PWR_PLL_BIT, 0,
0669         NULL, 0),
0670     SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
0671     SND_SOC_DAPM_DAC_E("DAC", NULL, SND_SOC_NOPM, 0, 0,
0672         r1015_dac_event, SND_SOC_DAPM_PRE_PMU |
0673         SND_SOC_DAPM_POST_PMD),
0674     SND_SOC_DAPM_OUT_DRV_E("Amp Drv", SND_SOC_NOPM, 0, 0, NULL, 0,
0675             rt1015_amp_drv_event, SND_SOC_DAPM_PRE_PMU |
0676             SND_SOC_DAPM_POST_PMU),
0677     SND_SOC_DAPM_OUTPUT("SPO"),
0678 };
0679 
0680 static const struct snd_soc_dapm_route rt1015_dapm_routes[] = {
0681     { "DAC", NULL, "AIFRX" },
0682     { "DAC", NULL, "PLL", rt1015_is_sys_clk_from_pll},
0683     { "Amp Drv", NULL, "DAC" },
0684     { "SPO", NULL, "Amp Drv" },
0685 };
0686 
0687 static int rt1015_hw_params(struct snd_pcm_substream *substream,
0688     struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
0689 {
0690     struct snd_soc_component *component = dai->component;
0691     struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
0692     int pre_div, frame_size, lrck;
0693     unsigned int val_len = 0;
0694 
0695     lrck = params_rate(params);
0696     pre_div = rl6231_get_clk_info(rt1015->sysclk, lrck);
0697     if (pre_div < 0) {
0698         dev_err(component->dev, "Unsupported clock rate\n");
0699         return -EINVAL;
0700     }
0701 
0702     frame_size = snd_soc_params_to_frame_size(params);
0703     if (frame_size < 0) {
0704         dev_err(component->dev, "Unsupported frame size: %d\n",
0705             frame_size);
0706         return -EINVAL;
0707     }
0708 
0709     dev_dbg(component->dev, "pre_div is %d for iis %d\n", pre_div, dai->id);
0710 
0711     dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
0712                 lrck, pre_div, dai->id);
0713 
0714     switch (params_width(params)) {
0715     case 16:
0716         break;
0717     case 20:
0718         val_len = RT1015_I2S_DL_20;
0719         break;
0720     case 24:
0721         val_len = RT1015_I2S_DL_24;
0722         break;
0723     case 8:
0724         val_len = RT1015_I2S_DL_8;
0725         break;
0726     default:
0727         return -EINVAL;
0728     }
0729 
0730     snd_soc_component_update_bits(component, RT1015_TDM_MASTER,
0731         RT1015_I2S_DL_MASK, val_len);
0732     snd_soc_component_update_bits(component, RT1015_CLK2,
0733         RT1015_FS_PD_MASK, pre_div << RT1015_FS_PD_SFT);
0734 
0735     return 0;
0736 }
0737 
0738 static int rt1015_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
0739 {
0740     struct snd_soc_component *component = dai->component;
0741     unsigned int reg_val = 0, reg_val2 = 0;
0742 
0743     switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
0744     case SND_SOC_DAIFMT_CBM_CFM:
0745         reg_val |= RT1015_TCON_TDM_MS_M;
0746         break;
0747     case SND_SOC_DAIFMT_CBS_CFS:
0748         reg_val |= RT1015_TCON_TDM_MS_S;
0749         break;
0750     default:
0751         return -EINVAL;
0752     }
0753 
0754     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0755     case SND_SOC_DAIFMT_NB_NF:
0756         break;
0757     case SND_SOC_DAIFMT_IB_NF:
0758         reg_val2 |= RT1015_TDM_INV_BCLK;
0759         break;
0760     default:
0761         return -EINVAL;
0762     }
0763 
0764     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0765     case SND_SOC_DAIFMT_I2S:
0766         break;
0767 
0768     case SND_SOC_DAIFMT_LEFT_J:
0769         reg_val |= RT1015_I2S_M_DF_LEFT;
0770         break;
0771 
0772     case SND_SOC_DAIFMT_DSP_A:
0773         reg_val |= RT1015_I2S_M_DF_PCM_A;
0774         break;
0775 
0776     case SND_SOC_DAIFMT_DSP_B:
0777         reg_val |= RT1015_I2S_M_DF_PCM_B;
0778         break;
0779 
0780     default:
0781         return -EINVAL;
0782     }
0783 
0784     snd_soc_component_update_bits(component, RT1015_TDM_MASTER,
0785             RT1015_TCON_TDM_MS_MASK | RT1015_I2S_M_DF_MASK,
0786             reg_val);
0787     snd_soc_component_update_bits(component, RT1015_TDM1_1,
0788             RT1015_TDM_INV_BCLK_MASK, reg_val2);
0789 
0790     return 0;
0791 }
0792 
0793 static int rt1015_set_component_sysclk(struct snd_soc_component *component,
0794         int clk_id, int source, unsigned int freq, int dir)
0795 {
0796     struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
0797     unsigned int reg_val = 0;
0798 
0799     if (freq == rt1015->sysclk && clk_id == rt1015->sysclk_src)
0800         return 0;
0801 
0802     switch (clk_id) {
0803     case RT1015_SCLK_S_MCLK:
0804         reg_val |= RT1015_CLK_SYS_PRE_SEL_MCLK;
0805         break;
0806 
0807     case RT1015_SCLK_S_PLL:
0808         reg_val |= RT1015_CLK_SYS_PRE_SEL_PLL;
0809         break;
0810 
0811     default:
0812         dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
0813         return -EINVAL;
0814     }
0815 
0816     rt1015->sysclk = freq;
0817     rt1015->sysclk_src = clk_id;
0818 
0819     dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
0820         freq, clk_id);
0821 
0822     snd_soc_component_update_bits(component, RT1015_CLK2,
0823             RT1015_CLK_SYS_PRE_SEL_MASK, reg_val);
0824 
0825     return 0;
0826 }
0827 
0828 static int rt1015_set_component_pll(struct snd_soc_component *component,
0829         int pll_id, int source, unsigned int freq_in,
0830         unsigned int freq_out)
0831 {
0832     struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
0833     struct rl6231_pll_code pll_code;
0834     int ret;
0835 
0836     if (!freq_in || !freq_out) {
0837         dev_dbg(component->dev, "PLL disabled\n");
0838 
0839         rt1015->pll_in = 0;
0840         rt1015->pll_out = 0;
0841 
0842         return 0;
0843     }
0844 
0845     if (source == rt1015->pll_src && freq_in == rt1015->pll_in &&
0846         freq_out == rt1015->pll_out)
0847         return 0;
0848 
0849     switch (source) {
0850     case RT1015_PLL_S_MCLK:
0851         snd_soc_component_update_bits(component, RT1015_CLK2,
0852             RT1015_PLL_SEL_MASK, RT1015_PLL_SEL_PLL_SRC2);
0853         break;
0854 
0855     case RT1015_PLL_S_BCLK:
0856         snd_soc_component_update_bits(component, RT1015_CLK2,
0857             RT1015_PLL_SEL_MASK, RT1015_PLL_SEL_BCLK);
0858         break;
0859 
0860     default:
0861         dev_err(component->dev, "Unknown PLL Source %d\n", source);
0862         return -EINVAL;
0863     }
0864 
0865     ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
0866     if (ret < 0) {
0867         dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
0868         return ret;
0869     }
0870 
0871     dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
0872         pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
0873         pll_code.n_code, pll_code.k_code);
0874 
0875     snd_soc_component_write(component, RT1015_PLL1,
0876         ((pll_code.m_bp ? 0 : pll_code.m_code) << RT1015_PLL_M_SFT) |
0877         (pll_code.m_bp << RT1015_PLL_M_BP_SFT) |
0878         pll_code.n_code);
0879     snd_soc_component_write(component, RT1015_PLL2,
0880         pll_code.k_code);
0881 
0882     rt1015->pll_in = freq_in;
0883     rt1015->pll_out = freq_out;
0884     rt1015->pll_src = source;
0885 
0886     return 0;
0887 }
0888 
0889 static int rt1015_set_tdm_slot(struct snd_soc_dai *dai,
0890     unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
0891 {
0892     struct snd_soc_component *component = dai->component;
0893     unsigned int val = 0, rx_slotnum, tx_slotnum;
0894     int ret = 0, first_bit;
0895 
0896     switch (slots) {
0897     case 2:
0898         val |= RT1015_I2S_TX_2CH;
0899         break;
0900     case 4:
0901         val |= RT1015_I2S_TX_4CH;
0902         break;
0903     case 6:
0904         val |= RT1015_I2S_TX_6CH;
0905         break;
0906     case 8:
0907         val |= RT1015_I2S_TX_8CH;
0908         break;
0909     default:
0910         ret = -EINVAL;
0911         goto _set_tdm_err_;
0912     }
0913 
0914     switch (slot_width) {
0915     case 16:
0916         val |= RT1015_I2S_CH_TX_LEN_16B;
0917         break;
0918     case 20:
0919         val |= RT1015_I2S_CH_TX_LEN_20B;
0920         break;
0921     case 24:
0922         val |= RT1015_I2S_CH_TX_LEN_24B;
0923         break;
0924     case 32:
0925         val |= RT1015_I2S_CH_TX_LEN_32B;
0926         break;
0927     default:
0928         ret = -EINVAL;
0929         goto _set_tdm_err_;
0930     }
0931 
0932     /* Rx slot configuration */
0933     rx_slotnum = hweight_long(rx_mask);
0934     if (rx_slotnum != 1) {
0935         ret = -EINVAL;
0936         dev_err(component->dev, "too many rx slots or zero slot\n");
0937         goto _set_tdm_err_;
0938     }
0939 
0940     /* This is an assumption that the system sends stereo audio to the amplifier typically.
0941      * And the stereo audio is placed in slot 0/2/4/6 as the starting slot.
0942      * The users could select the channel from L/R/L+R by "Mono LR Select" control.
0943      */
0944     first_bit = __ffs(rx_mask);
0945     switch (first_bit) {
0946     case 0:
0947     case 2:
0948     case 4:
0949     case 6:
0950         snd_soc_component_update_bits(component,
0951             RT1015_TDM1_4,
0952             RT1015_TDM_I2S_TX_L_DAC1_1_MASK |
0953             RT1015_TDM_I2S_TX_R_DAC1_1_MASK,
0954             (first_bit << RT1015_TDM_I2S_TX_L_DAC1_1_SFT) |
0955             ((first_bit+1) << RT1015_TDM_I2S_TX_R_DAC1_1_SFT));
0956         break;
0957     case 1:
0958     case 3:
0959     case 5:
0960     case 7:
0961         snd_soc_component_update_bits(component,
0962             RT1015_TDM1_4,
0963             RT1015_TDM_I2S_TX_L_DAC1_1_MASK |
0964             RT1015_TDM_I2S_TX_R_DAC1_1_MASK,
0965             ((first_bit-1) << RT1015_TDM_I2S_TX_L_DAC1_1_SFT) |
0966             (first_bit << RT1015_TDM_I2S_TX_R_DAC1_1_SFT));
0967         break;
0968     default:
0969         ret = -EINVAL;
0970         goto _set_tdm_err_;
0971     }
0972 
0973     /* Tx slot configuration */
0974     tx_slotnum = hweight_long(tx_mask);
0975     if (tx_slotnum) {
0976         ret = -EINVAL;
0977         dev_err(component->dev, "doesn't need to support tx slots\n");
0978         goto _set_tdm_err_;
0979     }
0980 
0981     snd_soc_component_update_bits(component, RT1015_TDM1_1,
0982         RT1015_I2S_CH_TX_MASK | RT1015_I2S_CH_RX_MASK |
0983         RT1015_I2S_CH_TX_LEN_MASK | RT1015_I2S_CH_RX_LEN_MASK, val);
0984 
0985 _set_tdm_err_:
0986     return ret;
0987 }
0988 
0989 static int rt1015_probe(struct snd_soc_component *component)
0990 {
0991     struct rt1015_priv *rt1015 =
0992         snd_soc_component_get_drvdata(component);
0993 
0994     rt1015->component = component;
0995 
0996     return 0;
0997 }
0998 
0999 static void rt1015_remove(struct snd_soc_component *component)
1000 {
1001     struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
1002 
1003     regmap_write(rt1015->regmap, RT1015_RESET, 0);
1004 }
1005 
1006 #define RT1015_STEREO_RATES SNDRV_PCM_RATE_8000_192000
1007 #define RT1015_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1008             SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1009 
1010 static const struct snd_soc_dai_ops rt1015_aif_dai_ops = {
1011     .hw_params = rt1015_hw_params,
1012     .set_fmt = rt1015_set_dai_fmt,
1013     .set_tdm_slot = rt1015_set_tdm_slot,
1014 };
1015 
1016 static struct snd_soc_dai_driver rt1015_dai[] = {
1017     {
1018         .name = "rt1015-aif",
1019         .id = 0,
1020         .playback = {
1021             .stream_name = "AIF Playback",
1022             .channels_min = 1,
1023             .channels_max = 4,
1024             .rates = RT1015_STEREO_RATES,
1025             .formats = RT1015_FORMATS,
1026         },
1027         .ops = &rt1015_aif_dai_ops,
1028     }
1029 };
1030 
1031 #ifdef CONFIG_PM
1032 static int rt1015_suspend(struct snd_soc_component *component)
1033 {
1034     struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
1035 
1036     regcache_cache_only(rt1015->regmap, true);
1037     regcache_mark_dirty(rt1015->regmap);
1038 
1039     return 0;
1040 }
1041 
1042 static int rt1015_resume(struct snd_soc_component *component)
1043 {
1044     struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
1045 
1046     regcache_cache_only(rt1015->regmap, false);
1047     regcache_sync(rt1015->regmap);
1048 
1049     if (rt1015->cali_done)
1050         rt1015_calibrate(rt1015);
1051 
1052     return 0;
1053 }
1054 #else
1055 #define rt1015_suspend NULL
1056 #define rt1015_resume NULL
1057 #endif
1058 
1059 static const struct snd_soc_component_driver soc_component_dev_rt1015 = {
1060     .probe = rt1015_probe,
1061     .remove = rt1015_remove,
1062     .suspend = rt1015_suspend,
1063     .resume = rt1015_resume,
1064     .controls = rt1015_snd_controls,
1065     .num_controls = ARRAY_SIZE(rt1015_snd_controls),
1066     .dapm_widgets = rt1015_dapm_widgets,
1067     .num_dapm_widgets = ARRAY_SIZE(rt1015_dapm_widgets),
1068     .dapm_routes = rt1015_dapm_routes,
1069     .num_dapm_routes = ARRAY_SIZE(rt1015_dapm_routes),
1070     .set_sysclk = rt1015_set_component_sysclk,
1071     .set_pll = rt1015_set_component_pll,
1072     .use_pmdown_time    = 1,
1073     .endianness     = 1,
1074 };
1075 
1076 static const struct regmap_config rt1015_regmap = {
1077     .reg_bits = 16,
1078     .val_bits = 16,
1079     .max_register = RT1015_S_BST_TIMING_INTER36,
1080     .volatile_reg = rt1015_volatile_register,
1081     .readable_reg = rt1015_readable_register,
1082     .cache_type = REGCACHE_RBTREE,
1083     .reg_defaults = rt1015_reg,
1084     .num_reg_defaults = ARRAY_SIZE(rt1015_reg),
1085 };
1086 
1087 static const struct i2c_device_id rt1015_i2c_id[] = {
1088     { "rt1015", 0 },
1089     { }
1090 };
1091 MODULE_DEVICE_TABLE(i2c, rt1015_i2c_id);
1092 
1093 #if defined(CONFIG_OF)
1094 static const struct of_device_id rt1015_of_match[] = {
1095     { .compatible = "realtek,rt1015", },
1096     {},
1097 };
1098 MODULE_DEVICE_TABLE(of, rt1015_of_match);
1099 #endif
1100 
1101 #ifdef CONFIG_ACPI
1102 static const struct acpi_device_id rt1015_acpi_match[] = {
1103     {"10EC1015", 0,},
1104     {},
1105 };
1106 MODULE_DEVICE_TABLE(acpi, rt1015_acpi_match);
1107 #endif
1108 
1109 static void rt1015_parse_dt(struct rt1015_priv *rt1015, struct device *dev)
1110 {
1111     device_property_read_u32(dev, "realtek,power-up-delay-ms",
1112         &rt1015->pdata.power_up_delay_ms);
1113 }
1114 
1115 static int rt1015_i2c_probe(struct i2c_client *i2c)
1116 {
1117     struct rt1015_platform_data *pdata = dev_get_platdata(&i2c->dev);
1118     struct rt1015_priv *rt1015;
1119     int ret;
1120     unsigned int val;
1121 
1122     rt1015 = devm_kzalloc(&i2c->dev, sizeof(*rt1015), GFP_KERNEL);
1123     if (!rt1015)
1124         return -ENOMEM;
1125 
1126     i2c_set_clientdata(i2c, rt1015);
1127 
1128     rt1015->pdata = i2s_default_platform_data;
1129 
1130     if (pdata)
1131         rt1015->pdata = *pdata;
1132     else
1133         rt1015_parse_dt(rt1015, &i2c->dev);
1134 
1135     rt1015->regmap = devm_regmap_init_i2c(i2c, &rt1015_regmap);
1136     if (IS_ERR(rt1015->regmap)) {
1137         ret = PTR_ERR(rt1015->regmap);
1138         dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1139             ret);
1140         return ret;
1141     }
1142 
1143     ret = regmap_read(rt1015->regmap, RT1015_DEVICE_ID, &val);
1144     if (ret) {
1145         dev_err(&i2c->dev,
1146             "Failed to read device register: %d\n", ret);
1147         return ret;
1148     } else if ((val != RT1015_DEVICE_ID_VAL) &&
1149             (val != RT1015_DEVICE_ID_VAL2)) {
1150         dev_err(&i2c->dev,
1151             "Device with ID register %x is not rt1015\n", val);
1152         return -ENODEV;
1153     }
1154 
1155     return devm_snd_soc_register_component(&i2c->dev,
1156         &soc_component_dev_rt1015,
1157         rt1015_dai, ARRAY_SIZE(rt1015_dai));
1158 }
1159 
1160 static void rt1015_i2c_shutdown(struct i2c_client *client)
1161 {
1162     struct rt1015_priv *rt1015 = i2c_get_clientdata(client);
1163 
1164     regmap_write(rt1015->regmap, RT1015_RESET, 0);
1165 }
1166 
1167 static struct i2c_driver rt1015_i2c_driver = {
1168     .driver = {
1169         .name = "rt1015",
1170         .of_match_table = of_match_ptr(rt1015_of_match),
1171         .acpi_match_table = ACPI_PTR(rt1015_acpi_match),
1172     },
1173     .probe_new = rt1015_i2c_probe,
1174     .shutdown = rt1015_i2c_shutdown,
1175     .id_table = rt1015_i2c_id,
1176 };
1177 module_i2c_driver(rt1015_i2c_driver);
1178 
1179 MODULE_DESCRIPTION("ASoC RT1015 driver");
1180 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
1181 MODULE_LICENSE("GPL v2");
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