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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * rt1011.c -- rt1011 ALSA SoC amplifier component driver
0004  *
0005  * Copyright(c) 2019 Realtek Semiconductor Corp.
0006  *
0007  * Author: Shuming Fan <shumingf@realtek.com>
0008  *
0009  */
0010 
0011 #include <linux/module.h>
0012 #include <linux/moduleparam.h>
0013 #include <linux/init.h>
0014 #include <linux/delay.h>
0015 #include <linux/pm.h>
0016 #include <linux/gpio.h>
0017 #include <linux/i2c.h>
0018 #include <linux/acpi.h>
0019 #include <linux/regmap.h>
0020 #include <linux/of_gpio.h>
0021 #include <linux/platform_device.h>
0022 #include <linux/firmware.h>
0023 #include <sound/core.h>
0024 #include <sound/pcm.h>
0025 #include <sound/pcm_params.h>
0026 #include <sound/soc.h>
0027 #include <sound/soc-dapm.h>
0028 #include <sound/initval.h>
0029 #include <sound/tlv.h>
0030 
0031 #include "rl6231.h"
0032 #include "rt1011.h"
0033 
0034 static int rt1011_calibrate(struct rt1011_priv *rt1011,
0035     unsigned char cali_flag);
0036 
0037 static const struct reg_sequence init_list[] = {
0038 
0039     { RT1011_POWER_9, 0xa840 },
0040 
0041     { RT1011_ADC_SET_5, 0x0a20 },
0042     { RT1011_DAC_SET_2, 0xa032 },
0043 
0044     { RT1011_SPK_PRO_DC_DET_1, 0xb00c },
0045     { RT1011_SPK_PRO_DC_DET_2, 0xcccc },
0046 
0047     { RT1011_A_TIMING_1, 0x6054 },
0048 
0049     { RT1011_POWER_7, 0x3e55 },
0050     { RT1011_POWER_8, 0x0520 },
0051     { RT1011_BOOST_CON_1, 0xe188 },
0052     { RT1011_POWER_4, 0x16f2 },
0053 
0054     { RT1011_CROSS_BQ_SET_1, 0x0004 },
0055     { RT1011_SIL_DET, 0xc313 },
0056     { RT1011_SINE_GEN_REG_1, 0x0707 },
0057 
0058     { RT1011_DC_CALIB_CLASSD_3, 0xcb00 },
0059 
0060     { RT1011_DAC_SET_1, 0xe702 },
0061     { RT1011_DAC_SET_3, 0x2004 },
0062 };
0063 
0064 static const struct reg_default rt1011_reg[] = {
0065     {0x0000, 0x0000},
0066     {0x0002, 0x0000},
0067     {0x0004, 0xa000},
0068     {0x0006, 0x0000},
0069     {0x0008, 0x0003},
0070     {0x000a, 0x087e},
0071     {0x000c, 0x0020},
0072     {0x000e, 0x9002},
0073     {0x0010, 0x0000},
0074     {0x0012, 0x0000},
0075     {0x0020, 0x0c40},
0076     {0x0022, 0x4313},
0077     {0x0076, 0x0000},
0078     {0x0078, 0x0000},
0079     {0x007a, 0x0000},
0080     {0x007c, 0x10ec},
0081     {0x007d, 0x1011},
0082     {0x00f0, 0x5000},
0083     {0x00f2, 0x0374},
0084     {0x00f3, 0x0000},
0085     {0x00f4, 0x0000},
0086     {0x0100, 0x0038},
0087     {0x0102, 0xff02},
0088     {0x0104, 0x0232},
0089     {0x0106, 0x200c},
0090     {0x0107, 0x0000},
0091     {0x0108, 0x2f2f},
0092     {0x010a, 0x2f2f},
0093     {0x010c, 0x002f},
0094     {0x010e, 0xe000},
0095     {0x0110, 0x0820},
0096     {0x0111, 0x4010},
0097     {0x0112, 0x0000},
0098     {0x0114, 0x0000},
0099     {0x0116, 0x0000},
0100     {0x0118, 0x0000},
0101     {0x011a, 0x0101},
0102     {0x011c, 0x4567},
0103     {0x011e, 0x0000},
0104     {0x0120, 0x0000},
0105     {0x0122, 0x0000},
0106     {0x0124, 0x0123},
0107     {0x0126, 0x4567},
0108     {0x0200, 0x0000},
0109     {0x0300, 0xffdd},
0110     {0x0302, 0x001e},
0111     {0x0311, 0x0000},
0112     {0x0313, 0x5254},
0113     {0x0314, 0x0062},
0114     {0x0316, 0x7f40},
0115     {0x0319, 0x000f},
0116     {0x031a, 0xffff},
0117     {0x031b, 0x0000},
0118     {0x031c, 0x009f},
0119     {0x031d, 0xffff},
0120     {0x031e, 0x0000},
0121     {0x031f, 0x0000},
0122     {0x0320, 0xe31c},
0123     {0x0321, 0x0000},
0124     {0x0322, 0x0000},
0125     {0x0324, 0x0000},
0126     {0x0326, 0x0002},
0127     {0x0328, 0x20b2},
0128     {0x0329, 0x0175},
0129     {0x032a, 0x32ad},
0130     {0x032b, 0x3455},
0131     {0x032c, 0x0528},
0132     {0x032d, 0xa800},
0133     {0x032e, 0x030e},
0134     {0x0330, 0x2080},
0135     {0x0332, 0x0034},
0136     {0x0334, 0x0000},
0137     {0x0508, 0x0010},
0138     {0x050a, 0x0018},
0139     {0x050c, 0x0000},
0140     {0x050d, 0xffff},
0141     {0x050e, 0x1f1f},
0142     {0x050f, 0x04ff},
0143     {0x0510, 0x4020},
0144     {0x0511, 0x01f0},
0145     {0x0512, 0x0702},
0146     {0x0516, 0xbb80},
0147     {0x0517, 0xffff},
0148     {0x0518, 0xffff},
0149     {0x0519, 0x307f},
0150     {0x051a, 0xffff},
0151     {0x051b, 0x0000},
0152     {0x051c, 0x0000},
0153     {0x051d, 0x2000},
0154     {0x051e, 0x0000},
0155     {0x051f, 0x0000},
0156     {0x0520, 0x0000},
0157     {0x0521, 0x1001},
0158     {0x0522, 0x7fff},
0159     {0x0524, 0x7fff},
0160     {0x0526, 0x0000},
0161     {0x0528, 0x0000},
0162     {0x052a, 0x0000},
0163     {0x0530, 0x0401},
0164     {0x0532, 0x3000},
0165     {0x0534, 0x0000},
0166     {0x0535, 0xffff},
0167     {0x0536, 0x101c},
0168     {0x0538, 0x1814},
0169     {0x053a, 0x100c},
0170     {0x053c, 0x0804},
0171     {0x053d, 0x0000},
0172     {0x053e, 0x0000},
0173     {0x053f, 0x0000},
0174     {0x0540, 0x0000},
0175     {0x0541, 0x0000},
0176     {0x0542, 0x0000},
0177     {0x0543, 0x0000},
0178     {0x0544, 0x001c},
0179     {0x0545, 0x1814},
0180     {0x0546, 0x100c},
0181     {0x0547, 0x0804},
0182     {0x0548, 0x0000},
0183     {0x0549, 0x0000},
0184     {0x054a, 0x0000},
0185     {0x054b, 0x0000},
0186     {0x054c, 0x0000},
0187     {0x054d, 0x0000},
0188     {0x054e, 0x0000},
0189     {0x054f, 0x0000},
0190     {0x0566, 0x0000},
0191     {0x0568, 0x20f1},
0192     {0x056a, 0x0007},
0193     {0x0600, 0x9d00},
0194     {0x0611, 0x2000},
0195     {0x0612, 0x505f},
0196     {0x0613, 0x0444},
0197     {0x0614, 0x4000},
0198     {0x0615, 0x4004},
0199     {0x0616, 0x0606},
0200     {0x0617, 0x8904},
0201     {0x0618, 0xe021},
0202     {0x0621, 0x2000},
0203     {0x0622, 0x505f},
0204     {0x0623, 0x0444},
0205     {0x0624, 0x4000},
0206     {0x0625, 0x4004},
0207     {0x0626, 0x0606},
0208     {0x0627, 0x8704},
0209     {0x0628, 0xe021},
0210     {0x0631, 0x2000},
0211     {0x0632, 0x517f},
0212     {0x0633, 0x0440},
0213     {0x0634, 0x4000},
0214     {0x0635, 0x4104},
0215     {0x0636, 0x0306},
0216     {0x0637, 0x8904},
0217     {0x0638, 0xe021},
0218     {0x0702, 0x0014},
0219     {0x0704, 0x0000},
0220     {0x0706, 0x0014},
0221     {0x0708, 0x0000},
0222     {0x070a, 0x0000},
0223     {0x0710, 0x0200},
0224     {0x0711, 0x0000},
0225     {0x0712, 0x0200},
0226     {0x0713, 0x0000},
0227     {0x0720, 0x0200},
0228     {0x0721, 0x0000},
0229     {0x0722, 0x0000},
0230     {0x0723, 0x0000},
0231     {0x0724, 0x0000},
0232     {0x0725, 0x0000},
0233     {0x0726, 0x0000},
0234     {0x0727, 0x0000},
0235     {0x0728, 0x0000},
0236     {0x0729, 0x0000},
0237     {0x0730, 0x0200},
0238     {0x0731, 0x0000},
0239     {0x0732, 0x0000},
0240     {0x0733, 0x0000},
0241     {0x0734, 0x0000},
0242     {0x0735, 0x0000},
0243     {0x0736, 0x0000},
0244     {0x0737, 0x0000},
0245     {0x0738, 0x0000},
0246     {0x0739, 0x0000},
0247     {0x0740, 0x0200},
0248     {0x0741, 0x0000},
0249     {0x0742, 0x0000},
0250     {0x0743, 0x0000},
0251     {0x0744, 0x0000},
0252     {0x0745, 0x0000},
0253     {0x0746, 0x0000},
0254     {0x0747, 0x0000},
0255     {0x0748, 0x0000},
0256     {0x0749, 0x0000},
0257     {0x0750, 0x0200},
0258     {0x0751, 0x0000},
0259     {0x0752, 0x0000},
0260     {0x0753, 0x0000},
0261     {0x0754, 0x0000},
0262     {0x0755, 0x0000},
0263     {0x0756, 0x0000},
0264     {0x0757, 0x0000},
0265     {0x0758, 0x0000},
0266     {0x0759, 0x0000},
0267     {0x0760, 0x0200},
0268     {0x0761, 0x0000},
0269     {0x0762, 0x0000},
0270     {0x0763, 0x0000},
0271     {0x0764, 0x0000},
0272     {0x0765, 0x0000},
0273     {0x0766, 0x0000},
0274     {0x0767, 0x0000},
0275     {0x0768, 0x0000},
0276     {0x0769, 0x0000},
0277     {0x0770, 0x0200},
0278     {0x0771, 0x0000},
0279     {0x0772, 0x0000},
0280     {0x0773, 0x0000},
0281     {0x0774, 0x0000},
0282     {0x0775, 0x0000},
0283     {0x0776, 0x0000},
0284     {0x0777, 0x0000},
0285     {0x0778, 0x0000},
0286     {0x0779, 0x0000},
0287     {0x0780, 0x0200},
0288     {0x0781, 0x0000},
0289     {0x0782, 0x0000},
0290     {0x0783, 0x0000},
0291     {0x0784, 0x0000},
0292     {0x0785, 0x0000},
0293     {0x0786, 0x0000},
0294     {0x0787, 0x0000},
0295     {0x0788, 0x0000},
0296     {0x0789, 0x0000},
0297     {0x0790, 0x0200},
0298     {0x0791, 0x0000},
0299     {0x0792, 0x0000},
0300     {0x0793, 0x0000},
0301     {0x0794, 0x0000},
0302     {0x0795, 0x0000},
0303     {0x0796, 0x0000},
0304     {0x0797, 0x0000},
0305     {0x0798, 0x0000},
0306     {0x0799, 0x0000},
0307     {0x07a0, 0x0200},
0308     {0x07a1, 0x0000},
0309     {0x07a2, 0x0000},
0310     {0x07a3, 0x0000},
0311     {0x07a4, 0x0000},
0312     {0x07a5, 0x0000},
0313     {0x07a6, 0x0000},
0314     {0x07a7, 0x0000},
0315     {0x07a8, 0x0000},
0316     {0x07a9, 0x0000},
0317     {0x07b0, 0x0200},
0318     {0x07b1, 0x0000},
0319     {0x07b2, 0x0000},
0320     {0x07b3, 0x0000},
0321     {0x07b4, 0x0000},
0322     {0x07b5, 0x0000},
0323     {0x07b6, 0x0000},
0324     {0x07b7, 0x0000},
0325     {0x07b8, 0x0000},
0326     {0x07b9, 0x0000},
0327     {0x07c0, 0x0200},
0328     {0x07c1, 0x0000},
0329     {0x07c2, 0x0000},
0330     {0x07c3, 0x0000},
0331     {0x07c4, 0x0000},
0332     {0x07c5, 0x0000},
0333     {0x07c6, 0x0000},
0334     {0x07c7, 0x0000},
0335     {0x07c8, 0x0000},
0336     {0x07c9, 0x0000},
0337     {0x1000, 0x4040},
0338     {0x1002, 0x6505},
0339     {0x1004, 0x5405},
0340     {0x1006, 0x5555},
0341     {0x1007, 0x003f},
0342     {0x1008, 0x7fd7},
0343     {0x1009, 0x770f},
0344     {0x100a, 0xfffe},
0345     {0x100b, 0xe000},
0346     {0x100c, 0x0000},
0347     {0x100d, 0x0007},
0348     {0x1010, 0xa433},
0349     {0x1020, 0x0000},
0350     {0x1022, 0x0000},
0351     {0x1024, 0x0000},
0352     {0x1200, 0x5a01},
0353     {0x1202, 0x6324},
0354     {0x1204, 0x0b00},
0355     {0x1206, 0x0000},
0356     {0x1208, 0x0000},
0357     {0x120a, 0x0024},
0358     {0x120c, 0x0000},
0359     {0x120e, 0x000e},
0360     {0x1210, 0x0000},
0361     {0x1212, 0x0000},
0362     {0x1300, 0x0701},
0363     {0x1302, 0x12f9},
0364     {0x1304, 0x3405},
0365     {0x1305, 0x0844},
0366     {0x1306, 0x5611},
0367     {0x1308, 0x555e},
0368     {0x130a, 0xa605},
0369     {0x130c, 0x2000},
0370     {0x130e, 0x0000},
0371     {0x130f, 0x0001},
0372     {0x1310, 0xaa48},
0373     {0x1312, 0x0285},
0374     {0x1314, 0xaaaa},
0375     {0x1316, 0xaaa0},
0376     {0x1318, 0x2aaa},
0377     {0x131a, 0xaa07},
0378     {0x1322, 0x0029},
0379     {0x1323, 0x4a52},
0380     {0x1324, 0x002c},
0381     {0x1325, 0x0b02},
0382     {0x1326, 0x002d},
0383     {0x1327, 0x6b5a},
0384     {0x1328, 0x002e},
0385     {0x1329, 0xcbb2},
0386     {0x132a, 0x0030},
0387     {0x132b, 0x2c0b},
0388     {0x1330, 0x0031},
0389     {0x1331, 0x8c63},
0390     {0x1332, 0x0032},
0391     {0x1333, 0xecbb},
0392     {0x1334, 0x0034},
0393     {0x1335, 0x4d13},
0394     {0x1336, 0x0037},
0395     {0x1337, 0x0dc3},
0396     {0x1338, 0x003d},
0397     {0x1339, 0xef7b},
0398     {0x133a, 0x0044},
0399     {0x133b, 0xd134},
0400     {0x133c, 0x0047},
0401     {0x133d, 0x91e4},
0402     {0x133e, 0x004d},
0403     {0x133f, 0xc370},
0404     {0x1340, 0x0053},
0405     {0x1341, 0xf4fd},
0406     {0x1342, 0x0060},
0407     {0x1343, 0x5816},
0408     {0x1344, 0x006c},
0409     {0x1345, 0xbb2e},
0410     {0x1346, 0x0072},
0411     {0x1347, 0xecbb},
0412     {0x1348, 0x0076},
0413     {0x1349, 0x5d97},
0414     {0x1500, 0x0702},
0415     {0x1502, 0x002f},
0416     {0x1504, 0x0000},
0417     {0x1510, 0x0064},
0418     {0x1512, 0x0000},
0419     {0x1514, 0xdf47},
0420     {0x1516, 0x079c},
0421     {0x1518, 0xfbf5},
0422     {0x151a, 0x00bc},
0423     {0x151c, 0x3b85},
0424     {0x151e, 0x02b3},
0425     {0x1520, 0x3333},
0426     {0x1522, 0x0000},
0427     {0x1524, 0x4000},
0428     {0x1528, 0x0064},
0429     {0x152a, 0x0000},
0430     {0x152c, 0x0000},
0431     {0x152e, 0x0000},
0432     {0x1530, 0x0000},
0433     {0x1532, 0x0000},
0434     {0x1534, 0x0000},
0435     {0x1536, 0x0000},
0436     {0x1538, 0x0040},
0437     {0x1539, 0x0000},
0438     {0x153a, 0x0040},
0439     {0x153b, 0x0000},
0440     {0x153c, 0x0064},
0441     {0x153e, 0x0bf9},
0442     {0x1540, 0xb2a9},
0443     {0x1544, 0x0200},
0444     {0x1546, 0x0000},
0445     {0x1548, 0x00ca},
0446     {0x1552, 0x03ff},
0447     {0x1554, 0x017f},
0448     {0x1556, 0x017f},
0449     {0x155a, 0x0000},
0450     {0x155c, 0x0000},
0451     {0x1560, 0x0040},
0452     {0x1562, 0x0000},
0453     {0x1570, 0x03ff},
0454     {0x1571, 0xdcff},
0455     {0x1572, 0x1e00},
0456     {0x1573, 0x224f},
0457     {0x1574, 0x0000},
0458     {0x1575, 0x0000},
0459     {0x1576, 0x1e00},
0460     {0x1577, 0x0000},
0461     {0x1578, 0x0000},
0462     {0x1579, 0x1128},
0463     {0x157a, 0x03ff},
0464     {0x157b, 0xdcff},
0465     {0x157c, 0x1e00},
0466     {0x157d, 0x224f},
0467     {0x157e, 0x0000},
0468     {0x157f, 0x0000},
0469     {0x1580, 0x1e00},
0470     {0x1581, 0x0000},
0471     {0x1582, 0x0000},
0472     {0x1583, 0x1128},
0473     {0x1590, 0x03ff},
0474     {0x1591, 0xdcff},
0475     {0x1592, 0x1e00},
0476     {0x1593, 0x224f},
0477     {0x1594, 0x0000},
0478     {0x1595, 0x0000},
0479     {0x1596, 0x1e00},
0480     {0x1597, 0x0000},
0481     {0x1598, 0x0000},
0482     {0x1599, 0x1128},
0483     {0x159a, 0x03ff},
0484     {0x159b, 0xdcff},
0485     {0x159c, 0x1e00},
0486     {0x159d, 0x224f},
0487     {0x159e, 0x0000},
0488     {0x159f, 0x0000},
0489     {0x15a0, 0x1e00},
0490     {0x15a1, 0x0000},
0491     {0x15a2, 0x0000},
0492     {0x15a3, 0x1128},
0493     {0x15b0, 0x007f},
0494     {0x15b1, 0xffff},
0495     {0x15b2, 0x007f},
0496     {0x15b3, 0xffff},
0497     {0x15b4, 0x007f},
0498     {0x15b5, 0xffff},
0499     {0x15b8, 0x007f},
0500     {0x15b9, 0xffff},
0501     {0x15bc, 0x0000},
0502     {0x15bd, 0x0000},
0503     {0x15be, 0xff00},
0504     {0x15bf, 0x0000},
0505     {0x15c0, 0xff00},
0506     {0x15c1, 0x0000},
0507     {0x15c3, 0xfc00},
0508     {0x15c4, 0xbb80},
0509     {0x15d0, 0x0000},
0510     {0x15d1, 0x0000},
0511     {0x15d2, 0x0000},
0512     {0x15d3, 0x0000},
0513     {0x15d4, 0x0000},
0514     {0x15d5, 0x0000},
0515     {0x15d6, 0x0000},
0516     {0x15d7, 0x0000},
0517     {0x15d8, 0x0200},
0518     {0x15d9, 0x0000},
0519     {0x15da, 0x0000},
0520     {0x15db, 0x0000},
0521     {0x15dc, 0x0000},
0522     {0x15dd, 0x0000},
0523     {0x15de, 0x0000},
0524     {0x15df, 0x0000},
0525     {0x15e0, 0x0000},
0526     {0x15e1, 0x0000},
0527     {0x15e2, 0x0200},
0528     {0x15e3, 0x0000},
0529     {0x15e4, 0x0000},
0530     {0x15e5, 0x0000},
0531     {0x15e6, 0x0000},
0532     {0x15e7, 0x0000},
0533     {0x15e8, 0x0000},
0534     {0x15e9, 0x0000},
0535     {0x15ea, 0x0000},
0536     {0x15eb, 0x0000},
0537     {0x15ec, 0x0200},
0538     {0x15ed, 0x0000},
0539     {0x15ee, 0x0000},
0540     {0x15ef, 0x0000},
0541     {0x15f0, 0x0000},
0542     {0x15f1, 0x0000},
0543     {0x15f2, 0x0000},
0544     {0x15f3, 0x0000},
0545     {0x15f4, 0x0000},
0546     {0x15f5, 0x0000},
0547     {0x15f6, 0x0200},
0548     {0x15f7, 0x0200},
0549     {0x15f8, 0x8200},
0550     {0x15f9, 0x0000},
0551     {0x1600, 0x007d},
0552     {0x1601, 0xa178},
0553     {0x1602, 0x00c2},
0554     {0x1603, 0x5383},
0555     {0x1604, 0x0000},
0556     {0x1605, 0x02c1},
0557     {0x1606, 0x007d},
0558     {0x1607, 0xa178},
0559     {0x1608, 0x00c2},
0560     {0x1609, 0x5383},
0561     {0x160a, 0x003e},
0562     {0x160b, 0xd37d},
0563     {0x1611, 0x3210},
0564     {0x1612, 0x7418},
0565     {0x1613, 0xc0ff},
0566     {0x1614, 0x0000},
0567     {0x1615, 0x00ff},
0568     {0x1616, 0x0000},
0569     {0x1617, 0x0000},
0570     {0x1621, 0x6210},
0571     {0x1622, 0x7418},
0572     {0x1623, 0xc0ff},
0573     {0x1624, 0x0000},
0574     {0x1625, 0x00ff},
0575     {0x1626, 0x0000},
0576     {0x1627, 0x0000},
0577     {0x1631, 0x3a14},
0578     {0x1632, 0x7418},
0579     {0x1633, 0xc3ff},
0580     {0x1634, 0x0000},
0581     {0x1635, 0x00ff},
0582     {0x1636, 0x0000},
0583     {0x1637, 0x0000},
0584     {0x1638, 0x0000},
0585     {0x163a, 0x0000},
0586     {0x163c, 0x0000},
0587     {0x163e, 0x0000},
0588     {0x1640, 0x0000},
0589     {0x1642, 0x0000},
0590     {0x1644, 0x0000},
0591     {0x1646, 0x0000},
0592     {0x1648, 0x0000},
0593     {0x1650, 0x0000},
0594     {0x1652, 0x0000},
0595     {0x1654, 0x0000},
0596     {0x1656, 0x0000},
0597     {0x1658, 0x0000},
0598     {0x1660, 0x0000},
0599     {0x1662, 0x0000},
0600     {0x1664, 0x0000},
0601     {0x1666, 0x0000},
0602     {0x1668, 0x0000},
0603     {0x1670, 0x0000},
0604     {0x1672, 0x0000},
0605     {0x1674, 0x0000},
0606     {0x1676, 0x0000},
0607     {0x1678, 0x0000},
0608     {0x1680, 0x0000},
0609     {0x1682, 0x0000},
0610     {0x1684, 0x0000},
0611     {0x1686, 0x0000},
0612     {0x1688, 0x0000},
0613     {0x1690, 0x0000},
0614     {0x1692, 0x0000},
0615     {0x1694, 0x0000},
0616     {0x1696, 0x0000},
0617     {0x1698, 0x0000},
0618     {0x1700, 0x0000},
0619     {0x1702, 0x0000},
0620     {0x1704, 0x0000},
0621     {0x1706, 0x0000},
0622     {0x1708, 0x0000},
0623     {0x1710, 0x0000},
0624     {0x1712, 0x0000},
0625     {0x1714, 0x0000},
0626     {0x1716, 0x0000},
0627     {0x1718, 0x0000},
0628     {0x1720, 0x0000},
0629     {0x1722, 0x0000},
0630     {0x1724, 0x0000},
0631     {0x1726, 0x0000},
0632     {0x1728, 0x0000},
0633     {0x1730, 0x0000},
0634     {0x1732, 0x0000},
0635     {0x1734, 0x0000},
0636     {0x1736, 0x0000},
0637     {0x1738, 0x0000},
0638     {0x173a, 0x0000},
0639     {0x173c, 0x0000},
0640     {0x173e, 0x0000},
0641     {0x17bb, 0x0500},
0642     {0x17bd, 0x0004},
0643     {0x17bf, 0x0004},
0644     {0x17c1, 0x0004},
0645     {0x17c2, 0x7fff},
0646     {0x17c3, 0x0000},
0647     {0x17c5, 0x0000},
0648     {0x17c7, 0x0000},
0649     {0x17c9, 0x0000},
0650     {0x17cb, 0x2010},
0651     {0x17cd, 0x0000},
0652     {0x17cf, 0x0000},
0653     {0x17d1, 0x0000},
0654     {0x17d3, 0x0000},
0655     {0x17d5, 0x0000},
0656     {0x17d7, 0x0000},
0657     {0x17d9, 0x0000},
0658     {0x17db, 0x0000},
0659     {0x17dd, 0x0000},
0660     {0x17df, 0x0000},
0661     {0x17e1, 0x0000},
0662     {0x17e3, 0x0000},
0663     {0x17e5, 0x0000},
0664     {0x17e7, 0x0000},
0665     {0x17e9, 0x0000},
0666     {0x17eb, 0x0000},
0667     {0x17ed, 0x0000},
0668     {0x17ef, 0x0000},
0669     {0x17f1, 0x0000},
0670     {0x17f3, 0x0000},
0671     {0x17f5, 0x0000},
0672     {0x17f7, 0x0000},
0673     {0x17f9, 0x0000},
0674     {0x17fb, 0x0000},
0675     {0x17fd, 0x0000},
0676     {0x17ff, 0x0000},
0677     {0x1801, 0x0000},
0678     {0x1803, 0x0000},
0679 };
0680 
0681 static int rt1011_reg_init(struct snd_soc_component *component)
0682 {
0683     struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
0684 
0685     regmap_multi_reg_write(rt1011->regmap,
0686         init_list, ARRAY_SIZE(init_list));
0687     return 0;
0688 }
0689 
0690 static bool rt1011_volatile_register(struct device *dev, unsigned int reg)
0691 {
0692     switch (reg) {
0693     case RT1011_RESET:
0694     case RT1011_SRC_2:
0695     case RT1011_CLK_DET:
0696     case RT1011_SIL_DET:
0697     case RT1011_VERSION_ID:
0698     case RT1011_VENDOR_ID:
0699     case RT1011_DEVICE_ID:
0700     case RT1011_DUM_RO:
0701     case RT1011_DAC_SET_3:
0702     case RT1011_PWM_CAL:
0703     case RT1011_SPK_VOL_TEST_OUT:
0704     case RT1011_VBAT_VOL_DET_1:
0705     case RT1011_VBAT_TEST_OUT_1:
0706     case RT1011_VBAT_TEST_OUT_2:
0707     case RT1011_VBAT_PROTECTION:
0708     case RT1011_VBAT_DET:
0709     case RT1011_BOOST_CON_1:
0710     case RT1011_SHORT_CIRCUIT_DET_1:
0711     case RT1011_SPK_TEMP_PROTECT_3:
0712     case RT1011_SPK_TEMP_PROTECT_6:
0713     case RT1011_SPK_PRO_DC_DET_3:
0714     case RT1011_SPK_PRO_DC_DET_7:
0715     case RT1011_SPK_PRO_DC_DET_8:
0716     case RT1011_SPL_1:
0717     case RT1011_SPL_4:
0718     case RT1011_EXCUR_PROTECT_1:
0719     case RT1011_CROSS_BQ_SET_1:
0720     case RT1011_CROSS_BQ_SET_2:
0721     case RT1011_BQ_SET_0:
0722     case RT1011_BQ_SET_1:
0723     case RT1011_BQ_SET_2:
0724     case RT1011_TEST_PAD_STATUS:
0725     case RT1011_DC_CALIB_CLASSD_1:
0726     case RT1011_DC_CALIB_CLASSD_5:
0727     case RT1011_DC_CALIB_CLASSD_6:
0728     case RT1011_DC_CALIB_CLASSD_7:
0729     case RT1011_DC_CALIB_CLASSD_8:
0730     case RT1011_SINE_GEN_REG_2:
0731     case RT1011_STP_CALIB_RS_TEMP:
0732     case RT1011_SPK_RESISTANCE_1:
0733     case RT1011_SPK_RESISTANCE_2:
0734     case RT1011_SPK_THERMAL:
0735     case RT1011_ALC_BK_GAIN_O:
0736     case RT1011_ALC_BK_GAIN_O_PRE:
0737     case RT1011_SPK_DC_O_23_16:
0738     case RT1011_SPK_DC_O_15_0:
0739     case RT1011_INIT_RECIPROCAL_SYN_24_16:
0740     case RT1011_INIT_RECIPROCAL_SYN_15_0:
0741     case RT1011_SPK_EXCURSION_23_16:
0742     case RT1011_SPK_EXCURSION_15_0:
0743     case RT1011_SEP_MAIN_OUT_23_16:
0744     case RT1011_SEP_MAIN_OUT_15_0:
0745     case RT1011_ALC_DRC_HB_INTERNAL_5:
0746     case RT1011_ALC_DRC_HB_INTERNAL_6:
0747     case RT1011_ALC_DRC_HB_INTERNAL_7:
0748     case RT1011_ALC_DRC_BB_INTERNAL_5:
0749     case RT1011_ALC_DRC_BB_INTERNAL_6:
0750     case RT1011_ALC_DRC_BB_INTERNAL_7:
0751     case RT1011_ALC_DRC_POS_INTERNAL_5:
0752     case RT1011_ALC_DRC_POS_INTERNAL_6:
0753     case RT1011_ALC_DRC_POS_INTERNAL_7:
0754     case RT1011_ALC_DRC_POS_INTERNAL_8:
0755     case RT1011_ALC_DRC_POS_INTERNAL_9:
0756     case RT1011_ALC_DRC_POS_INTERNAL_10:
0757     case RT1011_ALC_DRC_POS_INTERNAL_11:
0758     case RT1011_IRQ_1:
0759     case RT1011_EFUSE_CONTROL_1:
0760     case RT1011_EFUSE_CONTROL_2:
0761     case RT1011_EFUSE_MATCH_DONE ... RT1011_EFUSE_READ_R0_3_15_0:
0762         return true;
0763 
0764     default:
0765         return false;
0766     }
0767 }
0768 
0769 static bool rt1011_readable_register(struct device *dev, unsigned int reg)
0770 {
0771     switch (reg) {
0772     case RT1011_RESET:
0773     case RT1011_CLK_1:
0774     case RT1011_CLK_2:
0775     case RT1011_CLK_3:
0776     case RT1011_CLK_4:
0777     case RT1011_PLL_1:
0778     case RT1011_PLL_2:
0779     case RT1011_SRC_1:
0780     case RT1011_SRC_2:
0781     case RT1011_SRC_3:
0782     case RT1011_CLK_DET:
0783     case RT1011_SIL_DET:
0784     case RT1011_PRIV_INDEX:
0785     case RT1011_PRIV_DATA:
0786     case RT1011_CUSTOMER_ID:
0787     case RT1011_FM_VER:
0788     case RT1011_VERSION_ID:
0789     case RT1011_VENDOR_ID:
0790     case RT1011_DEVICE_ID:
0791     case RT1011_DUM_RW_0:
0792     case RT1011_DUM_YUN:
0793     case RT1011_DUM_RW_1:
0794     case RT1011_DUM_RO:
0795     case RT1011_MAN_I2C_DEV:
0796     case RT1011_DAC_SET_1:
0797     case RT1011_DAC_SET_2:
0798     case RT1011_DAC_SET_3:
0799     case RT1011_ADC_SET:
0800     case RT1011_ADC_SET_1:
0801     case RT1011_ADC_SET_2:
0802     case RT1011_ADC_SET_3:
0803     case RT1011_ADC_SET_4:
0804     case RT1011_ADC_SET_5:
0805     case RT1011_TDM_TOTAL_SET:
0806     case RT1011_TDM1_SET_TCON:
0807     case RT1011_TDM1_SET_1:
0808     case RT1011_TDM1_SET_2:
0809     case RT1011_TDM1_SET_3:
0810     case RT1011_TDM1_SET_4:
0811     case RT1011_TDM1_SET_5:
0812     case RT1011_TDM2_SET_1:
0813     case RT1011_TDM2_SET_2:
0814     case RT1011_TDM2_SET_3:
0815     case RT1011_TDM2_SET_4:
0816     case RT1011_TDM2_SET_5:
0817     case RT1011_PWM_CAL:
0818     case RT1011_MIXER_1:
0819     case RT1011_MIXER_2:
0820     case RT1011_ADRC_LIMIT:
0821     case RT1011_A_PRO:
0822     case RT1011_A_TIMING_1:
0823     case RT1011_A_TIMING_2:
0824     case RT1011_A_TEMP_SEN:
0825     case RT1011_SPK_VOL_DET_1:
0826     case RT1011_SPK_VOL_DET_2:
0827     case RT1011_SPK_VOL_TEST_OUT:
0828     case RT1011_VBAT_VOL_DET_1:
0829     case RT1011_VBAT_VOL_DET_2:
0830     case RT1011_VBAT_TEST_OUT_1:
0831     case RT1011_VBAT_TEST_OUT_2:
0832     case RT1011_VBAT_PROTECTION:
0833     case RT1011_VBAT_DET:
0834     case RT1011_POWER_1:
0835     case RT1011_POWER_2:
0836     case RT1011_POWER_3:
0837     case RT1011_POWER_4:
0838     case RT1011_POWER_5:
0839     case RT1011_POWER_6:
0840     case RT1011_POWER_7:
0841     case RT1011_POWER_8:
0842     case RT1011_POWER_9:
0843     case RT1011_CLASS_D_POS:
0844     case RT1011_BOOST_CON_1:
0845     case RT1011_BOOST_CON_2:
0846     case RT1011_ANALOG_CTRL:
0847     case RT1011_POWER_SEQ:
0848     case RT1011_SHORT_CIRCUIT_DET_1:
0849     case RT1011_SHORT_CIRCUIT_DET_2:
0850     case RT1011_SPK_TEMP_PROTECT_0:
0851     case RT1011_SPK_TEMP_PROTECT_1:
0852     case RT1011_SPK_TEMP_PROTECT_2:
0853     case RT1011_SPK_TEMP_PROTECT_3:
0854     case RT1011_SPK_TEMP_PROTECT_4:
0855     case RT1011_SPK_TEMP_PROTECT_5:
0856     case RT1011_SPK_TEMP_PROTECT_6:
0857     case RT1011_SPK_TEMP_PROTECT_7:
0858     case RT1011_SPK_TEMP_PROTECT_8:
0859     case RT1011_SPK_TEMP_PROTECT_9:
0860     case RT1011_SPK_PRO_DC_DET_1:
0861     case RT1011_SPK_PRO_DC_DET_2:
0862     case RT1011_SPK_PRO_DC_DET_3:
0863     case RT1011_SPK_PRO_DC_DET_4:
0864     case RT1011_SPK_PRO_DC_DET_5:
0865     case RT1011_SPK_PRO_DC_DET_6:
0866     case RT1011_SPK_PRO_DC_DET_7:
0867     case RT1011_SPK_PRO_DC_DET_8:
0868     case RT1011_SPL_1:
0869     case RT1011_SPL_2:
0870     case RT1011_SPL_3:
0871     case RT1011_SPL_4:
0872     case RT1011_THER_FOLD_BACK_1:
0873     case RT1011_THER_FOLD_BACK_2:
0874     case RT1011_EXCUR_PROTECT_1:
0875     case RT1011_EXCUR_PROTECT_2:
0876     case RT1011_EXCUR_PROTECT_3:
0877     case RT1011_EXCUR_PROTECT_4:
0878     case RT1011_BAT_GAIN_1:
0879     case RT1011_BAT_GAIN_2:
0880     case RT1011_BAT_GAIN_3:
0881     case RT1011_BAT_GAIN_4:
0882     case RT1011_BAT_GAIN_5:
0883     case RT1011_BAT_GAIN_6:
0884     case RT1011_BAT_GAIN_7:
0885     case RT1011_BAT_GAIN_8:
0886     case RT1011_BAT_GAIN_9:
0887     case RT1011_BAT_GAIN_10:
0888     case RT1011_BAT_GAIN_11:
0889     case RT1011_BAT_RT_THMAX_1:
0890     case RT1011_BAT_RT_THMAX_2:
0891     case RT1011_BAT_RT_THMAX_3:
0892     case RT1011_BAT_RT_THMAX_4:
0893     case RT1011_BAT_RT_THMAX_5:
0894     case RT1011_BAT_RT_THMAX_6:
0895     case RT1011_BAT_RT_THMAX_7:
0896     case RT1011_BAT_RT_THMAX_8:
0897     case RT1011_BAT_RT_THMAX_9:
0898     case RT1011_BAT_RT_THMAX_10:
0899     case RT1011_BAT_RT_THMAX_11:
0900     case RT1011_BAT_RT_THMAX_12:
0901     case RT1011_SPREAD_SPECTURM:
0902     case RT1011_PRO_GAIN_MODE:
0903     case RT1011_RT_DRC_CROSS:
0904     case RT1011_RT_DRC_HB_1:
0905     case RT1011_RT_DRC_HB_2:
0906     case RT1011_RT_DRC_HB_3:
0907     case RT1011_RT_DRC_HB_4:
0908     case RT1011_RT_DRC_HB_5:
0909     case RT1011_RT_DRC_HB_6:
0910     case RT1011_RT_DRC_HB_7:
0911     case RT1011_RT_DRC_HB_8:
0912     case RT1011_RT_DRC_BB_1:
0913     case RT1011_RT_DRC_BB_2:
0914     case RT1011_RT_DRC_BB_3:
0915     case RT1011_RT_DRC_BB_4:
0916     case RT1011_RT_DRC_BB_5:
0917     case RT1011_RT_DRC_BB_6:
0918     case RT1011_RT_DRC_BB_7:
0919     case RT1011_RT_DRC_BB_8:
0920     case RT1011_RT_DRC_POS_1:
0921     case RT1011_RT_DRC_POS_2:
0922     case RT1011_RT_DRC_POS_3:
0923     case RT1011_RT_DRC_POS_4:
0924     case RT1011_RT_DRC_POS_5:
0925     case RT1011_RT_DRC_POS_6:
0926     case RT1011_RT_DRC_POS_7:
0927     case RT1011_RT_DRC_POS_8:
0928     case RT1011_CROSS_BQ_SET_1:
0929     case RT1011_CROSS_BQ_SET_2:
0930     case RT1011_BQ_SET_0:
0931     case RT1011_BQ_SET_1:
0932     case RT1011_BQ_SET_2:
0933     case RT1011_BQ_PRE_GAIN_28_16:
0934     case RT1011_BQ_PRE_GAIN_15_0:
0935     case RT1011_BQ_POST_GAIN_28_16:
0936     case RT1011_BQ_POST_GAIN_15_0:
0937     case RT1011_BQ_H0_28_16 ... RT1011_BQ_A2_15_0:
0938     case RT1011_BQ_1_H0_28_16 ... RT1011_BQ_1_A2_15_0:
0939     case RT1011_BQ_2_H0_28_16 ... RT1011_BQ_2_A2_15_0:
0940     case RT1011_BQ_3_H0_28_16 ... RT1011_BQ_3_A2_15_0:
0941     case RT1011_BQ_4_H0_28_16 ... RT1011_BQ_4_A2_15_0:
0942     case RT1011_BQ_5_H0_28_16 ... RT1011_BQ_5_A2_15_0:
0943     case RT1011_BQ_6_H0_28_16 ... RT1011_BQ_6_A2_15_0:
0944     case RT1011_BQ_7_H0_28_16 ... RT1011_BQ_7_A2_15_0:
0945     case RT1011_BQ_8_H0_28_16 ... RT1011_BQ_8_A2_15_0:
0946     case RT1011_BQ_9_H0_28_16 ... RT1011_BQ_9_A2_15_0:
0947     case RT1011_BQ_10_H0_28_16 ... RT1011_BQ_10_A2_15_0:
0948     case RT1011_TEST_PAD_STATUS ... RT1011_PLL_INTERNAL_SET:
0949     case RT1011_TEST_OUT_1 ... RT1011_TEST_OUT_3:
0950     case RT1011_DC_CALIB_CLASSD_1 ... RT1011_DC_CALIB_CLASSD_10:
0951     case RT1011_CLASSD_INTERNAL_SET_1 ... RT1011_VREF_LV_1:
0952     case RT1011_SMART_BOOST_TIMING_1 ... RT1011_SMART_BOOST_TIMING_36:
0953     case RT1011_SINE_GEN_REG_1 ... RT1011_SINE_GEN_REG_3:
0954     case RT1011_STP_INITIAL_RS_TEMP ... RT1011_SPK_THERMAL:
0955     case RT1011_STP_OTP_TH ... RT1011_INIT_RECIPROCAL_SYN_15_0:
0956     case RT1011_STP_BQ_1_A1_L_28_16 ... RT1011_STP_BQ_1_H0_R_15_0:
0957     case RT1011_STP_BQ_2_A1_L_28_16 ... RT1011_SEP_RE_REG_15_0:
0958     case RT1011_DRC_CF_PARAMS_1 ... RT1011_DRC_CF_PARAMS_12:
0959     case RT1011_ALC_DRC_HB_INTERNAL_1 ... RT1011_ALC_DRC_HB_INTERNAL_7:
0960     case RT1011_ALC_DRC_BB_INTERNAL_1 ... RT1011_ALC_DRC_BB_INTERNAL_7:
0961     case RT1011_ALC_DRC_POS_INTERNAL_1 ... RT1011_ALC_DRC_POS_INTERNAL_8:
0962     case RT1011_ALC_DRC_POS_INTERNAL_9 ... RT1011_BQ_1_PARAMS_CHECK_5:
0963     case RT1011_BQ_2_PARAMS_CHECK_1 ... RT1011_BQ_2_PARAMS_CHECK_5:
0964     case RT1011_BQ_3_PARAMS_CHECK_1 ... RT1011_BQ_3_PARAMS_CHECK_5:
0965     case RT1011_BQ_4_PARAMS_CHECK_1 ... RT1011_BQ_4_PARAMS_CHECK_5:
0966     case RT1011_BQ_5_PARAMS_CHECK_1 ... RT1011_BQ_5_PARAMS_CHECK_5:
0967     case RT1011_BQ_6_PARAMS_CHECK_1 ... RT1011_BQ_6_PARAMS_CHECK_5:
0968     case RT1011_BQ_7_PARAMS_CHECK_1 ... RT1011_BQ_7_PARAMS_CHECK_5:
0969     case RT1011_BQ_8_PARAMS_CHECK_1 ... RT1011_BQ_8_PARAMS_CHECK_5:
0970     case RT1011_BQ_9_PARAMS_CHECK_1 ... RT1011_BQ_9_PARAMS_CHECK_5:
0971     case RT1011_BQ_10_PARAMS_CHECK_1 ... RT1011_BQ_10_PARAMS_CHECK_5:
0972     case RT1011_IRQ_1 ... RT1011_PART_NUMBER_EFUSE:
0973     case RT1011_EFUSE_CONTROL_1 ... RT1011_EFUSE_READ_R0_3_15_0:
0974         return true;
0975     default:
0976         return false;
0977     }
0978 }
0979 
0980 static const char * const rt1011_din_source_select[] = {
0981     "Left",
0982     "Right",
0983     "Left + Right average",
0984 };
0985 
0986 static SOC_ENUM_SINGLE_DECL(rt1011_din_source_enum, RT1011_CROSS_BQ_SET_1, 5,
0987     rt1011_din_source_select);
0988 
0989 static const char * const rt1011_tdm_data_out_select[] = {
0990     "TDM_O_LR", "BQ1", "DVOL", "BQ10", "ALC", "DMIX", "ADC_SRC_LR",
0991     "ADC_O_LR", "ADC_MONO", "RSPK_BPF_LR", "DMIX_ADD", "ENVELOPE_FS",
0992     "SEP_O_GAIN", "ALC_BK_GAIN", "STP_V_C", "DMIX_ABST"
0993 };
0994 
0995 static const char * const rt1011_tdm_l_ch_data_select[] = {
0996     "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7"
0997 };
0998 static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_l_dac1_enum, RT1011_TDM1_SET_4, 12,
0999     rt1011_tdm_l_ch_data_select);
1000 static SOC_ENUM_SINGLE_DECL(rt1011_tdm2_l_dac1_enum, RT1011_TDM2_SET_4, 12,
1001     rt1011_tdm_l_ch_data_select);
1002 
1003 static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_adc1_dat_enum,
1004     RT1011_ADCDAT_OUT_SOURCE, 0, rt1011_tdm_data_out_select);
1005 static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_adc1_loc_enum, RT1011_TDM1_SET_2, 0,
1006     rt1011_tdm_l_ch_data_select);
1007 
1008 static const char * const rt1011_adc_data_mode_select[] = {
1009     "Stereo", "Mono"
1010 };
1011 static SOC_ENUM_SINGLE_DECL(rt1011_adc_dout_mode_enum, RT1011_TDM1_SET_1, 12,
1012     rt1011_adc_data_mode_select);
1013 
1014 static const char * const rt1011_tdm_adc_data_len_control[] = {
1015     "1CH", "2CH", "3CH", "4CH", "5CH", "6CH", "7CH", "8CH"
1016 };
1017 static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_dout_len_enum, RT1011_TDM1_SET_2, 13,
1018     rt1011_tdm_adc_data_len_control);
1019 static SOC_ENUM_SINGLE_DECL(rt1011_tdm2_dout_len_enum, RT1011_TDM2_SET_2, 13,
1020     rt1011_tdm_adc_data_len_control);
1021 
1022 static const char * const rt1011_tdm_adc_swap_select[] = {
1023     "L/R", "R/L", "L/L", "R/R"
1024 };
1025 
1026 static SOC_ENUM_SINGLE_DECL(rt1011_tdm_adc1_1_enum, RT1011_TDM1_SET_3, 6,
1027     rt1011_tdm_adc_swap_select);
1028 static SOC_ENUM_SINGLE_DECL(rt1011_tdm_adc2_1_enum, RT1011_TDM1_SET_3, 4,
1029     rt1011_tdm_adc_swap_select);
1030 
1031 static void rt1011_reset(struct regmap *regmap)
1032 {
1033     regmap_write(regmap, RT1011_RESET, 0);
1034 }
1035 
1036 static int rt1011_recv_spk_mode_get(struct snd_kcontrol *kcontrol,
1037         struct snd_ctl_elem_value *ucontrol)
1038 {
1039     struct snd_soc_component *component =
1040         snd_soc_kcontrol_component(kcontrol);
1041     struct rt1011_priv *rt1011 =
1042         snd_soc_component_get_drvdata(component);
1043 
1044     ucontrol->value.integer.value[0] = rt1011->recv_spk_mode;
1045 
1046     return 0;
1047 }
1048 
1049 static int rt1011_recv_spk_mode_put(struct snd_kcontrol *kcontrol,
1050         struct snd_ctl_elem_value *ucontrol)
1051 {
1052     struct snd_soc_component *component =
1053         snd_soc_kcontrol_component(kcontrol);
1054     struct rt1011_priv *rt1011 =
1055         snd_soc_component_get_drvdata(component);
1056 
1057     if (ucontrol->value.integer.value[0] == rt1011->recv_spk_mode)
1058         return 0;
1059 
1060     if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1061         rt1011->recv_spk_mode = ucontrol->value.integer.value[0];
1062 
1063         if (rt1011->recv_spk_mode) {
1064 
1065             /* 1: recevier mode on */
1066             snd_soc_component_update_bits(component,
1067                 RT1011_CLASSD_INTERNAL_SET_3,
1068                 RT1011_REG_GAIN_CLASSD_RI_SPK_MASK,
1069                 RT1011_REG_GAIN_CLASSD_RI_410K);
1070             snd_soc_component_update_bits(component,
1071                 RT1011_CLASSD_INTERNAL_SET_1,
1072                 RT1011_RECV_MODE_SPK_MASK,
1073                 RT1011_RECV_MODE);
1074         } else {
1075             /* 0: speaker mode on */
1076             snd_soc_component_update_bits(component,
1077                 RT1011_CLASSD_INTERNAL_SET_3,
1078                 RT1011_REG_GAIN_CLASSD_RI_SPK_MASK,
1079                 RT1011_REG_GAIN_CLASSD_RI_72P5K);
1080             snd_soc_component_update_bits(component,
1081                 RT1011_CLASSD_INTERNAL_SET_1,
1082                 RT1011_RECV_MODE_SPK_MASK,
1083                 RT1011_SPK_MODE);
1084         }
1085     }
1086 
1087     return 0;
1088 }
1089 
1090 static bool rt1011_validate_bq_drc_coeff(unsigned short reg)
1091 {
1092     if ((reg == RT1011_DAC_SET_1) ||
1093         (reg >= RT1011_ADC_SET && reg <= RT1011_ADC_SET_1) ||
1094         (reg == RT1011_ADC_SET_4) || (reg == RT1011_ADC_SET_5) ||
1095         (reg == RT1011_MIXER_1) ||
1096         (reg == RT1011_A_TIMING_1) ||
1097         (reg >= RT1011_POWER_7 && reg <= RT1011_POWER_8) ||
1098         (reg == RT1011_CLASS_D_POS) || (reg == RT1011_ANALOG_CTRL) ||
1099         (reg >= RT1011_SPK_TEMP_PROTECT_0 && reg <= RT1011_SPK_TEMP_PROTECT_6) ||
1100         (reg >= RT1011_SPK_PRO_DC_DET_5 && reg <= RT1011_BAT_GAIN_1) ||
1101         (reg >= RT1011_RT_DRC_CROSS && reg <= RT1011_RT_DRC_POS_8) ||
1102         (reg >= RT1011_CROSS_BQ_SET_1 && reg <= RT1011_BQ_10_A2_15_0) ||
1103         (reg >= RT1011_SMART_BOOST_TIMING_1 && reg <= RT1011_SMART_BOOST_TIMING_36) ||
1104         (reg == RT1011_SINE_GEN_REG_1) ||
1105         (reg >= RT1011_STP_ALPHA_RECIPROCAL_MSB && reg <= RT1011_BQ_6_PARAMS_CHECK_5) ||
1106         (reg >= RT1011_BQ_7_PARAMS_CHECK_1 && reg <= RT1011_BQ_10_PARAMS_CHECK_5))
1107         return true;
1108 
1109     return false;
1110 }
1111 
1112 static int rt1011_bq_drc_coeff_get(struct snd_kcontrol *kcontrol,
1113                     struct snd_ctl_elem_value *ucontrol)
1114 {
1115     struct snd_soc_component *component =
1116         snd_soc_kcontrol_component(kcontrol);
1117     struct rt1011_priv *rt1011 =
1118         snd_soc_component_get_drvdata(component);
1119     struct rt1011_bq_drc_params *bq_drc_info;
1120     struct rt1011_bq_drc_params *params =
1121         (struct rt1011_bq_drc_params *)ucontrol->value.integer.value;
1122     unsigned int i, mode_idx = 0;
1123 
1124     if (strstr(ucontrol->id.name, "AdvanceMode Initial Set"))
1125         mode_idx = RT1011_ADVMODE_INITIAL_SET;
1126     else if (strstr(ucontrol->id.name, "AdvanceMode SEP BQ Coeff"))
1127         mode_idx = RT1011_ADVMODE_SEP_BQ_COEFF;
1128     else if (strstr(ucontrol->id.name, "AdvanceMode EQ BQ Coeff"))
1129         mode_idx = RT1011_ADVMODE_EQ_BQ_COEFF;
1130     else if (strstr(ucontrol->id.name, "AdvanceMode BQ UI Coeff"))
1131         mode_idx = RT1011_ADVMODE_BQ_UI_COEFF;
1132     else if (strstr(ucontrol->id.name, "AdvanceMode SmartBoost Coeff"))
1133         mode_idx = RT1011_ADVMODE_SMARTBOOST_COEFF;
1134     else
1135         return -EINVAL;
1136 
1137     pr_info("%s, id.name=%s, mode_idx=%d\n", __func__,
1138         ucontrol->id.name, mode_idx);
1139     bq_drc_info = rt1011->bq_drc_params[mode_idx];
1140 
1141     for (i = 0; i < RT1011_BQ_DRC_NUM; i++) {
1142         params[i].reg = bq_drc_info[i].reg;
1143         params[i].val = bq_drc_info[i].val;
1144     }
1145 
1146     return 0;
1147 }
1148 
1149 static int rt1011_bq_drc_coeff_put(struct snd_kcontrol *kcontrol,
1150                     struct snd_ctl_elem_value *ucontrol)
1151 {
1152     struct snd_soc_component *component =
1153         snd_soc_kcontrol_component(kcontrol);
1154     struct rt1011_priv *rt1011 =
1155         snd_soc_component_get_drvdata(component);
1156     struct rt1011_bq_drc_params *bq_drc_info;
1157     struct rt1011_bq_drc_params *params =
1158         (struct rt1011_bq_drc_params *)ucontrol->value.integer.value;
1159     unsigned int i, mode_idx = 0;
1160 
1161     if (strstr(ucontrol->id.name, "AdvanceMode Initial Set"))
1162         mode_idx = RT1011_ADVMODE_INITIAL_SET;
1163     else if (strstr(ucontrol->id.name, "AdvanceMode SEP BQ Coeff"))
1164         mode_idx = RT1011_ADVMODE_SEP_BQ_COEFF;
1165     else if (strstr(ucontrol->id.name, "AdvanceMode EQ BQ Coeff"))
1166         mode_idx = RT1011_ADVMODE_EQ_BQ_COEFF;
1167     else if (strstr(ucontrol->id.name, "AdvanceMode BQ UI Coeff"))
1168         mode_idx = RT1011_ADVMODE_BQ_UI_COEFF;
1169     else if (strstr(ucontrol->id.name, "AdvanceMode SmartBoost Coeff"))
1170         mode_idx = RT1011_ADVMODE_SMARTBOOST_COEFF;
1171     else
1172         return -EINVAL;
1173 
1174     bq_drc_info = rt1011->bq_drc_params[mode_idx];
1175     memset(bq_drc_info, 0,
1176         sizeof(struct rt1011_bq_drc_params) * RT1011_BQ_DRC_NUM);
1177 
1178     pr_info("%s, id.name=%s, mode_idx=%d\n", __func__,
1179         ucontrol->id.name, mode_idx);
1180     for (i = 0; i < RT1011_BQ_DRC_NUM; i++) {
1181         bq_drc_info[i].reg = params[i].reg;
1182         bq_drc_info[i].val = params[i].val;
1183     }
1184 
1185     for (i = 0; i < RT1011_BQ_DRC_NUM; i++) {
1186         if (bq_drc_info[i].reg == 0)
1187             break;
1188         else if (rt1011_validate_bq_drc_coeff(bq_drc_info[i].reg)) {
1189             snd_soc_component_write(component, bq_drc_info[i].reg,
1190                     bq_drc_info[i].val);
1191         }
1192     }
1193 
1194     return 0;
1195 }
1196 
1197 static int rt1011_bq_drc_info(struct snd_kcontrol *kcontrol,
1198              struct snd_ctl_elem_info *uinfo)
1199 {
1200     uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1201     uinfo->count = 128;
1202     uinfo->value.integer.max = 0x17ffffff;
1203 
1204     return 0;
1205 }
1206 
1207 #define RT1011_BQ_DRC(xname) \
1208 {   .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1209     .info = rt1011_bq_drc_info, \
1210     .get = rt1011_bq_drc_coeff_get, \
1211     .put = rt1011_bq_drc_coeff_put \
1212 }
1213 
1214 static int rt1011_r0_cali_get(struct snd_kcontrol *kcontrol,
1215         struct snd_ctl_elem_value *ucontrol)
1216 {
1217     struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1218     struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1219 
1220     ucontrol->value.integer.value[0] = rt1011->cali_done;
1221 
1222     return 0;
1223 }
1224 
1225 static int rt1011_r0_cali_put(struct snd_kcontrol *kcontrol,
1226         struct snd_ctl_elem_value *ucontrol)
1227 {
1228     struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1229     struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1230 
1231     rt1011->cali_done = 0;
1232     if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF &&
1233         ucontrol->value.integer.value[0])
1234         rt1011_calibrate(rt1011, 1);
1235 
1236     return 0;
1237 }
1238 
1239 static int rt1011_r0_load(struct rt1011_priv *rt1011)
1240 {
1241     if (!rt1011->r0_reg)
1242         return -EINVAL;
1243 
1244     /* write R0 to register */
1245     regmap_write(rt1011->regmap, RT1011_INIT_RECIPROCAL_REG_24_16,
1246         ((rt1011->r0_reg>>16) & 0x1ff));
1247     regmap_write(rt1011->regmap, RT1011_INIT_RECIPROCAL_REG_15_0,
1248         (rt1011->r0_reg & 0xffff));
1249     regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_4, 0x4080);
1250 
1251     return 0;
1252 }
1253 
1254 static int rt1011_r0_load_mode_get(struct snd_kcontrol *kcontrol,
1255         struct snd_ctl_elem_value *ucontrol)
1256 {
1257     struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1258     struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1259 
1260     ucontrol->value.integer.value[0] = rt1011->r0_reg;
1261 
1262     return 0;
1263 }
1264 
1265 static int rt1011_r0_load_mode_put(struct snd_kcontrol *kcontrol,
1266         struct snd_ctl_elem_value *ucontrol)
1267 {
1268     struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1269     struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1270     struct device *dev;
1271     unsigned int r0_integer, r0_factor, format;
1272 
1273     if (ucontrol->value.integer.value[0] == rt1011->r0_reg)
1274         return 0;
1275 
1276     if (ucontrol->value.integer.value[0] == 0)
1277         return -EINVAL;
1278 
1279     dev = regmap_get_device(rt1011->regmap);
1280     if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1281         rt1011->r0_reg = ucontrol->value.integer.value[0];
1282 
1283         format = 2147483648U; /* 2^24 * 128 */
1284         r0_integer = format / rt1011->r0_reg / 128;
1285         r0_factor = ((format / rt1011->r0_reg * 100) / 128)
1286                         - (r0_integer * 100);
1287         dev_info(dev, "New r0 resistance about %d.%02d ohm, reg=0x%X\n",
1288             r0_integer, r0_factor, rt1011->r0_reg);
1289 
1290         if (rt1011->r0_reg)
1291             rt1011_r0_load(rt1011);
1292     }
1293 
1294     return 0;
1295 }
1296 
1297 static int rt1011_r0_load_info(struct snd_kcontrol *kcontrol,
1298              struct snd_ctl_elem_info *uinfo)
1299 {
1300     uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1301     uinfo->count = 1;
1302     uinfo->value.integer.max = 0x1ffffff;
1303 
1304     return 0;
1305 }
1306 
1307 #define RT1011_R0_LOAD(xname) \
1308 {   .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1309     .info = rt1011_r0_load_info, \
1310     .get = rt1011_r0_load_mode_get, \
1311     .put = rt1011_r0_load_mode_put \
1312 }
1313 
1314 static const char * const rt1011_i2s_ref[] = {
1315     "None", "Left Channel", "Right Channel"
1316 };
1317 
1318 static SOC_ENUM_SINGLE_DECL(rt1011_i2s_ref_enum, 0, 0,
1319     rt1011_i2s_ref);
1320 
1321 static int rt1011_i2s_ref_put(struct snd_kcontrol *kcontrol,
1322         struct snd_ctl_elem_value *ucontrol)
1323 {
1324     struct snd_soc_component *component =
1325         snd_soc_kcontrol_component(kcontrol);
1326     struct rt1011_priv *rt1011 =
1327         snd_soc_component_get_drvdata(component);
1328 
1329     rt1011->i2s_ref = ucontrol->value.enumerated.item[0];
1330     switch (rt1011->i2s_ref) {
1331     case RT1011_I2S_REF_LEFT_CH:
1332         regmap_write(rt1011->regmap, RT1011_TDM_TOTAL_SET, 0x0240);
1333         regmap_write(rt1011->regmap, RT1011_TDM1_SET_2, 0x8);
1334         regmap_write(rt1011->regmap, RT1011_TDM1_SET_1, 0x1022);
1335         regmap_write(rt1011->regmap, RT1011_ADCDAT_OUT_SOURCE, 0x4);
1336         break;
1337     case RT1011_I2S_REF_RIGHT_CH:
1338         regmap_write(rt1011->regmap, RT1011_TDM_TOTAL_SET, 0x0240);
1339         regmap_write(rt1011->regmap, RT1011_TDM1_SET_2, 0x8);
1340         regmap_write(rt1011->regmap, RT1011_TDM1_SET_1, 0x10a2);
1341         regmap_write(rt1011->regmap, RT1011_ADCDAT_OUT_SOURCE, 0x4);
1342         break;
1343     default:
1344         dev_info(component->dev, "I2S Reference: Do nothing\n");
1345     }
1346 
1347     return 0;
1348 }
1349 
1350 static int rt1011_i2s_ref_get(struct snd_kcontrol *kcontrol,
1351         struct snd_ctl_elem_value *ucontrol)
1352 {
1353     struct snd_soc_component *component =
1354         snd_soc_kcontrol_component(kcontrol);
1355     struct rt1011_priv *rt1011 =
1356         snd_soc_component_get_drvdata(component);
1357 
1358     ucontrol->value.enumerated.item[0] = rt1011->i2s_ref;
1359 
1360     return 0;
1361 }
1362 
1363 static const struct snd_kcontrol_new rt1011_snd_controls[] = {
1364     /* I2S Data In Selection */
1365     SOC_ENUM("DIN Source", rt1011_din_source_enum),
1366 
1367     /* TDM Data In Selection */
1368     SOC_ENUM("TDM1 DIN Source", rt1011_tdm1_l_dac1_enum),
1369     SOC_ENUM("TDM2 DIN Source", rt1011_tdm2_l_dac1_enum),
1370 
1371     /* TDM1 Data Out Selection */
1372     SOC_ENUM("TDM1 DOUT Source", rt1011_tdm1_adc1_dat_enum),
1373     SOC_ENUM("TDM1 DOUT Location", rt1011_tdm1_adc1_loc_enum),
1374     SOC_ENUM("TDM1 ADC1DAT Swap Select", rt1011_tdm_adc1_1_enum),
1375     SOC_ENUM("TDM1 ADC2DAT Swap Select", rt1011_tdm_adc2_1_enum),
1376 
1377     /* Data Out Mode */
1378     SOC_ENUM("I2S ADC DOUT Mode", rt1011_adc_dout_mode_enum),
1379     SOC_ENUM("TDM1 DOUT Length", rt1011_tdm1_dout_len_enum),
1380     SOC_ENUM("TDM2 DOUT Length", rt1011_tdm2_dout_len_enum),
1381 
1382     /* Speaker/Receiver Mode */
1383     SOC_SINGLE_EXT("RECV SPK Mode", SND_SOC_NOPM, 0, 1, 0,
1384         rt1011_recv_spk_mode_get, rt1011_recv_spk_mode_put),
1385 
1386     /* BiQuad/DRC/SmartBoost Settings */
1387     RT1011_BQ_DRC("AdvanceMode Initial Set"),
1388     RT1011_BQ_DRC("AdvanceMode SEP BQ Coeff"),
1389     RT1011_BQ_DRC("AdvanceMode EQ BQ Coeff"),
1390     RT1011_BQ_DRC("AdvanceMode BQ UI Coeff"),
1391     RT1011_BQ_DRC("AdvanceMode SmartBoost Coeff"),
1392 
1393     /* R0 */
1394     SOC_SINGLE_EXT("R0 Calibration", SND_SOC_NOPM, 0, 1, 0,
1395         rt1011_r0_cali_get, rt1011_r0_cali_put),
1396     RT1011_R0_LOAD("R0 Load Mode"),
1397 
1398     /* R0 temperature */
1399     SOC_SINGLE("R0 Temperature", RT1011_STP_INITIAL_RESISTANCE_TEMP,
1400         2, 255, 0),
1401     /* I2S Reference */
1402     SOC_ENUM_EXT("I2S Reference", rt1011_i2s_ref_enum,
1403         rt1011_i2s_ref_get, rt1011_i2s_ref_put),
1404 };
1405 
1406 static int rt1011_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
1407              struct snd_soc_dapm_widget *sink)
1408 {
1409     struct snd_soc_component *component =
1410         snd_soc_dapm_to_component(source->dapm);
1411     struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1412 
1413     if (rt1011->sysclk_src == RT1011_FS_SYS_PRE_S_PLL1)
1414         return 1;
1415     else
1416         return 0;
1417 }
1418 
1419 static int rt1011_dac_event(struct snd_soc_dapm_widget *w,
1420     struct snd_kcontrol *kcontrol, int event)
1421 {
1422     struct snd_soc_component *component =
1423         snd_soc_dapm_to_component(w->dapm);
1424 
1425     switch (event) {
1426     case SND_SOC_DAPM_POST_PMU:
1427         snd_soc_component_update_bits(component,
1428             RT1011_SPK_TEMP_PROTECT_0,
1429             RT1011_STP_EN_MASK | RT1011_STP_RS_CLB_EN_MASK,
1430             RT1011_STP_EN | RT1011_STP_RS_CLB_EN);
1431         snd_soc_component_update_bits(component, RT1011_POWER_9,
1432             RT1011_POW_MNL_SDB_MASK, RT1011_POW_MNL_SDB);
1433         msleep(50);
1434         snd_soc_component_update_bits(component,
1435             RT1011_CLASSD_INTERNAL_SET_1,
1436             RT1011_DRIVER_READY_SPK, RT1011_DRIVER_READY_SPK);
1437         break;
1438     case SND_SOC_DAPM_PRE_PMD:
1439         snd_soc_component_update_bits(component, RT1011_POWER_9,
1440             RT1011_POW_MNL_SDB_MASK, 0);
1441         snd_soc_component_update_bits(component,
1442             RT1011_SPK_TEMP_PROTECT_0,
1443             RT1011_STP_EN_MASK | RT1011_STP_RS_CLB_EN_MASK, 0);
1444         msleep(200);
1445         snd_soc_component_update_bits(component,
1446             RT1011_CLASSD_INTERNAL_SET_1,
1447             RT1011_DRIVER_READY_SPK, 0);
1448         break;
1449 
1450     default:
1451         return 0;
1452     }
1453 
1454     return 0;
1455 }
1456 
1457 
1458 static const struct snd_soc_dapm_widget rt1011_dapm_widgets[] = {
1459     SND_SOC_DAPM_SUPPLY("LDO2", RT1011_POWER_1,
1460         RT1011_POW_LDO2_BIT, 0, NULL, 0),
1461     SND_SOC_DAPM_SUPPLY("ISENSE SPK", RT1011_POWER_1,
1462         RT1011_POW_ISENSE_SPK_BIT, 0, NULL, 0),
1463     SND_SOC_DAPM_SUPPLY("VSENSE SPK", RT1011_POWER_1,
1464         RT1011_POW_VSENSE_SPK_BIT, 0, NULL, 0),
1465 
1466     SND_SOC_DAPM_SUPPLY("PLL", RT1011_POWER_2,
1467         RT1011_PLLEN_BIT, 0, NULL, 0),
1468     SND_SOC_DAPM_SUPPLY("BG", RT1011_POWER_2,
1469         RT1011_POW_BG_BIT, 0, NULL, 0),
1470     SND_SOC_DAPM_SUPPLY("BG MBIAS", RT1011_POWER_2,
1471         RT1011_POW_BG_MBIAS_LV_BIT, 0, NULL, 0),
1472 
1473     SND_SOC_DAPM_SUPPLY("DET VBAT", RT1011_POWER_3,
1474         RT1011_POW_DET_VBAT_BIT, 0, NULL, 0),
1475     SND_SOC_DAPM_SUPPLY("MBIAS", RT1011_POWER_3,
1476         RT1011_POW_MBIAS_LV_BIT, 0, NULL, 0),
1477     SND_SOC_DAPM_SUPPLY("ADC I", RT1011_POWER_3,
1478         RT1011_POW_ADC_I_BIT, 0, NULL, 0),
1479     SND_SOC_DAPM_SUPPLY("ADC V", RT1011_POWER_3,
1480         RT1011_POW_ADC_V_BIT, 0, NULL, 0),
1481     SND_SOC_DAPM_SUPPLY("ADC T", RT1011_POWER_3,
1482         RT1011_POW_ADC_T_BIT, 0, NULL, 0),
1483     SND_SOC_DAPM_SUPPLY("DITHER ADC T", RT1011_POWER_3,
1484         RT1011_POWD_ADC_T_BIT, 0, NULL, 0),
1485     SND_SOC_DAPM_SUPPLY("MIX I", RT1011_POWER_3,
1486         RT1011_POW_MIX_I_BIT, 0, NULL, 0),
1487     SND_SOC_DAPM_SUPPLY("MIX V", RT1011_POWER_3,
1488         RT1011_POW_MIX_V_BIT, 0, NULL, 0),
1489     SND_SOC_DAPM_SUPPLY("SUM I", RT1011_POWER_3,
1490         RT1011_POW_SUM_I_BIT, 0, NULL, 0),
1491     SND_SOC_DAPM_SUPPLY("SUM V", RT1011_POWER_3,
1492         RT1011_POW_SUM_V_BIT, 0, NULL, 0),
1493     SND_SOC_DAPM_SUPPLY("MIX T", RT1011_POWER_3,
1494         RT1011_POW_MIX_T_BIT, 0, NULL, 0),
1495     SND_SOC_DAPM_SUPPLY("VREF", RT1011_POWER_3,
1496         RT1011_POW_VREF_LV_BIT, 0, NULL, 0),
1497 
1498     SND_SOC_DAPM_SUPPLY("BOOST SWR", RT1011_POWER_4,
1499         RT1011_POW_EN_SWR_BIT, 0, NULL, 0),
1500     SND_SOC_DAPM_SUPPLY("BGOK SWR", RT1011_POWER_4,
1501         RT1011_POW_EN_PASS_BGOK_SWR_BIT, 0, NULL, 0),
1502     SND_SOC_DAPM_SUPPLY("VPOK SWR", RT1011_POWER_4,
1503         RT1011_POW_EN_PASS_VPOK_SWR_BIT, 0, NULL, 0),
1504 
1505     SND_SOC_DAPM_SUPPLY("TEMP REG", RT1011_A_TEMP_SEN,
1506         RT1011_POW_TEMP_REG_BIT, 0, NULL, 0),
1507 
1508     /* Audio Interface */
1509     SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1510     /* Digital Interface */
1511     SND_SOC_DAPM_SUPPLY("DAC Power", RT1011_POWER_1,
1512         RT1011_POW_DAC_BIT, 0, NULL, 0),
1513     SND_SOC_DAPM_SUPPLY("CLK12M", RT1011_POWER_1,
1514         RT1011_POW_CLK12M_BIT, 0, NULL, 0),
1515     SND_SOC_DAPM_DAC_E("DAC", NULL, RT1011_DAC_SET_3,
1516         RT1011_DA_MUTE_EN_SFT, 1, rt1011_dac_event,
1517         SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1518 
1519     /* Output Lines */
1520     SND_SOC_DAPM_OUTPUT("SPO"),
1521 };
1522 
1523 static const struct snd_soc_dapm_route rt1011_dapm_routes[] = {
1524 
1525     { "DAC", NULL, "AIF1RX" },
1526     { "DAC", NULL, "DAC Power" },
1527     { "DAC", NULL, "LDO2" },
1528     { "DAC", NULL, "ISENSE SPK" },
1529     { "DAC", NULL, "VSENSE SPK" },
1530     { "DAC", NULL, "CLK12M" },
1531 
1532     { "DAC", NULL, "PLL", rt1011_is_sys_clk_from_pll },
1533     { "DAC", NULL, "BG" },
1534     { "DAC", NULL, "BG MBIAS" },
1535 
1536     { "DAC", NULL, "BOOST SWR" },
1537     { "DAC", NULL, "BGOK SWR" },
1538     { "DAC", NULL, "VPOK SWR" },
1539 
1540     { "DAC", NULL, "DET VBAT" },
1541     { "DAC", NULL, "MBIAS" },
1542     { "DAC", NULL, "VREF" },
1543     { "DAC", NULL, "ADC I" },
1544     { "DAC", NULL, "ADC V" },
1545     { "DAC", NULL, "ADC T" },
1546     { "DAC", NULL, "DITHER ADC T" },
1547     { "DAC", NULL, "MIX I" },
1548     { "DAC", NULL, "MIX V" },
1549     { "DAC", NULL, "SUM I" },
1550     { "DAC", NULL, "SUM V" },
1551     { "DAC", NULL, "MIX T" },
1552 
1553     { "DAC", NULL, "TEMP REG" },
1554 
1555     { "SPO", NULL, "DAC" },
1556 };
1557 
1558 static int rt1011_get_clk_info(int sclk, int rate)
1559 {
1560     int i;
1561     static const int pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
1562 
1563     if (sclk <= 0 || rate <= 0)
1564         return -EINVAL;
1565 
1566     rate = rate << 8;
1567     for (i = 0; i < ARRAY_SIZE(pd); i++)
1568         if (sclk == rate * pd[i])
1569             return i;
1570 
1571     return -EINVAL;
1572 }
1573 
1574 static int rt1011_hw_params(struct snd_pcm_substream *substream,
1575     struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1576 {
1577     struct snd_soc_component *component = dai->component;
1578     struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1579     unsigned int val_len = 0, ch_len = 0, val_clk, mask_clk;
1580     int pre_div, bclk_ms, frame_size;
1581 
1582     rt1011->lrck = params_rate(params);
1583     pre_div = rt1011_get_clk_info(rt1011->sysclk, rt1011->lrck);
1584     if (pre_div < 0) {
1585         dev_warn(component->dev, "Force using PLL ");
1586         snd_soc_dai_set_pll(dai, 0, RT1011_PLL1_S_BCLK,
1587             rt1011->lrck * 64, rt1011->lrck * 256);
1588         snd_soc_dai_set_sysclk(dai, RT1011_FS_SYS_PRE_S_PLL1,
1589             rt1011->lrck * 256, SND_SOC_CLOCK_IN);
1590         pre_div = 0;
1591     }
1592     frame_size = snd_soc_params_to_frame_size(params);
1593     if (frame_size < 0) {
1594         dev_err(component->dev, "Unsupported frame size: %d\n",
1595             frame_size);
1596         return -EINVAL;
1597     }
1598 
1599     bclk_ms = frame_size > 32;
1600     rt1011->bclk = rt1011->lrck * (32 << bclk_ms);
1601 
1602     dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
1603                 bclk_ms, pre_div, dai->id);
1604 
1605     dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
1606                 rt1011->lrck, pre_div, dai->id);
1607 
1608     switch (params_width(params)) {
1609     case 16:
1610         val_len |= RT1011_I2S_TX_DL_16B;
1611         val_len |= RT1011_I2S_RX_DL_16B;
1612         ch_len |= RT1011_I2S_CH_TX_LEN_16B;
1613         ch_len |= RT1011_I2S_CH_RX_LEN_16B;
1614         break;
1615     case 20:
1616         val_len |= RT1011_I2S_TX_DL_20B;
1617         val_len |= RT1011_I2S_RX_DL_20B;
1618         ch_len |= RT1011_I2S_CH_TX_LEN_20B;
1619         ch_len |= RT1011_I2S_CH_RX_LEN_20B;
1620         break;
1621     case 24:
1622         val_len |= RT1011_I2S_TX_DL_24B;
1623         val_len |= RT1011_I2S_RX_DL_24B;
1624         ch_len |= RT1011_I2S_CH_TX_LEN_24B;
1625         ch_len |= RT1011_I2S_CH_RX_LEN_24B;
1626         break;
1627     case 32:
1628         val_len |= RT1011_I2S_TX_DL_32B;
1629         val_len |= RT1011_I2S_RX_DL_32B;
1630         ch_len |= RT1011_I2S_CH_TX_LEN_32B;
1631         ch_len |= RT1011_I2S_CH_RX_LEN_32B;
1632         break;
1633     case 8:
1634         val_len |= RT1011_I2S_TX_DL_8B;
1635         val_len |= RT1011_I2S_RX_DL_8B;
1636         ch_len |= RT1011_I2S_CH_TX_LEN_8B;
1637         ch_len |= RT1011_I2S_CH_RX_LEN_8B;
1638         break;
1639     default:
1640         return -EINVAL;
1641     }
1642 
1643     switch (dai->id) {
1644     case RT1011_AIF1:
1645         mask_clk = RT1011_FS_SYS_DIV_MASK;
1646         val_clk = pre_div << RT1011_FS_SYS_DIV_SFT;
1647         snd_soc_component_update_bits(component, RT1011_TDM_TOTAL_SET,
1648             RT1011_I2S_TX_DL_MASK | RT1011_I2S_RX_DL_MASK,
1649             val_len);
1650         snd_soc_component_update_bits(component, RT1011_TDM1_SET_1,
1651             RT1011_I2S_CH_TX_LEN_MASK |
1652             RT1011_I2S_CH_RX_LEN_MASK,
1653             ch_len);
1654         break;
1655     default:
1656         dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
1657         return -EINVAL;
1658     }
1659 
1660     snd_soc_component_update_bits(component,
1661         RT1011_CLK_2, mask_clk, val_clk);
1662 
1663     return 0;
1664 }
1665 
1666 static int rt1011_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1667 {
1668     struct snd_soc_component *component = dai->component;
1669     struct snd_soc_dapm_context *dapm =
1670         snd_soc_component_get_dapm(component);
1671     unsigned int reg_val = 0, reg_bclk_inv = 0;
1672     int ret = 0;
1673 
1674     snd_soc_dapm_mutex_lock(dapm);
1675     switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1676     case SND_SOC_DAIFMT_CBS_CFS:
1677         reg_val |= RT1011_I2S_TDM_MS_S;
1678         break;
1679     default:
1680         ret = -EINVAL;
1681         goto _set_fmt_err_;
1682     }
1683 
1684     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1685     case SND_SOC_DAIFMT_NB_NF:
1686         break;
1687     case SND_SOC_DAIFMT_IB_NF:
1688         reg_bclk_inv |= RT1011_TDM_INV_BCLK;
1689         break;
1690     default:
1691         ret = -EINVAL;
1692         goto _set_fmt_err_;
1693     }
1694 
1695     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1696     case SND_SOC_DAIFMT_I2S:
1697         break;
1698     case SND_SOC_DAIFMT_LEFT_J:
1699         reg_val |= RT1011_I2S_TDM_DF_LEFT;
1700         break;
1701     case SND_SOC_DAIFMT_DSP_A:
1702         reg_val |= RT1011_I2S_TDM_DF_PCM_A;
1703         break;
1704     case SND_SOC_DAIFMT_DSP_B:
1705         reg_val |= RT1011_I2S_TDM_DF_PCM_B;
1706         break;
1707     default:
1708         ret = -EINVAL;
1709         goto _set_fmt_err_;
1710     }
1711 
1712     switch (dai->id) {
1713     case RT1011_AIF1:
1714         snd_soc_component_update_bits(component, RT1011_TDM_TOTAL_SET,
1715             RT1011_I2S_TDM_MS_MASK | RT1011_I2S_TDM_DF_MASK,
1716             reg_val);
1717         snd_soc_component_update_bits(component, RT1011_TDM1_SET_1,
1718             RT1011_TDM_INV_BCLK_MASK, reg_bclk_inv);
1719         snd_soc_component_update_bits(component, RT1011_TDM2_SET_1,
1720             RT1011_TDM_INV_BCLK_MASK, reg_bclk_inv);
1721         break;
1722     default:
1723         dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
1724         ret = -EINVAL;
1725     }
1726 
1727 _set_fmt_err_:
1728     snd_soc_dapm_mutex_unlock(dapm);
1729     return ret;
1730 }
1731 
1732 static int rt1011_set_component_sysclk(struct snd_soc_component *component,
1733         int clk_id, int source, unsigned int freq, int dir)
1734 {
1735     struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1736     unsigned int reg_val = 0;
1737 
1738     if (freq == rt1011->sysclk && clk_id == rt1011->sysclk_src)
1739         return 0;
1740 
1741     /* disable MCLK detect in default */
1742     snd_soc_component_update_bits(component, RT1011_CLK_DET,
1743             RT1011_EN_MCLK_DET_MASK, 0);
1744 
1745     switch (clk_id) {
1746     case RT1011_FS_SYS_PRE_S_MCLK:
1747         reg_val |= RT1011_FS_SYS_PRE_MCLK;
1748         snd_soc_component_update_bits(component, RT1011_CLK_DET,
1749             RT1011_EN_MCLK_DET_MASK, RT1011_EN_MCLK_DET);
1750         break;
1751     case RT1011_FS_SYS_PRE_S_BCLK:
1752         reg_val |= RT1011_FS_SYS_PRE_BCLK;
1753         break;
1754     case RT1011_FS_SYS_PRE_S_PLL1:
1755         reg_val |= RT1011_FS_SYS_PRE_PLL1;
1756         break;
1757     case RT1011_FS_SYS_PRE_S_RCCLK:
1758         reg_val |= RT1011_FS_SYS_PRE_RCCLK;
1759         break;
1760     default:
1761         dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
1762         return -EINVAL;
1763     }
1764     snd_soc_component_update_bits(component, RT1011_CLK_2,
1765         RT1011_FS_SYS_PRE_MASK, reg_val);
1766     rt1011->sysclk = freq;
1767     rt1011->sysclk_src = clk_id;
1768 
1769     dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
1770         freq, clk_id);
1771 
1772     return 0;
1773 }
1774 
1775 static int rt1011_set_component_pll(struct snd_soc_component *component,
1776         int pll_id, int source, unsigned int freq_in,
1777         unsigned int freq_out)
1778 {
1779     struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1780     struct rl6231_pll_code pll_code;
1781     int ret;
1782 
1783     if (source == rt1011->pll_src && freq_in == rt1011->pll_in &&
1784         freq_out == rt1011->pll_out)
1785         return 0;
1786 
1787     if (!freq_in || !freq_out) {
1788         dev_dbg(component->dev, "PLL disabled\n");
1789 
1790         rt1011->pll_in = 0;
1791         rt1011->pll_out = 0;
1792         snd_soc_component_update_bits(component, RT1011_CLK_2,
1793             RT1011_FS_SYS_PRE_MASK, RT1011_FS_SYS_PRE_BCLK);
1794         return 0;
1795     }
1796 
1797     switch (source) {
1798     case RT1011_PLL2_S_MCLK:
1799         snd_soc_component_update_bits(component, RT1011_CLK_2,
1800             RT1011_PLL2_SRC_MASK, RT1011_PLL2_SRC_MCLK);
1801         snd_soc_component_update_bits(component, RT1011_CLK_2,
1802             RT1011_PLL1_SRC_MASK, RT1011_PLL1_SRC_PLL2);
1803         snd_soc_component_update_bits(component, RT1011_CLK_DET,
1804             RT1011_EN_MCLK_DET_MASK, RT1011_EN_MCLK_DET);
1805         break;
1806     case RT1011_PLL1_S_BCLK:
1807         snd_soc_component_update_bits(component, RT1011_CLK_2,
1808                 RT1011_PLL1_SRC_MASK, RT1011_PLL1_SRC_BCLK);
1809         break;
1810     case RT1011_PLL2_S_RCCLK:
1811         snd_soc_component_update_bits(component, RT1011_CLK_2,
1812             RT1011_PLL2_SRC_MASK, RT1011_PLL2_SRC_RCCLK);
1813         snd_soc_component_update_bits(component, RT1011_CLK_2,
1814             RT1011_PLL1_SRC_MASK, RT1011_PLL1_SRC_PLL2);
1815         break;
1816     default:
1817         dev_err(component->dev, "Unknown PLL Source %d\n", source);
1818         return -EINVAL;
1819     }
1820 
1821     ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
1822     if (ret < 0) {
1823         dev_err(component->dev, "Unsupported input clock %d\n",
1824             freq_in);
1825         return ret;
1826     }
1827 
1828     dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
1829         pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
1830         pll_code.n_code, pll_code.k_code);
1831 
1832     snd_soc_component_write(component, RT1011_PLL_1,
1833         ((pll_code.m_bp ? 0 : pll_code.m_code) << RT1011_PLL1_QM_SFT) |
1834         (pll_code.m_bp << RT1011_PLL1_BPM_SFT) |
1835         pll_code.n_code);
1836     snd_soc_component_write(component, RT1011_PLL_2,
1837         pll_code.k_code);
1838 
1839     rt1011->pll_in = freq_in;
1840     rt1011->pll_out = freq_out;
1841     rt1011->pll_src = source;
1842 
1843     return 0;
1844 }
1845 
1846 static int rt1011_set_tdm_slot(struct snd_soc_dai *dai,
1847     unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1848 {
1849     struct snd_soc_component *component = dai->component;
1850     struct snd_soc_dapm_context *dapm =
1851         snd_soc_component_get_dapm(component);
1852     unsigned int val = 0, tdm_en = 0, rx_slotnum, tx_slotnum;
1853     int ret = 0, first_bit, last_bit;
1854 
1855     snd_soc_dapm_mutex_lock(dapm);
1856     if (rx_mask || tx_mask)
1857         tdm_en = RT1011_TDM_I2S_DOCK_EN_1;
1858 
1859     switch (slots) {
1860     case 4:
1861         val |= RT1011_I2S_TX_4CH;
1862         val |= RT1011_I2S_RX_4CH;
1863         break;
1864     case 6:
1865         val |= RT1011_I2S_TX_6CH;
1866         val |= RT1011_I2S_RX_6CH;
1867         break;
1868     case 8:
1869         val |= RT1011_I2S_TX_8CH;
1870         val |= RT1011_I2S_RX_8CH;
1871         break;
1872     case 2:
1873         break;
1874     default:
1875         ret = -EINVAL;
1876         goto _set_tdm_err_;
1877     }
1878 
1879     switch (slot_width) {
1880     case 20:
1881         val |= RT1011_I2S_CH_TX_LEN_20B;
1882         val |= RT1011_I2S_CH_RX_LEN_20B;
1883         break;
1884     case 24:
1885         val |= RT1011_I2S_CH_TX_LEN_24B;
1886         val |= RT1011_I2S_CH_RX_LEN_24B;
1887         break;
1888     case 32:
1889         val |= RT1011_I2S_CH_TX_LEN_32B;
1890         val |= RT1011_I2S_CH_RX_LEN_32B;
1891         break;
1892     case 16:
1893         break;
1894     default:
1895         ret = -EINVAL;
1896         goto _set_tdm_err_;
1897     }
1898 
1899     /* Rx slot configuration */
1900     rx_slotnum = hweight_long(rx_mask);
1901     if (rx_slotnum > 1 || !rx_slotnum) {
1902         ret = -EINVAL;
1903         dev_err(component->dev, "too many rx slots or zero slot\n");
1904         goto _set_tdm_err_;
1905     }
1906 
1907     first_bit = __ffs(rx_mask);
1908     switch (first_bit) {
1909     case 0:
1910     case 2:
1911     case 4:
1912     case 6:
1913         snd_soc_component_update_bits(component,
1914             RT1011_CROSS_BQ_SET_1, RT1011_MONO_LR_SEL_MASK,
1915             RT1011_MONO_L_CHANNEL);
1916         snd_soc_component_update_bits(component,
1917             RT1011_TDM1_SET_4,
1918             RT1011_TDM_I2S_TX_L_DAC1_1_MASK |
1919             RT1011_TDM_I2S_TX_R_DAC1_1_MASK,
1920             (first_bit << RT1011_TDM_I2S_TX_L_DAC1_1_SFT) |
1921             ((first_bit+1) << RT1011_TDM_I2S_TX_R_DAC1_1_SFT));
1922         break;
1923     case 1:
1924     case 3:
1925     case 5:
1926     case 7:
1927         snd_soc_component_update_bits(component,
1928             RT1011_CROSS_BQ_SET_1, RT1011_MONO_LR_SEL_MASK,
1929             RT1011_MONO_R_CHANNEL);
1930         snd_soc_component_update_bits(component,
1931             RT1011_TDM1_SET_4,
1932             RT1011_TDM_I2S_TX_L_DAC1_1_MASK |
1933             RT1011_TDM_I2S_TX_R_DAC1_1_MASK,
1934             ((first_bit-1) << RT1011_TDM_I2S_TX_L_DAC1_1_SFT) |
1935             (first_bit << RT1011_TDM_I2S_TX_R_DAC1_1_SFT));
1936         break;
1937     default:
1938         ret = -EINVAL;
1939         goto _set_tdm_err_;
1940     }
1941 
1942     /* Tx slot configuration */
1943     tx_slotnum = hweight_long(tx_mask);
1944     if (tx_slotnum > 2 || !tx_slotnum) {
1945         ret = -EINVAL;
1946         dev_err(component->dev, "too many tx slots or zero slot\n");
1947         goto _set_tdm_err_;
1948     }
1949 
1950     first_bit = __ffs(tx_mask);
1951     last_bit = __fls(tx_mask);
1952     if (last_bit - first_bit > 1) {
1953         ret = -EINVAL;
1954         dev_err(component->dev, "tx slot location error\n");
1955         goto _set_tdm_err_;
1956     }
1957 
1958     if (tx_slotnum == 1) {
1959         snd_soc_component_update_bits(component, RT1011_TDM1_SET_2,
1960             RT1011_TDM_I2S_DOCK_ADCDAT_LEN_1_MASK |
1961             RT1011_TDM_ADCDAT1_DATA_LOCATION, first_bit);
1962         switch (first_bit) {
1963         case 1:
1964             snd_soc_component_update_bits(component,
1965                 RT1011_TDM1_SET_3,
1966                 RT1011_TDM_I2S_RX_ADC1_1_MASK,
1967                 RT1011_TDM_I2S_RX_ADC1_1_LL);
1968             break;
1969         case 3:
1970             snd_soc_component_update_bits(component,
1971                 RT1011_TDM1_SET_3,
1972                 RT1011_TDM_I2S_RX_ADC2_1_MASK,
1973                 RT1011_TDM_I2S_RX_ADC2_1_LL);
1974             break;
1975         case 5:
1976             snd_soc_component_update_bits(component,
1977                 RT1011_TDM1_SET_3,
1978                 RT1011_TDM_I2S_RX_ADC3_1_MASK,
1979                 RT1011_TDM_I2S_RX_ADC3_1_LL);
1980             break;
1981         case 7:
1982             snd_soc_component_update_bits(component,
1983                 RT1011_TDM1_SET_3,
1984                 RT1011_TDM_I2S_RX_ADC4_1_MASK,
1985                 RT1011_TDM_I2S_RX_ADC4_1_LL);
1986             break;
1987         case 0:
1988             snd_soc_component_update_bits(component,
1989                 RT1011_TDM1_SET_3,
1990                 RT1011_TDM_I2S_RX_ADC1_1_MASK, 0);
1991             break;
1992         case 2:
1993             snd_soc_component_update_bits(component,
1994                 RT1011_TDM1_SET_3,
1995                 RT1011_TDM_I2S_RX_ADC2_1_MASK, 0);
1996             break;
1997         case 4:
1998             snd_soc_component_update_bits(component,
1999                 RT1011_TDM1_SET_3,
2000                 RT1011_TDM_I2S_RX_ADC3_1_MASK, 0);
2001             break;
2002         case 6:
2003             snd_soc_component_update_bits(component,
2004                 RT1011_TDM1_SET_3,
2005                 RT1011_TDM_I2S_RX_ADC4_1_MASK, 0);
2006             break;
2007         default:
2008             ret = -EINVAL;
2009             dev_dbg(component->dev,
2010                 "tx slot location error\n");
2011             goto _set_tdm_err_;
2012         }
2013     } else if (tx_slotnum == 2) {
2014         switch (first_bit) {
2015         case 0:
2016         case 2:
2017         case 4:
2018         case 6:
2019             snd_soc_component_update_bits(component,
2020                 RT1011_TDM1_SET_2,
2021                 RT1011_TDM_I2S_DOCK_ADCDAT_LEN_1_MASK |
2022                 RT1011_TDM_ADCDAT1_DATA_LOCATION,
2023                 RT1011_TDM_I2S_DOCK_ADCDAT_2CH | first_bit);
2024             break;
2025         default:
2026             ret = -EINVAL;
2027             dev_dbg(component->dev,
2028                 "tx slot location should be paired and start from slot0/2/4/6\n");
2029             goto _set_tdm_err_;
2030         }
2031     }
2032 
2033     snd_soc_component_update_bits(component, RT1011_TDM1_SET_1,
2034         RT1011_I2S_CH_TX_MASK | RT1011_I2S_CH_RX_MASK |
2035         RT1011_I2S_CH_TX_LEN_MASK | RT1011_I2S_CH_RX_LEN_MASK, val);
2036     snd_soc_component_update_bits(component, RT1011_TDM2_SET_1,
2037         RT1011_I2S_CH_TX_MASK | RT1011_I2S_CH_RX_MASK |
2038         RT1011_I2S_CH_TX_LEN_MASK | RT1011_I2S_CH_RX_LEN_MASK, val);
2039     snd_soc_component_update_bits(component, RT1011_TDM1_SET_2,
2040         RT1011_TDM_I2S_DOCK_EN_1_MASK, tdm_en);
2041     snd_soc_component_update_bits(component, RT1011_TDM2_SET_2,
2042         RT1011_TDM_I2S_DOCK_EN_2_MASK, tdm_en);
2043 
2044     snd_soc_component_update_bits(component, RT1011_TDM_TOTAL_SET,
2045         RT1011_ADCDAT1_PIN_CONFIG | RT1011_ADCDAT2_PIN_CONFIG,
2046         RT1011_ADCDAT1_OUTPUT | RT1011_ADCDAT2_OUTPUT);
2047 
2048 _set_tdm_err_:
2049     snd_soc_dapm_mutex_unlock(dapm);
2050     return ret;
2051 }
2052 
2053 static int rt1011_probe(struct snd_soc_component *component)
2054 {
2055     struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
2056     int i;
2057 
2058     rt1011->component = component;
2059 
2060     schedule_work(&rt1011->cali_work);
2061 
2062     rt1011->i2s_ref = 0;
2063     rt1011->bq_drc_params = devm_kcalloc(component->dev,
2064         RT1011_ADVMODE_NUM, sizeof(struct rt1011_bq_drc_params *),
2065         GFP_KERNEL);
2066     if (!rt1011->bq_drc_params)
2067         return -ENOMEM;
2068 
2069     for (i = 0; i < RT1011_ADVMODE_NUM; i++) {
2070         rt1011->bq_drc_params[i] = devm_kcalloc(component->dev,
2071             RT1011_BQ_DRC_NUM, sizeof(struct rt1011_bq_drc_params),
2072             GFP_KERNEL);
2073         if (!rt1011->bq_drc_params[i])
2074             return -ENOMEM;
2075     }
2076 
2077     return 0;
2078 }
2079 
2080 static void rt1011_remove(struct snd_soc_component *component)
2081 {
2082     struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
2083 
2084     cancel_work_sync(&rt1011->cali_work);
2085     rt1011_reset(rt1011->regmap);
2086 }
2087 
2088 #ifdef CONFIG_PM
2089 static int rt1011_suspend(struct snd_soc_component *component)
2090 {
2091     struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
2092 
2093     regcache_cache_only(rt1011->regmap, true);
2094     regcache_mark_dirty(rt1011->regmap);
2095 
2096     return 0;
2097 }
2098 
2099 static int rt1011_resume(struct snd_soc_component *component)
2100 {
2101     struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
2102 
2103     regcache_cache_only(rt1011->regmap, false);
2104     regcache_sync(rt1011->regmap);
2105 
2106     return 0;
2107 }
2108 #else
2109 #define rt1011_suspend NULL
2110 #define rt1011_resume NULL
2111 #endif
2112 
2113 static int rt1011_set_bias_level(struct snd_soc_component *component,
2114                  enum snd_soc_bias_level level)
2115 {
2116     switch (level) {
2117     case SND_SOC_BIAS_OFF:
2118         snd_soc_component_write(component,
2119             RT1011_SYSTEM_RESET_1, 0x0000);
2120         snd_soc_component_write(component,
2121             RT1011_SYSTEM_RESET_2, 0x0000);
2122         snd_soc_component_write(component,
2123             RT1011_SYSTEM_RESET_3, 0x0001);
2124         snd_soc_component_write(component,
2125             RT1011_SYSTEM_RESET_1, 0x003f);
2126         snd_soc_component_write(component,
2127             RT1011_SYSTEM_RESET_2, 0x7fd7);
2128         snd_soc_component_write(component,
2129             RT1011_SYSTEM_RESET_3, 0x770f);
2130         break;
2131     default:
2132         break;
2133     }
2134 
2135     return 0;
2136 }
2137 
2138 #define RT1011_STEREO_RATES SNDRV_PCM_RATE_8000_192000
2139 #define RT1011_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
2140             SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \
2141             SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2142 
2143 static const struct snd_soc_dai_ops rt1011_aif_dai_ops = {
2144     .hw_params = rt1011_hw_params,
2145     .set_fmt = rt1011_set_dai_fmt,
2146     .set_tdm_slot = rt1011_set_tdm_slot,
2147 };
2148 
2149 static struct snd_soc_dai_driver rt1011_dai[] = {
2150     {
2151         .name = "rt1011-aif",
2152         .playback = {
2153             .stream_name = "AIF1 Playback",
2154             .channels_min = 1,
2155             .channels_max = 2,
2156             .rates = RT1011_STEREO_RATES,
2157             .formats = RT1011_FORMATS,
2158         },
2159         .ops = &rt1011_aif_dai_ops,
2160     },
2161 };
2162 
2163 static const struct snd_soc_component_driver soc_component_dev_rt1011 = {
2164     .probe = rt1011_probe,
2165     .remove = rt1011_remove,
2166     .suspend = rt1011_suspend,
2167     .resume = rt1011_resume,
2168     .set_bias_level = rt1011_set_bias_level,
2169     .controls = rt1011_snd_controls,
2170     .num_controls = ARRAY_SIZE(rt1011_snd_controls),
2171     .dapm_widgets = rt1011_dapm_widgets,
2172     .num_dapm_widgets = ARRAY_SIZE(rt1011_dapm_widgets),
2173     .dapm_routes = rt1011_dapm_routes,
2174     .num_dapm_routes = ARRAY_SIZE(rt1011_dapm_routes),
2175     .set_sysclk = rt1011_set_component_sysclk,
2176     .set_pll = rt1011_set_component_pll,
2177     .use_pmdown_time = 1,
2178     .endianness = 1,
2179 };
2180 
2181 static const struct regmap_config rt1011_regmap = {
2182     .reg_bits = 16,
2183     .val_bits = 16,
2184     .max_register = RT1011_MAX_REG + 1,
2185     .volatile_reg = rt1011_volatile_register,
2186     .readable_reg = rt1011_readable_register,
2187     .cache_type = REGCACHE_RBTREE,
2188     .reg_defaults = rt1011_reg,
2189     .num_reg_defaults = ARRAY_SIZE(rt1011_reg),
2190     .use_single_read = true,
2191     .use_single_write = true,
2192 };
2193 
2194 #if defined(CONFIG_OF)
2195 static const struct of_device_id rt1011_of_match[] = {
2196     { .compatible = "realtek,rt1011", },
2197     {},
2198 };
2199 MODULE_DEVICE_TABLE(of, rt1011_of_match);
2200 #endif
2201 
2202 #ifdef CONFIG_ACPI
2203 static const struct acpi_device_id rt1011_acpi_match[] = {
2204     {"10EC1011", 0,},
2205     {},
2206 };
2207 MODULE_DEVICE_TABLE(acpi, rt1011_acpi_match);
2208 #endif
2209 
2210 static const struct i2c_device_id rt1011_i2c_id[] = {
2211     { "rt1011", 0 },
2212     { }
2213 };
2214 MODULE_DEVICE_TABLE(i2c, rt1011_i2c_id);
2215 
2216 static int rt1011_calibrate(struct rt1011_priv *rt1011, unsigned char cali_flag)
2217 {
2218     unsigned int value, count = 0, r0[3];
2219     unsigned int chk_cnt = 50; /* DONT change this */
2220     unsigned int dc_offset;
2221     unsigned int r0_integer, r0_factor, format;
2222     struct device *dev = regmap_get_device(rt1011->regmap);
2223     struct snd_soc_dapm_context *dapm =
2224         snd_soc_component_get_dapm(rt1011->component);
2225     int ret = 0;
2226 
2227     snd_soc_dapm_mutex_lock(dapm);
2228     regcache_cache_bypass(rt1011->regmap, true);
2229 
2230     regmap_write(rt1011->regmap, RT1011_RESET, 0x0000);
2231     regmap_write(rt1011->regmap, RT1011_SYSTEM_RESET_3, 0x740f);
2232     regmap_write(rt1011->regmap, RT1011_SYSTEM_RESET_3, 0x770f);
2233 
2234     /* RC clock */
2235     regmap_write(rt1011->regmap, RT1011_CLK_2, 0x9400);
2236     regmap_write(rt1011->regmap, RT1011_PLL_1, 0x0800);
2237     regmap_write(rt1011->regmap, RT1011_PLL_2, 0x0020);
2238     regmap_write(rt1011->regmap, RT1011_CLK_DET, 0x0800);
2239 
2240     /* ADC/DAC setting */
2241     regmap_write(rt1011->regmap, RT1011_ADC_SET_5, 0x0a20);
2242     regmap_write(rt1011->regmap, RT1011_DAC_SET_2, 0xe232);
2243     regmap_write(rt1011->regmap, RT1011_ADC_SET_4, 0xc000);
2244 
2245     /* DC detection */
2246     regmap_write(rt1011->regmap, RT1011_SPK_PRO_DC_DET_1, 0xb00c);
2247     regmap_write(rt1011->regmap, RT1011_SPK_PRO_DC_DET_2, 0xcccc);
2248 
2249     /* Power */
2250     regmap_write(rt1011->regmap, RT1011_POWER_1, 0xe0e0);
2251     regmap_write(rt1011->regmap, RT1011_POWER_3, 0x5003);
2252     regmap_write(rt1011->regmap, RT1011_POWER_9, 0xa860);
2253     regmap_write(rt1011->regmap, RT1011_DAC_SET_2, 0xa032);
2254 
2255     /* POW_PLL / POW_BG / POW_BG_MBIAS_LV / POW_V/I */
2256     regmap_write(rt1011->regmap, RT1011_POWER_2, 0x0007);
2257     regmap_write(rt1011->regmap, RT1011_POWER_3, 0x5ff7);
2258     regmap_write(rt1011->regmap, RT1011_A_TEMP_SEN, 0x7f44);
2259     regmap_write(rt1011->regmap, RT1011_A_TIMING_1, 0x4054);
2260     regmap_write(rt1011->regmap, RT1011_BAT_GAIN_1, 0x309c);
2261 
2262     /* DC offset from EFUSE */
2263     regmap_write(rt1011->regmap, RT1011_DC_CALIB_CLASSD_3, 0xcb00);
2264     regmap_write(rt1011->regmap, RT1011_BOOST_CON_1, 0xe080);
2265     regmap_write(rt1011->regmap, RT1011_POWER_4, 0x16f2);
2266     regmap_write(rt1011->regmap, RT1011_POWER_6, 0x36ad);
2267 
2268     /* mixer */
2269     regmap_write(rt1011->regmap, RT1011_MIXER_1, 0x3f1d);
2270 
2271     /* EFUSE read */
2272     regmap_write(rt1011->regmap, RT1011_EFUSE_CONTROL_1, 0x0d0a);
2273     msleep(30);
2274 
2275     regmap_read(rt1011->regmap, RT1011_EFUSE_ADC_OFFSET_18_16, &value);
2276     dc_offset = value << 16;
2277     regmap_read(rt1011->regmap, RT1011_EFUSE_ADC_OFFSET_15_0, &value);
2278     dc_offset |= (value & 0xffff);
2279     dev_info(dev, "ADC offset=0x%x\n", dc_offset);
2280     regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G0_20_16, &value);
2281     dc_offset = value << 16;
2282     regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G0_15_0, &value);
2283     dc_offset |= (value & 0xffff);
2284     dev_info(dev, "Gain0 offset=0x%x\n", dc_offset);
2285     regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G1_20_16, &value);
2286     dc_offset = value << 16;
2287     regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G1_15_0, &value);
2288     dc_offset |= (value & 0xffff);
2289     dev_info(dev, "Gain1 offset=0x%x\n", dc_offset);
2290 
2291     if (cali_flag) {
2292 
2293         regmap_write(rt1011->regmap, RT1011_ADC_SET_1, 0x2925);
2294         /* Class D on */
2295         regmap_write(rt1011->regmap, RT1011_CLASS_D_POS, 0x010e);
2296         regmap_write(rt1011->regmap,
2297             RT1011_CLASSD_INTERNAL_SET_1, 0x1701);
2298 
2299         /* STP enable */
2300         regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_0, 0x8000);
2301         regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_7, 0xf000);
2302         regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_4, 0x4040);
2303         regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_0, 0xc000);
2304         regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_6, 0x07c2);
2305 
2306         r0[0] = r0[1] = r0[2] = count = 0;
2307         while (count < chk_cnt) {
2308             msleep(100);
2309             regmap_read(rt1011->regmap,
2310                 RT1011_INIT_RECIPROCAL_SYN_24_16, &value);
2311             r0[count%3] = value << 16;
2312             regmap_read(rt1011->regmap,
2313                 RT1011_INIT_RECIPROCAL_SYN_15_0, &value);
2314             r0[count%3] |= value;
2315 
2316             if (r0[count%3] == 0)
2317                 continue;
2318 
2319             count++;
2320 
2321             if (r0[0] == r0[1] && r0[1] == r0[2])
2322                 break;
2323         }
2324         if (count > chk_cnt) {
2325             dev_err(dev, "Calibrate R0 Failure\n");
2326             ret = -EAGAIN;
2327         } else {
2328             format = 2147483648U; /* 2^24 * 128 */
2329             r0_integer = format / r0[0] / 128;
2330             r0_factor = ((format / r0[0] * 100) / 128)
2331                             - (r0_integer * 100);
2332             rt1011->r0_reg = r0[0];
2333             rt1011->cali_done = 1;
2334             dev_info(dev, "r0 resistance about %d.%02d ohm, reg=0x%X\n",
2335                 r0_integer, r0_factor, r0[0]);
2336         }
2337     }
2338 
2339     /* depop */
2340     regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_0, 0x0000);
2341     msleep(400);
2342     regmap_write(rt1011->regmap, RT1011_POWER_9, 0xa840);
2343     regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_6, 0x0702);
2344     regmap_write(rt1011->regmap, RT1011_MIXER_1, 0xffdd);
2345     regmap_write(rt1011->regmap, RT1011_CLASSD_INTERNAL_SET_1, 0x0701);
2346     regmap_write(rt1011->regmap, RT1011_DAC_SET_3, 0xe004);
2347     regmap_write(rt1011->regmap, RT1011_A_TEMP_SEN, 0x7f40);
2348     regmap_write(rt1011->regmap, RT1011_POWER_1, 0x0000);
2349     regmap_write(rt1011->regmap, RT1011_POWER_2, 0x0000);
2350     regmap_write(rt1011->regmap, RT1011_POWER_3, 0x0002);
2351     regmap_write(rt1011->regmap, RT1011_POWER_4, 0x00f2);
2352 
2353     regmap_write(rt1011->regmap, RT1011_RESET, 0x0000);
2354 
2355     if (cali_flag) {
2356         if (count <= chk_cnt) {
2357             regmap_write(rt1011->regmap,
2358                 RT1011_INIT_RECIPROCAL_REG_24_16,
2359                 ((r0[0]>>16) & 0x1ff));
2360             regmap_write(rt1011->regmap,
2361                 RT1011_INIT_RECIPROCAL_REG_15_0,
2362                 (r0[0] & 0xffff));
2363             regmap_write(rt1011->regmap,
2364                 RT1011_SPK_TEMP_PROTECT_4, 0x4080);
2365         }
2366     }
2367 
2368     regcache_cache_bypass(rt1011->regmap, false);
2369     regcache_mark_dirty(rt1011->regmap);
2370     regcache_sync(rt1011->regmap);
2371     snd_soc_dapm_mutex_unlock(dapm);
2372 
2373     return ret;
2374 }
2375 
2376 static void rt1011_calibration_work(struct work_struct *work)
2377 {
2378     struct rt1011_priv *rt1011 =
2379         container_of(work, struct rt1011_priv, cali_work);
2380     struct snd_soc_component *component = rt1011->component;
2381     unsigned int r0_integer, r0_factor, format;
2382 
2383     if (rt1011->r0_calib)
2384         rt1011_calibrate(rt1011, 0);
2385     else
2386         rt1011_calibrate(rt1011, 1);
2387 
2388     /*
2389      * This flag should reset after booting.
2390      * The factory test will do calibration again and use this flag to check
2391      * whether the calibration completed
2392      */
2393     rt1011->cali_done = 0;
2394 
2395     /* initial */
2396     rt1011_reg_init(component);
2397 
2398     /* Apply temperature and calibration data from device property */
2399     if (rt1011->temperature_calib <= 0xff &&
2400         rt1011->temperature_calib > 0) {
2401         snd_soc_component_update_bits(component,
2402             RT1011_STP_INITIAL_RESISTANCE_TEMP, 0x3ff,
2403             (rt1011->temperature_calib << 2));
2404     }
2405 
2406     if (rt1011->r0_calib) {
2407         rt1011->r0_reg = rt1011->r0_calib;
2408 
2409         format = 2147483648U; /* 2^24 * 128 */
2410         r0_integer = format / rt1011->r0_reg / 128;
2411         r0_factor = ((format / rt1011->r0_reg * 100) / 128)
2412                         - (r0_integer * 100);
2413         dev_info(component->dev, "DP r0 resistance about %d.%02d ohm, reg=0x%X\n",
2414             r0_integer, r0_factor, rt1011->r0_reg);
2415 
2416         rt1011_r0_load(rt1011);
2417     }
2418 
2419     snd_soc_component_write(component, RT1011_ADC_SET_1, 0x2925);
2420 }
2421 
2422 static int rt1011_parse_dp(struct rt1011_priv *rt1011, struct device *dev)
2423 {
2424     device_property_read_u32(dev, "realtek,temperature_calib",
2425         &rt1011->temperature_calib);
2426     device_property_read_u32(dev, "realtek,r0_calib",
2427         &rt1011->r0_calib);
2428 
2429     dev_dbg(dev, "%s: r0_calib: 0x%x, temperature_calib: 0x%x",
2430         __func__, rt1011->r0_calib, rt1011->temperature_calib);
2431 
2432     return 0;
2433 }
2434 
2435 static int rt1011_i2c_probe(struct i2c_client *i2c)
2436 {
2437     struct rt1011_priv *rt1011;
2438     int ret;
2439     unsigned int val;
2440 
2441     rt1011 = devm_kzalloc(&i2c->dev, sizeof(struct rt1011_priv),
2442                 GFP_KERNEL);
2443     if (!rt1011)
2444         return -ENOMEM;
2445 
2446     i2c_set_clientdata(i2c, rt1011);
2447 
2448     rt1011_parse_dp(rt1011, &i2c->dev);
2449 
2450     rt1011->regmap = devm_regmap_init_i2c(i2c, &rt1011_regmap);
2451     if (IS_ERR(rt1011->regmap)) {
2452         ret = PTR_ERR(rt1011->regmap);
2453         dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2454             ret);
2455         return ret;
2456     }
2457 
2458     regmap_read(rt1011->regmap, RT1011_DEVICE_ID, &val);
2459     if (val != RT1011_DEVICE_ID_NUM) {
2460         dev_err(&i2c->dev,
2461             "Device with ID register %x is not rt1011\n", val);
2462         return -ENODEV;
2463     }
2464 
2465     INIT_WORK(&rt1011->cali_work, rt1011_calibration_work);
2466 
2467     return devm_snd_soc_register_component(&i2c->dev,
2468         &soc_component_dev_rt1011,
2469         rt1011_dai, ARRAY_SIZE(rt1011_dai));
2470 
2471 }
2472 
2473 static void rt1011_i2c_shutdown(struct i2c_client *client)
2474 {
2475     struct rt1011_priv *rt1011 = i2c_get_clientdata(client);
2476 
2477     rt1011_reset(rt1011->regmap);
2478 }
2479 
2480 static struct i2c_driver rt1011_i2c_driver = {
2481     .driver = {
2482         .name = "rt1011",
2483         .of_match_table = of_match_ptr(rt1011_of_match),
2484         .acpi_match_table = ACPI_PTR(rt1011_acpi_match)
2485     },
2486     .probe_new = rt1011_i2c_probe,
2487     .shutdown = rt1011_i2c_shutdown,
2488     .id_table = rt1011_i2c_id,
2489 };
2490 module_i2c_driver(rt1011_i2c_driver);
2491 
2492 MODULE_DESCRIPTION("ASoC RT1011 amplifier driver");
2493 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>");
2494 MODULE_LICENSE("GPL");
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