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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Driver for the PCM512x CODECs
0004  *
0005  * Author:  Mark Brown <broonie@kernel.org>
0006  *      Copyright 2014 Linaro Ltd
0007  */
0008 
0009 
0010 #include <linux/init.h>
0011 #include <linux/module.h>
0012 #include <linux/clk.h>
0013 #include <linux/kernel.h>
0014 #include <linux/pm_runtime.h>
0015 #include <linux/regmap.h>
0016 #include <linux/regulator/consumer.h>
0017 #include <linux/gcd.h>
0018 #include <sound/soc.h>
0019 #include <sound/soc-dapm.h>
0020 #include <sound/pcm_params.h>
0021 #include <sound/tlv.h>
0022 
0023 #include "pcm512x.h"
0024 
0025 #define PCM512x_NUM_SUPPLIES 3
0026 static const char * const pcm512x_supply_names[PCM512x_NUM_SUPPLIES] = {
0027     "AVDD",
0028     "DVDD",
0029     "CPVDD",
0030 };
0031 
0032 struct pcm512x_priv {
0033     struct regmap *regmap;
0034     struct clk *sclk;
0035     struct regulator_bulk_data supplies[PCM512x_NUM_SUPPLIES];
0036     struct notifier_block supply_nb[PCM512x_NUM_SUPPLIES];
0037     int fmt;
0038     int pll_in;
0039     int pll_out;
0040     int pll_r;
0041     int pll_j;
0042     int pll_d;
0043     int pll_p;
0044     unsigned long real_pll;
0045     unsigned long overclock_pll;
0046     unsigned long overclock_dac;
0047     unsigned long overclock_dsp;
0048     int mute;
0049     struct mutex mutex;
0050     unsigned int bclk_ratio;
0051 };
0052 
0053 /*
0054  * We can't use the same notifier block for more than one supply and
0055  * there's no way I can see to get from a callback to the caller
0056  * except container_of().
0057  */
0058 #define PCM512x_REGULATOR_EVENT(n) \
0059 static int pcm512x_regulator_event_##n(struct notifier_block *nb, \
0060                       unsigned long event, void *data)    \
0061 { \
0062     struct pcm512x_priv *pcm512x = container_of(nb, struct pcm512x_priv, \
0063                             supply_nb[n]); \
0064     if (event & REGULATOR_EVENT_DISABLE) { \
0065         regcache_mark_dirty(pcm512x->regmap);   \
0066         regcache_cache_only(pcm512x->regmap, true); \
0067     } \
0068     return 0; \
0069 }
0070 
0071 PCM512x_REGULATOR_EVENT(0)
0072 PCM512x_REGULATOR_EVENT(1)
0073 PCM512x_REGULATOR_EVENT(2)
0074 
0075 static const struct reg_default pcm512x_reg_defaults[] = {
0076     { PCM512x_RESET,             0x00 },
0077     { PCM512x_POWER,             0x00 },
0078     { PCM512x_MUTE,              0x00 },
0079     { PCM512x_DSP,               0x00 },
0080     { PCM512x_PLL_REF,           0x00 },
0081     { PCM512x_DAC_REF,           0x00 },
0082     { PCM512x_DAC_ROUTING,       0x11 },
0083     { PCM512x_DSP_PROGRAM,       0x01 },
0084     { PCM512x_CLKDET,            0x00 },
0085     { PCM512x_AUTO_MUTE,         0x00 },
0086     { PCM512x_ERROR_DETECT,      0x00 },
0087     { PCM512x_DIGITAL_VOLUME_1,  0x00 },
0088     { PCM512x_DIGITAL_VOLUME_2,  0x30 },
0089     { PCM512x_DIGITAL_VOLUME_3,  0x30 },
0090     { PCM512x_DIGITAL_MUTE_1,    0x22 },
0091     { PCM512x_DIGITAL_MUTE_2,    0x00 },
0092     { PCM512x_DIGITAL_MUTE_3,    0x07 },
0093     { PCM512x_OUTPUT_AMPLITUDE,  0x00 },
0094     { PCM512x_ANALOG_GAIN_CTRL,  0x00 },
0095     { PCM512x_UNDERVOLTAGE_PROT, 0x00 },
0096     { PCM512x_ANALOG_MUTE_CTRL,  0x00 },
0097     { PCM512x_ANALOG_GAIN_BOOST, 0x00 },
0098     { PCM512x_VCOM_CTRL_1,       0x00 },
0099     { PCM512x_VCOM_CTRL_2,       0x01 },
0100     { PCM512x_BCLK_LRCLK_CFG,    0x00 },
0101     { PCM512x_MASTER_MODE,       0x7c },
0102     { PCM512x_GPIO_DACIN,        0x00 },
0103     { PCM512x_GPIO_PLLIN,        0x00 },
0104     { PCM512x_SYNCHRONIZE,       0x10 },
0105     { PCM512x_PLL_COEFF_0,       0x00 },
0106     { PCM512x_PLL_COEFF_1,       0x00 },
0107     { PCM512x_PLL_COEFF_2,       0x00 },
0108     { PCM512x_PLL_COEFF_3,       0x00 },
0109     { PCM512x_PLL_COEFF_4,       0x00 },
0110     { PCM512x_DSP_CLKDIV,        0x00 },
0111     { PCM512x_DAC_CLKDIV,        0x00 },
0112     { PCM512x_NCP_CLKDIV,        0x00 },
0113     { PCM512x_OSR_CLKDIV,        0x00 },
0114     { PCM512x_MASTER_CLKDIV_1,   0x00 },
0115     { PCM512x_MASTER_CLKDIV_2,   0x00 },
0116     { PCM512x_FS_SPEED_MODE,     0x00 },
0117     { PCM512x_IDAC_1,            0x01 },
0118     { PCM512x_IDAC_2,            0x00 },
0119     { PCM512x_I2S_1,             0x02 },
0120     { PCM512x_I2S_2,             0x00 },
0121 };
0122 
0123 static bool pcm512x_readable(struct device *dev, unsigned int reg)
0124 {
0125     switch (reg) {
0126     case PCM512x_RESET:
0127     case PCM512x_POWER:
0128     case PCM512x_MUTE:
0129     case PCM512x_PLL_EN:
0130     case PCM512x_SPI_MISO_FUNCTION:
0131     case PCM512x_DSP:
0132     case PCM512x_GPIO_EN:
0133     case PCM512x_BCLK_LRCLK_CFG:
0134     case PCM512x_DSP_GPIO_INPUT:
0135     case PCM512x_MASTER_MODE:
0136     case PCM512x_PLL_REF:
0137     case PCM512x_DAC_REF:
0138     case PCM512x_GPIO_DACIN:
0139     case PCM512x_GPIO_PLLIN:
0140     case PCM512x_SYNCHRONIZE:
0141     case PCM512x_PLL_COEFF_0:
0142     case PCM512x_PLL_COEFF_1:
0143     case PCM512x_PLL_COEFF_2:
0144     case PCM512x_PLL_COEFF_3:
0145     case PCM512x_PLL_COEFF_4:
0146     case PCM512x_DSP_CLKDIV:
0147     case PCM512x_DAC_CLKDIV:
0148     case PCM512x_NCP_CLKDIV:
0149     case PCM512x_OSR_CLKDIV:
0150     case PCM512x_MASTER_CLKDIV_1:
0151     case PCM512x_MASTER_CLKDIV_2:
0152     case PCM512x_FS_SPEED_MODE:
0153     case PCM512x_IDAC_1:
0154     case PCM512x_IDAC_2:
0155     case PCM512x_ERROR_DETECT:
0156     case PCM512x_I2S_1:
0157     case PCM512x_I2S_2:
0158     case PCM512x_DAC_ROUTING:
0159     case PCM512x_DSP_PROGRAM:
0160     case PCM512x_CLKDET:
0161     case PCM512x_AUTO_MUTE:
0162     case PCM512x_DIGITAL_VOLUME_1:
0163     case PCM512x_DIGITAL_VOLUME_2:
0164     case PCM512x_DIGITAL_VOLUME_3:
0165     case PCM512x_DIGITAL_MUTE_1:
0166     case PCM512x_DIGITAL_MUTE_2:
0167     case PCM512x_DIGITAL_MUTE_3:
0168     case PCM512x_GPIO_OUTPUT_1:
0169     case PCM512x_GPIO_OUTPUT_2:
0170     case PCM512x_GPIO_OUTPUT_3:
0171     case PCM512x_GPIO_OUTPUT_4:
0172     case PCM512x_GPIO_OUTPUT_5:
0173     case PCM512x_GPIO_OUTPUT_6:
0174     case PCM512x_GPIO_CONTROL_1:
0175     case PCM512x_GPIO_CONTROL_2:
0176     case PCM512x_OVERFLOW:
0177     case PCM512x_RATE_DET_1:
0178     case PCM512x_RATE_DET_2:
0179     case PCM512x_RATE_DET_3:
0180     case PCM512x_RATE_DET_4:
0181     case PCM512x_CLOCK_STATUS:
0182     case PCM512x_ANALOG_MUTE_DET:
0183     case PCM512x_GPIN:
0184     case PCM512x_DIGITAL_MUTE_DET:
0185     case PCM512x_OUTPUT_AMPLITUDE:
0186     case PCM512x_ANALOG_GAIN_CTRL:
0187     case PCM512x_UNDERVOLTAGE_PROT:
0188     case PCM512x_ANALOG_MUTE_CTRL:
0189     case PCM512x_ANALOG_GAIN_BOOST:
0190     case PCM512x_VCOM_CTRL_1:
0191     case PCM512x_VCOM_CTRL_2:
0192     case PCM512x_CRAM_CTRL:
0193     case PCM512x_FLEX_A:
0194     case PCM512x_FLEX_B:
0195         return true;
0196     default:
0197         /* There are 256 raw register addresses */
0198         return reg < 0xff;
0199     }
0200 }
0201 
0202 static bool pcm512x_volatile(struct device *dev, unsigned int reg)
0203 {
0204     switch (reg) {
0205     case PCM512x_PLL_EN:
0206     case PCM512x_OVERFLOW:
0207     case PCM512x_RATE_DET_1:
0208     case PCM512x_RATE_DET_2:
0209     case PCM512x_RATE_DET_3:
0210     case PCM512x_RATE_DET_4:
0211     case PCM512x_CLOCK_STATUS:
0212     case PCM512x_ANALOG_MUTE_DET:
0213     case PCM512x_GPIN:
0214     case PCM512x_DIGITAL_MUTE_DET:
0215     case PCM512x_CRAM_CTRL:
0216         return true;
0217     default:
0218         /* There are 256 raw register addresses */
0219         return reg < 0xff;
0220     }
0221 }
0222 
0223 static int pcm512x_overclock_pll_get(struct snd_kcontrol *kcontrol,
0224                      struct snd_ctl_elem_value *ucontrol)
0225 {
0226     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0227     struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
0228 
0229     ucontrol->value.integer.value[0] = pcm512x->overclock_pll;
0230     return 0;
0231 }
0232 
0233 static int pcm512x_overclock_pll_put(struct snd_kcontrol *kcontrol,
0234                      struct snd_ctl_elem_value *ucontrol)
0235 {
0236     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0237     struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
0238 
0239     switch (snd_soc_component_get_bias_level(component)) {
0240     case SND_SOC_BIAS_OFF:
0241     case SND_SOC_BIAS_STANDBY:
0242         break;
0243     default:
0244         return -EBUSY;
0245     }
0246 
0247     pcm512x->overclock_pll = ucontrol->value.integer.value[0];
0248     return 0;
0249 }
0250 
0251 static int pcm512x_overclock_dsp_get(struct snd_kcontrol *kcontrol,
0252                      struct snd_ctl_elem_value *ucontrol)
0253 {
0254     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0255     struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
0256 
0257     ucontrol->value.integer.value[0] = pcm512x->overclock_dsp;
0258     return 0;
0259 }
0260 
0261 static int pcm512x_overclock_dsp_put(struct snd_kcontrol *kcontrol,
0262                      struct snd_ctl_elem_value *ucontrol)
0263 {
0264     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0265     struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
0266 
0267     switch (snd_soc_component_get_bias_level(component)) {
0268     case SND_SOC_BIAS_OFF:
0269     case SND_SOC_BIAS_STANDBY:
0270         break;
0271     default:
0272         return -EBUSY;
0273     }
0274 
0275     pcm512x->overclock_dsp = ucontrol->value.integer.value[0];
0276     return 0;
0277 }
0278 
0279 static int pcm512x_overclock_dac_get(struct snd_kcontrol *kcontrol,
0280                      struct snd_ctl_elem_value *ucontrol)
0281 {
0282     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0283     struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
0284 
0285     ucontrol->value.integer.value[0] = pcm512x->overclock_dac;
0286     return 0;
0287 }
0288 
0289 static int pcm512x_overclock_dac_put(struct snd_kcontrol *kcontrol,
0290                      struct snd_ctl_elem_value *ucontrol)
0291 {
0292     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0293     struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
0294 
0295     switch (snd_soc_component_get_bias_level(component)) {
0296     case SND_SOC_BIAS_OFF:
0297     case SND_SOC_BIAS_STANDBY:
0298         break;
0299     default:
0300         return -EBUSY;
0301     }
0302 
0303     pcm512x->overclock_dac = ucontrol->value.integer.value[0];
0304     return 0;
0305 }
0306 
0307 static const DECLARE_TLV_DB_SCALE(digital_tlv, -10350, 50, 1);
0308 static const DECLARE_TLV_DB_SCALE(analog_tlv, -600, 600, 0);
0309 static const DECLARE_TLV_DB_SCALE(boost_tlv, 0, 80, 0);
0310 
0311 static const char * const pcm512x_dsp_program_texts[] = {
0312     "FIR interpolation with de-emphasis",
0313     "Low latency IIR with de-emphasis",
0314     "High attenuation with de-emphasis",
0315     "Fixed process flow",
0316     "Ringing-less low latency FIR",
0317 };
0318 
0319 static const unsigned int pcm512x_dsp_program_values[] = {
0320     1,
0321     2,
0322     3,
0323     5,
0324     7,
0325 };
0326 
0327 static SOC_VALUE_ENUM_SINGLE_DECL(pcm512x_dsp_program,
0328                   PCM512x_DSP_PROGRAM, 0, 0x1f,
0329                   pcm512x_dsp_program_texts,
0330                   pcm512x_dsp_program_values);
0331 
0332 static const char * const pcm512x_clk_missing_text[] = {
0333     "1s", "2s", "3s", "4s", "5s", "6s", "7s", "8s"
0334 };
0335 
0336 static const struct soc_enum pcm512x_clk_missing =
0337     SOC_ENUM_SINGLE(PCM512x_CLKDET, 0,  8, pcm512x_clk_missing_text);
0338 
0339 static const char * const pcm512x_autom_text[] = {
0340     "21ms", "106ms", "213ms", "533ms", "1.07s", "2.13s", "5.33s", "10.66s"
0341 };
0342 
0343 static const struct soc_enum pcm512x_autom_l =
0344     SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATML_SHIFT, 8,
0345             pcm512x_autom_text);
0346 
0347 static const struct soc_enum pcm512x_autom_r =
0348     SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATMR_SHIFT, 8,
0349             pcm512x_autom_text);
0350 
0351 static const char * const pcm512x_ramp_rate_text[] = {
0352     "1 sample/update", "2 samples/update", "4 samples/update",
0353     "Immediate"
0354 };
0355 
0356 static const struct soc_enum pcm512x_vndf =
0357     SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDF_SHIFT, 4,
0358             pcm512x_ramp_rate_text);
0359 
0360 static const struct soc_enum pcm512x_vnuf =
0361     SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUF_SHIFT, 4,
0362             pcm512x_ramp_rate_text);
0363 
0364 static const struct soc_enum pcm512x_vedf =
0365     SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDF_SHIFT, 4,
0366             pcm512x_ramp_rate_text);
0367 
0368 static const char * const pcm512x_ramp_step_text[] = {
0369     "4dB/step", "2dB/step", "1dB/step", "0.5dB/step"
0370 };
0371 
0372 static const struct soc_enum pcm512x_vnds =
0373     SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDS_SHIFT, 4,
0374             pcm512x_ramp_step_text);
0375 
0376 static const struct soc_enum pcm512x_vnus =
0377     SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUS_SHIFT, 4,
0378             pcm512x_ramp_step_text);
0379 
0380 static const struct soc_enum pcm512x_veds =
0381     SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDS_SHIFT, 4,
0382             pcm512x_ramp_step_text);
0383 
0384 static int pcm512x_update_mute(struct pcm512x_priv *pcm512x)
0385 {
0386     return regmap_update_bits(
0387         pcm512x->regmap, PCM512x_MUTE, PCM512x_RQML | PCM512x_RQMR,
0388         (!!(pcm512x->mute & 0x5) << PCM512x_RQML_SHIFT)
0389         | (!!(pcm512x->mute & 0x3) << PCM512x_RQMR_SHIFT));
0390 }
0391 
0392 static int pcm512x_digital_playback_switch_get(struct snd_kcontrol *kcontrol,
0393                            struct snd_ctl_elem_value *ucontrol)
0394 {
0395     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0396     struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
0397 
0398     mutex_lock(&pcm512x->mutex);
0399     ucontrol->value.integer.value[0] = !(pcm512x->mute & 0x4);
0400     ucontrol->value.integer.value[1] = !(pcm512x->mute & 0x2);
0401     mutex_unlock(&pcm512x->mutex);
0402 
0403     return 0;
0404 }
0405 
0406 static int pcm512x_digital_playback_switch_put(struct snd_kcontrol *kcontrol,
0407                            struct snd_ctl_elem_value *ucontrol)
0408 {
0409     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0410     struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
0411     int ret, changed = 0;
0412 
0413     mutex_lock(&pcm512x->mutex);
0414 
0415     if ((pcm512x->mute & 0x4) == (ucontrol->value.integer.value[0] << 2)) {
0416         pcm512x->mute ^= 0x4;
0417         changed = 1;
0418     }
0419     if ((pcm512x->mute & 0x2) == (ucontrol->value.integer.value[1] << 1)) {
0420         pcm512x->mute ^= 0x2;
0421         changed = 1;
0422     }
0423 
0424     if (changed) {
0425         ret = pcm512x_update_mute(pcm512x);
0426         if (ret != 0) {
0427             dev_err(component->dev,
0428                 "Failed to update digital mute: %d\n", ret);
0429             mutex_unlock(&pcm512x->mutex);
0430             return ret;
0431         }
0432     }
0433 
0434     mutex_unlock(&pcm512x->mutex);
0435 
0436     return changed;
0437 }
0438 
0439 static const struct snd_kcontrol_new pcm512x_controls[] = {
0440 SOC_DOUBLE_R_TLV("Digital Playback Volume", PCM512x_DIGITAL_VOLUME_2,
0441          PCM512x_DIGITAL_VOLUME_3, 0, 255, 1, digital_tlv),
0442 SOC_DOUBLE_TLV("Analogue Playback Volume", PCM512x_ANALOG_GAIN_CTRL,
0443            PCM512x_LAGN_SHIFT, PCM512x_RAGN_SHIFT, 1, 1, analog_tlv),
0444 SOC_DOUBLE_TLV("Analogue Playback Boost Volume", PCM512x_ANALOG_GAIN_BOOST,
0445            PCM512x_AGBL_SHIFT, PCM512x_AGBR_SHIFT, 1, 0, boost_tlv),
0446 {
0447     .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
0448     .name = "Digital Playback Switch",
0449     .index = 0,
0450     .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
0451     .info = snd_ctl_boolean_stereo_info,
0452     .get = pcm512x_digital_playback_switch_get,
0453     .put = pcm512x_digital_playback_switch_put
0454 },
0455 
0456 SOC_SINGLE("Deemphasis Switch", PCM512x_DSP, PCM512x_DEMP_SHIFT, 1, 1),
0457 SOC_ENUM("DSP Program", pcm512x_dsp_program),
0458 
0459 SOC_ENUM("Clock Missing Period", pcm512x_clk_missing),
0460 SOC_ENUM("Auto Mute Time Left", pcm512x_autom_l),
0461 SOC_ENUM("Auto Mute Time Right", pcm512x_autom_r),
0462 SOC_SINGLE("Auto Mute Mono Switch", PCM512x_DIGITAL_MUTE_3,
0463        PCM512x_ACTL_SHIFT, 1, 0),
0464 SOC_DOUBLE("Auto Mute Switch", PCM512x_DIGITAL_MUTE_3, PCM512x_AMLE_SHIFT,
0465        PCM512x_AMRE_SHIFT, 1, 0),
0466 
0467 SOC_ENUM("Volume Ramp Down Rate", pcm512x_vndf),
0468 SOC_ENUM("Volume Ramp Down Step", pcm512x_vnds),
0469 SOC_ENUM("Volume Ramp Up Rate", pcm512x_vnuf),
0470 SOC_ENUM("Volume Ramp Up Step", pcm512x_vnus),
0471 SOC_ENUM("Volume Ramp Down Emergency Rate", pcm512x_vedf),
0472 SOC_ENUM("Volume Ramp Down Emergency Step", pcm512x_veds),
0473 
0474 SOC_SINGLE_EXT("Max Overclock PLL", SND_SOC_NOPM, 0, 20, 0,
0475            pcm512x_overclock_pll_get, pcm512x_overclock_pll_put),
0476 SOC_SINGLE_EXT("Max Overclock DSP", SND_SOC_NOPM, 0, 40, 0,
0477            pcm512x_overclock_dsp_get, pcm512x_overclock_dsp_put),
0478 SOC_SINGLE_EXT("Max Overclock DAC", SND_SOC_NOPM, 0, 40, 0,
0479            pcm512x_overclock_dac_get, pcm512x_overclock_dac_put),
0480 };
0481 
0482 static const struct snd_soc_dapm_widget pcm512x_dapm_widgets[] = {
0483 SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0),
0484 SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0),
0485 
0486 SND_SOC_DAPM_OUTPUT("OUTL"),
0487 SND_SOC_DAPM_OUTPUT("OUTR"),
0488 };
0489 
0490 static const struct snd_soc_dapm_route pcm512x_dapm_routes[] = {
0491     { "DACL", NULL, "Playback" },
0492     { "DACR", NULL, "Playback" },
0493 
0494     { "OUTL", NULL, "DACL" },
0495     { "OUTR", NULL, "DACR" },
0496 };
0497 
0498 static unsigned long pcm512x_pll_max(struct pcm512x_priv *pcm512x)
0499 {
0500     return 25000000 + 25000000 * pcm512x->overclock_pll / 100;
0501 }
0502 
0503 static unsigned long pcm512x_dsp_max(struct pcm512x_priv *pcm512x)
0504 {
0505     return 50000000 + 50000000 * pcm512x->overclock_dsp / 100;
0506 }
0507 
0508 static unsigned long pcm512x_dac_max(struct pcm512x_priv *pcm512x,
0509                      unsigned long rate)
0510 {
0511     return rate + rate * pcm512x->overclock_dac / 100;
0512 }
0513 
0514 static unsigned long pcm512x_sck_max(struct pcm512x_priv *pcm512x)
0515 {
0516     if (!pcm512x->pll_out)
0517         return 25000000;
0518     return pcm512x_pll_max(pcm512x);
0519 }
0520 
0521 static unsigned long pcm512x_ncp_target(struct pcm512x_priv *pcm512x,
0522                     unsigned long dac_rate)
0523 {
0524     /*
0525      * If the DAC is not actually overclocked, use the good old
0526      * NCP target rate...
0527      */
0528     if (dac_rate <= 6144000)
0529         return 1536000;
0530     /*
0531      * ...but if the DAC is in fact overclocked, bump the NCP target
0532      * rate to get the recommended dividers even when overclocking.
0533      */
0534     return pcm512x_dac_max(pcm512x, 1536000);
0535 }
0536 
0537 static const u32 pcm512x_dai_rates[] = {
0538     8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
0539     88200, 96000, 176400, 192000, 384000,
0540 };
0541 
0542 static const struct snd_pcm_hw_constraint_list constraints_slave = {
0543     .count = ARRAY_SIZE(pcm512x_dai_rates),
0544     .list  = pcm512x_dai_rates,
0545 };
0546 
0547 static int pcm512x_hw_rule_rate(struct snd_pcm_hw_params *params,
0548                 struct snd_pcm_hw_rule *rule)
0549 {
0550     struct pcm512x_priv *pcm512x = rule->private;
0551     struct snd_interval ranges[2];
0552     int frame_size;
0553 
0554     frame_size = snd_soc_params_to_frame_size(params);
0555     if (frame_size < 0)
0556         return frame_size;
0557 
0558     switch (frame_size) {
0559     case 32:
0560         /* No hole when the frame size is 32. */
0561         return 0;
0562     case 48:
0563     case 64:
0564         /* There is only one hole in the range of supported
0565          * rates, but it moves with the frame size.
0566          */
0567         memset(ranges, 0, sizeof(ranges));
0568         ranges[0].min = 8000;
0569         ranges[0].max = pcm512x_sck_max(pcm512x) / frame_size / 2;
0570         ranges[1].min = DIV_ROUND_UP(16000000, frame_size);
0571         ranges[1].max = 384000;
0572         break;
0573     default:
0574         return -EINVAL;
0575     }
0576 
0577     return snd_interval_ranges(hw_param_interval(params, rule->var),
0578                    ARRAY_SIZE(ranges), ranges, 0);
0579 }
0580 
0581 static int pcm512x_dai_startup_master(struct snd_pcm_substream *substream,
0582                       struct snd_soc_dai *dai)
0583 {
0584     struct snd_soc_component *component = dai->component;
0585     struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
0586     struct device *dev = dai->dev;
0587     struct snd_pcm_hw_constraint_ratnums *constraints_no_pll;
0588     struct snd_ratnum *rats_no_pll;
0589 
0590     if (IS_ERR(pcm512x->sclk)) {
0591         dev_err(dev, "Need SCLK for master mode: %ld\n",
0592             PTR_ERR(pcm512x->sclk));
0593         return PTR_ERR(pcm512x->sclk);
0594     }
0595 
0596     if (pcm512x->pll_out)
0597         return snd_pcm_hw_rule_add(substream->runtime, 0,
0598                        SNDRV_PCM_HW_PARAM_RATE,
0599                        pcm512x_hw_rule_rate,
0600                        pcm512x,
0601                        SNDRV_PCM_HW_PARAM_FRAME_BITS,
0602                        SNDRV_PCM_HW_PARAM_CHANNELS, -1);
0603 
0604     constraints_no_pll = devm_kzalloc(dev, sizeof(*constraints_no_pll),
0605                       GFP_KERNEL);
0606     if (!constraints_no_pll)
0607         return -ENOMEM;
0608     constraints_no_pll->nrats = 1;
0609     rats_no_pll = devm_kzalloc(dev, sizeof(*rats_no_pll), GFP_KERNEL);
0610     if (!rats_no_pll)
0611         return -ENOMEM;
0612     constraints_no_pll->rats = rats_no_pll;
0613     rats_no_pll->num = clk_get_rate(pcm512x->sclk) / 64;
0614     rats_no_pll->den_min = 1;
0615     rats_no_pll->den_max = 128;
0616     rats_no_pll->den_step = 1;
0617 
0618     return snd_pcm_hw_constraint_ratnums(substream->runtime, 0,
0619                          SNDRV_PCM_HW_PARAM_RATE,
0620                          constraints_no_pll);
0621 }
0622 
0623 static int pcm512x_dai_startup_slave(struct snd_pcm_substream *substream,
0624                      struct snd_soc_dai *dai)
0625 {
0626     struct snd_soc_component *component = dai->component;
0627     struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
0628     struct device *dev = dai->dev;
0629     struct regmap *regmap = pcm512x->regmap;
0630 
0631     if (IS_ERR(pcm512x->sclk)) {
0632         dev_info(dev, "No SCLK, using BCLK: %ld\n",
0633              PTR_ERR(pcm512x->sclk));
0634 
0635         /* Disable reporting of missing SCLK as an error */
0636         regmap_update_bits(regmap, PCM512x_ERROR_DETECT,
0637                    PCM512x_IDCH, PCM512x_IDCH);
0638 
0639         /* Switch PLL input to BCLK */
0640         regmap_update_bits(regmap, PCM512x_PLL_REF,
0641                    PCM512x_SREF, PCM512x_SREF_BCK);
0642     }
0643 
0644     return snd_pcm_hw_constraint_list(substream->runtime, 0,
0645                       SNDRV_PCM_HW_PARAM_RATE,
0646                       &constraints_slave);
0647 }
0648 
0649 static int pcm512x_dai_startup(struct snd_pcm_substream *substream,
0650                    struct snd_soc_dai *dai)
0651 {
0652     struct snd_soc_component *component = dai->component;
0653     struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
0654 
0655     switch (pcm512x->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0656     case SND_SOC_DAIFMT_CBP_CFP:
0657     case SND_SOC_DAIFMT_CBP_CFC:
0658         return pcm512x_dai_startup_master(substream, dai);
0659 
0660     case SND_SOC_DAIFMT_CBC_CFC:
0661         return pcm512x_dai_startup_slave(substream, dai);
0662 
0663     default:
0664         return -EINVAL;
0665     }
0666 }
0667 
0668 static int pcm512x_set_bias_level(struct snd_soc_component *component,
0669                   enum snd_soc_bias_level level)
0670 {
0671     struct pcm512x_priv *pcm512x = dev_get_drvdata(component->dev);
0672     int ret;
0673 
0674     switch (level) {
0675     case SND_SOC_BIAS_ON:
0676     case SND_SOC_BIAS_PREPARE:
0677         break;
0678 
0679     case SND_SOC_BIAS_STANDBY:
0680         ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
0681                      PCM512x_RQST, 0);
0682         if (ret != 0) {
0683             dev_err(component->dev, "Failed to remove standby: %d\n",
0684                 ret);
0685             return ret;
0686         }
0687         break;
0688 
0689     case SND_SOC_BIAS_OFF:
0690         ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
0691                      PCM512x_RQST, PCM512x_RQST);
0692         if (ret != 0) {
0693             dev_err(component->dev, "Failed to request standby: %d\n",
0694                 ret);
0695             return ret;
0696         }
0697         break;
0698     }
0699 
0700     return 0;
0701 }
0702 
0703 static unsigned long pcm512x_find_sck(struct snd_soc_dai *dai,
0704                       unsigned long bclk_rate)
0705 {
0706     struct device *dev = dai->dev;
0707     struct snd_soc_component *component = dai->component;
0708     struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
0709     unsigned long sck_rate;
0710     int pow2;
0711 
0712     /* 64 MHz <= pll_rate <= 100 MHz, VREF mode */
0713     /* 16 MHz <= sck_rate <=  25 MHz, VREF mode */
0714 
0715     /* select sck_rate as a multiple of bclk_rate but still with
0716      * as many factors of 2 as possible, as that makes it easier
0717      * to find a fast DAC rate
0718      */
0719     pow2 = 1 << fls((pcm512x_pll_max(pcm512x) - 16000000) / bclk_rate);
0720     for (; pow2; pow2 >>= 1) {
0721         sck_rate = rounddown(pcm512x_pll_max(pcm512x),
0722                      bclk_rate * pow2);
0723         if (sck_rate >= 16000000)
0724             break;
0725     }
0726     if (!pow2) {
0727         dev_err(dev, "Impossible to generate a suitable SCK\n");
0728         return 0;
0729     }
0730 
0731     dev_dbg(dev, "sck_rate %lu\n", sck_rate);
0732     return sck_rate;
0733 }
0734 
0735 /* pll_rate = pllin_rate * R * J.D / P
0736  * 1 <= R <= 16
0737  * 1 <= J <= 63
0738  * 0 <= D <= 9999
0739  * 1 <= P <= 15
0740  * 64 MHz <= pll_rate <= 100 MHz
0741  * if D == 0
0742  *     1 MHz <= pllin_rate / P <= 20 MHz
0743  * else if D > 0
0744  *     6.667 MHz <= pllin_rate / P <= 20 MHz
0745  *     4 <= J <= 11
0746  *     R = 1
0747  */
0748 static int pcm512x_find_pll_coeff(struct snd_soc_dai *dai,
0749                   unsigned long pllin_rate,
0750                   unsigned long pll_rate)
0751 {
0752     struct device *dev = dai->dev;
0753     struct snd_soc_component *component = dai->component;
0754     struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
0755     unsigned long common;
0756     int R, J, D, P;
0757     unsigned long K; /* 10000 * J.D */
0758     unsigned long num;
0759     unsigned long den;
0760 
0761     common = gcd(pll_rate, pllin_rate);
0762     dev_dbg(dev, "pll %lu pllin %lu common %lu\n",
0763         pll_rate, pllin_rate, common);
0764     num = pll_rate / common;
0765     den = pllin_rate / common;
0766 
0767     /* pllin_rate / P (or here, den) cannot be greater than 20 MHz */
0768     if (pllin_rate / den > 20000000 && num < 8) {
0769         num *= DIV_ROUND_UP(pllin_rate / den, 20000000);
0770         den *= DIV_ROUND_UP(pllin_rate / den, 20000000);
0771     }
0772     dev_dbg(dev, "num / den = %lu / %lu\n", num, den);
0773 
0774     P = den;
0775     if (den <= 15 && num <= 16 * 63
0776         && 1000000 <= pllin_rate / P && pllin_rate / P <= 20000000) {
0777         /* Try the case with D = 0 */
0778         D = 0;
0779         /* factor 'num' into J and R, such that R <= 16 and J <= 63 */
0780         for (R = 16; R; R--) {
0781             if (num % R)
0782                 continue;
0783             J = num / R;
0784             if (J == 0 || J > 63)
0785                 continue;
0786 
0787             dev_dbg(dev, "R * J / P = %d * %d / %d\n", R, J, P);
0788             pcm512x->real_pll = pll_rate;
0789             goto done;
0790         }
0791         /* no luck */
0792     }
0793 
0794     R = 1;
0795 
0796     if (num > 0xffffffffUL / 10000)
0797         goto fallback;
0798 
0799     /* Try to find an exact pll_rate using the D > 0 case */
0800     common = gcd(10000 * num, den);
0801     num = 10000 * num / common;
0802     den /= common;
0803     dev_dbg(dev, "num %lu den %lu common %lu\n", num, den, common);
0804 
0805     for (P = den; P <= 15; P++) {
0806         if (pllin_rate / P < 6667000 || 200000000 < pllin_rate / P)
0807             continue;
0808         if (num * P % den)
0809             continue;
0810         K = num * P / den;
0811         /* J == 12 is ok if D == 0 */
0812         if (K < 40000 || K > 120000)
0813             continue;
0814 
0815         J = K / 10000;
0816         D = K % 10000;
0817         dev_dbg(dev, "J.D / P = %d.%04d / %d\n", J, D, P);
0818         pcm512x->real_pll = pll_rate;
0819         goto done;
0820     }
0821 
0822     /* Fall back to an approximate pll_rate */
0823 
0824 fallback:
0825     /* find smallest possible P */
0826     P = DIV_ROUND_UP(pllin_rate, 20000000);
0827     if (!P)
0828         P = 1;
0829     else if (P > 15) {
0830         dev_err(dev, "Need a slower clock as pll-input\n");
0831         return -EINVAL;
0832     }
0833     if (pllin_rate / P < 6667000) {
0834         dev_err(dev, "Need a faster clock as pll-input\n");
0835         return -EINVAL;
0836     }
0837     K = DIV_ROUND_CLOSEST_ULL(10000ULL * pll_rate * P, pllin_rate);
0838     if (K < 40000)
0839         K = 40000;
0840     /* J == 12 is ok if D == 0 */
0841     if (K > 120000)
0842         K = 120000;
0843     J = K / 10000;
0844     D = K % 10000;
0845     dev_dbg(dev, "J.D / P ~ %d.%04d / %d\n", J, D, P);
0846     pcm512x->real_pll = DIV_ROUND_DOWN_ULL((u64)K * pllin_rate, 10000 * P);
0847 
0848 done:
0849     pcm512x->pll_r = R;
0850     pcm512x->pll_j = J;
0851     pcm512x->pll_d = D;
0852     pcm512x->pll_p = P;
0853     return 0;
0854 }
0855 
0856 static unsigned long pcm512x_pllin_dac_rate(struct snd_soc_dai *dai,
0857                         unsigned long osr_rate,
0858                         unsigned long pllin_rate)
0859 {
0860     struct snd_soc_component *component = dai->component;
0861     struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
0862     unsigned long dac_rate;
0863 
0864     if (!pcm512x->pll_out)
0865         return 0; /* no PLL to bypass, force SCK as DAC input */
0866 
0867     if (pllin_rate % osr_rate)
0868         return 0; /* futile, quit early */
0869 
0870     /* run DAC no faster than 6144000 Hz */
0871     for (dac_rate = rounddown(pcm512x_dac_max(pcm512x, 6144000), osr_rate);
0872          dac_rate;
0873          dac_rate -= osr_rate) {
0874 
0875         if (pllin_rate / dac_rate > 128)
0876             return 0; /* DAC divider would be too big */
0877 
0878         if (!(pllin_rate % dac_rate))
0879             return dac_rate;
0880 
0881         dac_rate -= osr_rate;
0882     }
0883 
0884     return 0;
0885 }
0886 
0887 static int pcm512x_set_dividers(struct snd_soc_dai *dai,
0888                 struct snd_pcm_hw_params *params)
0889 {
0890     struct device *dev = dai->dev;
0891     struct snd_soc_component *component = dai->component;
0892     struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
0893     unsigned long pllin_rate = 0;
0894     unsigned long pll_rate;
0895     unsigned long sck_rate;
0896     unsigned long mck_rate;
0897     unsigned long bclk_rate;
0898     unsigned long sample_rate;
0899     unsigned long osr_rate;
0900     unsigned long dacsrc_rate;
0901     int bclk_div;
0902     int lrclk_div;
0903     int dsp_div;
0904     int dac_div;
0905     unsigned long dac_rate;
0906     int ncp_div;
0907     int osr_div;
0908     int ret;
0909     int idac;
0910     int fssp;
0911     int gpio;
0912 
0913     if (pcm512x->bclk_ratio > 0) {
0914         lrclk_div = pcm512x->bclk_ratio;
0915     } else {
0916         lrclk_div = snd_soc_params_to_frame_size(params);
0917 
0918         if (lrclk_div == 0) {
0919             dev_err(dev, "No LRCLK?\n");
0920             return -EINVAL;
0921         }
0922     }
0923 
0924     if (!pcm512x->pll_out) {
0925         sck_rate = clk_get_rate(pcm512x->sclk);
0926         bclk_rate = params_rate(params) * lrclk_div;
0927         bclk_div = DIV_ROUND_CLOSEST(sck_rate, bclk_rate);
0928 
0929         mck_rate = sck_rate;
0930     } else {
0931         ret = snd_soc_params_to_bclk(params);
0932         if (ret < 0) {
0933             dev_err(dev, "Failed to find suitable BCLK: %d\n", ret);
0934             return ret;
0935         }
0936         if (ret == 0) {
0937             dev_err(dev, "No BCLK?\n");
0938             return -EINVAL;
0939         }
0940         bclk_rate = ret;
0941 
0942         pllin_rate = clk_get_rate(pcm512x->sclk);
0943 
0944         sck_rate = pcm512x_find_sck(dai, bclk_rate);
0945         if (!sck_rate)
0946             return -EINVAL;
0947         pll_rate = 4 * sck_rate;
0948 
0949         ret = pcm512x_find_pll_coeff(dai, pllin_rate, pll_rate);
0950         if (ret != 0)
0951             return ret;
0952 
0953         ret = regmap_write(pcm512x->regmap,
0954                    PCM512x_PLL_COEFF_0, pcm512x->pll_p - 1);
0955         if (ret != 0) {
0956             dev_err(dev, "Failed to write PLL P: %d\n", ret);
0957             return ret;
0958         }
0959 
0960         ret = regmap_write(pcm512x->regmap,
0961                    PCM512x_PLL_COEFF_1, pcm512x->pll_j);
0962         if (ret != 0) {
0963             dev_err(dev, "Failed to write PLL J: %d\n", ret);
0964             return ret;
0965         }
0966 
0967         ret = regmap_write(pcm512x->regmap,
0968                    PCM512x_PLL_COEFF_2, pcm512x->pll_d >> 8);
0969         if (ret != 0) {
0970             dev_err(dev, "Failed to write PLL D msb: %d\n", ret);
0971             return ret;
0972         }
0973 
0974         ret = regmap_write(pcm512x->regmap,
0975                    PCM512x_PLL_COEFF_3, pcm512x->pll_d & 0xff);
0976         if (ret != 0) {
0977             dev_err(dev, "Failed to write PLL D lsb: %d\n", ret);
0978             return ret;
0979         }
0980 
0981         ret = regmap_write(pcm512x->regmap,
0982                    PCM512x_PLL_COEFF_4, pcm512x->pll_r - 1);
0983         if (ret != 0) {
0984             dev_err(dev, "Failed to write PLL R: %d\n", ret);
0985             return ret;
0986         }
0987 
0988         mck_rate = pcm512x->real_pll;
0989 
0990         bclk_div = DIV_ROUND_CLOSEST(sck_rate, bclk_rate);
0991     }
0992 
0993     if (bclk_div > 128) {
0994         dev_err(dev, "Failed to find BCLK divider\n");
0995         return -EINVAL;
0996     }
0997 
0998     /* the actual rate */
0999     sample_rate = sck_rate / bclk_div / lrclk_div;
1000     osr_rate = 16 * sample_rate;
1001 
1002     /* run DSP no faster than 50 MHz */
1003     dsp_div = mck_rate > pcm512x_dsp_max(pcm512x) ? 2 : 1;
1004 
1005     dac_rate = pcm512x_pllin_dac_rate(dai, osr_rate, pllin_rate);
1006     if (dac_rate) {
1007         /* the desired clock rate is "compatible" with the pll input
1008          * clock, so use that clock as dac input instead of the pll
1009          * output clock since the pll will introduce jitter and thus
1010          * noise.
1011          */
1012         dev_dbg(dev, "using pll input as dac input\n");
1013         ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF,
1014                      PCM512x_SDAC, PCM512x_SDAC_GPIO);
1015         if (ret != 0) {
1016             dev_err(component->dev,
1017                 "Failed to set gpio as dacref: %d\n", ret);
1018             return ret;
1019         }
1020 
1021         gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1;
1022         ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_DACIN,
1023                      PCM512x_GREF, gpio);
1024         if (ret != 0) {
1025             dev_err(component->dev,
1026                 "Failed to set gpio %d as dacin: %d\n",
1027                 pcm512x->pll_in, ret);
1028             return ret;
1029         }
1030 
1031         dacsrc_rate = pllin_rate;
1032     } else {
1033         /* run DAC no faster than 6144000 Hz */
1034         unsigned long dac_mul = pcm512x_dac_max(pcm512x, 6144000)
1035             / osr_rate;
1036         unsigned long sck_mul = sck_rate / osr_rate;
1037 
1038         for (; dac_mul; dac_mul--) {
1039             if (!(sck_mul % dac_mul))
1040                 break;
1041         }
1042         if (!dac_mul) {
1043             dev_err(dev, "Failed to find DAC rate\n");
1044             return -EINVAL;
1045         }
1046 
1047         dac_rate = dac_mul * osr_rate;
1048         dev_dbg(dev, "dac_rate %lu sample_rate %lu\n",
1049             dac_rate, sample_rate);
1050 
1051         ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF,
1052                      PCM512x_SDAC, PCM512x_SDAC_SCK);
1053         if (ret != 0) {
1054             dev_err(component->dev,
1055                 "Failed to set sck as dacref: %d\n", ret);
1056             return ret;
1057         }
1058 
1059         dacsrc_rate = sck_rate;
1060     }
1061 
1062     osr_div = DIV_ROUND_CLOSEST(dac_rate, osr_rate);
1063     if (osr_div > 128) {
1064         dev_err(dev, "Failed to find OSR divider\n");
1065         return -EINVAL;
1066     }
1067 
1068     dac_div = DIV_ROUND_CLOSEST(dacsrc_rate, dac_rate);
1069     if (dac_div > 128) {
1070         dev_err(dev, "Failed to find DAC divider\n");
1071         return -EINVAL;
1072     }
1073     dac_rate = dacsrc_rate / dac_div;
1074 
1075     ncp_div = DIV_ROUND_CLOSEST(dac_rate,
1076                     pcm512x_ncp_target(pcm512x, dac_rate));
1077     if (ncp_div > 128 || dac_rate / ncp_div > 2048000) {
1078         /* run NCP no faster than 2048000 Hz, but why? */
1079         ncp_div = DIV_ROUND_UP(dac_rate, 2048000);
1080         if (ncp_div > 128) {
1081             dev_err(dev, "Failed to find NCP divider\n");
1082             return -EINVAL;
1083         }
1084     }
1085 
1086     idac = mck_rate / (dsp_div * sample_rate);
1087 
1088     ret = regmap_write(pcm512x->regmap, PCM512x_DSP_CLKDIV, dsp_div - 1);
1089     if (ret != 0) {
1090         dev_err(dev, "Failed to write DSP divider: %d\n", ret);
1091         return ret;
1092     }
1093 
1094     ret = regmap_write(pcm512x->regmap, PCM512x_DAC_CLKDIV, dac_div - 1);
1095     if (ret != 0) {
1096         dev_err(dev, "Failed to write DAC divider: %d\n", ret);
1097         return ret;
1098     }
1099 
1100     ret = regmap_write(pcm512x->regmap, PCM512x_NCP_CLKDIV, ncp_div - 1);
1101     if (ret != 0) {
1102         dev_err(dev, "Failed to write NCP divider: %d\n", ret);
1103         return ret;
1104     }
1105 
1106     ret = regmap_write(pcm512x->regmap, PCM512x_OSR_CLKDIV, osr_div - 1);
1107     if (ret != 0) {
1108         dev_err(dev, "Failed to write OSR divider: %d\n", ret);
1109         return ret;
1110     }
1111 
1112     ret = regmap_write(pcm512x->regmap,
1113                PCM512x_MASTER_CLKDIV_1, bclk_div - 1);
1114     if (ret != 0) {
1115         dev_err(dev, "Failed to write BCLK divider: %d\n", ret);
1116         return ret;
1117     }
1118 
1119     ret = regmap_write(pcm512x->regmap,
1120                PCM512x_MASTER_CLKDIV_2, lrclk_div - 1);
1121     if (ret != 0) {
1122         dev_err(dev, "Failed to write LRCLK divider: %d\n", ret);
1123         return ret;
1124     }
1125 
1126     ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_1, idac >> 8);
1127     if (ret != 0) {
1128         dev_err(dev, "Failed to write IDAC msb divider: %d\n", ret);
1129         return ret;
1130     }
1131 
1132     ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_2, idac & 0xff);
1133     if (ret != 0) {
1134         dev_err(dev, "Failed to write IDAC lsb divider: %d\n", ret);
1135         return ret;
1136     }
1137 
1138     if (sample_rate <= pcm512x_dac_max(pcm512x, 48000))
1139         fssp = PCM512x_FSSP_48KHZ;
1140     else if (sample_rate <= pcm512x_dac_max(pcm512x, 96000))
1141         fssp = PCM512x_FSSP_96KHZ;
1142     else if (sample_rate <= pcm512x_dac_max(pcm512x, 192000))
1143         fssp = PCM512x_FSSP_192KHZ;
1144     else
1145         fssp = PCM512x_FSSP_384KHZ;
1146     ret = regmap_update_bits(pcm512x->regmap, PCM512x_FS_SPEED_MODE,
1147                  PCM512x_FSSP, fssp);
1148     if (ret != 0) {
1149         dev_err(component->dev, "Failed to set fs speed: %d\n", ret);
1150         return ret;
1151     }
1152 
1153     dev_dbg(component->dev, "DSP divider %d\n", dsp_div);
1154     dev_dbg(component->dev, "DAC divider %d\n", dac_div);
1155     dev_dbg(component->dev, "NCP divider %d\n", ncp_div);
1156     dev_dbg(component->dev, "OSR divider %d\n", osr_div);
1157     dev_dbg(component->dev, "BCK divider %d\n", bclk_div);
1158     dev_dbg(component->dev, "LRCK divider %d\n", lrclk_div);
1159     dev_dbg(component->dev, "IDAC %d\n", idac);
1160     dev_dbg(component->dev, "1<<FSSP %d\n", 1 << fssp);
1161 
1162     return 0;
1163 }
1164 
1165 static int pcm512x_hw_params(struct snd_pcm_substream *substream,
1166                  struct snd_pcm_hw_params *params,
1167                  struct snd_soc_dai *dai)
1168 {
1169     struct snd_soc_component *component = dai->component;
1170     struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
1171     int alen;
1172     int gpio;
1173     int ret;
1174 
1175     dev_dbg(component->dev, "hw_params %u Hz, %u channels\n",
1176         params_rate(params),
1177         params_channels(params));
1178 
1179     switch (params_width(params)) {
1180     case 16:
1181         alen = PCM512x_ALEN_16;
1182         break;
1183     case 20:
1184         alen = PCM512x_ALEN_20;
1185         break;
1186     case 24:
1187         alen = PCM512x_ALEN_24;
1188         break;
1189     case 32:
1190         alen = PCM512x_ALEN_32;
1191         break;
1192     default:
1193         dev_err(component->dev, "Bad frame size: %d\n",
1194             params_width(params));
1195         return -EINVAL;
1196     }
1197 
1198     ret = regmap_update_bits(pcm512x->regmap, PCM512x_I2S_1,
1199                  PCM512x_ALEN, alen);
1200     if (ret != 0) {
1201         dev_err(component->dev, "Failed to set frame size: %d\n", ret);
1202         return ret;
1203     }
1204 
1205     if ((pcm512x->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) ==
1206         SND_SOC_DAIFMT_CBC_CFC) {
1207         ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT,
1208                      PCM512x_DCAS, 0);
1209         if (ret != 0) {
1210             dev_err(component->dev,
1211                 "Failed to enable clock divider autoset: %d\n",
1212                 ret);
1213             return ret;
1214         }
1215         goto skip_pll;
1216     }
1217 
1218     if (pcm512x->pll_out) {
1219         ret = regmap_write(pcm512x->regmap, PCM512x_FLEX_A, 0x11);
1220         if (ret != 0) {
1221             dev_err(component->dev, "Failed to set FLEX_A: %d\n", ret);
1222             return ret;
1223         }
1224 
1225         ret = regmap_write(pcm512x->regmap, PCM512x_FLEX_B, 0xff);
1226         if (ret != 0) {
1227             dev_err(component->dev, "Failed to set FLEX_B: %d\n", ret);
1228             return ret;
1229         }
1230 
1231         ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT,
1232                      PCM512x_IDFS | PCM512x_IDBK
1233                      | PCM512x_IDSK | PCM512x_IDCH
1234                      | PCM512x_IDCM | PCM512x_DCAS
1235                      | PCM512x_IPLK,
1236                      PCM512x_IDFS | PCM512x_IDBK
1237                      | PCM512x_IDSK | PCM512x_IDCH
1238                      | PCM512x_DCAS);
1239         if (ret != 0) {
1240             dev_err(component->dev,
1241                 "Failed to ignore auto-clock failures: %d\n",
1242                 ret);
1243             return ret;
1244         }
1245     } else {
1246         ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT,
1247                      PCM512x_IDFS | PCM512x_IDBK
1248                      | PCM512x_IDSK | PCM512x_IDCH
1249                      | PCM512x_IDCM | PCM512x_DCAS
1250                      | PCM512x_IPLK,
1251                      PCM512x_IDFS | PCM512x_IDBK
1252                      | PCM512x_IDSK | PCM512x_IDCH
1253                      | PCM512x_DCAS | PCM512x_IPLK);
1254         if (ret != 0) {
1255             dev_err(component->dev,
1256                 "Failed to ignore auto-clock failures: %d\n",
1257                 ret);
1258             return ret;
1259         }
1260 
1261         ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_EN,
1262                      PCM512x_PLLE, 0);
1263         if (ret != 0) {
1264             dev_err(component->dev, "Failed to disable pll: %d\n", ret);
1265             return ret;
1266         }
1267     }
1268 
1269     ret = pcm512x_set_dividers(dai, params);
1270     if (ret != 0)
1271         return ret;
1272 
1273     if (pcm512x->pll_out) {
1274         ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_REF,
1275                      PCM512x_SREF, PCM512x_SREF_GPIO);
1276         if (ret != 0) {
1277             dev_err(component->dev,
1278                 "Failed to set gpio as pllref: %d\n", ret);
1279             return ret;
1280         }
1281 
1282         gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1;
1283         ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_PLLIN,
1284                      PCM512x_GREF, gpio);
1285         if (ret != 0) {
1286             dev_err(component->dev,
1287                 "Failed to set gpio %d as pllin: %d\n",
1288                 pcm512x->pll_in, ret);
1289             return ret;
1290         }
1291 
1292         ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_EN,
1293                      PCM512x_PLLE, PCM512x_PLLE);
1294         if (ret != 0) {
1295             dev_err(component->dev, "Failed to enable pll: %d\n", ret);
1296             return ret;
1297         }
1298 
1299         gpio = PCM512x_G1OE << (pcm512x->pll_out - 1);
1300         ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_EN,
1301                      gpio, gpio);
1302         if (ret != 0) {
1303             dev_err(component->dev, "Failed to enable gpio %d: %d\n",
1304                 pcm512x->pll_out, ret);
1305             return ret;
1306         }
1307 
1308         gpio = PCM512x_GPIO_OUTPUT_1 + pcm512x->pll_out - 1;
1309         ret = regmap_update_bits(pcm512x->regmap, gpio,
1310                      PCM512x_GxSL, PCM512x_GxSL_PLLCK);
1311         if (ret != 0) {
1312             dev_err(component->dev, "Failed to output pll on %d: %d\n",
1313                 ret, pcm512x->pll_out);
1314             return ret;
1315         }
1316     }
1317 
1318     ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE,
1319                  PCM512x_RQSY, PCM512x_RQSY_HALT);
1320     if (ret != 0) {
1321         dev_err(component->dev, "Failed to halt clocks: %d\n", ret);
1322         return ret;
1323     }
1324 
1325     ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE,
1326                  PCM512x_RQSY, PCM512x_RQSY_RESUME);
1327     if (ret != 0) {
1328         dev_err(component->dev, "Failed to resume clocks: %d\n", ret);
1329         return ret;
1330     }
1331 
1332 skip_pll:
1333     return 0;
1334 }
1335 
1336 static int pcm512x_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1337 {
1338     struct snd_soc_component *component = dai->component;
1339     struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
1340     int afmt;
1341     int offset = 0;
1342     int clock_output;
1343     int provider_mode;
1344     int ret;
1345 
1346     switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
1347     case SND_SOC_DAIFMT_CBC_CFC:
1348         clock_output = 0;
1349         provider_mode = 0;
1350         break;
1351     case SND_SOC_DAIFMT_CBP_CFP:
1352         clock_output = PCM512x_BCKO | PCM512x_LRKO;
1353         provider_mode = PCM512x_RLRK | PCM512x_RBCK;
1354         break;
1355     case SND_SOC_DAIFMT_CBP_CFC:
1356         clock_output = PCM512x_BCKO;
1357         provider_mode = PCM512x_RBCK;
1358         break;
1359     default:
1360         return -EINVAL;
1361     }
1362 
1363     ret = regmap_update_bits(pcm512x->regmap, PCM512x_BCLK_LRCLK_CFG,
1364                  PCM512x_BCKP | PCM512x_BCKO | PCM512x_LRKO,
1365                  clock_output);
1366     if (ret != 0) {
1367         dev_err(component->dev, "Failed to enable clock output: %d\n", ret);
1368         return ret;
1369     }
1370 
1371     ret = regmap_update_bits(pcm512x->regmap, PCM512x_MASTER_MODE,
1372                  PCM512x_RLRK | PCM512x_RBCK,
1373                  provider_mode);
1374     if (ret != 0) {
1375         dev_err(component->dev, "Failed to enable provider mode: %d\n", ret);
1376         return ret;
1377     }
1378 
1379     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1380     case SND_SOC_DAIFMT_I2S:
1381         afmt = PCM512x_AFMT_I2S;
1382         break;
1383     case SND_SOC_DAIFMT_RIGHT_J:
1384         afmt = PCM512x_AFMT_RTJ;
1385         break;
1386     case SND_SOC_DAIFMT_LEFT_J:
1387         afmt = PCM512x_AFMT_LTJ;
1388         break;
1389     case SND_SOC_DAIFMT_DSP_A:
1390         offset = 1;
1391         fallthrough;
1392     case SND_SOC_DAIFMT_DSP_B:
1393         afmt = PCM512x_AFMT_DSP;
1394         break;
1395     default:
1396         dev_err(component->dev, "unsupported DAI format: 0x%x\n",
1397             pcm512x->fmt);
1398         return -EINVAL;
1399     }
1400 
1401     ret = regmap_update_bits(pcm512x->regmap, PCM512x_I2S_1,
1402                  PCM512x_AFMT, afmt);
1403     if (ret != 0) {
1404         dev_err(component->dev, "Failed to set data format: %d\n", ret);
1405         return ret;
1406     }
1407 
1408     ret = regmap_update_bits(pcm512x->regmap, PCM512x_I2S_2,
1409                  0xFF, offset);
1410     if (ret != 0) {
1411         dev_err(component->dev, "Failed to set data offset: %d\n", ret);
1412         return ret;
1413     }
1414 
1415     pcm512x->fmt = fmt;
1416 
1417     return 0;
1418 }
1419 
1420 static int pcm512x_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
1421 {
1422     struct snd_soc_component *component = dai->component;
1423     struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
1424 
1425     if (ratio > 256)
1426         return -EINVAL;
1427 
1428     pcm512x->bclk_ratio = ratio;
1429 
1430     return 0;
1431 }
1432 
1433 static int pcm512x_mute(struct snd_soc_dai *dai, int mute, int direction)
1434 {
1435     struct snd_soc_component *component = dai->component;
1436     struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
1437     int ret;
1438     unsigned int mute_det;
1439 
1440     mutex_lock(&pcm512x->mutex);
1441 
1442     if (mute) {
1443         pcm512x->mute |= 0x1;
1444         ret = regmap_update_bits(pcm512x->regmap, PCM512x_MUTE,
1445                      PCM512x_RQML | PCM512x_RQMR,
1446                      PCM512x_RQML | PCM512x_RQMR);
1447         if (ret != 0) {
1448             dev_err(component->dev,
1449                 "Failed to set digital mute: %d\n", ret);
1450             goto unlock;
1451         }
1452 
1453         regmap_read_poll_timeout(pcm512x->regmap,
1454                      PCM512x_ANALOG_MUTE_DET,
1455                      mute_det, (mute_det & 0x3) == 0,
1456                      200, 10000);
1457     } else {
1458         pcm512x->mute &= ~0x1;
1459         ret = pcm512x_update_mute(pcm512x);
1460         if (ret != 0) {
1461             dev_err(component->dev,
1462                 "Failed to update digital mute: %d\n", ret);
1463             goto unlock;
1464         }
1465 
1466         regmap_read_poll_timeout(pcm512x->regmap,
1467                      PCM512x_ANALOG_MUTE_DET,
1468                      mute_det,
1469                      (mute_det & 0x3)
1470                      == ((~pcm512x->mute >> 1) & 0x3),
1471                      200, 10000);
1472     }
1473 
1474 unlock:
1475     mutex_unlock(&pcm512x->mutex);
1476 
1477     return ret;
1478 }
1479 
1480 static const struct snd_soc_dai_ops pcm512x_dai_ops = {
1481     .startup = pcm512x_dai_startup,
1482     .hw_params = pcm512x_hw_params,
1483     .set_fmt = pcm512x_set_fmt,
1484     .mute_stream = pcm512x_mute,
1485     .set_bclk_ratio = pcm512x_set_bclk_ratio,
1486     .no_capture_mute = 1,
1487 };
1488 
1489 static struct snd_soc_dai_driver pcm512x_dai = {
1490     .name = "pcm512x-hifi",
1491     .playback = {
1492         .stream_name = "Playback",
1493         .channels_min = 2,
1494         .channels_max = 2,
1495         .rates = SNDRV_PCM_RATE_CONTINUOUS,
1496         .rate_min = 8000,
1497         .rate_max = 384000,
1498         .formats = SNDRV_PCM_FMTBIT_S16_LE |
1499                SNDRV_PCM_FMTBIT_S24_LE |
1500                SNDRV_PCM_FMTBIT_S32_LE
1501     },
1502     .ops = &pcm512x_dai_ops,
1503 };
1504 
1505 static const struct snd_soc_component_driver pcm512x_component_driver = {
1506     .set_bias_level     = pcm512x_set_bias_level,
1507     .controls       = pcm512x_controls,
1508     .num_controls       = ARRAY_SIZE(pcm512x_controls),
1509     .dapm_widgets       = pcm512x_dapm_widgets,
1510     .num_dapm_widgets   = ARRAY_SIZE(pcm512x_dapm_widgets),
1511     .dapm_routes        = pcm512x_dapm_routes,
1512     .num_dapm_routes    = ARRAY_SIZE(pcm512x_dapm_routes),
1513     .use_pmdown_time    = 1,
1514     .endianness     = 1,
1515 };
1516 
1517 static const struct regmap_range_cfg pcm512x_range = {
1518     .name = "Pages", .range_min = PCM512x_VIRT_BASE,
1519     .range_max = PCM512x_MAX_REGISTER,
1520     .selector_reg = PCM512x_PAGE,
1521     .selector_mask = 0xff,
1522     .window_start = 0, .window_len = 0x100,
1523 };
1524 
1525 const struct regmap_config pcm512x_regmap = {
1526     .reg_bits = 8,
1527     .val_bits = 8,
1528 
1529     .readable_reg = pcm512x_readable,
1530     .volatile_reg = pcm512x_volatile,
1531 
1532     .ranges = &pcm512x_range,
1533     .num_ranges = 1,
1534 
1535     .max_register = PCM512x_MAX_REGISTER,
1536     .reg_defaults = pcm512x_reg_defaults,
1537     .num_reg_defaults = ARRAY_SIZE(pcm512x_reg_defaults),
1538     .cache_type = REGCACHE_RBTREE,
1539 };
1540 EXPORT_SYMBOL_GPL(pcm512x_regmap);
1541 
1542 int pcm512x_probe(struct device *dev, struct regmap *regmap)
1543 {
1544     struct pcm512x_priv *pcm512x;
1545     int i, ret;
1546 
1547     pcm512x = devm_kzalloc(dev, sizeof(struct pcm512x_priv), GFP_KERNEL);
1548     if (!pcm512x)
1549         return -ENOMEM;
1550 
1551     mutex_init(&pcm512x->mutex);
1552 
1553     dev_set_drvdata(dev, pcm512x);
1554     pcm512x->regmap = regmap;
1555 
1556     for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++)
1557         pcm512x->supplies[i].supply = pcm512x_supply_names[i];
1558 
1559     ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pcm512x->supplies),
1560                       pcm512x->supplies);
1561     if (ret != 0) {
1562         dev_err(dev, "Failed to get supplies: %d\n", ret);
1563         return ret;
1564     }
1565 
1566     pcm512x->supply_nb[0].notifier_call = pcm512x_regulator_event_0;
1567     pcm512x->supply_nb[1].notifier_call = pcm512x_regulator_event_1;
1568     pcm512x->supply_nb[2].notifier_call = pcm512x_regulator_event_2;
1569 
1570     for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++) {
1571         ret = devm_regulator_register_notifier(
1572                         pcm512x->supplies[i].consumer,
1573                         &pcm512x->supply_nb[i]);
1574         if (ret != 0) {
1575             dev_err(dev,
1576                 "Failed to register regulator notifier: %d\n",
1577                 ret);
1578         }
1579     }
1580 
1581     ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies),
1582                     pcm512x->supplies);
1583     if (ret != 0) {
1584         dev_err(dev, "Failed to enable supplies: %d\n", ret);
1585         return ret;
1586     }
1587 
1588     /* Reset the device, verifying I/O in the process for I2C */
1589     ret = regmap_write(regmap, PCM512x_RESET,
1590                PCM512x_RSTM | PCM512x_RSTR);
1591     if (ret != 0) {
1592         dev_err(dev, "Failed to reset device: %d\n", ret);
1593         goto err;
1594     }
1595 
1596     ret = regmap_write(regmap, PCM512x_RESET, 0);
1597     if (ret != 0) {
1598         dev_err(dev, "Failed to reset device: %d\n", ret);
1599         goto err;
1600     }
1601 
1602     pcm512x->sclk = devm_clk_get(dev, NULL);
1603     if (PTR_ERR(pcm512x->sclk) == -EPROBE_DEFER) {
1604         ret = -EPROBE_DEFER;
1605         goto err;
1606     }
1607     if (!IS_ERR(pcm512x->sclk)) {
1608         ret = clk_prepare_enable(pcm512x->sclk);
1609         if (ret != 0) {
1610             dev_err(dev, "Failed to enable SCLK: %d\n", ret);
1611             goto err;
1612         }
1613     }
1614 
1615     /* Default to standby mode */
1616     ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
1617                  PCM512x_RQST, PCM512x_RQST);
1618     if (ret != 0) {
1619         dev_err(dev, "Failed to request standby: %d\n",
1620             ret);
1621         goto err_clk;
1622     }
1623 
1624     pm_runtime_set_active(dev);
1625     pm_runtime_enable(dev);
1626     pm_runtime_idle(dev);
1627 
1628 #ifdef CONFIG_OF
1629     if (dev->of_node) {
1630         const struct device_node *np = dev->of_node;
1631         u32 val;
1632 
1633         if (of_property_read_u32(np, "pll-in", &val) >= 0) {
1634             if (val > 6) {
1635                 dev_err(dev, "Invalid pll-in\n");
1636                 ret = -EINVAL;
1637                 goto err_clk;
1638             }
1639             pcm512x->pll_in = val;
1640         }
1641 
1642         if (of_property_read_u32(np, "pll-out", &val) >= 0) {
1643             if (val > 6) {
1644                 dev_err(dev, "Invalid pll-out\n");
1645                 ret = -EINVAL;
1646                 goto err_clk;
1647             }
1648             pcm512x->pll_out = val;
1649         }
1650 
1651         if (!pcm512x->pll_in != !pcm512x->pll_out) {
1652             dev_err(dev,
1653                 "Error: both pll-in and pll-out, or none\n");
1654             ret = -EINVAL;
1655             goto err_clk;
1656         }
1657         if (pcm512x->pll_in && pcm512x->pll_in == pcm512x->pll_out) {
1658             dev_err(dev, "Error: pll-in == pll-out\n");
1659             ret = -EINVAL;
1660             goto err_clk;
1661         }
1662     }
1663 #endif
1664 
1665     ret = devm_snd_soc_register_component(dev, &pcm512x_component_driver,
1666                     &pcm512x_dai, 1);
1667     if (ret != 0) {
1668         dev_err(dev, "Failed to register CODEC: %d\n", ret);
1669         goto err_pm;
1670     }
1671 
1672     return 0;
1673 
1674 err_pm:
1675     pm_runtime_disable(dev);
1676 err_clk:
1677     if (!IS_ERR(pcm512x->sclk))
1678         clk_disable_unprepare(pcm512x->sclk);
1679 err:
1680     regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies),
1681                      pcm512x->supplies);
1682     return ret;
1683 }
1684 EXPORT_SYMBOL_GPL(pcm512x_probe);
1685 
1686 void pcm512x_remove(struct device *dev)
1687 {
1688     struct pcm512x_priv *pcm512x = dev_get_drvdata(dev);
1689 
1690     pm_runtime_disable(dev);
1691     if (!IS_ERR(pcm512x->sclk))
1692         clk_disable_unprepare(pcm512x->sclk);
1693     regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies),
1694                    pcm512x->supplies);
1695 }
1696 EXPORT_SYMBOL_GPL(pcm512x_remove);
1697 
1698 #ifdef CONFIG_PM
1699 static int pcm512x_suspend(struct device *dev)
1700 {
1701     struct pcm512x_priv *pcm512x = dev_get_drvdata(dev);
1702     int ret;
1703 
1704     ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
1705                  PCM512x_RQPD, PCM512x_RQPD);
1706     if (ret != 0) {
1707         dev_err(dev, "Failed to request power down: %d\n", ret);
1708         return ret;
1709     }
1710 
1711     ret = regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies),
1712                      pcm512x->supplies);
1713     if (ret != 0) {
1714         dev_err(dev, "Failed to disable supplies: %d\n", ret);
1715         return ret;
1716     }
1717 
1718     if (!IS_ERR(pcm512x->sclk))
1719         clk_disable_unprepare(pcm512x->sclk);
1720 
1721     return 0;
1722 }
1723 
1724 static int pcm512x_resume(struct device *dev)
1725 {
1726     struct pcm512x_priv *pcm512x = dev_get_drvdata(dev);
1727     int ret;
1728 
1729     if (!IS_ERR(pcm512x->sclk)) {
1730         ret = clk_prepare_enable(pcm512x->sclk);
1731         if (ret != 0) {
1732             dev_err(dev, "Failed to enable SCLK: %d\n", ret);
1733             return ret;
1734         }
1735     }
1736 
1737     ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies),
1738                     pcm512x->supplies);
1739     if (ret != 0) {
1740         dev_err(dev, "Failed to enable supplies: %d\n", ret);
1741         return ret;
1742     }
1743 
1744     regcache_cache_only(pcm512x->regmap, false);
1745     ret = regcache_sync(pcm512x->regmap);
1746     if (ret != 0) {
1747         dev_err(dev, "Failed to sync cache: %d\n", ret);
1748         return ret;
1749     }
1750 
1751     ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
1752                  PCM512x_RQPD, 0);
1753     if (ret != 0) {
1754         dev_err(dev, "Failed to remove power down: %d\n", ret);
1755         return ret;
1756     }
1757 
1758     return 0;
1759 }
1760 #endif
1761 
1762 const struct dev_pm_ops pcm512x_pm_ops = {
1763     SET_RUNTIME_PM_OPS(pcm512x_suspend, pcm512x_resume, NULL)
1764 };
1765 EXPORT_SYMBOL_GPL(pcm512x_pm_ops);
1766 
1767 MODULE_DESCRIPTION("ASoC PCM512x codec driver");
1768 MODULE_AUTHOR("Mark Brown <broonie@kernel.org>");
1769 MODULE_LICENSE("GPL v2");
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