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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * PCM3168A codec driver
0004  *
0005  * Copyright (C) 2015 Imagination Technologies Ltd.
0006  *
0007  * Author: Damien Horsley <Damien.Horsley@imgtec.com>
0008  */
0009 
0010 #include <linux/clk.h>
0011 #include <linux/delay.h>
0012 #include <linux/gpio/consumer.h>
0013 #include <linux/module.h>
0014 #include <linux/of_gpio.h>
0015 #include <linux/pm_runtime.h>
0016 #include <linux/regulator/consumer.h>
0017 
0018 #include <sound/pcm_params.h>
0019 #include <sound/soc.h>
0020 #include <sound/tlv.h>
0021 
0022 #include "pcm3168a.h"
0023 
0024 #define PCM3168A_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
0025              SNDRV_PCM_FMTBIT_S24_3LE | \
0026              SNDRV_PCM_FMTBIT_S24_LE)
0027 
0028 #define PCM3168A_FMT_I2S        0x0
0029 #define PCM3168A_FMT_LEFT_J     0x1
0030 #define PCM3168A_FMT_RIGHT_J        0x2
0031 #define PCM3168A_FMT_RIGHT_J_16     0x3
0032 #define PCM3168A_FMT_DSP_A      0x4
0033 #define PCM3168A_FMT_DSP_B      0x5
0034 #define PCM3168A_FMT_I2S_TDM        0x6
0035 #define PCM3168A_FMT_LEFT_J_TDM     0x7
0036 
0037 static const char *const pcm3168a_supply_names[] = {
0038     "VDD1",
0039     "VDD2",
0040     "VCCAD1",
0041     "VCCAD2",
0042     "VCCDA1",
0043     "VCCDA2"
0044 };
0045 
0046 #define PCM3168A_DAI_DAC        0
0047 #define PCM3168A_DAI_ADC        1
0048 
0049 /* ADC/DAC side parameters */
0050 struct pcm3168a_io_params {
0051     bool provider_mode;
0052     unsigned int format;
0053     int tdm_slots;
0054     u32 tdm_mask;
0055     int slot_width;
0056 };
0057 
0058 struct pcm3168a_priv {
0059     struct regulator_bulk_data supplies[ARRAY_SIZE(pcm3168a_supply_names)];
0060     struct regmap *regmap;
0061     struct clk *scki;
0062     struct gpio_desc *gpio_rst;
0063     unsigned long sysclk;
0064 
0065     struct pcm3168a_io_params io_params[2];
0066     struct snd_soc_dai_driver dai_drv[2];
0067 };
0068 
0069 static const char *const pcm3168a_roll_off[] = { "Sharp", "Slow" };
0070 
0071 static SOC_ENUM_SINGLE_DECL(pcm3168a_d1_roll_off, PCM3168A_DAC_OP_FLT,
0072         PCM3168A_DAC_FLT_SHIFT, pcm3168a_roll_off);
0073 static SOC_ENUM_SINGLE_DECL(pcm3168a_d2_roll_off, PCM3168A_DAC_OP_FLT,
0074         PCM3168A_DAC_FLT_SHIFT + 1, pcm3168a_roll_off);
0075 static SOC_ENUM_SINGLE_DECL(pcm3168a_d3_roll_off, PCM3168A_DAC_OP_FLT,
0076         PCM3168A_DAC_FLT_SHIFT + 2, pcm3168a_roll_off);
0077 static SOC_ENUM_SINGLE_DECL(pcm3168a_d4_roll_off, PCM3168A_DAC_OP_FLT,
0078         PCM3168A_DAC_FLT_SHIFT + 3, pcm3168a_roll_off);
0079 
0080 static const char *const pcm3168a_volume_type[] = {
0081         "Individual", "Master + Individual" };
0082 
0083 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_volume_type, PCM3168A_DAC_ATT_DEMP_ZF,
0084         PCM3168A_DAC_ATMDDA_SHIFT, pcm3168a_volume_type);
0085 
0086 static const char *const pcm3168a_att_speed_mult[] = { "2048", "4096" };
0087 
0088 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_att_mult, PCM3168A_DAC_ATT_DEMP_ZF,
0089         PCM3168A_DAC_ATSPDA_SHIFT, pcm3168a_att_speed_mult);
0090 
0091 static const char *const pcm3168a_demp[] = {
0092         "Disabled", "48khz", "44.1khz", "32khz" };
0093 
0094 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_demp, PCM3168A_DAC_ATT_DEMP_ZF,
0095         PCM3168A_DAC_DEMP_SHIFT, pcm3168a_demp);
0096 
0097 static const char *const pcm3168a_zf_func[] = {
0098         "DAC 1/2/3/4 AND", "DAC 1/2/3/4 OR", "DAC 1/2/3 AND",
0099         "DAC 1/2/3 OR", "DAC 4 AND", "DAC 4 OR" };
0100 
0101 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_zf_func, PCM3168A_DAC_ATT_DEMP_ZF,
0102         PCM3168A_DAC_AZRO_SHIFT, pcm3168a_zf_func);
0103 
0104 static const char *const pcm3168a_pol[] = { "Active High", "Active Low" };
0105 
0106 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_zf_pol, PCM3168A_DAC_ATT_DEMP_ZF,
0107         PCM3168A_DAC_ATSPDA_SHIFT, pcm3168a_pol);
0108 
0109 static const char *const pcm3168a_con[] = { "Differential", "Single-Ended" };
0110 
0111 static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc1_con, PCM3168A_ADC_SEAD,
0112                 0, 1, pcm3168a_con);
0113 static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc2_con, PCM3168A_ADC_SEAD,
0114                 2, 3, pcm3168a_con);
0115 static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc3_con, PCM3168A_ADC_SEAD,
0116                 4, 5, pcm3168a_con);
0117 
0118 static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_volume_type, PCM3168A_ADC_ATT_OVF,
0119         PCM3168A_ADC_ATMDAD_SHIFT, pcm3168a_volume_type);
0120 
0121 static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_att_mult, PCM3168A_ADC_ATT_OVF,
0122         PCM3168A_ADC_ATSPAD_SHIFT, pcm3168a_att_speed_mult);
0123 
0124 static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_ov_pol, PCM3168A_ADC_ATT_OVF,
0125         PCM3168A_ADC_OVFP_SHIFT, pcm3168a_pol);
0126 
0127 /* -100db to 0db, register values 0-54 cause mute */
0128 static const DECLARE_TLV_DB_SCALE(pcm3168a_dac_tlv, -10050, 50, 1);
0129 
0130 /* -100db to 20db, register values 0-14 cause mute */
0131 static const DECLARE_TLV_DB_SCALE(pcm3168a_adc_tlv, -10050, 50, 1);
0132 
0133 static const struct snd_kcontrol_new pcm3168a_snd_controls[] = {
0134     SOC_SINGLE("DAC Power-Save Switch", PCM3168A_DAC_PWR_MST_FMT,
0135             PCM3168A_DAC_PSMDA_SHIFT, 1, 1),
0136     SOC_ENUM("DAC1 Digital Filter roll-off", pcm3168a_d1_roll_off),
0137     SOC_ENUM("DAC2 Digital Filter roll-off", pcm3168a_d2_roll_off),
0138     SOC_ENUM("DAC3 Digital Filter roll-off", pcm3168a_d3_roll_off),
0139     SOC_ENUM("DAC4 Digital Filter roll-off", pcm3168a_d4_roll_off),
0140     SOC_DOUBLE("DAC1 Invert Switch", PCM3168A_DAC_INV, 0, 1, 1, 0),
0141     SOC_DOUBLE("DAC2 Invert Switch", PCM3168A_DAC_INV, 2, 3, 1, 0),
0142     SOC_DOUBLE("DAC3 Invert Switch", PCM3168A_DAC_INV, 4, 5, 1, 0),
0143     SOC_DOUBLE("DAC4 Invert Switch", PCM3168A_DAC_INV, 6, 7, 1, 0),
0144     SOC_ENUM("DAC Volume Control Type", pcm3168a_dac_volume_type),
0145     SOC_ENUM("DAC Volume Rate Multiplier", pcm3168a_dac_att_mult),
0146     SOC_ENUM("DAC De-Emphasis", pcm3168a_dac_demp),
0147     SOC_ENUM("DAC Zero Flag Function", pcm3168a_dac_zf_func),
0148     SOC_ENUM("DAC Zero Flag Polarity", pcm3168a_dac_zf_pol),
0149     SOC_SINGLE_RANGE_TLV("Master Playback Volume",
0150             PCM3168A_DAC_VOL_MASTER, 0, 54, 255, 0,
0151             pcm3168a_dac_tlv),
0152     SOC_DOUBLE_R_RANGE_TLV("DAC1 Playback Volume",
0153             PCM3168A_DAC_VOL_CHAN_START,
0154             PCM3168A_DAC_VOL_CHAN_START + 1,
0155             0, 54, 255, 0, pcm3168a_dac_tlv),
0156     SOC_DOUBLE_R_RANGE_TLV("DAC2 Playback Volume",
0157             PCM3168A_DAC_VOL_CHAN_START + 2,
0158             PCM3168A_DAC_VOL_CHAN_START + 3,
0159             0, 54, 255, 0, pcm3168a_dac_tlv),
0160     SOC_DOUBLE_R_RANGE_TLV("DAC3 Playback Volume",
0161             PCM3168A_DAC_VOL_CHAN_START + 4,
0162             PCM3168A_DAC_VOL_CHAN_START + 5,
0163             0, 54, 255, 0, pcm3168a_dac_tlv),
0164     SOC_DOUBLE_R_RANGE_TLV("DAC4 Playback Volume",
0165             PCM3168A_DAC_VOL_CHAN_START + 6,
0166             PCM3168A_DAC_VOL_CHAN_START + 7,
0167             0, 54, 255, 0, pcm3168a_dac_tlv),
0168     SOC_SINGLE("ADC1 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB,
0169             PCM3168A_ADC_BYP_SHIFT, 1, 1),
0170     SOC_SINGLE("ADC2 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB,
0171             PCM3168A_ADC_BYP_SHIFT + 1, 1, 1),
0172     SOC_SINGLE("ADC3 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB,
0173             PCM3168A_ADC_BYP_SHIFT + 2, 1, 1),
0174     SOC_ENUM("ADC1 Connection Type", pcm3168a_adc1_con),
0175     SOC_ENUM("ADC2 Connection Type", pcm3168a_adc2_con),
0176     SOC_ENUM("ADC3 Connection Type", pcm3168a_adc3_con),
0177     SOC_DOUBLE("ADC1 Invert Switch", PCM3168A_ADC_INV, 0, 1, 1, 0),
0178     SOC_DOUBLE("ADC2 Invert Switch", PCM3168A_ADC_INV, 2, 3, 1, 0),
0179     SOC_DOUBLE("ADC3 Invert Switch", PCM3168A_ADC_INV, 4, 5, 1, 0),
0180     SOC_DOUBLE("ADC1 Mute Switch", PCM3168A_ADC_MUTE, 0, 1, 1, 0),
0181     SOC_DOUBLE("ADC2 Mute Switch", PCM3168A_ADC_MUTE, 2, 3, 1, 0),
0182     SOC_DOUBLE("ADC3 Mute Switch", PCM3168A_ADC_MUTE, 4, 5, 1, 0),
0183     SOC_ENUM("ADC Volume Control Type", pcm3168a_adc_volume_type),
0184     SOC_ENUM("ADC Volume Rate Multiplier", pcm3168a_adc_att_mult),
0185     SOC_ENUM("ADC Overflow Flag Polarity", pcm3168a_adc_ov_pol),
0186     SOC_SINGLE_RANGE_TLV("Master Capture Volume",
0187             PCM3168A_ADC_VOL_MASTER, 0, 14, 255, 0,
0188             pcm3168a_adc_tlv),
0189     SOC_DOUBLE_R_RANGE_TLV("ADC1 Capture Volume",
0190             PCM3168A_ADC_VOL_CHAN_START,
0191             PCM3168A_ADC_VOL_CHAN_START + 1,
0192             0, 14, 255, 0, pcm3168a_adc_tlv),
0193     SOC_DOUBLE_R_RANGE_TLV("ADC2 Capture Volume",
0194             PCM3168A_ADC_VOL_CHAN_START + 2,
0195             PCM3168A_ADC_VOL_CHAN_START + 3,
0196             0, 14, 255, 0, pcm3168a_adc_tlv),
0197     SOC_DOUBLE_R_RANGE_TLV("ADC3 Capture Volume",
0198             PCM3168A_ADC_VOL_CHAN_START + 4,
0199             PCM3168A_ADC_VOL_CHAN_START + 5,
0200             0, 14, 255, 0, pcm3168a_adc_tlv)
0201 };
0202 
0203 static const struct snd_soc_dapm_widget pcm3168a_dapm_widgets[] = {
0204     SND_SOC_DAPM_DAC("DAC1", "Playback", PCM3168A_DAC_OP_FLT,
0205             PCM3168A_DAC_OPEDA_SHIFT, 1),
0206     SND_SOC_DAPM_DAC("DAC2", "Playback", PCM3168A_DAC_OP_FLT,
0207             PCM3168A_DAC_OPEDA_SHIFT + 1, 1),
0208     SND_SOC_DAPM_DAC("DAC3", "Playback", PCM3168A_DAC_OP_FLT,
0209             PCM3168A_DAC_OPEDA_SHIFT + 2, 1),
0210     SND_SOC_DAPM_DAC("DAC4", "Playback", PCM3168A_DAC_OP_FLT,
0211             PCM3168A_DAC_OPEDA_SHIFT + 3, 1),
0212 
0213     SND_SOC_DAPM_OUTPUT("AOUT1L"),
0214     SND_SOC_DAPM_OUTPUT("AOUT1R"),
0215     SND_SOC_DAPM_OUTPUT("AOUT2L"),
0216     SND_SOC_DAPM_OUTPUT("AOUT2R"),
0217     SND_SOC_DAPM_OUTPUT("AOUT3L"),
0218     SND_SOC_DAPM_OUTPUT("AOUT3R"),
0219     SND_SOC_DAPM_OUTPUT("AOUT4L"),
0220     SND_SOC_DAPM_OUTPUT("AOUT4R"),
0221 
0222     SND_SOC_DAPM_ADC("ADC1", "Capture", PCM3168A_ADC_PWR_HPFB,
0223             PCM3168A_ADC_PSVAD_SHIFT, 1),
0224     SND_SOC_DAPM_ADC("ADC2", "Capture", PCM3168A_ADC_PWR_HPFB,
0225             PCM3168A_ADC_PSVAD_SHIFT + 1, 1),
0226     SND_SOC_DAPM_ADC("ADC3", "Capture", PCM3168A_ADC_PWR_HPFB,
0227             PCM3168A_ADC_PSVAD_SHIFT + 2, 1),
0228 
0229     SND_SOC_DAPM_INPUT("AIN1L"),
0230     SND_SOC_DAPM_INPUT("AIN1R"),
0231     SND_SOC_DAPM_INPUT("AIN2L"),
0232     SND_SOC_DAPM_INPUT("AIN2R"),
0233     SND_SOC_DAPM_INPUT("AIN3L"),
0234     SND_SOC_DAPM_INPUT("AIN3R")
0235 };
0236 
0237 static const struct snd_soc_dapm_route pcm3168a_dapm_routes[] = {
0238     /* Playback */
0239     { "AOUT1L", NULL, "DAC1" },
0240     { "AOUT1R", NULL, "DAC1" },
0241 
0242     { "AOUT2L", NULL, "DAC2" },
0243     { "AOUT2R", NULL, "DAC2" },
0244 
0245     { "AOUT3L", NULL, "DAC3" },
0246     { "AOUT3R", NULL, "DAC3" },
0247 
0248     { "AOUT4L", NULL, "DAC4" },
0249     { "AOUT4R", NULL, "DAC4" },
0250 
0251     /* Capture */
0252     { "ADC1", NULL, "AIN1L" },
0253     { "ADC1", NULL, "AIN1R" },
0254 
0255     { "ADC2", NULL, "AIN2L" },
0256     { "ADC2", NULL, "AIN2R" },
0257 
0258     { "ADC3", NULL, "AIN3L" },
0259     { "ADC3", NULL, "AIN3R" }
0260 };
0261 
0262 static unsigned int pcm3168a_scki_ratios[] = {
0263     768,
0264     512,
0265     384,
0266     256,
0267     192,
0268     128
0269 };
0270 
0271 #define PCM3168A_NUM_SCKI_RATIOS_DAC    ARRAY_SIZE(pcm3168a_scki_ratios)
0272 #define PCM3168A_NUM_SCKI_RATIOS_ADC    (ARRAY_SIZE(pcm3168a_scki_ratios) - 2)
0273 
0274 #define PCM3168A_MAX_SYSCLK     36864000
0275 
0276 static int pcm3168a_reset(struct pcm3168a_priv *pcm3168a)
0277 {
0278     int ret;
0279 
0280     ret = regmap_write(pcm3168a->regmap, PCM3168A_RST_SMODE, 0);
0281     if (ret)
0282         return ret;
0283 
0284     /* Internal reset is de-asserted after 3846 SCKI cycles */
0285     msleep(DIV_ROUND_UP(3846 * 1000, pcm3168a->sysclk));
0286 
0287     return regmap_write(pcm3168a->regmap, PCM3168A_RST_SMODE,
0288             PCM3168A_MRST_MASK | PCM3168A_SRST_MASK);
0289 }
0290 
0291 static int pcm3168a_mute(struct snd_soc_dai *dai, int mute, int direction)
0292 {
0293     struct snd_soc_component *component = dai->component;
0294     struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component);
0295 
0296     regmap_write(pcm3168a->regmap, PCM3168A_DAC_MUTE, mute ? 0xff : 0);
0297 
0298     return 0;
0299 }
0300 
0301 static int pcm3168a_set_dai_sysclk(struct snd_soc_dai *dai,
0302                   int clk_id, unsigned int freq, int dir)
0303 {
0304     struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(dai->component);
0305     int ret;
0306 
0307     /*
0308      * Some sound card sets 0 Hz as reset,
0309      * but it is impossible to set. Ignore it here
0310      */
0311     if (freq == 0)
0312         return 0;
0313 
0314     if (freq > PCM3168A_MAX_SYSCLK)
0315         return -EINVAL;
0316 
0317     ret = clk_set_rate(pcm3168a->scki, freq);
0318     if (ret)
0319         return ret;
0320 
0321     pcm3168a->sysclk = freq;
0322 
0323     return 0;
0324 }
0325 
0326 static void pcm3168a_update_fixup_pcm_stream(struct snd_soc_dai *dai)
0327 {
0328     struct snd_soc_component *component = dai->component;
0329     struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component);
0330     struct pcm3168a_io_params *io_params = &pcm3168a->io_params[dai->id];
0331     u64 formats = SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE;
0332     unsigned int channel_max = dai->id == PCM3168A_DAI_DAC ? 8 : 6;
0333 
0334     if (io_params->format == SND_SOC_DAIFMT_RIGHT_J) {
0335         /* S16_LE is only supported in RIGHT_J mode */
0336         formats |= SNDRV_PCM_FMTBIT_S16_LE;
0337 
0338         /*
0339          * If multi DIN/DOUT is not selected, RIGHT_J can only support
0340          * two channels (no TDM support)
0341          */
0342         if (io_params->tdm_slots != 2)
0343             channel_max = 2;
0344     }
0345 
0346     if (dai->id == PCM3168A_DAI_DAC) {
0347         dai->driver->playback.channels_max = channel_max;
0348         dai->driver->playback.formats = formats;
0349     } else {
0350         dai->driver->capture.channels_max = channel_max;
0351         dai->driver->capture.formats = formats;
0352     }
0353 }
0354 
0355 static int pcm3168a_set_dai_fmt(struct snd_soc_dai *dai, unsigned int format)
0356 {
0357     struct snd_soc_component *component = dai->component;
0358     struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component);
0359     struct pcm3168a_io_params *io_params = &pcm3168a->io_params[dai->id];
0360     bool provider_mode;
0361 
0362     switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
0363     case SND_SOC_DAIFMT_LEFT_J:
0364     case SND_SOC_DAIFMT_I2S:
0365     case SND_SOC_DAIFMT_RIGHT_J:
0366     case SND_SOC_DAIFMT_DSP_A:
0367     case SND_SOC_DAIFMT_DSP_B:
0368         break;
0369     default:
0370         dev_err(component->dev, "unsupported dai format\n");
0371         return -EINVAL;
0372     }
0373 
0374     switch (format & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0375     case SND_SOC_DAIFMT_CBC_CFC:
0376         provider_mode = false;
0377         break;
0378     case SND_SOC_DAIFMT_CBP_CFP:
0379         provider_mode = true;
0380         break;
0381     default:
0382         dev_err(component->dev, "unsupported provider mode\n");
0383         return -EINVAL;
0384     }
0385 
0386     switch (format & SND_SOC_DAIFMT_INV_MASK) {
0387     case SND_SOC_DAIFMT_NB_NF:
0388         break;
0389     default:
0390         return -EINVAL;
0391     }
0392 
0393     io_params->provider_mode = provider_mode;
0394     io_params->format = format & SND_SOC_DAIFMT_FORMAT_MASK;
0395 
0396     pcm3168a_update_fixup_pcm_stream(dai);
0397 
0398     return 0;
0399 }
0400 
0401 static int pcm3168a_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
0402                  unsigned int rx_mask, int slots,
0403                  int slot_width)
0404 {
0405     struct snd_soc_component *component = dai->component;
0406     struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component);
0407     struct pcm3168a_io_params *io_params = &pcm3168a->io_params[dai->id];
0408 
0409     if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) {
0410         dev_err(component->dev,
0411             "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n",
0412             tx_mask, rx_mask, slots);
0413         return -EINVAL;
0414     }
0415 
0416     if (slot_width &&
0417         (slot_width != 16 && slot_width != 24 && slot_width != 32 )) {
0418         dev_err(component->dev, "Unsupported slot_width %d\n",
0419             slot_width);
0420         return -EINVAL;
0421     }
0422 
0423     io_params->tdm_slots = slots;
0424     io_params->slot_width = slot_width;
0425     /* Ignore the not relevant mask for the DAI/direction */
0426     if (dai->id == PCM3168A_DAI_DAC)
0427         io_params->tdm_mask = tx_mask;
0428     else
0429         io_params->tdm_mask = rx_mask;
0430 
0431     pcm3168a_update_fixup_pcm_stream(dai);
0432 
0433     return 0;
0434 }
0435 
0436 static int pcm3168a_hw_params(struct snd_pcm_substream *substream,
0437                  struct snd_pcm_hw_params *params,
0438                  struct snd_soc_dai *dai)
0439 {
0440     struct snd_soc_component *component = dai->component;
0441     struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component);
0442     struct pcm3168a_io_params *io_params = &pcm3168a->io_params[dai->id];
0443     bool provider_mode, tdm_mode;
0444     unsigned int format;
0445     unsigned int reg, mask, ms, ms_shift, fmt, fmt_shift, ratio, tdm_slots;
0446     int i, num_scki_ratios, slot_width;
0447 
0448     if (dai->id == PCM3168A_DAI_DAC) {
0449         num_scki_ratios = PCM3168A_NUM_SCKI_RATIOS_DAC;
0450         reg = PCM3168A_DAC_PWR_MST_FMT;
0451         mask = PCM3168A_DAC_MSDA_MASK | PCM3168A_DAC_FMT_MASK;
0452         ms_shift = PCM3168A_DAC_MSDA_SHIFT;
0453         fmt_shift = PCM3168A_DAC_FMT_SHIFT;
0454     } else {
0455         num_scki_ratios = PCM3168A_NUM_SCKI_RATIOS_ADC;
0456         reg = PCM3168A_ADC_MST_FMT;
0457         mask = PCM3168A_ADC_MSAD_MASK | PCM3168A_ADC_FMTAD_MASK;
0458         ms_shift = PCM3168A_ADC_MSAD_SHIFT;
0459         fmt_shift = PCM3168A_ADC_FMTAD_SHIFT;
0460     }
0461 
0462     provider_mode = io_params->provider_mode;
0463 
0464     if (provider_mode) {
0465         ratio = pcm3168a->sysclk / params_rate(params);
0466 
0467         for (i = 0; i < num_scki_ratios; i++) {
0468             if (pcm3168a_scki_ratios[i] == ratio)
0469                 break;
0470         }
0471 
0472         if (i == num_scki_ratios) {
0473             dev_err(component->dev, "unsupported sysclk ratio\n");
0474             return -EINVAL;
0475         }
0476 
0477         ms = (i + 1);
0478     } else {
0479         ms = 0;
0480     }
0481 
0482     format = io_params->format;
0483 
0484     if (io_params->slot_width)
0485         slot_width = io_params->slot_width;
0486     else
0487         slot_width = params_width(params);
0488 
0489     switch (slot_width) {
0490     case 16:
0491         if (provider_mode || (format != SND_SOC_DAIFMT_RIGHT_J)) {
0492             dev_err(component->dev, "16-bit slots are supported only for consumer mode using right justified\n");
0493             return -EINVAL;
0494         }
0495         break;
0496     case 24:
0497         if (provider_mode || (format == SND_SOC_DAIFMT_DSP_A) ||
0498                          (format == SND_SOC_DAIFMT_DSP_B)) {
0499             dev_err(component->dev, "24-bit slots not supported in provider mode, or consumer mode using DSP\n");
0500             return -EINVAL;
0501         }
0502         break;
0503     case 32:
0504         break;
0505     default:
0506         dev_err(component->dev, "unsupported frame size: %d\n", slot_width);
0507         return -EINVAL;
0508     }
0509 
0510     if (io_params->tdm_slots)
0511         tdm_slots = io_params->tdm_slots;
0512     else
0513         tdm_slots = params_channels(params);
0514 
0515     /*
0516      * Switch the codec to TDM mode when more than 2 TDM slots are needed
0517      * for the stream.
0518      * If pcm3168a->tdm_slots is not set or set to more than 2 (8/6 usually)
0519      * then DIN1/DOUT1 is used in TDM mode.
0520      * If pcm3168a->tdm_slots is set to 2 then DIN1/2/3/4 and DOUT1/2/3 is
0521      * used in normal mode, no need to switch to TDM modes.
0522      */
0523     tdm_mode = (tdm_slots > 2);
0524 
0525     if (tdm_mode) {
0526         switch (format) {
0527         case SND_SOC_DAIFMT_I2S:
0528         case SND_SOC_DAIFMT_DSP_A:
0529         case SND_SOC_DAIFMT_LEFT_J:
0530         case SND_SOC_DAIFMT_DSP_B:
0531             break;
0532         default:
0533             dev_err(component->dev,
0534                 "TDM is supported under DSP/I2S/Left_J only\n");
0535             return -EINVAL;
0536         }
0537     }
0538 
0539     switch (format) {
0540     case SND_SOC_DAIFMT_I2S:
0541         fmt = tdm_mode ? PCM3168A_FMT_I2S_TDM : PCM3168A_FMT_I2S;
0542         break;
0543     case SND_SOC_DAIFMT_LEFT_J:
0544         fmt = tdm_mode ? PCM3168A_FMT_LEFT_J_TDM : PCM3168A_FMT_LEFT_J;
0545         break;
0546     case SND_SOC_DAIFMT_RIGHT_J:
0547         fmt = (slot_width == 16) ? PCM3168A_FMT_RIGHT_J_16 :
0548                        PCM3168A_FMT_RIGHT_J;
0549         break;
0550     case SND_SOC_DAIFMT_DSP_A:
0551         fmt = tdm_mode ? PCM3168A_FMT_I2S_TDM : PCM3168A_FMT_DSP_A;
0552         break;
0553     case SND_SOC_DAIFMT_DSP_B:
0554         fmt = tdm_mode ? PCM3168A_FMT_LEFT_J_TDM : PCM3168A_FMT_DSP_B;
0555         break;
0556     default:
0557         return -EINVAL;
0558     }
0559 
0560     regmap_update_bits(pcm3168a->regmap, reg, mask,
0561             (ms << ms_shift) | (fmt << fmt_shift));
0562 
0563     return 0;
0564 }
0565 
0566 static u64 pcm3168a_dai_formats[] = {
0567     /*
0568      * Select below from Sound Card, not here
0569      *  SND_SOC_DAIFMT_CBC_CFC
0570      *  SND_SOC_DAIFMT_CBP_CFP
0571      */
0572 
0573     /*
0574      * First Priority
0575      */
0576     SND_SOC_POSSIBLE_DAIFMT_I2S |
0577     SND_SOC_POSSIBLE_DAIFMT_LEFT_J,
0578     /*
0579      * Second Priority
0580      *
0581      * These have picky limitation.
0582      * see
0583      *  pcm3168a_hw_params()
0584      */
0585     SND_SOC_POSSIBLE_DAIFMT_RIGHT_J |
0586     SND_SOC_POSSIBLE_DAIFMT_DSP_A   |
0587     SND_SOC_POSSIBLE_DAIFMT_DSP_B,
0588 };
0589 
0590 static const struct snd_soc_dai_ops pcm3168a_dai_ops = {
0591     .set_fmt    = pcm3168a_set_dai_fmt,
0592     .set_sysclk = pcm3168a_set_dai_sysclk,
0593     .hw_params  = pcm3168a_hw_params,
0594     .mute_stream    = pcm3168a_mute,
0595     .set_tdm_slot   = pcm3168a_set_tdm_slot,
0596     .no_capture_mute = 1,
0597     .auto_selectable_formats    = pcm3168a_dai_formats,
0598     .num_auto_selectable_formats    = ARRAY_SIZE(pcm3168a_dai_formats),
0599 };
0600 
0601 static struct snd_soc_dai_driver pcm3168a_dais[] = {
0602     {
0603         .name = "pcm3168a-dac",
0604         .id = PCM3168A_DAI_DAC,
0605         .playback = {
0606             .stream_name = "Playback",
0607             .channels_min = 1,
0608             .channels_max = 8,
0609             .rates = SNDRV_PCM_RATE_8000_192000,
0610             .formats = PCM3168A_FORMATS
0611         },
0612         .ops = &pcm3168a_dai_ops
0613     },
0614     {
0615         .name = "pcm3168a-adc",
0616         .id = PCM3168A_DAI_ADC,
0617         .capture = {
0618             .stream_name = "Capture",
0619             .channels_min = 1,
0620             .channels_max = 6,
0621             .rates = SNDRV_PCM_RATE_8000_96000,
0622             .formats = PCM3168A_FORMATS
0623         },
0624         .ops = &pcm3168a_dai_ops
0625     },
0626 };
0627 
0628 static const struct reg_default pcm3168a_reg_default[] = {
0629     { PCM3168A_RST_SMODE, PCM3168A_MRST_MASK | PCM3168A_SRST_MASK },
0630     { PCM3168A_DAC_PWR_MST_FMT, 0x00 },
0631     { PCM3168A_DAC_OP_FLT, 0x00 },
0632     { PCM3168A_DAC_INV, 0x00 },
0633     { PCM3168A_DAC_MUTE, 0x00 },
0634     { PCM3168A_DAC_ZERO, 0x00 },
0635     { PCM3168A_DAC_ATT_DEMP_ZF, 0x00 },
0636     { PCM3168A_DAC_VOL_MASTER, 0xff },
0637     { PCM3168A_DAC_VOL_CHAN_START, 0xff },
0638     { PCM3168A_DAC_VOL_CHAN_START + 1, 0xff },
0639     { PCM3168A_DAC_VOL_CHAN_START + 2, 0xff },
0640     { PCM3168A_DAC_VOL_CHAN_START + 3, 0xff },
0641     { PCM3168A_DAC_VOL_CHAN_START + 4, 0xff },
0642     { PCM3168A_DAC_VOL_CHAN_START + 5, 0xff },
0643     { PCM3168A_DAC_VOL_CHAN_START + 6, 0xff },
0644     { PCM3168A_DAC_VOL_CHAN_START + 7, 0xff },
0645     { PCM3168A_ADC_SMODE, 0x00 },
0646     { PCM3168A_ADC_MST_FMT, 0x00 },
0647     { PCM3168A_ADC_PWR_HPFB, 0x00 },
0648     { PCM3168A_ADC_SEAD, 0x00 },
0649     { PCM3168A_ADC_INV, 0x00 },
0650     { PCM3168A_ADC_MUTE, 0x00 },
0651     { PCM3168A_ADC_OV, 0x00 },
0652     { PCM3168A_ADC_ATT_OVF, 0x00 },
0653     { PCM3168A_ADC_VOL_MASTER, 0xd3 },
0654     { PCM3168A_ADC_VOL_CHAN_START, 0xd3 },
0655     { PCM3168A_ADC_VOL_CHAN_START + 1, 0xd3 },
0656     { PCM3168A_ADC_VOL_CHAN_START + 2, 0xd3 },
0657     { PCM3168A_ADC_VOL_CHAN_START + 3, 0xd3 },
0658     { PCM3168A_ADC_VOL_CHAN_START + 4, 0xd3 },
0659     { PCM3168A_ADC_VOL_CHAN_START + 5, 0xd3 }
0660 };
0661 
0662 static bool pcm3168a_readable_register(struct device *dev, unsigned int reg)
0663 {
0664     if (reg >= PCM3168A_RST_SMODE)
0665         return true;
0666     else
0667         return false;
0668 }
0669 
0670 static bool pcm3168a_volatile_register(struct device *dev, unsigned int reg)
0671 {
0672     switch (reg) {
0673     case PCM3168A_RST_SMODE:
0674     case PCM3168A_DAC_ZERO:
0675     case PCM3168A_ADC_OV:
0676         return true;
0677     default:
0678         return false;
0679     }
0680 }
0681 
0682 static bool pcm3168a_writeable_register(struct device *dev, unsigned int reg)
0683 {
0684     if (reg < PCM3168A_RST_SMODE)
0685         return false;
0686 
0687     switch (reg) {
0688     case PCM3168A_DAC_ZERO:
0689     case PCM3168A_ADC_OV:
0690         return false;
0691     default:
0692         return true;
0693     }
0694 }
0695 
0696 const struct regmap_config pcm3168a_regmap = {
0697     .reg_bits = 8,
0698     .val_bits = 8,
0699 
0700     .max_register = PCM3168A_ADC_VOL_CHAN_START + 5,
0701     .reg_defaults = pcm3168a_reg_default,
0702     .num_reg_defaults = ARRAY_SIZE(pcm3168a_reg_default),
0703     .readable_reg = pcm3168a_readable_register,
0704     .volatile_reg = pcm3168a_volatile_register,
0705     .writeable_reg = pcm3168a_writeable_register,
0706     .cache_type = REGCACHE_FLAT
0707 };
0708 EXPORT_SYMBOL_GPL(pcm3168a_regmap);
0709 
0710 static const struct snd_soc_component_driver pcm3168a_driver = {
0711     .controls       = pcm3168a_snd_controls,
0712     .num_controls       = ARRAY_SIZE(pcm3168a_snd_controls),
0713     .dapm_widgets       = pcm3168a_dapm_widgets,
0714     .num_dapm_widgets   = ARRAY_SIZE(pcm3168a_dapm_widgets),
0715     .dapm_routes        = pcm3168a_dapm_routes,
0716     .num_dapm_routes    = ARRAY_SIZE(pcm3168a_dapm_routes),
0717     .use_pmdown_time    = 1,
0718     .endianness     = 1,
0719 };
0720 
0721 int pcm3168a_probe(struct device *dev, struct regmap *regmap)
0722 {
0723     struct pcm3168a_priv *pcm3168a;
0724     int ret, i;
0725 
0726     pcm3168a = devm_kzalloc(dev, sizeof(*pcm3168a), GFP_KERNEL);
0727     if (pcm3168a == NULL)
0728         return -ENOMEM;
0729 
0730     dev_set_drvdata(dev, pcm3168a);
0731 
0732     /*
0733      * Request the reset (connected to RST pin) gpio line as non exclusive
0734      * as the same reset line might be connected to multiple pcm3168a codec
0735      *
0736      * The RST is low active, we want the GPIO line to be high initially, so
0737      * request the initial level to LOW which in practice means DEASSERTED:
0738      * The deasserted level of GPIO_ACTIVE_LOW is HIGH.
0739      */
0740     pcm3168a->gpio_rst = devm_gpiod_get_optional(dev, "reset",
0741                         GPIOD_OUT_LOW |
0742                         GPIOD_FLAGS_BIT_NONEXCLUSIVE);
0743     if (IS_ERR(pcm3168a->gpio_rst))
0744         return dev_err_probe(dev, PTR_ERR(pcm3168a->gpio_rst),
0745                      "failed to acquire RST gpio\n");
0746 
0747     pcm3168a->scki = devm_clk_get(dev, "scki");
0748     if (IS_ERR(pcm3168a->scki))
0749         return dev_err_probe(dev, PTR_ERR(pcm3168a->scki),
0750                      "failed to acquire clock 'scki'\n");
0751 
0752     ret = clk_prepare_enable(pcm3168a->scki);
0753     if (ret) {
0754         dev_err(dev, "Failed to enable mclk: %d\n", ret);
0755         return ret;
0756     }
0757 
0758     pcm3168a->sysclk = clk_get_rate(pcm3168a->scki);
0759 
0760     for (i = 0; i < ARRAY_SIZE(pcm3168a->supplies); i++)
0761         pcm3168a->supplies[i].supply = pcm3168a_supply_names[i];
0762 
0763     ret = devm_regulator_bulk_get(dev,
0764             ARRAY_SIZE(pcm3168a->supplies), pcm3168a->supplies);
0765     if (ret) {
0766         dev_err_probe(dev, ret, "failed to request supplies\n");
0767         goto err_clk;
0768     }
0769 
0770     ret = regulator_bulk_enable(ARRAY_SIZE(pcm3168a->supplies),
0771                     pcm3168a->supplies);
0772     if (ret) {
0773         dev_err(dev, "failed to enable supplies: %d\n", ret);
0774         goto err_clk;
0775     }
0776 
0777     pcm3168a->regmap = regmap;
0778     if (IS_ERR(pcm3168a->regmap)) {
0779         ret = PTR_ERR(pcm3168a->regmap);
0780         dev_err(dev, "failed to allocate regmap: %d\n", ret);
0781         goto err_regulator;
0782     }
0783 
0784     if (pcm3168a->gpio_rst) {
0785         /*
0786          * The device is taken out from reset via GPIO line, wait for
0787          * 3846 SCKI clock cycles for the internal reset de-assertion
0788          */
0789         msleep(DIV_ROUND_UP(3846 * 1000, pcm3168a->sysclk));
0790     } else {
0791         ret = pcm3168a_reset(pcm3168a);
0792         if (ret) {
0793             dev_err(dev, "Failed to reset device: %d\n", ret);
0794             goto err_regulator;
0795         }
0796     }
0797 
0798     pm_runtime_set_active(dev);
0799     pm_runtime_enable(dev);
0800     pm_runtime_idle(dev);
0801 
0802     memcpy(pcm3168a->dai_drv, pcm3168a_dais, sizeof(pcm3168a->dai_drv));
0803     ret = devm_snd_soc_register_component(dev, &pcm3168a_driver,
0804                           pcm3168a->dai_drv,
0805                           ARRAY_SIZE(pcm3168a->dai_drv));
0806     if (ret) {
0807         dev_err(dev, "failed to register component: %d\n", ret);
0808         goto err_regulator;
0809     }
0810 
0811     return 0;
0812 
0813 err_regulator:
0814     regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies),
0815             pcm3168a->supplies);
0816 err_clk:
0817     clk_disable_unprepare(pcm3168a->scki);
0818 
0819     return ret;
0820 }
0821 EXPORT_SYMBOL_GPL(pcm3168a_probe);
0822 
0823 static void pcm3168a_disable(struct device *dev)
0824 {
0825     struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev);
0826 
0827     regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies),
0828                    pcm3168a->supplies);
0829     clk_disable_unprepare(pcm3168a->scki);
0830 }
0831 
0832 void pcm3168a_remove(struct device *dev)
0833 {
0834     struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev);
0835 
0836     /*
0837      * The RST is low active, we want the GPIO line to be low when the
0838      * driver is removed, so set level to 1 which in practice means
0839      * ASSERTED:
0840      * The asserted level of GPIO_ACTIVE_LOW is LOW.
0841      */
0842     gpiod_set_value_cansleep(pcm3168a->gpio_rst, 1);
0843     pm_runtime_disable(dev);
0844 #ifndef CONFIG_PM
0845     pcm3168a_disable(dev);
0846 #endif
0847 }
0848 EXPORT_SYMBOL_GPL(pcm3168a_remove);
0849 
0850 #ifdef CONFIG_PM
0851 static int pcm3168a_rt_resume(struct device *dev)
0852 {
0853     struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev);
0854     int ret;
0855 
0856     ret = clk_prepare_enable(pcm3168a->scki);
0857     if (ret) {
0858         dev_err(dev, "Failed to enable mclk: %d\n", ret);
0859         return ret;
0860     }
0861 
0862     ret = regulator_bulk_enable(ARRAY_SIZE(pcm3168a->supplies),
0863                     pcm3168a->supplies);
0864     if (ret) {
0865         dev_err(dev, "Failed to enable supplies: %d\n", ret);
0866         goto err_clk;
0867     }
0868 
0869     ret = pcm3168a_reset(pcm3168a);
0870     if (ret) {
0871         dev_err(dev, "Failed to reset device: %d\n", ret);
0872         goto err_regulator;
0873     }
0874 
0875     regcache_cache_only(pcm3168a->regmap, false);
0876 
0877     regcache_mark_dirty(pcm3168a->regmap);
0878 
0879     ret = regcache_sync(pcm3168a->regmap);
0880     if (ret) {
0881         dev_err(dev, "Failed to sync regmap: %d\n", ret);
0882         goto err_regulator;
0883     }
0884 
0885     return 0;
0886 
0887 err_regulator:
0888     regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies),
0889                    pcm3168a->supplies);
0890 err_clk:
0891     clk_disable_unprepare(pcm3168a->scki);
0892 
0893     return ret;
0894 }
0895 
0896 static int pcm3168a_rt_suspend(struct device *dev)
0897 {
0898     struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev);
0899 
0900     regcache_cache_only(pcm3168a->regmap, true);
0901 
0902     pcm3168a_disable(dev);
0903 
0904     return 0;
0905 }
0906 #endif
0907 
0908 const struct dev_pm_ops pcm3168a_pm_ops = {
0909     SET_RUNTIME_PM_OPS(pcm3168a_rt_suspend, pcm3168a_rt_resume, NULL)
0910 };
0911 EXPORT_SYMBOL_GPL(pcm3168a_pm_ops);
0912 
0913 MODULE_DESCRIPTION("PCM3168A codec driver");
0914 MODULE_AUTHOR("Damien Horsley <Damien.Horsley@imgtec.com>");
0915 MODULE_LICENSE("GPL v2");
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