soc/codecs/pcm186x.h

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Texas Instruments PCM186x Universal Audio ADC
0004  *
0005  * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com
0006  *  Andreas Dannenberg <dannenberg@ti.com>
0007  *  Andrew F. Davis <afd@ti.com>
0008  */
0009
0010 #ifndef _PCM186X_H_
0011 #define _PCM186X_H_
0012
0013 #include <linux/pm.h>
0014 #include <linux/regmap.h>
0015
0016 enum pcm186x_type {
0017     PCM1862,
0018     PCM1863,
0019     PCM1864,
0020     PCM1865,
0021 };
0022
0023 #define PCM186X_RATES   SNDRV_PCM_RATE_8000_192000
0024 #define PCM186X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
0025              SNDRV_PCM_FMTBIT_S20_3LE |\
0026              SNDRV_PCM_FMTBIT_S24_LE | \
0027              SNDRV_PCM_FMTBIT_S32_LE)
0028
0029 #define PCM186X_PAGE_LEN        0x0100
0030 #define PCM186X_PAGE_BASE(n)        (PCM186X_PAGE_LEN * n)
0031
0032 /* The page selection register address is the same on all pages */
0033 #define PCM186X_PAGE            0
0034
0035 /* Register Definitions - Page 0 */
0036 #define PCM186X_PGA_VAL_CH1_L       (PCM186X_PAGE_BASE(0) +   1)
0037 #define PCM186X_PGA_VAL_CH1_R       (PCM186X_PAGE_BASE(0) +   2)
0038 #define PCM186X_PGA_VAL_CH2_L       (PCM186X_PAGE_BASE(0) +   3)
0039 #define PCM186X_PGA_VAL_CH2_R       (PCM186X_PAGE_BASE(0) +   4)
0040 #define PCM186X_PGA_CTRL        (PCM186X_PAGE_BASE(0) +   5)
0041 #define PCM186X_ADC1_INPUT_SEL_L    (PCM186X_PAGE_BASE(0) +   6)
0042 #define PCM186X_ADC1_INPUT_SEL_R    (PCM186X_PAGE_BASE(0) +   7)
0043 #define PCM186X_ADC2_INPUT_SEL_L    (PCM186X_PAGE_BASE(0) +   8)
0044 #define PCM186X_ADC2_INPUT_SEL_R    (PCM186X_PAGE_BASE(0) +   9)
0045 #define PCM186X_AUXADC_INPUT_SEL    (PCM186X_PAGE_BASE(0) +  10)
0046 #define PCM186X_PCM_CFG         (PCM186X_PAGE_BASE(0) +  11)
0047 #define PCM186X_TDM_TX_SEL      (PCM186X_PAGE_BASE(0) +  12)
0048 #define PCM186X_TDM_TX_OFFSET       (PCM186X_PAGE_BASE(0) +  13)
0049 #define PCM186X_TDM_RX_OFFSET       (PCM186X_PAGE_BASE(0) +  14)
0050 #define PCM186X_DPGA_VAL_CH1_L      (PCM186X_PAGE_BASE(0) +  15)
0051 #define PCM186X_GPIO1_0_CTRL        (PCM186X_PAGE_BASE(0) +  16)
0052 #define PCM186X_GPIO3_2_CTRL        (PCM186X_PAGE_BASE(0) +  17)
0053 #define PCM186X_GPIO1_0_DIR_CTRL    (PCM186X_PAGE_BASE(0) +  18)
0054 #define PCM186X_GPIO3_2_DIR_CTRL    (PCM186X_PAGE_BASE(0) +  19)
0055 #define PCM186X_GPIO_IN_OUT     (PCM186X_PAGE_BASE(0) +  20)
0056 #define PCM186X_GPIO_PULL_CTRL      (PCM186X_PAGE_BASE(0) +  21)
0057 #define PCM186X_DPGA_VAL_CH1_R      (PCM186X_PAGE_BASE(0) +  22)
0058 #define PCM186X_DPGA_VAL_CH2_L      (PCM186X_PAGE_BASE(0) +  23)
0059 #define PCM186X_DPGA_VAL_CH2_R      (PCM186X_PAGE_BASE(0) +  24)
0060 #define PCM186X_DPGA_GAIN_CTRL      (PCM186X_PAGE_BASE(0) +  25)
0061 #define PCM186X_DPGA_MIC_CTRL       (PCM186X_PAGE_BASE(0) +  26)
0062 #define PCM186X_DIN_RESAMP_CTRL     (PCM186X_PAGE_BASE(0) +  27)
0063 #define PCM186X_CLK_CTRL        (PCM186X_PAGE_BASE(0) +  32)
0064 #define PCM186X_DSP1_CLK_DIV        (PCM186X_PAGE_BASE(0) +  33)
0065 #define PCM186X_DSP2_CLK_DIV        (PCM186X_PAGE_BASE(0) +  34)
0066 #define PCM186X_ADC_CLK_DIV     (PCM186X_PAGE_BASE(0) +  35)
0067 #define PCM186X_PLL_SCK_DIV     (PCM186X_PAGE_BASE(0) +  37)
0068 #define PCM186X_BCK_DIV         (PCM186X_PAGE_BASE(0) +  38)
0069 #define PCM186X_LRK_DIV         (PCM186X_PAGE_BASE(0) +  39)
0070 #define PCM186X_PLL_CTRL        (PCM186X_PAGE_BASE(0) +  40)
0071 #define PCM186X_PLL_P_DIV       (PCM186X_PAGE_BASE(0) +  41)
0072 #define PCM186X_PLL_R_DIV       (PCM186X_PAGE_BASE(0) +  42)
0073 #define PCM186X_PLL_J_DIV       (PCM186X_PAGE_BASE(0) +  43)
0074 #define PCM186X_PLL_D_DIV_LSB       (PCM186X_PAGE_BASE(0) +  44)
0075 #define PCM186X_PLL_D_DIV_MSB       (PCM186X_PAGE_BASE(0) +  45)
0076 #define PCM186X_SIGDET_MODE     (PCM186X_PAGE_BASE(0) +  48)
0077 #define PCM186X_SIGDET_MASK     (PCM186X_PAGE_BASE(0) +  49)
0078 #define PCM186X_SIGDET_STAT     (PCM186X_PAGE_BASE(0) +  50)
0079 #define PCM186X_SIGDET_LOSS_TIME    (PCM186X_PAGE_BASE(0) +  52)
0080 #define PCM186X_SIGDET_SCAN_TIME    (PCM186X_PAGE_BASE(0) +  53)
0081 #define PCM186X_SIGDET_INT_INTVL    (PCM186X_PAGE_BASE(0) +  54)
0082 #define PCM186X_SIGDET_DC_REF_CH1_L (PCM186X_PAGE_BASE(0) +  64)
0083 #define PCM186X_SIGDET_DC_DIFF_CH1_L    (PCM186X_PAGE_BASE(0) +  65)
0084 #define PCM186X_SIGDET_DC_LEV_CH1_L (PCM186X_PAGE_BASE(0) +  66)
0085 #define PCM186X_SIGDET_DC_REF_CH1_R (PCM186X_PAGE_BASE(0) +  67)
0086 #define PCM186X_SIGDET_DC_DIFF_CH1_R    (PCM186X_PAGE_BASE(0) +  68)
0087 #define PCM186X_SIGDET_DC_LEV_CH1_R (PCM186X_PAGE_BASE(0) +  69)
0088 #define PCM186X_SIGDET_DC_REF_CH2_L (PCM186X_PAGE_BASE(0) +  70)
0089 #define PCM186X_SIGDET_DC_DIFF_CH2_L    (PCM186X_PAGE_BASE(0) +  71)
0090 #define PCM186X_SIGDET_DC_LEV_CH2_L (PCM186X_PAGE_BASE(0) +  72)
0091 #define PCM186X_SIGDET_DC_REF_CH2_R (PCM186X_PAGE_BASE(0) +  73)
0092 #define PCM186X_SIGDET_DC_DIFF_CH2_R    (PCM186X_PAGE_BASE(0) +  74)
0093 #define PCM186X_SIGDET_DC_LEV_CH2_R (PCM186X_PAGE_BASE(0) +  75)
0094 #define PCM186X_SIGDET_DC_REF_CH3_L (PCM186X_PAGE_BASE(0) +  76)
0095 #define PCM186X_SIGDET_DC_DIFF_CH3_L    (PCM186X_PAGE_BASE(0) +  77)
0096 #define PCM186X_SIGDET_DC_LEV_CH3_L (PCM186X_PAGE_BASE(0) +  78)
0097 #define PCM186X_SIGDET_DC_REF_CH3_R (PCM186X_PAGE_BASE(0) +  79)
0098 #define PCM186X_SIGDET_DC_DIFF_CH3_R    (PCM186X_PAGE_BASE(0) +  80)
0099 #define PCM186X_SIGDET_DC_LEV_CH3_R (PCM186X_PAGE_BASE(0) +  81)
0100 #define PCM186X_SIGDET_DC_REF_CH4_L (PCM186X_PAGE_BASE(0) +  82)
0101 #define PCM186X_SIGDET_DC_DIFF_CH4_L    (PCM186X_PAGE_BASE(0) +  83)
0102 #define PCM186X_SIGDET_DC_LEV_CH4_L (PCM186X_PAGE_BASE(0) +  84)
0103 #define PCM186X_SIGDET_DC_REF_CH4_R (PCM186X_PAGE_BASE(0) +  85)
0104 #define PCM186X_SIGDET_DC_DIFF_CH4_R    (PCM186X_PAGE_BASE(0) +  86)
0105 #define PCM186X_SIGDET_DC_LEV_CH4_R (PCM186X_PAGE_BASE(0) +  87)
0106 #define PCM186X_AUXADC_DATA_CTRL    (PCM186X_PAGE_BASE(0) +  88)
0107 #define PCM186X_AUXADC_DATA_LSB     (PCM186X_PAGE_BASE(0) +  89)
0108 #define PCM186X_AUXADC_DATA_MSB     (PCM186X_PAGE_BASE(0) +  90)
0109 #define PCM186X_INT_ENABLE      (PCM186X_PAGE_BASE(0) +  96)
0110 #define PCM186X_INT_FLAG        (PCM186X_PAGE_BASE(0) +  97)
0111 #define PCM186X_INT_POL_WIDTH       (PCM186X_PAGE_BASE(0) +  98)
0112 #define PCM186X_POWER_CTRL      (PCM186X_PAGE_BASE(0) + 112)
0113 #define PCM186X_FILTER_MUTE_CTRL    (PCM186X_PAGE_BASE(0) + 113)
0114 #define PCM186X_DEVICE_STATUS       (PCM186X_PAGE_BASE(0) + 114)
0115 #define PCM186X_FSAMPLE_STATUS      (PCM186X_PAGE_BASE(0) + 115)
0116 #define PCM186X_DIV_STATUS      (PCM186X_PAGE_BASE(0) + 116)
0117 #define PCM186X_CLK_STATUS      (PCM186X_PAGE_BASE(0) + 117)
0118 #define PCM186X_SUPPLY_STATUS       (PCM186X_PAGE_BASE(0) + 120)
0119
0120 /* Register Definitions - Page 1 */
0121 #define PCM186X_MMAP_STAT_CTRL      (PCM186X_PAGE_BASE(1) +   1)
0122 #define PCM186X_MMAP_ADDRESS        (PCM186X_PAGE_BASE(1) +   2)
0123 #define PCM186X_MEM_WDATA0      (PCM186X_PAGE_BASE(1) +   4)
0124 #define PCM186X_MEM_WDATA1      (PCM186X_PAGE_BASE(1) +   5)
0125 #define PCM186X_MEM_WDATA2      (PCM186X_PAGE_BASE(1) +   6)
0126 #define PCM186X_MEM_WDATA3      (PCM186X_PAGE_BASE(1) +   7)
0127 #define PCM186X_MEM_RDATA0      (PCM186X_PAGE_BASE(1) +   8)
0128 #define PCM186X_MEM_RDATA1      (PCM186X_PAGE_BASE(1) +   9)
0129 #define PCM186X_MEM_RDATA2      (PCM186X_PAGE_BASE(1) +  10)
0130 #define PCM186X_MEM_RDATA3      (PCM186X_PAGE_BASE(1) +  11)
0131
0132 /* Register Definitions - Page 3 */
0133 #define PCM186X_OSC_PWR_DOWN_CTRL   (PCM186X_PAGE_BASE(3) +  18)
0134 #define PCM186X_MIC_BIAS_CTRL       (PCM186X_PAGE_BASE(3) +  21)
0135
0136 /* Register Definitions - Page 253 */
0137 #define PCM186X_CURR_TRIM_CTRL      (PCM186X_PAGE_BASE(253) +  20)
0138
0139 #define PCM186X_MAX_REGISTER        PCM186X_CURR_TRIM_CTRL
0140
0141 /* PCM186X_PAGE */
0142 #define PCM186X_RESET           0xfe
0143
0144 /* PCM186X_ADCX_INPUT_SEL_X */
0145 #define PCM186X_ADC_INPUT_SEL_POL   BIT(7)
0146 #define PCM186X_ADC_INPUT_SEL_MASK  GENMASK(5, 0)
0147
0148 /* PCM186X_PCM_CFG */
0149 #define PCM186X_PCM_CFG_RX_WLEN_MASK    GENMASK(7, 6)
0150 #define PCM186X_PCM_CFG_RX_WLEN_SHIFT   6
0151 #define PCM186X_PCM_CFG_RX_WLEN_32  0x00
0152 #define PCM186X_PCM_CFG_RX_WLEN_24  0x01
0153 #define PCM186X_PCM_CFG_RX_WLEN_20  0x02
0154 #define PCM186X_PCM_CFG_RX_WLEN_16  0x03
0155 #define PCM186X_PCM_CFG_TDM_LRCK_MODE   BIT(4)
0156 #define PCM186X_PCM_CFG_TX_WLEN_MASK    GENMASK(3, 2)
0157 #define PCM186X_PCM_CFG_TX_WLEN_SHIFT   2
0158 #define PCM186X_PCM_CFG_TX_WLEN_32  0x00
0159 #define PCM186X_PCM_CFG_TX_WLEN_24  0x01
0160 #define PCM186X_PCM_CFG_TX_WLEN_20  0x02
0161 #define PCM186X_PCM_CFG_TX_WLEN_16  0x03
0162 #define PCM186X_PCM_CFG_FMT_MASK    GENMASK(1, 0)
0163 #define PCM186X_PCM_CFG_FMT_SHIFT   0
0164 #define PCM186X_PCM_CFG_FMT_I2S     0x00
0165 #define PCM186X_PCM_CFG_FMT_LEFTJ   0x01
0166 #define PCM186X_PCM_CFG_FMT_RIGHTJ  0x02
0167 #define PCM186X_PCM_CFG_FMT_TDM     0x03
0168
0169 /* PCM186X_TDM_TX_SEL */
0170 #define PCM186X_TDM_TX_SEL_2CH      0x00
0171 #define PCM186X_TDM_TX_SEL_4CH      0x01
0172 #define PCM186X_TDM_TX_SEL_6CH      0x02
0173 #define PCM186X_TDM_TX_SEL_MASK     0x03
0174
0175 /* PCM186X_CLK_CTRL */
0176 #define PCM186X_CLK_CTRL_SCK_XI_SEL1    BIT(7)
0177 #define PCM186X_CLK_CTRL_SCK_XI_SEL0    BIT(6)
0178 #define PCM186X_CLK_CTRL_SCK_SRC_PLL    BIT(5)
0179 #define PCM186X_CLK_CTRL_MST_MODE   BIT(4)
0180 #define PCM186X_CLK_CTRL_ADC_SRC_PLL    BIT(3)
0181 #define PCM186X_CLK_CTRL_DSP2_SRC_PLL   BIT(2)
0182 #define PCM186X_CLK_CTRL_DSP1_SRC_PLL   BIT(1)
0183 #define PCM186X_CLK_CTRL_CLKDET_EN  BIT(0)
0184
0185 /* PCM186X_PLL_CTRL */
0186 #define PCM186X_PLL_CTRL_LOCK       BIT(4)
0187 #define PCM186X_PLL_CTRL_REF_SEL    BIT(1)
0188 #define PCM186X_PLL_CTRL_EN     BIT(0)
0189
0190 /* PCM186X_POWER_CTRL */
0191 #define PCM186X_PWR_CTRL_PWRDN      BIT(2)
0192 #define PCM186X_PWR_CTRL_SLEEP      BIT(1)
0193 #define PCM186X_PWR_CTRL_STBY       BIT(0)
0194
0195 /* PCM186X_CLK_STATUS */
0196 #define PCM186X_CLK_STATUS_LRCKHLT  BIT(6)
0197 #define PCM186X_CLK_STATUS_BCKHLT   BIT(5)
0198 #define PCM186X_CLK_STATUS_SCKHLT   BIT(4)
0199 #define PCM186X_CLK_STATUS_LRCKERR  BIT(2)
0200 #define PCM186X_CLK_STATUS_BCKERR   BIT(1)
0201 #define PCM186X_CLK_STATUS_SCKERR   BIT(0)
0202
0203 /* PCM186X_SUPPLY_STATUS */
0204 #define PCM186X_SUPPLY_STATUS_DVDD  BIT(2)
0205 #define PCM186X_SUPPLY_STATUS_AVDD  BIT(1)
0206 #define PCM186X_SUPPLY_STATUS_LDO   BIT(0)
0207
0208 /* PCM186X_MMAP_STAT_CTRL */
0209 #define PCM186X_MMAP_STAT_DONE      BIT(4)
0210 #define PCM186X_MMAP_STAT_BUSY      BIT(2)
0211 #define PCM186X_MMAP_STAT_R_REQ     BIT(1)
0212 #define PCM186X_MMAP_STAT_W_REQ     BIT(0)
0213
0214 extern const struct regmap_config pcm186x_regmap;
0215
0216 int pcm186x_probe(struct device *dev, enum pcm186x_type type, int irq,
0217           struct regmap *regmap);
0218
0219 #endif /* _PCM186X_H_ */