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0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * NAU88L24 ALSA SoC audio driver
0004  *
0005  * Copyright 2016 Nuvoton Technology Corp.
0006  * Author: John Hsu <KCHSU0@nuvoton.com>
0007  */
0008 
0009 #ifndef __NAU8824_H__
0010 #define __NAU8824_H__
0011 
0012 #define NAU8824_REG_RESET           0x00
0013 #define NAU8824_REG_ENA_CTRL            0x01
0014 #define NAU8824_REG_CLK_GATING_ENA      0x02
0015 #define NAU8824_REG_CLK_DIVIDER     0x03
0016 #define NAU8824_REG_FLL1            0x04
0017 #define NAU8824_REG_FLL2            0x05
0018 #define NAU8824_REG_FLL3            0x06
0019 #define NAU8824_REG_FLL4            0x07
0020 #define NAU8824_REG_FLL5            0x08
0021 #define NAU8824_REG_FLL6            0x09
0022 #define NAU8824_REG_FLL_VCO_RSV     0x0A
0023 #define NAU8824_REG_JACK_DET_CTRL       0x0D
0024 #define NAU8824_REG_INTERRUPT_SETTING_1 0x0F
0025 #define NAU8824_REG_IRQ         0x10
0026 #define NAU8824_REG_CLEAR_INT_REG       0x11
0027 #define NAU8824_REG_INTERRUPT_SETTING   0x12
0028 #define NAU8824_REG_SAR_ADC         0x13
0029 #define NAU8824_REG_VDET_COEFFICIENT        0x14
0030 #define NAU8824_REG_VDET_THRESHOLD_1    0x15
0031 #define NAU8824_REG_VDET_THRESHOLD_2    0x16
0032 #define NAU8824_REG_VDET_THRESHOLD_3    0x17
0033 #define NAU8824_REG_VDET_THRESHOLD_4    0x18
0034 #define NAU8824_REG_GPIO_SEL            0x1A
0035 #define NAU8824_REG_PORT0_I2S_PCM_CTRL_1    0x1C
0036 #define NAU8824_REG_PORT0_I2S_PCM_CTRL_2    0x1D
0037 #define NAU8824_REG_PORT0_LEFT_TIME_SLOT    0x1E
0038 #define NAU8824_REG_PORT0_RIGHT_TIME_SLOT   0x1F
0039 #define NAU8824_REG_TDM_CTRL            0x20
0040 #define NAU8824_REG_ADC_HPF_FILTER      0x23
0041 #define NAU8824_REG_ADC_FILTER_CTRL     0x24
0042 #define NAU8824_REG_DAC_FILTER_CTRL_1   0x25
0043 #define NAU8824_REG_DAC_FILTER_CTRL_2   0x26
0044 #define NAU8824_REG_NOTCH_FILTER_1      0x27
0045 #define NAU8824_REG_NOTCH_FILTER_2      0x28
0046 #define NAU8824_REG_EQ1_LOW         0x29
0047 #define NAU8824_REG_EQ2_EQ3         0x2A
0048 #define NAU8824_REG_EQ4_EQ5         0x2B
0049 #define NAU8824_REG_ADC_CH0_DGAIN_CTRL  0x2D
0050 #define NAU8824_REG_ADC_CH1_DGAIN_CTRL  0x2E
0051 #define NAU8824_REG_ADC_CH2_DGAIN_CTRL  0x2F
0052 #define NAU8824_REG_ADC_CH3_DGAIN_CTRL  0x30
0053 #define NAU8824_REG_DAC_MUTE_CTRL       0x31
0054 #define NAU8824_REG_DAC_CH0_DGAIN_CTRL  0x32
0055 #define NAU8824_REG_DAC_CH1_DGAIN_CTRL  0x33
0056 #define NAU8824_REG_ADC_TO_DAC_ST       0x34
0057 #define NAU8824_REG_DRC_KNEE_IP12_ADC_CH01  0x38
0058 #define NAU8824_REG_DRC_KNEE_IP34_ADC_CH01  0x39
0059 #define NAU8824_REG_DRC_SLOPE_ADC_CH01  0x3A
0060 #define NAU8824_REG_DRC_ATKDCY_ADC_CH01 0x3B
0061 #define NAU8824_REG_DRC_KNEE_IP12_ADC_CH23  0x3C
0062 #define NAU8824_REG_DRC_KNEE_IP34_ADC_CH23  0x3D
0063 #define NAU8824_REG_DRC_SLOPE_ADC_CH23  0x3E
0064 #define NAU8824_REG_DRC_ATKDCY_ADC_CH23 0x3F
0065 #define NAU8824_REG_DRC_GAINL_ADC0      0x40
0066 #define NAU8824_REG_DRC_GAINL_ADC1      0x41
0067 #define NAU8824_REG_DRC_GAINL_ADC2      0x42
0068 #define NAU8824_REG_DRC_GAINL_ADC3      0x43
0069 #define NAU8824_REG_DRC_KNEE_IP12_DAC   0x45
0070 #define NAU8824_REG_DRC_KNEE_IP34_DAC   0x46
0071 #define NAU8824_REG_DRC_SLOPE_DAC       0x47
0072 #define NAU8824_REG_DRC_ATKDCY_DAC      0x48
0073 #define NAU8824_REG_DRC_GAIN_DAC_CH0    0x49
0074 #define NAU8824_REG_DRC_GAIN_DAC_CH1    0x4A
0075 #define NAU8824_REG_MODE            0x4C
0076 #define NAU8824_REG_MODE1           0x4D
0077 #define NAU8824_REG_MODE2           0x4E
0078 #define NAU8824_REG_CLASSG          0x50
0079 #define NAU8824_REG_OTP_EFUSE           0x51
0080 #define NAU8824_REG_OTPDOUT_1       0x53
0081 #define NAU8824_REG_OTPDOUT_2       0x54
0082 #define NAU8824_REG_MISC_CTRL           0x55
0083 #define NAU8824_REG_I2C_TIMEOUT     0x56
0084 #define NAU8824_REG_TEST_MODE       0x57
0085 #define NAU8824_REG_I2C_DEVICE_ID       0x58
0086 #define NAU8824_REG_SAR_ADC_DATA_OUT    0x59
0087 #define NAU8824_REG_BIAS_ADJ            0x66
0088 #define NAU8824_REG_PGA_GAIN            0x67
0089 #define NAU8824_REG_TRIM_SETTINGS       0x68
0090 #define NAU8824_REG_ANALOG_CONTROL_1    0x69
0091 #define NAU8824_REG_ANALOG_CONTROL_2    0x6A
0092 #define NAU8824_REG_ENABLE_LO           0x6B
0093 #define NAU8824_REG_GAIN_LO         0x6C
0094 #define NAU8824_REG_CLASSD_GAIN_1       0x6D
0095 #define NAU8824_REG_CLASSD_GAIN_2       0x6E
0096 #define NAU8824_REG_ANALOG_ADC_1        0x71
0097 #define NAU8824_REG_ANALOG_ADC_2        0x72
0098 #define NAU8824_REG_RDAC            0x73
0099 #define NAU8824_REG_MIC_BIAS            0x74
0100 #define NAU8824_REG_HS_VOLUME_CONTROL   0x75
0101 #define NAU8824_REG_BOOST           0x76
0102 #define NAU8824_REG_FEPGA           0x77
0103 #define NAU8824_REG_FEPGA_II            0x78
0104 #define NAU8824_REG_FEPGA_SE            0x79
0105 #define NAU8824_REG_FEPGA_ATTENUATION   0x7A
0106 #define NAU8824_REG_ATT_PORT0       0x7B
0107 #define NAU8824_REG_ATT_PORT1       0x7C
0108 #define NAU8824_REG_POWER_UP_CONTROL    0x7F
0109 #define NAU8824_REG_CHARGE_PUMP_CONTROL 0x80
0110 #define NAU8824_REG_CHARGE_PUMP_INPUT   0x81
0111 #define NAU8824_REG_MAX         NAU8824_REG_CHARGE_PUMP_INPUT
0112 /* 16-bit control register address, and 16-bits control register data */
0113 #define NAU8824_REG_ADDR_LEN        16
0114 #define NAU8824_REG_DATA_LEN        16
0115 
0116 
0117 /* ENA_CTRL (0x1) */
0118 #define NAU8824_DMIC_LCH_EDGE_CH23  (0x1 << 12)
0119 #define NAU8824_DMIC_LCH_EDGE_CH01  (0x1 << 11)
0120 #define NAU8824_JD_SLEEP_MODE       (0x1 << 10)
0121 #define NAU8824_ADC_CH3_DMIC_SFT    9
0122 #define NAU8824_ADC_CH3_DMIC_EN (0x1 << NAU8824_ADC_CH3_DMIC_SFT)
0123 #define NAU8824_ADC_CH2_DMIC_SFT    8
0124 #define NAU8824_ADC_CH2_DMIC_EN (0x1 << NAU8824_ADC_CH2_DMIC_SFT)
0125 #define NAU8824_ADC_CH1_DMIC_SFT    7
0126 #define NAU8824_ADC_CH1_DMIC_EN (0x1 << NAU8824_ADC_CH1_DMIC_SFT)
0127 #define NAU8824_ADC_CH0_DMIC_SFT    6
0128 #define NAU8824_ADC_CH0_DMIC_EN (0x1 << NAU8824_ADC_CH0_DMIC_SFT)
0129 #define NAU8824_DAC_CH1_EN      (0x1 << 5)
0130 #define NAU8824_DAC_CH0_EN      (0x1 << 4)
0131 #define NAU8824_ADC_CH3_EN      (0x1 << 3)
0132 #define NAU8824_ADC_CH2_EN      (0x1 << 2)
0133 #define NAU8824_ADC_CH1_EN      (0x1 << 1)
0134 #define NAU8824_ADC_CH0_EN      0x1
0135 
0136 /* CLK_GATING_ENA (0x02) */
0137 #define NAU8824_CLK_ADC_CH23_EN (0x1 << 15)
0138 #define NAU8824_CLK_ADC_CH01_EN (0x1 << 14)
0139 #define NAU8824_CLK_DAC_CH1_EN  (0x1 << 13)
0140 #define NAU8824_CLK_DAC_CH0_EN  (0x1 << 12)
0141 #define NAU8824_CLK_I2S_EN      (0x1 << 7)
0142 #define NAU8824_CLK_GAIN_EN     (0x1 << 5)
0143 #define NAU8824_CLK_SAR_EN      (0x1 << 3)
0144 #define NAU8824_CLK_DMIC_CH23_EN    (0x1 << 1)
0145 
0146 /* CLK_DIVIDER (0x3) */
0147 #define NAU8824_CLK_SRC_SFT     15
0148 #define NAU8824_CLK_SRC_MASK        (1 << NAU8824_CLK_SRC_SFT)
0149 #define NAU8824_CLK_SRC_VCO     (1 << NAU8824_CLK_SRC_SFT)
0150 #define NAU8824_CLK_SRC_MCLK        (0 << NAU8824_CLK_SRC_SFT)
0151 #define NAU8824_CLK_MCLK_SRC_MASK   (0xf << 0)
0152 #define NAU8824_CLK_DMIC_SRC_SFT    10
0153 #define NAU8824_CLK_DMIC_SRC_MASK   (0x7 << NAU8824_CLK_DMIC_SRC_SFT)
0154 #define NAU8824_CLK_ADC_SRC_SFT 6
0155 #define NAU8824_CLK_ADC_SRC_MASK    (0x3 << NAU8824_CLK_ADC_SRC_SFT)
0156 #define NAU8824_CLK_DAC_SRC_SFT 4
0157 #define NAU8824_CLK_DAC_SRC_MASK    (0x3 << NAU8824_CLK_DAC_SRC_SFT)
0158 
0159 /* FLL1 (0x04) */
0160 #define NAU8824_FLL_RATIO_MASK  (0x7f << 0)
0161 
0162 /* FLL3 (0x06) */
0163 #define NAU8824_FLL_INTEGER_MASK    (0x3ff << 0)
0164 #define NAU8824_FLL_CLK_SRC_SFT 10
0165 #define NAU8824_FLL_CLK_SRC_MASK    (0x3 << NAU8824_FLL_CLK_SRC_SFT)
0166 #define NAU8824_FLL_CLK_SRC_MCLK    (0 << NAU8824_FLL_CLK_SRC_SFT)
0167 #define NAU8824_FLL_CLK_SRC_BLK (0x2 << NAU8824_FLL_CLK_SRC_SFT)
0168 #define NAU8824_FLL_CLK_SRC_FS      (0x3 << NAU8824_FLL_CLK_SRC_SFT)
0169 
0170 /* FLL4 (0x07) */
0171 #define NAU8824_FLL_REF_DIV_SFT 10
0172 #define NAU8824_FLL_REF_DIV_MASK    (0x3 << NAU8824_FLL_REF_DIV_SFT)
0173 
0174 /* FLL5 (0x08) */
0175 #define NAU8824_FLL_PDB_DAC_EN  (0x1 << 15)
0176 #define NAU8824_FLL_LOOP_FTR_EN (0x1 << 14)
0177 #define NAU8824_FLL_CLK_SW_MASK (0x1 << 13)
0178 #define NAU8824_FLL_CLK_SW_N2       (0x1 << 13)
0179 #define NAU8824_FLL_CLK_SW_REF  (0x0 << 13)
0180 #define NAU8824_FLL_FTR_SW_MASK (0x1 << 12)
0181 #define NAU8824_FLL_FTR_SW_ACCU (0x1 << 12)
0182 #define NAU8824_FLL_FTR_SW_FILTER   (0x0 << 12)
0183 
0184 /* FLL6 (0x9) */
0185 #define NAU8824_DCO_EN          (0x1 << 15)
0186 #define NAU8824_SDM_EN          (0x1 << 14)
0187 
0188 /* IRQ (0x10) */
0189 #define NAU8824_SHORT_CIRCUIT_IRQ       (0x1 << 7)
0190 #define NAU8824_IMPEDANCE_MEAS_IRQ      (0x1 << 6)
0191 #define NAU8824_KEY_RELEASE_IRQ     (0x1 << 5)
0192 #define NAU8824_KEY_LONG_PRESS_IRQ      (0x1 << 4)
0193 #define NAU8824_KEY_SHORT_PRESS_IRQ     (0x1 << 3)
0194 #define NAU8824_JACK_EJECTION_DETECTED  (0x1 << 1)
0195 #define NAU8824_JACK_INSERTION_DETECTED 0x1
0196 
0197 /* JACK_DET_CTRL (0x0D) */
0198 #define NAU8824_JACK_EJECT_DT_SFT   2
0199 #define NAU8824_JACK_EJECT_DT_MASK (0x3 << NAU8824_JACK_EJECT_DT_SFT)
0200 #define NAU8824_JACK_LOGIC      (0x1 << 1)
0201 
0202 
0203 /* INTERRUPT_SETTING_1 (0x0F) */
0204 #define NAU8824_IRQ_EJECT_EN        (0x1 << 9)
0205 #define NAU8824_IRQ_INSERT_EN       (0x1 << 8)
0206 
0207 /* INTERRUPT_SETTING (0x12) */
0208 #define NAU8824_IRQ_KEY_RELEASE_DIS     (0x1 << 5)
0209 #define NAU8824_IRQ_KEY_SHORT_PRESS_DIS (0x1 << 3)
0210 #define NAU8824_IRQ_EJECT_DIS           (0x1 << 1)
0211 #define NAU8824_IRQ_INSERT_DIS      0x1
0212 
0213 /* SAR_ADC (0x13) */
0214 #define NAU8824_SAR_ADC_EN_SFT      12
0215 #define NAU8824_SAR_TRACKING_GAIN_SFT   8
0216 #define NAU8824_SAR_TRACKING_GAIN_MASK  (0x7 << NAU8824_SAR_TRACKING_GAIN_SFT)
0217 #define NAU8824_SAR_COMPARE_TIME_SFT    2
0218 #define NAU8824_SAR_COMPARE_TIME_MASK   (3 << 2)
0219 #define NAU8824_SAR_SAMPLING_TIME_SFT   0
0220 #define NAU8824_SAR_SAMPLING_TIME_MASK  (3 << 0)
0221 
0222 /* VDET_COEFFICIENT (0x14) */
0223 #define NAU8824_SHORTKEY_DEBOUNCE_SFT   12
0224 #define NAU8824_SHORTKEY_DEBOUNCE_MASK  (0x3 << NAU8824_SHORTKEY_DEBOUNCE_SFT)
0225 #define NAU8824_LEVELS_NR_SFT           8
0226 #define NAU8824_LEVELS_NR_MASK      (0x7 << 8)
0227 #define NAU8824_HYSTERESIS_SFT      0
0228 #define NAU8824_HYSTERESIS_MASK     0xf
0229 
0230 /* PORT0_I2S_PCM_CTRL_1 (0x1C) */
0231 #define NAU8824_I2S_BP_SFT      7
0232 #define NAU8824_I2S_BP_MASK     (1 << NAU8824_I2S_BP_SFT)
0233 #define NAU8824_I2S_BP_INV      (1 << NAU8824_I2S_BP_SFT)
0234 #define NAU8824_I2S_PCMB_SFT        6
0235 #define NAU8824_I2S_PCMB_EN     (1 << NAU8824_I2S_PCMB_SFT)
0236 #define NAU8824_I2S_DL_SFT      2
0237 #define NAU8824_I2S_DL_MASK     (0x3 << NAU8824_I2S_DL_SFT)
0238 #define NAU8824_I2S_DL_16       (0 << NAU8824_I2S_DL_SFT)
0239 #define NAU8824_I2S_DL_20       (1 << NAU8824_I2S_DL_SFT)
0240 #define NAU8824_I2S_DL_24       (2 << NAU8824_I2S_DL_SFT)
0241 #define NAU8824_I2S_DL_32       (3 << NAU8824_I2S_DL_SFT)
0242 #define NAU8824_I2S_DF_MASK     0x3
0243 #define NAU8824_I2S_DF_RIGTH        0
0244 #define NAU8824_I2S_DF_LEFT     1
0245 #define NAU8824_I2S_DF_I2S      2
0246 #define NAU8824_I2S_DF_PCM_AB       3
0247 
0248 
0249 /* PORT0_I2S_PCM_CTRL_2 (0x1D) */
0250 #define NAU8824_I2S_LRC_DIV_SFT 12
0251 #define NAU8824_I2S_LRC_DIV_MASK    (0x3 << NAU8824_I2S_LRC_DIV_SFT)
0252 #define NAU8824_I2S_MS_SFT      3
0253 #define NAU8824_I2S_MS_MASK     (1 << NAU8824_I2S_MS_SFT)
0254 #define NAU8824_I2S_MS_MASTER       (1 << NAU8824_I2S_MS_SFT)
0255 #define NAU8824_I2S_MS_SLAVE        (0 << NAU8824_I2S_MS_SFT)
0256 #define NAU8824_I2S_BLK_DIV_MASK    0x7
0257 
0258 /* PORT0_LEFT_TIME_SLOT (0x1E) */
0259 #define NAU8824_TSLOT_L_MASK    0x3ff
0260 
0261 /* TDM_CTRL (0x20) */
0262 #define NAU8824_TDM_MODE        (0x1 << 15)
0263 #define NAU8824_TDM_OFFSET_EN       (0x1 << 14)
0264 #define NAU8824_TDM_DACL_RX_SFT 6
0265 #define NAU8824_TDM_DACL_RX_MASK    (0x3 << NAU8824_TDM_DACL_RX_SFT)
0266 #define NAU8824_TDM_DACR_RX_SFT 4
0267 #define NAU8824_TDM_DACR_RX_MASK    (0x3 << NAU8824_TDM_DACR_RX_SFT)
0268 #define NAU8824_TDM_TX_MASK     0xf
0269 
0270 /* ADC_FILTER_CTRL (0x24) */
0271 #define NAU8824_ADC_SYNC_DOWN_MASK  0x3
0272 #define NAU8824_ADC_SYNC_DOWN_32    0
0273 #define NAU8824_ADC_SYNC_DOWN_64    1
0274 #define NAU8824_ADC_SYNC_DOWN_128   2
0275 #define NAU8824_ADC_SYNC_DOWN_256   3
0276 
0277 /* DAC_FILTER_CTRL_1 (0x25) */
0278 #define NAU8824_DAC_CICCLP_OFF  (0x1 << 7)
0279 #define NAU8824_DAC_OVERSAMPLE_MASK 0x7
0280 #define NAU8824_DAC_OVERSAMPLE_64   0
0281 #define NAU8824_DAC_OVERSAMPLE_256  1
0282 #define NAU8824_DAC_OVERSAMPLE_128  2
0283 #define NAU8824_DAC_OVERSAMPLE_32   4
0284 
0285 /* DAC_MUTE_CTRL (0x31) */
0286 #define NAU8824_DAC_CH01_MIX        0x3
0287 #define NAU8824_DAC_ZC_EN       (0x1 << 11)
0288 
0289 /* DAC_CH0_DGAIN_CTRL (0x32) */
0290 #define NAU8824_DAC_CH0_SEL_SFT 9
0291 #define NAU8824_DAC_CH0_SEL_MASK    (0x1 << NAU8824_DAC_CH0_SEL_SFT)
0292 #define NAU8824_DAC_CH0_SEL_I2S0    (0x0 << NAU8824_DAC_CH0_SEL_SFT)
0293 #define NAU8824_DAC_CH0_SEL_I2S1    (0x1 << NAU8824_DAC_CH0_SEL_SFT)
0294 #define NAU8824_DAC_CH0_VOL_MASK    0x1ff
0295 
0296 /* DAC_CH1_DGAIN_CTRL (0x33) */
0297 #define NAU8824_DAC_CH1_SEL_SFT 9
0298 #define NAU8824_DAC_CH1_SEL_MASK    (0x1 << NAU8824_DAC_CH1_SEL_SFT)
0299 #define NAU8824_DAC_CH1_SEL_I2S0    (0x0 << NAU8824_DAC_CH1_SEL_SFT)
0300 #define NAU8824_DAC_CH1_SEL_I2S1    (0x1 << NAU8824_DAC_CH1_SEL_SFT)
0301 #define NAU8824_DAC_CH1_VOL_MASK    0x1ff
0302 
0303 /* CLASSG (0x50) */
0304 #define NAU8824_CLASSG_TIMER_SFT    8
0305 #define NAU8824_CLASSG_TIMER_MASK   (0x3f << NAU8824_CLASSG_TIMER_SFT)
0306 #define NAU8824_CLASSG_LDAC_EN_SFT  2
0307 #define NAU8824_CLASSG_RDAC_EN_SFT  1
0308 #define NAU8824_CLASSG_EN_SFT       0
0309 
0310 /* SAR_ADC_DATA_OUT (0x59) */
0311 #define NAU8824_SAR_ADC_DATA_MASK   0xff
0312 
0313 /* BIAS_ADJ (0x66) */
0314 #define NAU8824_VMID            (1 << 6)
0315 #define NAU8824_VMID_SEL_SFT        4
0316 #define NAU8824_VMID_SEL_MASK       (3 << NAU8824_VMID_SEL_SFT)
0317 #define NAU8824_DMIC2_EN_SFT        3
0318 #define NAU8824_DMIC1_EN_SFT        2
0319 
0320 /* TRIM_SETTINGS (0x68) */
0321 #define NAU8824_DRV_CURR_INC        (1 << 15)
0322 
0323 /* ANALOG_CONTROL_1 (0x69) */
0324 #define NAU8824_DMIC_CLK_DRV_STRG   (1 << 3)
0325 #define NAU8824_DMIC_CLK_SLEW_FAST  (0x7)
0326 
0327 /* ANALOG_CONTROL_2 (0x6A) */
0328 #define NAU8824_CLASSD_CLAMP_DIS_SFT    3
0329 #define NAU8824_CLASSD_CLAMP_DIS    (0x1 << NAU8824_CLASSD_CLAMP_DIS_SFT)
0330 
0331 /* ENABLE_LO (0x6B) */
0332 #define NAU8824_TEST_DAC_SFT        14
0333 #define NAU8824_TEST_DAC_EN     (0x3 << NAU8824_TEST_DAC_SFT)
0334 #define NAU8824_DACL_HPR_EN_SFT 3
0335 #define NAU8824_DACL_HPR_EN     (0x1 << NAU8824_DACL_HPR_EN_SFT)
0336 #define NAU8824_DACR_HPR_EN_SFT 2
0337 #define NAU8824_DACR_HPR_EN     (0x1 << NAU8824_DACR_HPR_EN_SFT)
0338 #define NAU8824_DACR_HPL_EN_SFT 1
0339 #define NAU8824_DACR_HPL_EN     (0x1 << NAU8824_DACR_HPL_EN_SFT)
0340 #define NAU8824_DACL_HPL_EN_SFT 0
0341 #define NAU8824_DACL_HPL_EN     0x1
0342 
0343 /* CLASSD_GAIN_1 (0x6D) */
0344 #define NAU8824_CLASSD_GAIN_1R_SFT  8
0345 #define NAU8824_CLASSD_GAIN_1R_MASK (0x1f << NAU8824_CLASSD_GAIN_1R_SFT)
0346 #define NAU8824_CLASSD_EN_SFT       7
0347 #define NAU8824_CLASSD_EN       (0x1 << NAU8824_CLASSD_EN_SFT)
0348 #define NAU8824_CLASSD_GAIN_1L_MASK 0x1f
0349 
0350 /* CLASSD_GAIN_2 (0x6E) */
0351 #define NAU8824_CLASSD_GAIN_2R_SFT  8
0352 #define NAU8824_CLASSD_GAIN_2R_MASK (0x1f << NAU8824_CLASSD_GAIN_1R_SFT)
0353 #define NAU8824_CLASSD_EN_SFT       7
0354 #define NAU8824_CLASSD_EN       (0x1 << NAU8824_CLASSD_EN_SFT)
0355 #define NAU8824_CLASSD_GAIN_2L_MASK 0x1f
0356 
0357 /* ANALOG_ADC_2 (0x72) */
0358 #define NAU8824_ADCR_EN_SFT     7
0359 #define NAU8824_ADCL_EN_SFT     6
0360 
0361 /* RDAC (0x73) */
0362 #define NAU8824_DACR_EN_SFT     13
0363 #define NAU8824_DACL_EN_SFT     12
0364 #define NAU8824_DACR_CLK_SFT        9
0365 #define NAU8824_DACL_CLK_SFT        8
0366 #define NAU8824_RDAC_CLK_DELAY_SFT  4
0367 #define NAU8824_RDAC_CLK_DELAY_MASK (0x7 << NAU8824_RDAC_CLK_DELAY_SFT)
0368 #define NAU8824_RDAC_VREF_SFT       2
0369 #define NAU8824_RDAC_VREF_MASK  (0x3 << NAU8824_RDAC_VREF_SFT)
0370 
0371 /* MIC_BIAS (0x74) */
0372 #define NAU8824_MICBIAS_JKSLV       (1 << 14)
0373 #define NAU8824_MICBIAS_JKR2        (1 << 12)
0374 #define NAU8824_MICBIAS_POWERUP_SFT 8
0375 #define NAU8824_MICBIAS_VOLTAGE_SFT 0
0376 #define NAU8824_MICBIAS_VOLTAGE_MASK    0x7
0377 
0378 /* BOOST (0x76) */
0379 #define NAU8824_PRECHARGE_DIS           (0x1 << 13)
0380 #define NAU8824_GLOBAL_BIAS_EN      (0x1 << 12)
0381 #define NAU8824_HP_BOOST_DIS_SFT        9
0382 #define NAU8824_HP_BOOST_DIS        (0x1 << NAU8824_HP_BOOST_DIS_SFT)
0383 #define NAU8824_HP_BOOST_G_DIS_SFT      8
0384 #define NAU8824_HP_BOOST_G_DIS      (0x1 << NAU8824_HP_BOOST_G_DIS_SFT)
0385 #define NAU8824_SHORT_SHUTDOWN_DIG_EN   (1 << 7)
0386 #define NAU8824_SHORT_SHUTDOWN_EN       (1 << 6)
0387 
0388 /* FEPGA (0x77) */
0389 #define NAU8824_FEPGA_MODER_SHORT_SFT   7
0390 #define NAU8824_FEPGA_MODER_SHORT_EN    (0x1 << NAU8824_FEPGA_MODER_SHORT_SFT)
0391 #define NAU8824_FEPGA_MODER_MIC2_SFT        5
0392 #define NAU8824_FEPGA_MODER_MIC2_EN (0x1 << NAU8824_FEPGA_MODER_MIC2_SFT)
0393 #define NAU8824_FEPGA_MODER_HSMIC_SFT   4
0394 #define NAU8824_FEPGA_MODER_HSMIC_EN    (0x1 << NAU8824_FEPGA_MODER_HSMIC_SFT)
0395 #define NAU8824_FEPGA_MODEL_SHORT_SFT   3
0396 #define NAU8824_FEPGA_MODEL_SHORT_EN    (0x1 << NAU8824_FEPGA_MODEL_SHORT_SFT)
0397 #define NAU8824_FEPGA_MODEL_MIC1_SFT        1
0398 #define NAU8824_FEPGA_MODEL_MIC1_EN (0x1 << NAU8824_FEPGA_MODEL_MIC1_SFT)
0399 #define NAU8824_FEPGA_MODEL_HSMIC_SFT   0
0400 #define NAU8824_FEPGA_MODEL_HSMIC_EN    (0x1 << NAU8824_FEPGA_MODEL_HSMIC_SFT)
0401 
0402 /* FEPGA_II (0x78) */
0403 #define NAU8824_FEPGA_GAINR_SFT 5
0404 #define NAU8824_FEPGA_GAINR_MASK    (0x1f << NAU8824_FEPGA_GAINR_SFT)
0405 #define NAU8824_FEPGA_GAINL_SFT 0
0406 #define NAU8824_FEPGA_GAINL_MASK    0x1f
0407 
0408 /* CHARGE_PUMP_CONTROL (0x80) */
0409 #define NAU8824_JAMNODCLOW      (0x1 << 15)
0410 #define NAU8824_SPKR_PULL_DOWN  (0x1 << 13)
0411 #define NAU8824_SPKL_PULL_DOWN  (0x1 << 12)
0412 #define NAU8824_POWER_DOWN_DACR (0x1 << 9)
0413 #define NAU8824_POWER_DOWN_DACL (0x1 << 8)
0414 #define NAU8824_CHARGE_PUMP_EN_SFT  5
0415 #define NAU8824_CHARGE_PUMP_EN  (0x1 << NAU8824_CHARGE_PUMP_EN_SFT)
0416 
0417 
0418 #define NAU8824_CODEC_DAI "nau8824-hifi"
0419 
0420 /* System Clock Source */
0421 enum {
0422     NAU8824_CLK_DIS,
0423     NAU8824_CLK_MCLK,
0424     NAU8824_CLK_INTERNAL,
0425     NAU8824_CLK_FLL_MCLK,
0426     NAU8824_CLK_FLL_BLK,
0427     NAU8824_CLK_FLL_FS,
0428 };
0429 
0430 struct nau8824 {
0431     struct device *dev;
0432     struct regmap *regmap;
0433     struct snd_soc_dapm_context *dapm;
0434     struct snd_soc_jack *jack;
0435     struct work_struct jdet_work;
0436     struct semaphore jd_sem;
0437     int fs;
0438     int irq;
0439     int resume_lock;
0440     int micbias_voltage;
0441     int vref_impedance;
0442     int jkdet_polarity;
0443     int sar_threshold_num;
0444     int sar_threshold[8];
0445     int sar_hysteresis;
0446     int sar_voltage;
0447     int sar_compare_time;
0448     int sar_sampling_time;
0449     int key_debounce;
0450     int jack_eject_debounce;
0451 };
0452 
0453 struct nau8824_fll {
0454     int mclk_src;
0455     int ratio;
0456     int fll_frac;
0457     int fll_int;
0458     int clk_ref_div;
0459 };
0460 
0461 struct nau8824_fll_attr {
0462     unsigned int param;
0463     unsigned int val;
0464 };
0465 
0466 struct nau8824_osr_attr {
0467     unsigned int osr;
0468     unsigned int clk_src;
0469 };
0470 
0471 
0472 int nau8824_enable_jack_detect(struct snd_soc_component *component,
0473     struct snd_soc_jack *jack);
0474 const char *nau8824_components(void);
0475 
0476 #endif              /* _NAU8824_H */
0477
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