soc/codecs/nau8822.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * nau8822.h  --  NAU8822 ALSA SoC Audio driver
0004  *
0005  * Copyright 2017 Nuvoton Technology Crop.
0006  *
0007  * Author: David Lin <ctlin0@nuvoton.com>
0008  * Co-author: John Hsu <kchsu0@nuvoton.com>
0009  * Co-author: Seven Li <wtli@nuvoton.com>
0010  */
0011
0012 #ifndef __NAU8822_H__
0013 #define __NAU8822_H__
0014
0015 #define NAU8822_REG_RESET           0x00
0016 #define NAU8822_REG_POWER_MANAGEMENT_1      0x01
0017 #define NAU8822_REG_POWER_MANAGEMENT_2      0x02
0018 #define NAU8822_REG_POWER_MANAGEMENT_3      0x03
0019 #define NAU8822_REG_AUDIO_INTERFACE     0x04
0020 #define NAU8822_REG_COMPANDING_CONTROL      0x05
0021 #define NAU8822_REG_CLOCKING            0x06
0022 #define NAU8822_REG_ADDITIONAL_CONTROL      0x07
0023 #define NAU8822_REG_GPIO_CONTROL        0x08
0024 #define NAU8822_REG_JACK_DETECT_CONTROL_1   0x09
0025 #define NAU8822_REG_DAC_CONTROL         0x0A
0026 #define NAU8822_REG_LEFT_DAC_DIGITAL_VOLUME 0x0B
0027 #define NAU8822_REG_RIGHT_DAC_DIGITAL_VOLUME    0x0C
0028 #define NAU8822_REG_JACK_DETECT_CONTROL_2   0x0D
0029 #define NAU8822_REG_ADC_CONTROL         0x0E
0030 #define NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME 0x0F
0031 #define NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME    0x10
0032 #define NAU8822_REG_EQ1             0x12
0033 #define NAU8822_REG_EQ2             0x13
0034 #define NAU8822_REG_EQ3             0x14
0035 #define NAU8822_REG_EQ4             0x15
0036 #define NAU8822_REG_EQ5             0x16
0037 #define NAU8822_REG_DAC_LIMITER_1       0x18
0038 #define NAU8822_REG_DAC_LIMITER_2       0x19
0039 #define NAU8822_REG_NOTCH_FILTER_1      0x1B
0040 #define NAU8822_REG_NOTCH_FILTER_2      0x1C
0041 #define NAU8822_REG_NOTCH_FILTER_3      0x1D
0042 #define NAU8822_REG_NOTCH_FILTER_4      0x1E
0043 #define NAU8822_REG_ALC_CONTROL_1       0x20
0044 #define NAU8822_REG_ALC_CONTROL_2       0x21
0045 #define NAU8822_REG_ALC_CONTROL_3       0x22
0046 #define NAU8822_REG_NOISE_GATE          0x23
0047 #define NAU8822_REG_PLL_N           0x24
0048 #define NAU8822_REG_PLL_K1          0x25
0049 #define NAU8822_REG_PLL_K2          0x26
0050 #define NAU8822_REG_PLL_K3          0x27
0051 #define NAU8822_REG_3D_CONTROL          0x29
0052 #define NAU8822_REG_RIGHT_SPEAKER_CONTROL   0x2B
0053 #define NAU8822_REG_INPUT_CONTROL       0x2C
0054 #define NAU8822_REG_LEFT_INP_PGA_CONTROL    0x2D
0055 #define NAU8822_REG_RIGHT_INP_PGA_CONTROL   0x2E
0056 #define NAU8822_REG_LEFT_ADC_BOOST_CONTROL  0x2F
0057 #define NAU8822_REG_RIGHT_ADC_BOOST_CONTROL 0x30
0058 #define NAU8822_REG_OUTPUT_CONTROL      0x31
0059 #define NAU8822_REG_LEFT_MIXER_CONTROL      0x32
0060 #define NAU8822_REG_RIGHT_MIXER_CONTROL     0x33
0061 #define NAU8822_REG_LHP_VOLUME          0x34
0062 #define NAU8822_REG_RHP_VOLUME          0x35
0063 #define NAU8822_REG_LSPKOUT_VOLUME      0x36
0064 #define NAU8822_REG_RSPKOUT_VOLUME      0x37
0065 #define NAU8822_REG_AUX2_MIXER          0x38
0066 #define NAU8822_REG_AUX1_MIXER          0x39
0067 #define NAU8822_REG_POWER_MANAGEMENT_4      0x3A
0068 #define NAU8822_REG_LEFT_TIME_SLOT      0x3B
0069 #define NAU8822_REG_MISC            0x3C
0070 #define NAU8822_REG_RIGHT_TIME_SLOT     0x3D
0071 #define NAU8822_REG_DEVICE_REVISION     0x3E
0072 #define NAU8822_REG_DEVICE_ID           0x3F
0073 #define NAU8822_REG_DAC_DITHER          0x41
0074 #define NAU8822_REG_ALC_ENHANCE_1       0x46
0075 #define NAU8822_REG_ALC_ENHANCE_2       0x47
0076 #define NAU8822_REG_192KHZ_SAMPLING     0x48
0077 #define NAU8822_REG_MISC_CONTROL        0x49
0078 #define NAU8822_REG_INPUT_TIEOFF        0x4A
0079 #define NAU8822_REG_POWER_REDUCTION     0x4B
0080 #define NAU8822_REG_AGC_PEAK2PEAK       0x4C
0081 #define NAU8822_REG_AGC_PEAK_DETECT     0x4D
0082 #define NAU8822_REG_AUTOMUTE_CONTROL        0x4E
0083 #define NAU8822_REG_OUTPUT_TIEOFF       0x4F
0084 #define NAU8822_REG_MAX_REGISTER        NAU8822_REG_OUTPUT_TIEOFF
0085
0086 /* NAU8822_REG_POWER_MANAGEMENT_1 (0x1) */
0087 #define NAU8822_REFIMP_MASK         0x3
0088 #define NAU8822_REFIMP_80K          0x1
0089 #define NAU8822_REFIMP_300K         0x2
0090 #define NAU8822_REFIMP_3K           0x3
0091 #define NAU8822_IOBUF_EN            (0x1 << 2)
0092 #define NAU8822_ABIAS_EN            (0x1 << 3)
0093 #define NAU8822_PLL_EN_MASK         (0x1 << 5)
0094 #define NAU8822_PLL_ON              (0x1 << 5)
0095 #define NAU8822_PLL_OFF             (0x0 << 5)
0096
0097 /* NAU8822_REG_AUDIO_INTERFACE (0x4) */
0098 #define NAU8822_AIFMT_MASK          (0x3 << 3)
0099 #define NAU8822_WLEN_MASK           (0x3 << 5)
0100 #define NAU8822_WLEN_20             (0x1 << 5)
0101 #define NAU8822_WLEN_24             (0x2 << 5)
0102 #define NAU8822_WLEN_32             (0x3 << 5)
0103 #define NAU8822_LRP_MASK            (0x1 << 7)
0104 #define NAU8822_BCLKP_MASK          (0x1 << 8)
0105
0106 /* NAU8822_REG_COMPANDING_CONTROL (0x5) */
0107 #define NAU8822_ADDAP_SFT           0
0108 #define NAU8822_ADCCM_SFT           1
0109 #define NAU8822_DACCM_SFT           3
0110
0111 /* NAU8822_REG_CLOCKING (0x6) */
0112 #define NAU8822_CLKIOEN_MASK            0x1
0113 #define NAU8822_CLK_MASTER          0x1
0114 #define NAU8822_CLK_SLAVE           0x0
0115 #define NAU8822_MCLKSEL_SFT         5
0116 #define NAU8822_MCLKSEL_MASK            (0x7 << 5)
0117 #define NAU8822_BCLKSEL_SFT         2
0118 #define NAU8822_BCLKSEL_MASK            (0x7 << 2)
0119 #define NAU8822_BCLKDIV_1           (0x0 << 2)
0120 #define NAU8822_BCLKDIV_2           (0x1 << 2)
0121 #define NAU8822_BCLKDIV_4           (0x2 << 2)
0122 #define NAU8822_BCLKDIV_8           (0x3 << 2)
0123 #define NAU8822_BCLKDIV_16          (0x4 << 2)
0124 #define NAU8822_CLKM_MASK           (0x1 << 8)
0125 #define NAU8822_CLKM_MCLK           (0x0 << 8)
0126 #define NAU8822_CLKM_PLL            (0x1 << 8)
0127
0128 /* NAU8822_REG_ADDITIONAL_CONTROL (0x08) */
0129 #define NAU8822_SMPLR_SFT           1
0130 #define NAU8822_SMPLR_MASK          (0x7 << 1)
0131 #define NAU8822_SMPLR_48K           (0x0 << 1)
0132 #define NAU8822_SMPLR_32K           (0x1 << 1)
0133 #define NAU8822_SMPLR_24K           (0x2 << 1)
0134 #define NAU8822_SMPLR_16K           (0x3 << 1)
0135 #define NAU8822_SMPLR_12K           (0x4 << 1)
0136 #define NAU8822_SMPLR_8K            (0x5 << 1)
0137
0138 /* NAU8822_REG_EQ1 (0x12) */
0139 #define NAU8822_EQ1GC_SFT           0
0140 #define NAU8822_EQ1CF_SFT           5
0141 #define NAU8822_EQM_SFT             8
0142
0143 /* NAU8822_REG_EQ2 (0x13) */
0144 #define NAU8822_EQ2GC_SFT           0
0145 #define NAU8822_EQ2CF_SFT           5
0146 #define NAU8822_EQ2BW_SFT           8
0147
0148 /* NAU8822_REG_EQ3 (0x14) */
0149 #define NAU8822_EQ3GC_SFT           0
0150 #define NAU8822_EQ3CF_SFT           5
0151 #define NAU8822_EQ3BW_SFT           8
0152
0153 /* NAU8822_REG_EQ4 (0x15) */
0154 #define NAU8822_EQ4GC_SFT           0
0155 #define NAU8822_EQ4CF_SFT           5
0156 #define NAU8822_EQ4BW_SFT           8
0157
0158 /* NAU8822_REG_EQ5 (0x16) */
0159 #define NAU8822_EQ5GC_SFT           0
0160 #define NAU8822_EQ5CF_SFT           5
0161
0162 /* NAU8822_REG_ALC_CONTROL_1 (0x20) */
0163 #define NAU8822_ALCMINGAIN_SFT          0
0164 #define NAU8822_ALCMXGAIN_SFT           3
0165 #define NAU8822_ALCEN_SFT           7
0166
0167 /* NAU8822_REG_ALC_CONTROL_2 (0x21) */
0168 #define NAU8822_ALCSL_SFT           0
0169 #define NAU8822_ALCHT_SFT           4
0170
0171 /* NAU8822_REG_ALC_CONTROL_3 (0x22) */
0172 #define NAU8822_ALCATK_SFT          0
0173 #define NAU8822_ALCDCY_SFT          4
0174 #define NAU8822_ALCM_SFT            8
0175
0176 /* NAU8822_REG_PLL_N (0x24) */
0177 #define NAU8822_PLLMCLK_DIV2            (0x1 << 4)
0178 #define NAU8822_PLLN_MASK           0xF
0179
0180 #define NAU8822_PLLK1_SFT           18
0181 #define NAU8822_PLLK1_MASK          0x3F
0182
0183 /* NAU8822_REG_PLL_K2 (0x26) */
0184 #define NAU8822_PLLK2_SFT           9
0185 #define NAU8822_PLLK2_MASK          0x1FF
0186
0187 /* NAU8822_REG_PLL_K3 (0x27) */
0188 #define NAU8822_PLLK3_MASK          0x1FF
0189
0190 /* System Clock Source */
0191 enum {
0192     NAU8822_CLK_MCLK,
0193     NAU8822_CLK_PLL,
0194 };
0195
0196 struct nau8822_pll {
0197     int pre_factor;
0198     int mclk_scaler;
0199     int pll_frac;
0200     int pll_int;
0201     int freq_in;
0202     int freq_out;
0203 };
0204
0205 /* Codec Private Data */
0206 struct nau8822 {
0207     struct device *dev;
0208     struct regmap *regmap;
0209     int mclk_idx;
0210     struct nau8822_pll pll;
0211     int sysclk;
0212     int div_id;
0213 };
0214
0215 #endif  /* __NAU8822_H__ */