Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // nau8822.c  --  NAU8822 ALSA Soc Audio driver
0004 //
0005 // Copyright 2017 Nuvoton Technology Crop.
0006 //
0007 // Author: David Lin <ctlin0@nuvoton.com>
0008 // Co-author: John Hsu <kchsu0@nuvoton.com>
0009 // Co-author: Seven Li <wtli@nuvoton.com>
0010 //
0011 // Based on WM8974.c
0012 
0013 #include <linux/module.h>
0014 #include <linux/moduleparam.h>
0015 #include <linux/kernel.h>
0016 #include <linux/init.h>
0017 #include <linux/delay.h>
0018 #include <linux/pm.h>
0019 #include <linux/i2c.h>
0020 #include <linux/regmap.h>
0021 #include <linux/slab.h>
0022 #include <sound/core.h>
0023 #include <sound/pcm.h>
0024 #include <sound/pcm_params.h>
0025 #include <sound/soc.h>
0026 #include <sound/initval.h>
0027 #include <sound/tlv.h>
0028 #include <asm/div64.h>
0029 #include "nau8822.h"
0030 
0031 #define NAU_PLL_FREQ_MAX 100000000
0032 #define NAU_PLL_FREQ_MIN 90000000
0033 #define NAU_PLL_REF_MAX 33000000
0034 #define NAU_PLL_REF_MIN 8000000
0035 #define NAU_PLL_OPTOP_MIN 6
0036 
0037 static const int nau8822_mclk_scaler[] = { 10, 15, 20, 30, 40, 60, 80, 120 };
0038 
0039 static const struct reg_default nau8822_reg_defaults[] = {
0040     { NAU8822_REG_POWER_MANAGEMENT_1, 0x0000 },
0041     { NAU8822_REG_POWER_MANAGEMENT_2, 0x0000 },
0042     { NAU8822_REG_POWER_MANAGEMENT_3, 0x0000 },
0043     { NAU8822_REG_AUDIO_INTERFACE, 0x0050 },
0044     { NAU8822_REG_COMPANDING_CONTROL, 0x0000 },
0045     { NAU8822_REG_CLOCKING, 0x0140 },
0046     { NAU8822_REG_ADDITIONAL_CONTROL, 0x0000 },
0047     { NAU8822_REG_GPIO_CONTROL, 0x0000 },
0048     { NAU8822_REG_JACK_DETECT_CONTROL_1, 0x0000 },
0049     { NAU8822_REG_DAC_CONTROL, 0x0000 },
0050     { NAU8822_REG_LEFT_DAC_DIGITAL_VOLUME, 0x00ff },
0051     { NAU8822_REG_RIGHT_DAC_DIGITAL_VOLUME, 0x00ff },
0052     { NAU8822_REG_JACK_DETECT_CONTROL_2, 0x0000 },
0053     { NAU8822_REG_ADC_CONTROL, 0x0100 },
0054     { NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME, 0x00ff },
0055     { NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME, 0x00ff },
0056     { NAU8822_REG_EQ1, 0x012c },
0057     { NAU8822_REG_EQ2, 0x002c },
0058     { NAU8822_REG_EQ3, 0x002c },
0059     { NAU8822_REG_EQ4, 0x002c },
0060     { NAU8822_REG_EQ5, 0x002c },
0061     { NAU8822_REG_DAC_LIMITER_1, 0x0032 },
0062     { NAU8822_REG_DAC_LIMITER_2, 0x0000 },
0063     { NAU8822_REG_NOTCH_FILTER_1, 0x0000 },
0064     { NAU8822_REG_NOTCH_FILTER_2, 0x0000 },
0065     { NAU8822_REG_NOTCH_FILTER_3, 0x0000 },
0066     { NAU8822_REG_NOTCH_FILTER_4, 0x0000 },
0067     { NAU8822_REG_ALC_CONTROL_1, 0x0038 },
0068     { NAU8822_REG_ALC_CONTROL_2, 0x000b },
0069     { NAU8822_REG_ALC_CONTROL_3, 0x0032 },
0070     { NAU8822_REG_NOISE_GATE, 0x0010 },
0071     { NAU8822_REG_PLL_N, 0x0008 },
0072     { NAU8822_REG_PLL_K1, 0x000c },
0073     { NAU8822_REG_PLL_K2, 0x0093 },
0074     { NAU8822_REG_PLL_K3, 0x00e9 },
0075     { NAU8822_REG_3D_CONTROL, 0x0000 },
0076     { NAU8822_REG_RIGHT_SPEAKER_CONTROL, 0x0000 },
0077     { NAU8822_REG_INPUT_CONTROL, 0x0033 },
0078     { NAU8822_REG_LEFT_INP_PGA_CONTROL, 0x0010 },
0079     { NAU8822_REG_RIGHT_INP_PGA_CONTROL, 0x0010 },
0080     { NAU8822_REG_LEFT_ADC_BOOST_CONTROL, 0x0100 },
0081     { NAU8822_REG_RIGHT_ADC_BOOST_CONTROL, 0x0100 },
0082     { NAU8822_REG_OUTPUT_CONTROL, 0x0002 },
0083     { NAU8822_REG_LEFT_MIXER_CONTROL, 0x0001 },
0084     { NAU8822_REG_RIGHT_MIXER_CONTROL, 0x0001 },
0085     { NAU8822_REG_LHP_VOLUME, 0x0039 },
0086     { NAU8822_REG_RHP_VOLUME, 0x0039 },
0087     { NAU8822_REG_LSPKOUT_VOLUME, 0x0039 },
0088     { NAU8822_REG_RSPKOUT_VOLUME, 0x0039 },
0089     { NAU8822_REG_AUX2_MIXER, 0x0001 },
0090     { NAU8822_REG_AUX1_MIXER, 0x0001 },
0091     { NAU8822_REG_POWER_MANAGEMENT_4, 0x0000 },
0092     { NAU8822_REG_LEFT_TIME_SLOT, 0x0000 },
0093     { NAU8822_REG_MISC, 0x0020 },
0094     { NAU8822_REG_RIGHT_TIME_SLOT, 0x0000 },
0095     { NAU8822_REG_DEVICE_REVISION, 0x007f },
0096     { NAU8822_REG_DEVICE_ID, 0x001a },
0097     { NAU8822_REG_DAC_DITHER, 0x0114 },
0098     { NAU8822_REG_ALC_ENHANCE_1, 0x0000 },
0099     { NAU8822_REG_ALC_ENHANCE_2, 0x0000 },
0100     { NAU8822_REG_192KHZ_SAMPLING, 0x0008 },
0101     { NAU8822_REG_MISC_CONTROL, 0x0000 },
0102     { NAU8822_REG_INPUT_TIEOFF, 0x0000 },
0103     { NAU8822_REG_POWER_REDUCTION, 0x0000 },
0104     { NAU8822_REG_AGC_PEAK2PEAK, 0x0000 },
0105     { NAU8822_REG_AGC_PEAK_DETECT, 0x0000 },
0106     { NAU8822_REG_AUTOMUTE_CONTROL, 0x0000 },
0107     { NAU8822_REG_OUTPUT_TIEOFF, 0x0000 },
0108 };
0109 
0110 static bool nau8822_readable_reg(struct device *dev, unsigned int reg)
0111 {
0112     switch (reg) {
0113     case NAU8822_REG_RESET ... NAU8822_REG_JACK_DETECT_CONTROL_1:
0114     case NAU8822_REG_DAC_CONTROL ... NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME:
0115     case NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME:
0116     case NAU8822_REG_EQ1 ... NAU8822_REG_EQ5:
0117     case NAU8822_REG_DAC_LIMITER_1 ... NAU8822_REG_DAC_LIMITER_2:
0118     case NAU8822_REG_NOTCH_FILTER_1 ... NAU8822_REG_NOTCH_FILTER_4:
0119     case NAU8822_REG_ALC_CONTROL_1 ...NAU8822_REG_PLL_K3:
0120     case NAU8822_REG_3D_CONTROL:
0121     case NAU8822_REG_RIGHT_SPEAKER_CONTROL:
0122     case NAU8822_REG_INPUT_CONTROL ... NAU8822_REG_LEFT_ADC_BOOST_CONTROL:
0123     case NAU8822_REG_RIGHT_ADC_BOOST_CONTROL ... NAU8822_REG_AUX1_MIXER:
0124     case NAU8822_REG_POWER_MANAGEMENT_4 ... NAU8822_REG_DEVICE_ID:
0125     case NAU8822_REG_DAC_DITHER:
0126     case NAU8822_REG_ALC_ENHANCE_1 ... NAU8822_REG_MISC_CONTROL:
0127     case NAU8822_REG_INPUT_TIEOFF ... NAU8822_REG_OUTPUT_TIEOFF:
0128         return true;
0129     default:
0130         return false;
0131     }
0132 }
0133 
0134 static bool nau8822_writeable_reg(struct device *dev, unsigned int reg)
0135 {
0136     switch (reg) {
0137     case NAU8822_REG_RESET ... NAU8822_REG_JACK_DETECT_CONTROL_1:
0138     case NAU8822_REG_DAC_CONTROL ... NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME:
0139     case NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME:
0140     case NAU8822_REG_EQ1 ... NAU8822_REG_EQ5:
0141     case NAU8822_REG_DAC_LIMITER_1 ... NAU8822_REG_DAC_LIMITER_2:
0142     case NAU8822_REG_NOTCH_FILTER_1 ... NAU8822_REG_NOTCH_FILTER_4:
0143     case NAU8822_REG_ALC_CONTROL_1 ...NAU8822_REG_PLL_K3:
0144     case NAU8822_REG_3D_CONTROL:
0145     case NAU8822_REG_RIGHT_SPEAKER_CONTROL:
0146     case NAU8822_REG_INPUT_CONTROL ... NAU8822_REG_LEFT_ADC_BOOST_CONTROL:
0147     case NAU8822_REG_RIGHT_ADC_BOOST_CONTROL ... NAU8822_REG_AUX1_MIXER:
0148     case NAU8822_REG_POWER_MANAGEMENT_4 ... NAU8822_REG_DEVICE_ID:
0149     case NAU8822_REG_DAC_DITHER:
0150     case NAU8822_REG_ALC_ENHANCE_1 ... NAU8822_REG_MISC_CONTROL:
0151     case NAU8822_REG_INPUT_TIEOFF ... NAU8822_REG_OUTPUT_TIEOFF:
0152         return true;
0153     default:
0154         return false;
0155     }
0156 }
0157 
0158 static bool nau8822_volatile(struct device *dev, unsigned int reg)
0159 {
0160     switch (reg) {
0161     case NAU8822_REG_RESET:
0162     case NAU8822_REG_DEVICE_REVISION:
0163     case NAU8822_REG_DEVICE_ID:
0164     case NAU8822_REG_AGC_PEAK2PEAK:
0165     case NAU8822_REG_AGC_PEAK_DETECT:
0166     case NAU8822_REG_AUTOMUTE_CONTROL:
0167         return true;
0168     default:
0169         return false;
0170     }
0171 }
0172 
0173 /* The EQ parameters get function is to get the 5 band equalizer control.
0174  * The regmap raw read can't work here because regmap doesn't provide
0175  * value format for value width of 9 bits. Therefore, the driver reads data
0176  * from cache and makes value format according to the endianness of
0177  * bytes type control element.
0178  */
0179 static int nau8822_eq_get(struct snd_kcontrol *kcontrol,
0180     struct snd_ctl_elem_value *ucontrol)
0181 {
0182     struct snd_soc_component *component =
0183             snd_soc_kcontrol_component(kcontrol);
0184     struct soc_bytes_ext *params = (void *)kcontrol->private_value;
0185     int i, reg;
0186     u16 reg_val, *val;
0187 
0188     val = (u16 *)ucontrol->value.bytes.data;
0189     reg = NAU8822_REG_EQ1;
0190     for (i = 0; i < params->max / sizeof(u16); i++) {
0191         reg_val = snd_soc_component_read(component, reg + i);
0192         /* conversion of 16-bit integers between native CPU format
0193          * and big endian format
0194          */
0195         reg_val = cpu_to_be16(reg_val);
0196         memcpy(val + i, &reg_val, sizeof(reg_val));
0197     }
0198 
0199     return 0;
0200 }
0201 
0202 /* The EQ parameters put function is to make configuration of 5 band equalizer
0203  * control. These configuration includes central frequency, equalizer gain,
0204  * cut-off frequency, bandwidth control, and equalizer path.
0205  * The regmap raw write can't work here because regmap doesn't provide
0206  * register and value format for register with address 7 bits and value 9 bits.
0207  * Therefore, the driver makes value format according to the endianness of
0208  * bytes type control element and writes data to codec.
0209  */
0210 static int nau8822_eq_put(struct snd_kcontrol *kcontrol,
0211     struct snd_ctl_elem_value *ucontrol)
0212 {
0213     struct snd_soc_component *component =
0214             snd_soc_kcontrol_component(kcontrol);
0215     struct soc_bytes_ext *params = (void *)kcontrol->private_value;
0216     void *data;
0217     u16 *val, value;
0218     int i, reg, ret;
0219 
0220     data = kmemdup(ucontrol->value.bytes.data,
0221         params->max, GFP_KERNEL | GFP_DMA);
0222     if (!data)
0223         return -ENOMEM;
0224 
0225     val = (u16 *)data;
0226     reg = NAU8822_REG_EQ1;
0227     for (i = 0; i < params->max / sizeof(u16); i++) {
0228         /* conversion of 16-bit integers between native CPU format
0229          * and big endian format
0230          */
0231         value = be16_to_cpu(*(val + i));
0232         ret = snd_soc_component_write(component, reg + i, value);
0233         if (ret) {
0234             dev_err(component->dev,
0235                 "EQ configuration fail, register: %x ret: %d\n",
0236                 reg + i, ret);
0237             kfree(data);
0238             return ret;
0239         }
0240     }
0241     kfree(data);
0242 
0243     return 0;
0244 }
0245 
0246 static const char * const nau8822_companding[] = {
0247     "Off", "NC", "u-law", "A-law"};
0248 
0249 static const struct soc_enum nau8822_companding_adc_enum =
0250     SOC_ENUM_SINGLE(NAU8822_REG_COMPANDING_CONTROL, NAU8822_ADCCM_SFT,
0251         ARRAY_SIZE(nau8822_companding), nau8822_companding);
0252 
0253 static const struct soc_enum nau8822_companding_dac_enum =
0254     SOC_ENUM_SINGLE(NAU8822_REG_COMPANDING_CONTROL, NAU8822_DACCM_SFT,
0255         ARRAY_SIZE(nau8822_companding), nau8822_companding);
0256 
0257 static const char * const nau8822_eqmode[] = {"Capture", "Playback"};
0258 
0259 static const struct soc_enum nau8822_eqmode_enum =
0260     SOC_ENUM_SINGLE(NAU8822_REG_EQ1, NAU8822_EQM_SFT,
0261         ARRAY_SIZE(nau8822_eqmode), nau8822_eqmode);
0262 
0263 static const char * const nau8822_alc1[] = {"Off", "Right", "Left", "Both"};
0264 static const char * const nau8822_alc3[] = {"Normal", "Limiter"};
0265 
0266 static const struct soc_enum nau8822_alc_enable_enum =
0267     SOC_ENUM_SINGLE(NAU8822_REG_ALC_CONTROL_1, NAU8822_ALCEN_SFT,
0268         ARRAY_SIZE(nau8822_alc1), nau8822_alc1);
0269 
0270 static const struct soc_enum nau8822_alc_mode_enum =
0271     SOC_ENUM_SINGLE(NAU8822_REG_ALC_CONTROL_3, NAU8822_ALCM_SFT,
0272         ARRAY_SIZE(nau8822_alc3), nau8822_alc3);
0273 
0274 static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
0275 static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1200, 75, 0);
0276 static const DECLARE_TLV_DB_SCALE(spk_tlv, -5700, 100, 0);
0277 static const DECLARE_TLV_DB_SCALE(pga_boost_tlv, 0, 2000, 0);
0278 static const DECLARE_TLV_DB_SCALE(boost_tlv, -1500, 300, 1);
0279 static const DECLARE_TLV_DB_SCALE(limiter_tlv, 0, 100, 0);
0280 
0281 static const struct snd_kcontrol_new nau8822_snd_controls[] = {
0282     SOC_ENUM("ADC Companding", nau8822_companding_adc_enum),
0283     SOC_ENUM("DAC Companding", nau8822_companding_dac_enum),
0284 
0285     SOC_ENUM("EQ Function", nau8822_eqmode_enum),
0286     SND_SOC_BYTES_EXT("EQ Parameters", 10,
0287           nau8822_eq_get, nau8822_eq_put),
0288 
0289     SOC_DOUBLE("DAC Inversion Switch",
0290         NAU8822_REG_DAC_CONTROL, 0, 1, 1, 0),
0291     SOC_DOUBLE_R_TLV("PCM Volume",
0292         NAU8822_REG_LEFT_DAC_DIGITAL_VOLUME,
0293         NAU8822_REG_RIGHT_DAC_DIGITAL_VOLUME, 0, 255, 0, digital_tlv),
0294 
0295     SOC_SINGLE("High Pass Filter Switch",
0296         NAU8822_REG_ADC_CONTROL, 8, 1, 0),
0297     SOC_SINGLE("High Pass Cut Off",
0298         NAU8822_REG_ADC_CONTROL, 4, 7, 0),
0299 
0300     SOC_DOUBLE("ADC Inversion Switch",
0301         NAU8822_REG_ADC_CONTROL, 0, 1, 1, 0),
0302     SOC_DOUBLE_R_TLV("ADC Volume",
0303         NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME,
0304         NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME, 0, 255, 0, digital_tlv),
0305 
0306     SOC_SINGLE("DAC Limiter Switch",
0307         NAU8822_REG_DAC_LIMITER_1, 8, 1, 0),
0308     SOC_SINGLE("DAC Limiter Decay",
0309         NAU8822_REG_DAC_LIMITER_1, 4, 15, 0),
0310     SOC_SINGLE("DAC Limiter Attack",
0311         NAU8822_REG_DAC_LIMITER_1, 0, 15, 0),
0312     SOC_SINGLE("DAC Limiter Threshold",
0313         NAU8822_REG_DAC_LIMITER_2, 4, 7, 0),
0314     SOC_SINGLE_TLV("DAC Limiter Volume",
0315         NAU8822_REG_DAC_LIMITER_2, 0, 12, 0, limiter_tlv),
0316 
0317     SOC_ENUM("ALC Mode", nau8822_alc_mode_enum),
0318     SOC_ENUM("ALC Enable Switch", nau8822_alc_enable_enum),
0319     SOC_SINGLE("ALC Min Gain",
0320         NAU8822_REG_ALC_CONTROL_1, 0, 7, 0),
0321     SOC_SINGLE("ALC Max Gain",
0322         NAU8822_REG_ALC_CONTROL_1, 3, 7, 0),
0323     SOC_SINGLE("ALC Hold",
0324         NAU8822_REG_ALC_CONTROL_2, 4, 10, 0),
0325     SOC_SINGLE("ALC Target",
0326         NAU8822_REG_ALC_CONTROL_2, 0, 15, 0),
0327     SOC_SINGLE("ALC Decay",
0328         NAU8822_REG_ALC_CONTROL_3, 4, 10, 0),
0329     SOC_SINGLE("ALC Attack",
0330         NAU8822_REG_ALC_CONTROL_3, 0, 10, 0),
0331     SOC_SINGLE("ALC Noise Gate Switch",
0332         NAU8822_REG_NOISE_GATE, 3, 1, 0),
0333     SOC_SINGLE("ALC Noise Gate Threshold",
0334         NAU8822_REG_NOISE_GATE, 0, 7, 0),
0335 
0336     SOC_DOUBLE_R("PGA ZC Switch",
0337         NAU8822_REG_LEFT_INP_PGA_CONTROL,
0338         NAU8822_REG_RIGHT_INP_PGA_CONTROL,
0339         7, 1, 0),
0340     SOC_DOUBLE_R_TLV("PGA Volume",
0341         NAU8822_REG_LEFT_INP_PGA_CONTROL,
0342         NAU8822_REG_RIGHT_INP_PGA_CONTROL, 0, 63, 0, inpga_tlv),
0343 
0344     SOC_DOUBLE_R("Headphone ZC Switch",
0345         NAU8822_REG_LHP_VOLUME,
0346         NAU8822_REG_RHP_VOLUME, 7, 1, 0),
0347     SOC_DOUBLE_R("Headphone Playback Switch",
0348         NAU8822_REG_LHP_VOLUME,
0349         NAU8822_REG_RHP_VOLUME, 6, 1, 1),
0350     SOC_DOUBLE_R_TLV("Headphone Volume",
0351         NAU8822_REG_LHP_VOLUME,
0352         NAU8822_REG_RHP_VOLUME, 0, 63, 0, spk_tlv),
0353 
0354     SOC_DOUBLE_R("Speaker ZC Switch",
0355         NAU8822_REG_LSPKOUT_VOLUME,
0356         NAU8822_REG_RSPKOUT_VOLUME, 7, 1, 0),
0357     SOC_DOUBLE_R("Speaker Playback Switch",
0358         NAU8822_REG_LSPKOUT_VOLUME,
0359         NAU8822_REG_RSPKOUT_VOLUME, 6, 1, 1),
0360     SOC_DOUBLE_R_TLV("Speaker Volume",
0361         NAU8822_REG_LSPKOUT_VOLUME,
0362         NAU8822_REG_RSPKOUT_VOLUME, 0, 63, 0, spk_tlv),
0363 
0364     SOC_DOUBLE_R("AUXOUT Playback Switch",
0365         NAU8822_REG_AUX2_MIXER,
0366         NAU8822_REG_AUX1_MIXER, 6, 1, 1),
0367 
0368     SOC_DOUBLE_R_TLV("PGA Boost Volume",
0369         NAU8822_REG_LEFT_ADC_BOOST_CONTROL,
0370         NAU8822_REG_RIGHT_ADC_BOOST_CONTROL, 8, 1, 0, pga_boost_tlv),
0371     SOC_DOUBLE_R_TLV("L2/R2 Boost Volume",
0372         NAU8822_REG_LEFT_ADC_BOOST_CONTROL,
0373         NAU8822_REG_RIGHT_ADC_BOOST_CONTROL, 4, 7, 0, boost_tlv),
0374     SOC_DOUBLE_R_TLV("Aux Boost Volume",
0375         NAU8822_REG_LEFT_ADC_BOOST_CONTROL,
0376         NAU8822_REG_RIGHT_ADC_BOOST_CONTROL, 0, 7, 0, boost_tlv),
0377 
0378     SOC_SINGLE("DAC 128x Oversampling Switch",
0379         NAU8822_REG_DAC_CONTROL, 5, 1, 0),
0380     SOC_SINGLE("ADC 128x Oversampling Switch",
0381         NAU8822_REG_ADC_CONTROL, 5, 1, 0),
0382 };
0383 
0384 /* LMAIN and RMAIN Mixer */
0385 static const struct snd_kcontrol_new nau8822_left_out_mixer[] = {
0386     SOC_DAPM_SINGLE("LINMIX Switch",
0387         NAU8822_REG_LEFT_MIXER_CONTROL, 1, 1, 0),
0388     SOC_DAPM_SINGLE("LAUX Switch",
0389         NAU8822_REG_LEFT_MIXER_CONTROL, 5, 1, 0),
0390     SOC_DAPM_SINGLE("LDAC Switch",
0391         NAU8822_REG_LEFT_MIXER_CONTROL, 0, 1, 0),
0392     SOC_DAPM_SINGLE("RDAC Switch",
0393         NAU8822_REG_OUTPUT_CONTROL, 5, 1, 0),
0394 };
0395 
0396 static const struct snd_kcontrol_new nau8822_right_out_mixer[] = {
0397     SOC_DAPM_SINGLE("RINMIX Switch",
0398         NAU8822_REG_RIGHT_MIXER_CONTROL, 1, 1, 0),
0399     SOC_DAPM_SINGLE("RAUX Switch",
0400         NAU8822_REG_RIGHT_MIXER_CONTROL, 5, 1, 0),
0401     SOC_DAPM_SINGLE("RDAC Switch",
0402         NAU8822_REG_RIGHT_MIXER_CONTROL, 0, 1, 0),
0403     SOC_DAPM_SINGLE("LDAC Switch",
0404         NAU8822_REG_OUTPUT_CONTROL, 6, 1, 0),
0405 };
0406 
0407 /* AUX1 and AUX2 Mixer */
0408 static const struct snd_kcontrol_new nau8822_auxout1_mixer[] = {
0409     SOC_DAPM_SINGLE("RDAC Switch", NAU8822_REG_AUX1_MIXER, 0, 1, 0),
0410     SOC_DAPM_SINGLE("RMIX Switch", NAU8822_REG_AUX1_MIXER, 1, 1, 0),
0411     SOC_DAPM_SINGLE("RINMIX Switch", NAU8822_REG_AUX1_MIXER, 2, 1, 0),
0412     SOC_DAPM_SINGLE("LDAC Switch", NAU8822_REG_AUX1_MIXER, 3, 1, 0),
0413     SOC_DAPM_SINGLE("LMIX Switch", NAU8822_REG_AUX1_MIXER, 4, 1, 0),
0414 };
0415 
0416 static const struct snd_kcontrol_new nau8822_auxout2_mixer[] = {
0417     SOC_DAPM_SINGLE("LDAC Switch", NAU8822_REG_AUX2_MIXER, 0, 1, 0),
0418     SOC_DAPM_SINGLE("LMIX Switch", NAU8822_REG_AUX2_MIXER, 1, 1, 0),
0419     SOC_DAPM_SINGLE("LINMIX Switch", NAU8822_REG_AUX2_MIXER, 2, 1, 0),
0420     SOC_DAPM_SINGLE("AUX1MIX Output Switch",
0421         NAU8822_REG_AUX2_MIXER, 3, 1, 0),
0422 };
0423 
0424 /* Input PGA */
0425 static const struct snd_kcontrol_new nau8822_left_input_mixer[] = {
0426     SOC_DAPM_SINGLE("L2 Switch", NAU8822_REG_INPUT_CONTROL, 2, 1, 0),
0427     SOC_DAPM_SINGLE("MicN Switch", NAU8822_REG_INPUT_CONTROL, 1, 1, 0),
0428     SOC_DAPM_SINGLE("MicP Switch", NAU8822_REG_INPUT_CONTROL, 0, 1, 0),
0429 };
0430 static const struct snd_kcontrol_new nau8822_right_input_mixer[] = {
0431     SOC_DAPM_SINGLE("R2 Switch", NAU8822_REG_INPUT_CONTROL, 6, 1, 0),
0432     SOC_DAPM_SINGLE("MicN Switch", NAU8822_REG_INPUT_CONTROL, 5, 1, 0),
0433     SOC_DAPM_SINGLE("MicP Switch", NAU8822_REG_INPUT_CONTROL, 4, 1, 0),
0434 };
0435 
0436 /* Loopback Switch */
0437 static const struct snd_kcontrol_new nau8822_loopback =
0438     SOC_DAPM_SINGLE("Switch", NAU8822_REG_COMPANDING_CONTROL,
0439         NAU8822_ADDAP_SFT, 1, 0);
0440 
0441 static int check_mclk_select_pll(struct snd_soc_dapm_widget *source,
0442              struct snd_soc_dapm_widget *sink)
0443 {
0444     struct snd_soc_component *component =
0445         snd_soc_dapm_to_component(source->dapm);
0446     unsigned int value;
0447 
0448     value = snd_soc_component_read(component, NAU8822_REG_CLOCKING);
0449 
0450     return (value & NAU8822_CLKM_MASK);
0451 }
0452 
0453 static const struct snd_soc_dapm_widget nau8822_dapm_widgets[] = {
0454     SND_SOC_DAPM_DAC("Left DAC", "Left HiFi Playback",
0455         NAU8822_REG_POWER_MANAGEMENT_3, 0, 0),
0456     SND_SOC_DAPM_DAC("Right DAC", "Right HiFi Playback",
0457         NAU8822_REG_POWER_MANAGEMENT_3, 1, 0),
0458     SND_SOC_DAPM_ADC("Left ADC", "Left HiFi Capture",
0459         NAU8822_REG_POWER_MANAGEMENT_2, 0, 0),
0460     SND_SOC_DAPM_ADC("Right ADC", "Right HiFi Capture",
0461         NAU8822_REG_POWER_MANAGEMENT_2, 1, 0),
0462 
0463     SOC_MIXER_ARRAY("Left Output Mixer",
0464         NAU8822_REG_POWER_MANAGEMENT_3, 2, 0, nau8822_left_out_mixer),
0465     SOC_MIXER_ARRAY("Right Output Mixer",
0466         NAU8822_REG_POWER_MANAGEMENT_3, 3, 0, nau8822_right_out_mixer),
0467     SOC_MIXER_ARRAY("AUX1 Output Mixer",
0468         NAU8822_REG_POWER_MANAGEMENT_1, 7, 0, nau8822_auxout1_mixer),
0469     SOC_MIXER_ARRAY("AUX2 Output Mixer",
0470         NAU8822_REG_POWER_MANAGEMENT_1, 6, 0, nau8822_auxout2_mixer),
0471 
0472     SOC_MIXER_ARRAY("Left Input Mixer",
0473         NAU8822_REG_POWER_MANAGEMENT_2,
0474         2, 0, nau8822_left_input_mixer),
0475     SOC_MIXER_ARRAY("Right Input Mixer",
0476         NAU8822_REG_POWER_MANAGEMENT_2,
0477         3, 0, nau8822_right_input_mixer),
0478 
0479     SND_SOC_DAPM_PGA("Left Boost Mixer",
0480         NAU8822_REG_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
0481     SND_SOC_DAPM_PGA("Right Boost Mixer",
0482         NAU8822_REG_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
0483 
0484     SND_SOC_DAPM_PGA("Left Capture PGA",
0485         NAU8822_REG_LEFT_INP_PGA_CONTROL, 6, 1, NULL, 0),
0486     SND_SOC_DAPM_PGA("Right Capture PGA",
0487         NAU8822_REG_RIGHT_INP_PGA_CONTROL, 6, 1, NULL, 0),
0488 
0489     SND_SOC_DAPM_PGA("Left Headphone Out",
0490         NAU8822_REG_POWER_MANAGEMENT_2, 7, 0, NULL, 0),
0491     SND_SOC_DAPM_PGA("Right Headphone Out",
0492         NAU8822_REG_POWER_MANAGEMENT_2, 8, 0, NULL, 0),
0493 
0494     SND_SOC_DAPM_PGA("Left Speaker Out",
0495          NAU8822_REG_POWER_MANAGEMENT_3, 6, 0, NULL, 0),
0496     SND_SOC_DAPM_PGA("Right Speaker Out",
0497         NAU8822_REG_POWER_MANAGEMENT_3, 5, 0, NULL, 0),
0498 
0499     SND_SOC_DAPM_PGA("AUX1 Out",
0500         NAU8822_REG_POWER_MANAGEMENT_3, 8, 0, NULL, 0),
0501     SND_SOC_DAPM_PGA("AUX2 Out",
0502         NAU8822_REG_POWER_MANAGEMENT_3, 7, 0, NULL, 0),
0503 
0504     SND_SOC_DAPM_SUPPLY("Mic Bias",
0505         NAU8822_REG_POWER_MANAGEMENT_1, 4, 0, NULL, 0),
0506     SND_SOC_DAPM_SUPPLY("PLL",
0507         NAU8822_REG_POWER_MANAGEMENT_1, 5, 0, NULL, 0),
0508 
0509     SND_SOC_DAPM_SWITCH("Digital Loopback", SND_SOC_NOPM, 0, 0,
0510         &nau8822_loopback),
0511 
0512     SND_SOC_DAPM_INPUT("LMICN"),
0513     SND_SOC_DAPM_INPUT("LMICP"),
0514     SND_SOC_DAPM_INPUT("RMICN"),
0515     SND_SOC_DAPM_INPUT("RMICP"),
0516     SND_SOC_DAPM_INPUT("LAUX"),
0517     SND_SOC_DAPM_INPUT("RAUX"),
0518     SND_SOC_DAPM_INPUT("L2"),
0519     SND_SOC_DAPM_INPUT("R2"),
0520     SND_SOC_DAPM_OUTPUT("LHP"),
0521     SND_SOC_DAPM_OUTPUT("RHP"),
0522     SND_SOC_DAPM_OUTPUT("LSPK"),
0523     SND_SOC_DAPM_OUTPUT("RSPK"),
0524     SND_SOC_DAPM_OUTPUT("AUXOUT1"),
0525     SND_SOC_DAPM_OUTPUT("AUXOUT2"),
0526 };
0527 
0528 static const struct snd_soc_dapm_route nau8822_dapm_routes[] = {
0529     {"Right DAC", NULL, "PLL", check_mclk_select_pll},
0530     {"Left DAC", NULL, "PLL", check_mclk_select_pll},
0531 
0532     /* LMAIN and RMAIN Mixer */
0533     {"Right Output Mixer", "LDAC Switch", "Left DAC"},
0534     {"Right Output Mixer", "RDAC Switch", "Right DAC"},
0535     {"Right Output Mixer", "RAUX Switch", "RAUX"},
0536     {"Right Output Mixer", "RINMIX Switch", "Right Boost Mixer"},
0537 
0538     {"Left Output Mixer", "LDAC Switch", "Left DAC"},
0539     {"Left Output Mixer", "RDAC Switch", "Right DAC"},
0540     {"Left Output Mixer", "LAUX Switch", "LAUX"},
0541     {"Left Output Mixer", "LINMIX Switch", "Left Boost Mixer"},
0542 
0543     /* AUX1 and AUX2 Mixer */
0544     {"AUX1 Output Mixer", "RDAC Switch", "Right DAC"},
0545     {"AUX1 Output Mixer", "RMIX Switch", "Right Output Mixer"},
0546     {"AUX1 Output Mixer", "RINMIX Switch", "Right Boost Mixer"},
0547     {"AUX1 Output Mixer", "LDAC Switch", "Left DAC"},
0548     {"AUX1 Output Mixer", "LMIX Switch", "Left Output Mixer"},
0549 
0550     {"AUX2 Output Mixer", "LDAC Switch", "Left DAC"},
0551     {"AUX2 Output Mixer", "LMIX Switch", "Left Output Mixer"},
0552     {"AUX2 Output Mixer", "LINMIX Switch", "Left Boost Mixer"},
0553     {"AUX2 Output Mixer", "AUX1MIX Output Switch", "AUX1 Output Mixer"},
0554 
0555     /* Outputs */
0556     {"Right Headphone Out", NULL, "Right Output Mixer"},
0557     {"RHP", NULL, "Right Headphone Out"},
0558 
0559     {"Left Headphone Out", NULL, "Left Output Mixer"},
0560     {"LHP", NULL, "Left Headphone Out"},
0561 
0562     {"Right Speaker Out", NULL, "Right Output Mixer"},
0563     {"RSPK", NULL, "Right Speaker Out"},
0564 
0565     {"Left Speaker Out", NULL, "Left Output Mixer"},
0566     {"LSPK", NULL, "Left Speaker Out"},
0567 
0568     {"AUX1 Out", NULL, "AUX1 Output Mixer"},
0569     {"AUX2 Out", NULL, "AUX2 Output Mixer"},
0570     {"AUXOUT1", NULL, "AUX1 Out"},
0571     {"AUXOUT2", NULL, "AUX2 Out"},
0572 
0573     /* Boost Mixer */
0574     {"Right ADC", NULL, "PLL", check_mclk_select_pll},
0575     {"Left ADC", NULL, "PLL", check_mclk_select_pll},
0576 
0577     {"Right ADC", NULL, "Right Boost Mixer"},
0578 
0579     {"Right Boost Mixer", NULL, "RAUX"},
0580     {"Right Boost Mixer", NULL, "Right Capture PGA"},
0581     {"Right Boost Mixer", NULL, "R2"},
0582 
0583     {"Left ADC", NULL, "Left Boost Mixer"},
0584 
0585     {"Left Boost Mixer", NULL, "LAUX"},
0586     {"Left Boost Mixer", NULL, "Left Capture PGA"},
0587     {"Left Boost Mixer", NULL, "L2"},
0588 
0589     /* Input PGA */
0590     {"Right Capture PGA", NULL, "Right Input Mixer"},
0591     {"Left Capture PGA", NULL, "Left Input Mixer"},
0592 
0593     /* Enable Microphone Power */
0594     {"Right Capture PGA", NULL, "Mic Bias"},
0595     {"Left Capture PGA", NULL, "Mic Bias"},
0596 
0597     {"Right Input Mixer", "R2 Switch", "R2"},
0598     {"Right Input Mixer", "MicN Switch", "RMICN"},
0599     {"Right Input Mixer", "MicP Switch", "RMICP"},
0600 
0601     {"Left Input Mixer", "L2 Switch", "L2"},
0602     {"Left Input Mixer", "MicN Switch", "LMICN"},
0603     {"Left Input Mixer", "MicP Switch", "LMICP"},
0604 
0605     /* Digital Loopback */
0606     {"Digital Loopback", "Switch", "Left ADC"},
0607     {"Digital Loopback", "Switch", "Right ADC"},
0608     {"Left DAC", NULL, "Digital Loopback"},
0609     {"Right DAC", NULL, "Digital Loopback"},
0610 };
0611 
0612 static int nau8822_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
0613                  unsigned int freq, int dir)
0614 {
0615     struct snd_soc_component *component = dai->component;
0616     struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component);
0617 
0618     nau8822->div_id = clk_id;
0619     nau8822->sysclk = freq;
0620     dev_dbg(component->dev, "master sysclk %dHz, source %s\n", freq,
0621         clk_id == NAU8822_CLK_PLL ? "PLL" : "MCLK");
0622 
0623     return 0;
0624 }
0625 
0626 static int nau8822_calc_pll(unsigned int pll_in, unsigned int fs,
0627                 struct nau8822_pll *pll_param)
0628 {
0629     u64 f2, f2_max, pll_ratio;
0630     int i, scal_sel;
0631 
0632     if (pll_in > NAU_PLL_REF_MAX || pll_in < NAU_PLL_REF_MIN)
0633         return -EINVAL;
0634     f2_max = 0;
0635     scal_sel = ARRAY_SIZE(nau8822_mclk_scaler);
0636 
0637     for (i = 0; i < scal_sel; i++) {
0638         f2 = 256 * fs * 4 * nau8822_mclk_scaler[i] / 10;
0639         if (f2 > NAU_PLL_FREQ_MIN && f2 < NAU_PLL_FREQ_MAX &&
0640             f2_max < f2) {
0641             f2_max = f2;
0642             scal_sel = i;
0643         }
0644     }
0645 
0646     if (ARRAY_SIZE(nau8822_mclk_scaler) == scal_sel)
0647         return -EINVAL;
0648     pll_param->mclk_scaler = scal_sel;
0649     f2 = f2_max;
0650 
0651     /* Calculate the PLL 4-bit integer input and the PLL 24-bit fractional
0652      * input; round up the 24+4bit.
0653      */
0654     pll_ratio = div_u64(f2 << 28, pll_in);
0655     pll_param->pre_factor = 0;
0656     if (((pll_ratio >> 28) & 0xF) < NAU_PLL_OPTOP_MIN) {
0657         pll_ratio <<= 1;
0658         pll_param->pre_factor = 1;
0659     }
0660     pll_param->pll_int = (pll_ratio >> 28) & 0xF;
0661     pll_param->pll_frac = ((pll_ratio & 0xFFFFFFF) >> 4);
0662 
0663     return 0;
0664 }
0665 
0666 static int nau8822_config_clkdiv(struct snd_soc_dai *dai, int div, int rate)
0667 {
0668     struct snd_soc_component *component = dai->component;
0669     struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component);
0670     struct nau8822_pll *pll = &nau8822->pll;
0671     int i, sclk, imclk;
0672 
0673     switch (nau8822->div_id) {
0674     case NAU8822_CLK_MCLK:
0675         /* Configure the master clock prescaler div to make system
0676          * clock to approximate the internal master clock (IMCLK);
0677          * and large or equal to IMCLK.
0678          */
0679         div = 0;
0680         imclk = rate * 256;
0681         for (i = 1; i < ARRAY_SIZE(nau8822_mclk_scaler); i++) {
0682             sclk = (nau8822->sysclk * 10) / nau8822_mclk_scaler[i];
0683             if (sclk < imclk)
0684                 break;
0685             div = i;
0686         }
0687         dev_dbg(component->dev, "master clock prescaler %x for fs %d\n",
0688             div, rate);
0689 
0690         /* master clock from MCLK and disable PLL */
0691         snd_soc_component_update_bits(component,
0692             NAU8822_REG_CLOCKING, NAU8822_MCLKSEL_MASK,
0693             (div << NAU8822_MCLKSEL_SFT));
0694         snd_soc_component_update_bits(component,
0695             NAU8822_REG_CLOCKING, NAU8822_CLKM_MASK,
0696             NAU8822_CLKM_MCLK);
0697         break;
0698 
0699     case NAU8822_CLK_PLL:
0700         /* master clock from PLL and enable PLL */
0701         if (pll->mclk_scaler != div) {
0702             dev_err(component->dev,
0703             "master clock prescaler not meet PLL parameters\n");
0704             return -EINVAL;
0705         }
0706         snd_soc_component_update_bits(component,
0707             NAU8822_REG_CLOCKING, NAU8822_MCLKSEL_MASK,
0708             (div << NAU8822_MCLKSEL_SFT));
0709         snd_soc_component_update_bits(component,
0710             NAU8822_REG_CLOCKING, NAU8822_CLKM_MASK,
0711             NAU8822_CLKM_PLL);
0712         break;
0713 
0714     default:
0715         return -EINVAL;
0716     }
0717 
0718     return 0;
0719 }
0720 
0721 static int nau8822_set_pll(struct snd_soc_dai *dai, int pll_id, int source,
0722                 unsigned int freq_in, unsigned int freq_out)
0723 {
0724     struct snd_soc_component *component = dai->component;
0725     struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component);
0726     struct nau8822_pll *pll_param = &nau8822->pll;
0727     int ret, fs;
0728 
0729     if (freq_in == pll_param->freq_in &&
0730         freq_out == pll_param->freq_out)
0731         return 0;
0732 
0733     if (freq_out == 0) {
0734         dev_dbg(component->dev, "PLL disabled\n");
0735         snd_soc_component_update_bits(component,
0736             NAU8822_REG_POWER_MANAGEMENT_1, NAU8822_PLL_EN_MASK, NAU8822_PLL_OFF);
0737         return 0;
0738     }
0739 
0740     fs = freq_out / 256;
0741 
0742     ret = nau8822_calc_pll(freq_in, fs, pll_param);
0743     if (ret < 0) {
0744         dev_err(component->dev, "Unsupported input clock %d\n",
0745             freq_in);
0746         return ret;
0747     }
0748 
0749     dev_info(component->dev,
0750         "pll_int=%x pll_frac=%x mclk_scaler=%x pre_factor=%x\n",
0751         pll_param->pll_int, pll_param->pll_frac,
0752         pll_param->mclk_scaler, pll_param->pre_factor);
0753 
0754     snd_soc_component_update_bits(component,
0755         NAU8822_REG_POWER_MANAGEMENT_1, NAU8822_PLL_EN_MASK, NAU8822_PLL_OFF);
0756     snd_soc_component_update_bits(component,
0757         NAU8822_REG_PLL_N, NAU8822_PLLMCLK_DIV2 | NAU8822_PLLN_MASK,
0758         (pll_param->pre_factor ? NAU8822_PLLMCLK_DIV2 : 0) |
0759         pll_param->pll_int);
0760     snd_soc_component_write(component,
0761         NAU8822_REG_PLL_K1, (pll_param->pll_frac >> NAU8822_PLLK1_SFT) &
0762         NAU8822_PLLK1_MASK);
0763     snd_soc_component_write(component,
0764         NAU8822_REG_PLL_K2, (pll_param->pll_frac >> NAU8822_PLLK2_SFT) &
0765         NAU8822_PLLK2_MASK);
0766     snd_soc_component_write(component,
0767         NAU8822_REG_PLL_K3, pll_param->pll_frac & NAU8822_PLLK3_MASK);
0768     snd_soc_component_update_bits(component,
0769         NAU8822_REG_CLOCKING, NAU8822_MCLKSEL_MASK,
0770         pll_param->mclk_scaler << NAU8822_MCLKSEL_SFT);
0771     snd_soc_component_update_bits(component,
0772         NAU8822_REG_CLOCKING, NAU8822_CLKM_MASK, NAU8822_CLKM_PLL);
0773     snd_soc_component_update_bits(component,
0774         NAU8822_REG_POWER_MANAGEMENT_1, NAU8822_PLL_EN_MASK, NAU8822_PLL_ON);
0775 
0776     pll_param->freq_in = freq_in;
0777     pll_param->freq_out = freq_out;
0778 
0779     return 0;
0780 }
0781 
0782 static int nau8822_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
0783 {
0784     struct snd_soc_component *component = dai->component;
0785     u16 ctrl1_val = 0, ctrl2_val = 0;
0786 
0787     dev_dbg(component->dev, "%s\n", __func__);
0788 
0789     switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
0790     case SND_SOC_DAIFMT_CBM_CFM:
0791         ctrl2_val |= 1;
0792         break;
0793     case SND_SOC_DAIFMT_CBS_CFS:
0794         ctrl2_val &= ~1;
0795         break;
0796     default:
0797         return -EINVAL;
0798     }
0799 
0800     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0801     case SND_SOC_DAIFMT_I2S:
0802         ctrl1_val |= 0x10;
0803         break;
0804     case SND_SOC_DAIFMT_RIGHT_J:
0805         break;
0806     case SND_SOC_DAIFMT_LEFT_J:
0807         ctrl1_val |= 0x8;
0808         break;
0809     case SND_SOC_DAIFMT_DSP_A:
0810         ctrl1_val |= 0x18;
0811         break;
0812     default:
0813         return -EINVAL;
0814     }
0815 
0816     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0817     case SND_SOC_DAIFMT_NB_NF:
0818         break;
0819     case SND_SOC_DAIFMT_IB_IF:
0820         ctrl1_val |= 0x180;
0821         break;
0822     case SND_SOC_DAIFMT_IB_NF:
0823         ctrl1_val |= 0x100;
0824         break;
0825     case SND_SOC_DAIFMT_NB_IF:
0826         ctrl1_val |= 0x80;
0827         break;
0828     default:
0829         return -EINVAL;
0830     }
0831 
0832     snd_soc_component_update_bits(component,
0833         NAU8822_REG_AUDIO_INTERFACE,
0834         NAU8822_AIFMT_MASK | NAU8822_LRP_MASK | NAU8822_BCLKP_MASK,
0835         ctrl1_val);
0836     snd_soc_component_update_bits(component,
0837         NAU8822_REG_CLOCKING, NAU8822_CLKIOEN_MASK, ctrl2_val);
0838 
0839     return 0;
0840 }
0841 
0842 static int nau8822_hw_params(struct snd_pcm_substream *substream,
0843                 struct snd_pcm_hw_params *params,
0844                 struct snd_soc_dai *dai)
0845 {
0846     struct snd_soc_component *component = dai->component;
0847     struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component);
0848     int val_len = 0, val_rate = 0;
0849     unsigned int ctrl_val, bclk_fs, bclk_div;
0850 
0851     /* make BCLK and LRC divide configuration if the codec as master. */
0852     ctrl_val = snd_soc_component_read(component, NAU8822_REG_CLOCKING);
0853     if (ctrl_val & NAU8822_CLK_MASTER) {
0854         /* get the bclk and fs ratio */
0855         bclk_fs = snd_soc_params_to_bclk(params) / params_rate(params);
0856         if (bclk_fs <= 32)
0857             bclk_div = NAU8822_BCLKDIV_8;
0858         else if (bclk_fs <= 64)
0859             bclk_div = NAU8822_BCLKDIV_4;
0860         else if (bclk_fs <= 128)
0861             bclk_div = NAU8822_BCLKDIV_2;
0862         else
0863             return -EINVAL;
0864         snd_soc_component_update_bits(component, NAU8822_REG_CLOCKING,
0865                 NAU8822_BCLKSEL_MASK, bclk_div);
0866     }
0867 
0868     switch (params_format(params)) {
0869     case SNDRV_PCM_FORMAT_S16_LE:
0870         break;
0871     case SNDRV_PCM_FORMAT_S20_3LE:
0872         val_len |= NAU8822_WLEN_20;
0873         break;
0874     case SNDRV_PCM_FORMAT_S24_LE:
0875         val_len |= NAU8822_WLEN_24;
0876         break;
0877     case SNDRV_PCM_FORMAT_S32_LE:
0878         val_len |= NAU8822_WLEN_32;
0879         break;
0880     default:
0881         return -EINVAL;
0882     }
0883 
0884     switch (params_rate(params)) {
0885     case 8000:
0886         val_rate |= NAU8822_SMPLR_8K;
0887         break;
0888     case 11025:
0889         val_rate |= NAU8822_SMPLR_12K;
0890         break;
0891     case 16000:
0892         val_rate |= NAU8822_SMPLR_16K;
0893         break;
0894     case 22050:
0895         val_rate |= NAU8822_SMPLR_24K;
0896         break;
0897     case 32000:
0898         val_rate |= NAU8822_SMPLR_32K;
0899         break;
0900     case 44100:
0901     case 48000:
0902         break;
0903     default:
0904         return -EINVAL;
0905     }
0906 
0907     snd_soc_component_update_bits(component,
0908         NAU8822_REG_AUDIO_INTERFACE, NAU8822_WLEN_MASK, val_len);
0909     snd_soc_component_update_bits(component,
0910         NAU8822_REG_ADDITIONAL_CONTROL, NAU8822_SMPLR_MASK, val_rate);
0911 
0912     /* If the master clock is from MCLK, provide the runtime FS for driver
0913      * to get the master clock prescaler configuration.
0914      */
0915     if (nau8822->div_id == NAU8822_CLK_MCLK)
0916         nau8822_config_clkdiv(dai, 0, params_rate(params));
0917 
0918     return 0;
0919 }
0920 
0921 static int nau8822_mute(struct snd_soc_dai *dai, int mute, int direction)
0922 {
0923     struct snd_soc_component *component = dai->component;
0924 
0925     dev_dbg(component->dev, "%s: %d\n", __func__, mute);
0926 
0927     if (mute)
0928         snd_soc_component_update_bits(component,
0929             NAU8822_REG_DAC_CONTROL, 0x40, 0x40);
0930     else
0931         snd_soc_component_update_bits(component,
0932             NAU8822_REG_DAC_CONTROL, 0x40, 0);
0933 
0934     return 0;
0935 }
0936 
0937 static int nau8822_set_bias_level(struct snd_soc_component *component,
0938                  enum snd_soc_bias_level level)
0939 {
0940     switch (level) {
0941     case SND_SOC_BIAS_ON:
0942     case SND_SOC_BIAS_PREPARE:
0943         snd_soc_component_update_bits(component,
0944             NAU8822_REG_POWER_MANAGEMENT_1,
0945             NAU8822_REFIMP_MASK, NAU8822_REFIMP_80K);
0946         break;
0947 
0948     case SND_SOC_BIAS_STANDBY:
0949         snd_soc_component_update_bits(component,
0950             NAU8822_REG_POWER_MANAGEMENT_1,
0951             NAU8822_IOBUF_EN | NAU8822_ABIAS_EN,
0952             NAU8822_IOBUF_EN | NAU8822_ABIAS_EN);
0953 
0954         if (snd_soc_component_get_bias_level(component) ==
0955             SND_SOC_BIAS_OFF) {
0956             snd_soc_component_update_bits(component,
0957                 NAU8822_REG_POWER_MANAGEMENT_1,
0958                 NAU8822_REFIMP_MASK, NAU8822_REFIMP_3K);
0959             mdelay(100);
0960         }
0961         snd_soc_component_update_bits(component,
0962             NAU8822_REG_POWER_MANAGEMENT_1,
0963             NAU8822_REFIMP_MASK, NAU8822_REFIMP_300K);
0964         break;
0965 
0966     case SND_SOC_BIAS_OFF:
0967         snd_soc_component_write(component,
0968             NAU8822_REG_POWER_MANAGEMENT_1, 0);
0969         snd_soc_component_write(component,
0970             NAU8822_REG_POWER_MANAGEMENT_2, 0);
0971         snd_soc_component_write(component,
0972             NAU8822_REG_POWER_MANAGEMENT_3, 0);
0973         break;
0974     }
0975 
0976     dev_dbg(component->dev, "%s: %d\n", __func__, level);
0977 
0978     return 0;
0979 }
0980 
0981 #define NAU8822_RATES (SNDRV_PCM_RATE_8000_48000)
0982 
0983 #define NAU8822_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
0984     SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
0985 
0986 static const struct snd_soc_dai_ops nau8822_dai_ops = {
0987     .hw_params  = nau8822_hw_params,
0988     .mute_stream    = nau8822_mute,
0989     .set_fmt    = nau8822_set_dai_fmt,
0990     .set_sysclk = nau8822_set_dai_sysclk,
0991     .set_pll    = nau8822_set_pll,
0992     .no_capture_mute = 1,
0993 };
0994 
0995 static struct snd_soc_dai_driver nau8822_dai = {
0996     .name = "nau8822-hifi",
0997     .playback = {
0998         .stream_name = "Playback",
0999         .channels_min = 1,
1000         .channels_max = 2,
1001         .rates = NAU8822_RATES,
1002         .formats = NAU8822_FORMATS,
1003     },
1004     .capture = {
1005         .stream_name = "Capture",
1006         .channels_min = 1,
1007         .channels_max = 2,
1008         .rates = NAU8822_RATES,
1009         .formats = NAU8822_FORMATS,
1010     },
1011     .ops = &nau8822_dai_ops,
1012     .symmetric_rate = 1,
1013 };
1014 
1015 static int nau8822_suspend(struct snd_soc_component *component)
1016 {
1017     struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component);
1018 
1019     snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
1020 
1021     regcache_mark_dirty(nau8822->regmap);
1022 
1023     return 0;
1024 }
1025 
1026 static int nau8822_resume(struct snd_soc_component *component)
1027 {
1028     struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component);
1029 
1030     regcache_sync(nau8822->regmap);
1031 
1032     snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
1033 
1034     return 0;
1035 }
1036 
1037 /*
1038  * These registers contain an "update" bit - bit 8. This means, for example,
1039  * that one can write new DAC digital volume for both channels, but only when
1040  * the update bit is set, will also the volume be updated - simultaneously for
1041  * both channels.
1042  */
1043 static const int update_reg[] = {
1044     NAU8822_REG_LEFT_DAC_DIGITAL_VOLUME,
1045     NAU8822_REG_RIGHT_DAC_DIGITAL_VOLUME,
1046     NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME,
1047     NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME,
1048     NAU8822_REG_LEFT_INP_PGA_CONTROL,
1049     NAU8822_REG_RIGHT_INP_PGA_CONTROL,
1050     NAU8822_REG_LHP_VOLUME,
1051     NAU8822_REG_RHP_VOLUME,
1052     NAU8822_REG_LSPKOUT_VOLUME,
1053     NAU8822_REG_RSPKOUT_VOLUME,
1054 };
1055 
1056 static int nau8822_probe(struct snd_soc_component *component)
1057 {
1058     int i;
1059 
1060     /*
1061      * Set the update bit in all registers, that have one. This way all
1062      * writes to those registers will also cause the update bit to be
1063      * written.
1064      */
1065     for (i = 0; i < ARRAY_SIZE(update_reg); i++)
1066         snd_soc_component_update_bits(component,
1067             update_reg[i], 0x100, 0x100);
1068 
1069     return 0;
1070 }
1071 
1072 static const struct snd_soc_component_driver soc_component_dev_nau8822 = {
1073     .probe              = nau8822_probe,
1074     .suspend            = nau8822_suspend,
1075     .resume             = nau8822_resume,
1076     .set_bias_level         = nau8822_set_bias_level,
1077     .controls           = nau8822_snd_controls,
1078     .num_controls           = ARRAY_SIZE(nau8822_snd_controls),
1079     .dapm_widgets           = nau8822_dapm_widgets,
1080     .num_dapm_widgets       = ARRAY_SIZE(nau8822_dapm_widgets),
1081     .dapm_routes            = nau8822_dapm_routes,
1082     .num_dapm_routes        = ARRAY_SIZE(nau8822_dapm_routes),
1083     .idle_bias_on           = 1,
1084     .use_pmdown_time        = 1,
1085     .endianness         = 1,
1086 };
1087 
1088 static const struct regmap_config nau8822_regmap_config = {
1089     .reg_bits = 7,
1090     .val_bits = 9,
1091 
1092     .max_register = NAU8822_REG_MAX_REGISTER,
1093     .volatile_reg = nau8822_volatile,
1094 
1095     .readable_reg = nau8822_readable_reg,
1096     .writeable_reg = nau8822_writeable_reg,
1097 
1098     .cache_type = REGCACHE_RBTREE,
1099     .reg_defaults = nau8822_reg_defaults,
1100     .num_reg_defaults = ARRAY_SIZE(nau8822_reg_defaults),
1101 };
1102 
1103 static int nau8822_i2c_probe(struct i2c_client *i2c)
1104 {
1105     struct device *dev = &i2c->dev;
1106     struct nau8822 *nau8822 = dev_get_platdata(dev);
1107     int ret;
1108 
1109     if (!nau8822) {
1110         nau8822 = devm_kzalloc(dev, sizeof(*nau8822), GFP_KERNEL);
1111         if (nau8822 == NULL)
1112             return -ENOMEM;
1113     }
1114     i2c_set_clientdata(i2c, nau8822);
1115 
1116     nau8822->regmap = devm_regmap_init_i2c(i2c, &nau8822_regmap_config);
1117     if (IS_ERR(nau8822->regmap)) {
1118         ret = PTR_ERR(nau8822->regmap);
1119         dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
1120         return ret;
1121     }
1122     nau8822->dev = dev;
1123 
1124     /* Reset the codec */
1125     ret = regmap_write(nau8822->regmap, NAU8822_REG_RESET, 0x00);
1126     if (ret != 0) {
1127         dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);
1128         return ret;
1129     }
1130 
1131     ret = devm_snd_soc_register_component(dev, &soc_component_dev_nau8822,
1132                         &nau8822_dai, 1);
1133     if (ret != 0) {
1134         dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);
1135         return ret;
1136     }
1137 
1138     return 0;
1139 }
1140 
1141 static const struct i2c_device_id nau8822_i2c_id[] = {
1142     { "nau8822", 0 },
1143     { }
1144 };
1145 MODULE_DEVICE_TABLE(i2c, nau8822_i2c_id);
1146 
1147 #ifdef CONFIG_OF
1148 static const struct of_device_id nau8822_of_match[] = {
1149     { .compatible = "nuvoton,nau8822", },
1150     { }
1151 };
1152 MODULE_DEVICE_TABLE(of, nau8822_of_match);
1153 #endif
1154 
1155 static struct i2c_driver nau8822_i2c_driver = {
1156     .driver = {
1157         .name = "nau8822",
1158         .of_match_table = of_match_ptr(nau8822_of_match),
1159     },
1160     .probe_new = nau8822_i2c_probe,
1161     .id_table = nau8822_i2c_id,
1162 };
1163 module_i2c_driver(nau8822_i2c_driver);
1164 
1165 MODULE_DESCRIPTION("ASoC NAU8822 codec driver");
1166 MODULE_AUTHOR("David Lin <ctlin0@nuvoton.com>");
1167 MODULE_LICENSE("GPL v2");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!