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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 //
0003 // nau8821.c -- Nuvoton NAU88L21 audio codec driver
0004 //
0005 // Copyright 2021 Nuvoton Technology Corp.
0006 // Author: John Hsu <kchsu0@nuvoton.com>
0007 // Co-author: Seven Lee <wtli@nuvoton.com>
0008 //
0009 
0010 #include <linux/acpi.h>
0011 #include <linux/clk.h>
0012 #include <linux/delay.h>
0013 #include <linux/init.h>
0014 #include <linux/i2c.h>
0015 #include <linux/module.h>
0016 #include <linux/math64.h>
0017 #include <linux/regmap.h>
0018 #include <linux/slab.h>
0019 #include <sound/core.h>
0020 #include <sound/initval.h>
0021 #include <sound/jack.h>
0022 #include <sound/pcm.h>
0023 #include <sound/pcm_params.h>
0024 #include <sound/soc.h>
0025 #include <sound/tlv.h>
0026 #include "nau8821.h"
0027 
0028 #define NAU_FREF_MAX 13500000
0029 #define NAU_FVCO_MAX 100000000
0030 #define NAU_FVCO_MIN 90000000
0031 
0032 #define NAU8821_BUTTON SND_JACK_BTN_0
0033 
0034 /* the maximum frequency of CLK_ADC and CLK_DAC */
0035 #define CLK_DA_AD_MAX 6144000
0036 
0037 static int nau8821_configure_sysclk(struct nau8821 *nau8821,
0038     int clk_id, unsigned int freq);
0039 static bool nau8821_is_jack_inserted(struct regmap *regmap);
0040 
0041 struct nau8821_fll {
0042     int mclk_src;
0043     int ratio;
0044     int fll_frac;
0045     int fll_int;
0046     int clk_ref_div;
0047 };
0048 
0049 struct nau8821_fll_attr {
0050     unsigned int param;
0051     unsigned int val;
0052 };
0053 
0054 /* scaling for mclk from sysclk_src output */
0055 static const struct nau8821_fll_attr mclk_src_scaling[] = {
0056     { 1, 0x0 },
0057     { 2, 0x2 },
0058     { 4, 0x3 },
0059     { 8, 0x4 },
0060     { 16, 0x5 },
0061     { 32, 0x6 },
0062     { 3, 0x7 },
0063     { 6, 0xa },
0064     { 12, 0xb },
0065     { 24, 0xc },
0066     { 48, 0xd },
0067     { 96, 0xe },
0068     { 5, 0xf },
0069 };
0070 
0071 /* ratio for input clk freq */
0072 static const struct nau8821_fll_attr fll_ratio[] = {
0073     { 512000, 0x01 },
0074     { 256000, 0x02 },
0075     { 128000, 0x04 },
0076     { 64000, 0x08 },
0077     { 32000, 0x10 },
0078     { 8000, 0x20 },
0079     { 4000, 0x40 },
0080 };
0081 
0082 static const struct nau8821_fll_attr fll_pre_scalar[] = {
0083     { 0, 0x0 },
0084     { 1, 0x1 },
0085     { 2, 0x2 },
0086     { 3, 0x3 },
0087 };
0088 
0089 /* over sampling rate */
0090 struct nau8821_osr_attr {
0091     unsigned int osr;
0092     unsigned int clk_src;
0093 };
0094 
0095 static const struct nau8821_osr_attr osr_dac_sel[] = {
0096     { 64, 2 },  /* OSR 64, SRC 1/4 */
0097     { 256, 0 }, /* OSR 256, SRC 1 */
0098     { 128, 1 }, /* OSR 128, SRC 1/2 */
0099     { 0, 0 },
0100     { 32, 3 },  /* OSR 32, SRC 1/8 */
0101 };
0102 
0103 static const struct nau8821_osr_attr osr_adc_sel[] = {
0104     { 32, 3 },  /* OSR 32, SRC 1/8 */
0105     { 64, 2 },  /* OSR 64, SRC 1/4 */
0106     { 128, 1 }, /* OSR 128, SRC 1/2 */
0107     { 256, 0 }, /* OSR 256, SRC 1 */
0108 };
0109 
0110 struct nau8821_dmic_speed {
0111     unsigned int param;
0112     unsigned int val;
0113 };
0114 
0115 static const struct nau8821_dmic_speed dmic_speed_sel[] = {
0116     { 0, 0x0 }, /*SPEED 1, SRC 1 */
0117     { 1, 0x1 }, /*SPEED 2, SRC 1/2 */
0118     { 2, 0x2 }, /*SPEED 4, SRC 1/4 */
0119     { 3, 0x3 }, /*SPEED 8, SRC 1/8 */
0120 };
0121 
0122 static const struct reg_default nau8821_reg_defaults[] = {
0123     { NAU8821_R01_ENA_CTRL, 0x00ff },
0124     { NAU8821_R03_CLK_DIVIDER, 0x0050 },
0125     { NAU8821_R04_FLL1, 0x0 },
0126     { NAU8821_R05_FLL2, 0x00bc },
0127     { NAU8821_R06_FLL3, 0x0008 },
0128     { NAU8821_R07_FLL4, 0x0010 },
0129     { NAU8821_R08_FLL5, 0x4000 },
0130     { NAU8821_R09_FLL6, 0x6900 },
0131     { NAU8821_R0A_FLL7, 0x0031 },
0132     { NAU8821_R0B_FLL8, 0x26e9 },
0133     { NAU8821_R0D_JACK_DET_CTRL, 0x0 },
0134     { NAU8821_R0F_INTERRUPT_MASK, 0x0 },
0135     { NAU8821_R12_INTERRUPT_DIS_CTRL, 0xffff },
0136     { NAU8821_R13_DMIC_CTRL, 0x0 },
0137     { NAU8821_R1A_GPIO12_CTRL, 0x0 },
0138     { NAU8821_R1B_TDM_CTRL, 0x0 },
0139     { NAU8821_R1C_I2S_PCM_CTRL1, 0x000a },
0140     { NAU8821_R1D_I2S_PCM_CTRL2, 0x8010 },
0141     { NAU8821_R1E_LEFT_TIME_SLOT, 0x0 },
0142     { NAU8821_R1F_RIGHT_TIME_SLOT, 0x0 },
0143     { NAU8821_R21_BIQ0_COF1, 0x0 },
0144     { NAU8821_R22_BIQ0_COF2, 0x0 },
0145     { NAU8821_R23_BIQ0_COF3, 0x0 },
0146     { NAU8821_R24_BIQ0_COF4, 0x0 },
0147     { NAU8821_R25_BIQ0_COF5, 0x0 },
0148     { NAU8821_R26_BIQ0_COF6, 0x0 },
0149     { NAU8821_R27_BIQ0_COF7, 0x0 },
0150     { NAU8821_R28_BIQ0_COF8, 0x0 },
0151     { NAU8821_R29_BIQ0_COF9, 0x0 },
0152     { NAU8821_R2A_BIQ0_COF10, 0x0 },
0153     { NAU8821_R2B_ADC_RATE, 0x0002 },
0154     { NAU8821_R2C_DAC_CTRL1, 0x0082 },
0155     { NAU8821_R2D_DAC_CTRL2, 0x0 },
0156     { NAU8821_R2F_DAC_DGAIN_CTRL, 0x0 },
0157     { NAU8821_R30_ADC_DGAIN_CTRL, 0x0 },
0158     { NAU8821_R31_MUTE_CTRL, 0x0 },
0159     { NAU8821_R32_HSVOL_CTRL, 0x0 },
0160     { NAU8821_R34_DACR_CTRL, 0xcfcf },
0161     { NAU8821_R35_ADC_DGAIN_CTRL1, 0xcfcf },
0162     { NAU8821_R36_ADC_DRC_KNEE_IP12, 0x1486 },
0163     { NAU8821_R37_ADC_DRC_KNEE_IP34, 0x0f12 },
0164     { NAU8821_R38_ADC_DRC_SLOPES, 0x25ff },
0165     { NAU8821_R39_ADC_DRC_ATKDCY, 0x3457 },
0166     { NAU8821_R3A_DAC_DRC_KNEE_IP12, 0x1486 },
0167     { NAU8821_R3B_DAC_DRC_KNEE_IP34, 0x0f12 },
0168     { NAU8821_R3C_DAC_DRC_SLOPES, 0x25f9 },
0169     { NAU8821_R3D_DAC_DRC_ATKDCY, 0x3457 },
0170     { NAU8821_R41_BIQ1_COF1, 0x0 },
0171     { NAU8821_R42_BIQ1_COF2, 0x0 },
0172     { NAU8821_R43_BIQ1_COF3, 0x0 },
0173     { NAU8821_R44_BIQ1_COF4, 0x0 },
0174     { NAU8821_R45_BIQ1_COF5, 0x0 },
0175     { NAU8821_R46_BIQ1_COF6, 0x0 },
0176     { NAU8821_R47_BIQ1_COF7, 0x0 },
0177     { NAU8821_R48_BIQ1_COF8, 0x0 },
0178     { NAU8821_R49_BIQ1_COF9, 0x0 },
0179     { NAU8821_R4A_BIQ1_COF10, 0x0 },
0180     { NAU8821_R4B_CLASSG_CTRL, 0x0 },
0181     { NAU8821_R4C_IMM_MODE_CTRL, 0x0 },
0182     { NAU8821_R4D_IMM_RMS_L, 0x0 },
0183     { NAU8821_R53_OTPDOUT_1, 0xaad8 },
0184     { NAU8821_R54_OTPDOUT_2, 0x0002 },
0185     { NAU8821_R55_MISC_CTRL, 0x0 },
0186     { NAU8821_R66_BIAS_ADJ, 0x0 },
0187     { NAU8821_R68_TRIM_SETTINGS, 0x0 },
0188     { NAU8821_R69_ANALOG_CONTROL_1, 0x0 },
0189     { NAU8821_R6A_ANALOG_CONTROL_2, 0x0 },
0190     { NAU8821_R6B_PGA_MUTE, 0x0 },
0191     { NAU8821_R71_ANALOG_ADC_1, 0x0011 },
0192     { NAU8821_R72_ANALOG_ADC_2, 0x0020 },
0193     { NAU8821_R73_RDAC, 0x0008 },
0194     { NAU8821_R74_MIC_BIAS, 0x0006 },
0195     { NAU8821_R76_BOOST, 0x0 },
0196     { NAU8821_R77_FEPGA, 0x0 },
0197     { NAU8821_R7E_PGA_GAIN, 0x0 },
0198     { NAU8821_R7F_POWER_UP_CONTROL, 0x0 },
0199     { NAU8821_R80_CHARGE_PUMP, 0x0 },
0200 };
0201 
0202 static bool nau8821_readable_reg(struct device *dev, unsigned int reg)
0203 {
0204     switch (reg) {
0205     case NAU8821_R00_RESET ... NAU8821_R01_ENA_CTRL:
0206     case NAU8821_R03_CLK_DIVIDER ... NAU8821_R0B_FLL8:
0207     case NAU8821_R0D_JACK_DET_CTRL:
0208     case NAU8821_R0F_INTERRUPT_MASK ... NAU8821_R13_DMIC_CTRL:
0209     case NAU8821_R1A_GPIO12_CTRL ... NAU8821_R1F_RIGHT_TIME_SLOT:
0210     case NAU8821_R21_BIQ0_COF1 ... NAU8821_R2D_DAC_CTRL2:
0211     case NAU8821_R2F_DAC_DGAIN_CTRL ... NAU8821_R32_HSVOL_CTRL:
0212     case NAU8821_R34_DACR_CTRL ... NAU8821_R3D_DAC_DRC_ATKDCY:
0213     case NAU8821_R41_BIQ1_COF1 ... NAU8821_R4F_FUSE_CTRL3:
0214     case NAU8821_R51_FUSE_CTRL1:
0215     case NAU8821_R53_OTPDOUT_1 ... NAU8821_R55_MISC_CTRL:
0216     case NAU8821_R58_I2C_DEVICE_ID ... NAU8821_R5A_SOFTWARE_RST:
0217     case NAU8821_R66_BIAS_ADJ:
0218     case NAU8821_R68_TRIM_SETTINGS ... NAU8821_R6B_PGA_MUTE:
0219     case NAU8821_R71_ANALOG_ADC_1 ... NAU8821_R74_MIC_BIAS:
0220     case NAU8821_R76_BOOST ... NAU8821_R77_FEPGA:
0221     case NAU8821_R7E_PGA_GAIN ... NAU8821_R82_GENERAL_STATUS:
0222         return true;
0223     default:
0224         return false;
0225     }
0226 }
0227 
0228 static bool nau8821_writeable_reg(struct device *dev, unsigned int reg)
0229 {
0230     switch (reg) {
0231     case NAU8821_R00_RESET ... NAU8821_R01_ENA_CTRL:
0232     case NAU8821_R03_CLK_DIVIDER ... NAU8821_R0B_FLL8:
0233     case NAU8821_R0D_JACK_DET_CTRL:
0234     case NAU8821_R0F_INTERRUPT_MASK:
0235     case NAU8821_R11_INT_CLR_KEY_STATUS ... NAU8821_R13_DMIC_CTRL:
0236     case NAU8821_R1A_GPIO12_CTRL ... NAU8821_R1F_RIGHT_TIME_SLOT:
0237     case NAU8821_R21_BIQ0_COF1 ... NAU8821_R2D_DAC_CTRL2:
0238     case NAU8821_R2F_DAC_DGAIN_CTRL ... NAU8821_R32_HSVOL_CTRL:
0239     case NAU8821_R34_DACR_CTRL ... NAU8821_R3D_DAC_DRC_ATKDCY:
0240     case NAU8821_R41_BIQ1_COF1 ... NAU8821_R4C_IMM_MODE_CTRL:
0241     case NAU8821_R4E_FUSE_CTRL2 ... NAU8821_R4F_FUSE_CTRL3:
0242     case NAU8821_R51_FUSE_CTRL1:
0243     case NAU8821_R55_MISC_CTRL:
0244     case NAU8821_R5A_SOFTWARE_RST:
0245     case NAU8821_R66_BIAS_ADJ:
0246     case NAU8821_R68_TRIM_SETTINGS ... NAU8821_R6B_PGA_MUTE:
0247     case NAU8821_R71_ANALOG_ADC_1 ... NAU8821_R74_MIC_BIAS:
0248     case NAU8821_R76_BOOST ... NAU8821_R77_FEPGA:
0249     case NAU8821_R7E_PGA_GAIN ... NAU8821_R80_CHARGE_PUMP:
0250         return true;
0251     default:
0252         return false;
0253     }
0254 }
0255 
0256 static bool nau8821_volatile_reg(struct device *dev, unsigned int reg)
0257 {
0258     switch (reg) {
0259     case NAU8821_R00_RESET:
0260     case NAU8821_R10_IRQ_STATUS ... NAU8821_R11_INT_CLR_KEY_STATUS:
0261     case NAU8821_R21_BIQ0_COF1 ... NAU8821_R2A_BIQ0_COF10:
0262     case NAU8821_R41_BIQ1_COF1 ... NAU8821_R4A_BIQ1_COF10:
0263     case NAU8821_R4D_IMM_RMS_L:
0264     case NAU8821_R53_OTPDOUT_1 ... NAU8821_R54_OTPDOUT_2:
0265     case NAU8821_R58_I2C_DEVICE_ID ... NAU8821_R5A_SOFTWARE_RST:
0266     case NAU8821_R81_CHARGE_PUMP_INPUT_READ ... NAU8821_R82_GENERAL_STATUS:
0267         return true;
0268     default:
0269         return false;
0270     }
0271 }
0272 
0273 static int nau8821_biq_coeff_get(struct snd_kcontrol *kcontrol,
0274     struct snd_ctl_elem_value *ucontrol)
0275 {
0276     struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
0277     struct soc_bytes_ext *params = (void *)kcontrol->private_value;
0278 
0279     if (!component->regmap)
0280         return -EINVAL;
0281 
0282     regmap_raw_read(component->regmap, NAU8821_R21_BIQ0_COF1,
0283         ucontrol->value.bytes.data, params->max);
0284 
0285     return 0;
0286 }
0287 
0288 static int nau8821_biq_coeff_put(struct snd_kcontrol *kcontrol,
0289     struct snd_ctl_elem_value *ucontrol)
0290 {
0291     struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
0292     struct soc_bytes_ext *params = (void *)kcontrol->private_value;
0293     void *data;
0294 
0295     if (!component->regmap)
0296         return -EINVAL;
0297 
0298     data = kmemdup(ucontrol->value.bytes.data,
0299         params->max, GFP_KERNEL | GFP_DMA);
0300     if (!data)
0301         return -ENOMEM;
0302 
0303     regmap_raw_write(component->regmap, NAU8821_R21_BIQ0_COF1,
0304         data, params->max);
0305 
0306     kfree(data);
0307 
0308     return 0;
0309 }
0310 
0311 static const char * const nau8821_adc_decimation[] = {
0312     "32", "64", "128", "256" };
0313 
0314 static const struct soc_enum nau8821_adc_decimation_enum =
0315     SOC_ENUM_SINGLE(NAU8821_R2B_ADC_RATE, NAU8821_ADC_SYNC_DOWN_SFT,
0316         ARRAY_SIZE(nau8821_adc_decimation), nau8821_adc_decimation);
0317 
0318 static const char * const nau8821_dac_oversampl[] = {
0319     "64", "256", "128", "", "32" };
0320 
0321 static const struct soc_enum nau8821_dac_oversampl_enum =
0322     SOC_ENUM_SINGLE(NAU8821_R2C_DAC_CTRL1, NAU8821_DAC_OVERSAMPLE_SFT,
0323         ARRAY_SIZE(nau8821_dac_oversampl), nau8821_dac_oversampl);
0324 
0325 static const DECLARE_TLV_DB_MINMAX_MUTE(adc_vol_tlv, -6600, 2400);
0326 static const DECLARE_TLV_DB_MINMAX_MUTE(sidetone_vol_tlv, -4200, 0);
0327 static const DECLARE_TLV_DB_MINMAX(hp_vol_tlv, -900, 0);
0328 static const DECLARE_TLV_DB_SCALE(playback_vol_tlv, -6600, 50, 1);
0329 static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600);
0330 static const DECLARE_TLV_DB_MINMAX_MUTE(crosstalk_vol_tlv, -7000, 2400);
0331 
0332 static const struct snd_kcontrol_new nau8821_controls[] = {
0333     SOC_DOUBLE_TLV("Mic Volume", NAU8821_R35_ADC_DGAIN_CTRL1,
0334         NAU8821_ADCL_CH_VOL_SFT, NAU8821_ADCR_CH_VOL_SFT,
0335         0xff, 0, adc_vol_tlv),
0336     SOC_DOUBLE_TLV("Headphone Bypass Volume", NAU8821_R30_ADC_DGAIN_CTRL,
0337         12, 8, 0x0f, 0, sidetone_vol_tlv),
0338     SOC_DOUBLE_TLV("Headphone Volume", NAU8821_R32_HSVOL_CTRL,
0339         NAU8821_HPL_VOL_SFT, NAU8821_HPR_VOL_SFT, 0x3, 1, hp_vol_tlv),
0340     SOC_DOUBLE_TLV("Digital Playback Volume", NAU8821_R34_DACR_CTRL,
0341         NAU8821_DACL_CH_VOL_SFT, NAU8821_DACR_CH_VOL_SFT,
0342         0xcf, 0, playback_vol_tlv),
0343     SOC_DOUBLE_TLV("Frontend PGA Volume", NAU8821_R7E_PGA_GAIN,
0344         NAU8821_PGA_GAIN_L_SFT, NAU8821_PGA_GAIN_R_SFT,
0345         37, 0, fepga_gain_tlv),
0346     SOC_DOUBLE_TLV("Headphone Crosstalk Volume",
0347         NAU8821_R2F_DAC_DGAIN_CTRL,
0348         0, 8, 0xff, 0, crosstalk_vol_tlv),
0349 
0350     SOC_ENUM("ADC Decimation Rate", nau8821_adc_decimation_enum),
0351     SOC_ENUM("DAC Oversampling Rate", nau8821_dac_oversampl_enum),
0352     SND_SOC_BYTES_EXT("BIQ Coefficients", 20,
0353         nau8821_biq_coeff_get, nau8821_biq_coeff_put),
0354     SOC_SINGLE("ADC Phase Switch", NAU8821_R1B_TDM_CTRL,
0355         NAU8821_ADCPHS_SFT, 1, 0),
0356 };
0357 
0358 static const struct snd_kcontrol_new nau8821_dmic_mode_switch =
0359     SOC_DAPM_SINGLE("Switch", NAU8821_R13_DMIC_CTRL,
0360         NAU8821_DMIC_EN_SFT, 1, 0);
0361 
0362 static int dmic_clock_control(struct snd_soc_dapm_widget *w,
0363         struct snd_kcontrol *k, int  event)
0364 {
0365     struct snd_soc_component *component =
0366         snd_soc_dapm_to_component(w->dapm);
0367     struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
0368     int i, speed_selection = -1, clk_adc_src, clk_adc;
0369     unsigned int clk_divider_r03;
0370 
0371     /* The DMIC clock is gotten from adc clock divided by
0372      * CLK_DMIC_SRC (1, 2, 4, 8). The clock has to be equal or
0373      * less than nau8821->dmic_clk_threshold.
0374      */
0375     regmap_read(nau8821->regmap, NAU8821_R03_CLK_DIVIDER,
0376         &clk_divider_r03);
0377     clk_adc_src = (clk_divider_r03 & NAU8821_CLK_ADC_SRC_MASK)
0378         >> NAU8821_CLK_ADC_SRC_SFT;
0379     clk_adc = (nau8821->fs * 256) >> clk_adc_src;
0380 
0381     for (i = 0 ; i < 4 ; i++)
0382         if ((clk_adc >> dmic_speed_sel[i].param) <=
0383             nau8821->dmic_clk_threshold) {
0384             speed_selection = dmic_speed_sel[i].val;
0385             break;
0386         }
0387     if (i == 4)
0388         return -EINVAL;
0389 
0390     dev_dbg(nau8821->dev,
0391         "clk_adc=%d, dmic_clk_threshold = %d, param=%d, val = %d\n",
0392         clk_adc, nau8821->dmic_clk_threshold,
0393         dmic_speed_sel[i].param, dmic_speed_sel[i].val);
0394     regmap_update_bits(nau8821->regmap, NAU8821_R13_DMIC_CTRL,
0395         NAU8821_DMIC_SRC_MASK,
0396         (speed_selection << NAU8821_DMIC_SRC_SFT));
0397 
0398     return 0;
0399 }
0400 
0401 static int nau8821_left_adc_event(struct snd_soc_dapm_widget *w,
0402     struct snd_kcontrol *kcontrol, int event)
0403 {
0404     struct snd_soc_component *component =
0405         snd_soc_dapm_to_component(w->dapm);
0406     struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
0407 
0408     switch (event) {
0409     case SND_SOC_DAPM_POST_PMU:
0410         msleep(125);
0411         regmap_update_bits(nau8821->regmap, NAU8821_R01_ENA_CTRL,
0412             NAU8821_EN_ADCL, NAU8821_EN_ADCL);
0413         break;
0414     case SND_SOC_DAPM_POST_PMD:
0415         regmap_update_bits(nau8821->regmap,
0416             NAU8821_R01_ENA_CTRL, NAU8821_EN_ADCL, 0);
0417         break;
0418     default:
0419         return -EINVAL;
0420     }
0421 
0422     return 0;
0423 }
0424 
0425 static int nau8821_right_adc_event(struct snd_soc_dapm_widget *w,
0426     struct snd_kcontrol *kcontrol, int event)
0427 {
0428     struct snd_soc_component *component =
0429         snd_soc_dapm_to_component(w->dapm);
0430     struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
0431 
0432     switch (event) {
0433     case SND_SOC_DAPM_POST_PMU:
0434         msleep(125);
0435         regmap_update_bits(nau8821->regmap, NAU8821_R01_ENA_CTRL,
0436             NAU8821_EN_ADCR, NAU8821_EN_ADCR);
0437         break;
0438     case SND_SOC_DAPM_POST_PMD:
0439         regmap_update_bits(nau8821->regmap,
0440             NAU8821_R01_ENA_CTRL, NAU8821_EN_ADCR, 0);
0441         break;
0442     default:
0443         return -EINVAL;
0444     }
0445 
0446     return 0;
0447 }
0448 
0449 static int nau8821_pump_event(struct snd_soc_dapm_widget *w,
0450     struct snd_kcontrol *kcontrol, int event)
0451 {
0452     struct snd_soc_component *component =
0453         snd_soc_dapm_to_component(w->dapm);
0454     struct nau8821 *nau8821 =
0455         snd_soc_component_get_drvdata(component);
0456 
0457     switch (event) {
0458     case SND_SOC_DAPM_POST_PMU:
0459         /* Prevent startup click by letting charge pump to ramp up */
0460         msleep(20);
0461         regmap_update_bits(nau8821->regmap, NAU8821_R80_CHARGE_PUMP,
0462             NAU8821_JAMNODCLOW, NAU8821_JAMNODCLOW);
0463         break;
0464     case SND_SOC_DAPM_PRE_PMD:
0465         regmap_update_bits(nau8821->regmap, NAU8821_R80_CHARGE_PUMP,
0466             NAU8821_JAMNODCLOW, 0);
0467         break;
0468     default:
0469         return -EINVAL;
0470     }
0471 
0472     return 0;
0473 }
0474 
0475 static int nau8821_output_dac_event(struct snd_soc_dapm_widget *w,
0476     struct snd_kcontrol *kcontrol, int event)
0477 {
0478     struct snd_soc_component *component =
0479         snd_soc_dapm_to_component(w->dapm);
0480     struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
0481 
0482     switch (event) {
0483     case SND_SOC_DAPM_PRE_PMU:
0484         /* Disables the TESTDAC to let DAC signal pass through. */
0485         regmap_update_bits(nau8821->regmap, NAU8821_R66_BIAS_ADJ,
0486             NAU8821_BIAS_TESTDAC_EN, 0);
0487         break;
0488     case SND_SOC_DAPM_POST_PMD:
0489         regmap_update_bits(nau8821->regmap, NAU8821_R66_BIAS_ADJ,
0490             NAU8821_BIAS_TESTDAC_EN, NAU8821_BIAS_TESTDAC_EN);
0491         break;
0492     default:
0493         return -EINVAL;
0494     }
0495 
0496     return 0;
0497 }
0498 
0499 static int system_clock_control(struct snd_soc_dapm_widget *w,
0500                 struct snd_kcontrol *k, int  event)
0501 {
0502     struct snd_soc_component *component =
0503         snd_soc_dapm_to_component(w->dapm);
0504     struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
0505 
0506     if (SND_SOC_DAPM_EVENT_OFF(event)) {
0507         dev_dbg(nau8821->dev, "system clock control : POWER OFF\n");
0508         /* Set clock source to disable or internal clock before the
0509          * playback or capture end. Codec needs clock for Jack
0510          * detection and button press if jack inserted; otherwise,
0511          * the clock should be closed.
0512          */
0513         if (nau8821_is_jack_inserted(nau8821->regmap)) {
0514             nau8821_configure_sysclk(nau8821,
0515                 NAU8821_CLK_INTERNAL, 0);
0516         } else {
0517             nau8821_configure_sysclk(nau8821, NAU8821_CLK_DIS, 0);
0518         }
0519     }
0520     return 0;
0521 }
0522 
0523 static const struct snd_soc_dapm_widget nau8821_dapm_widgets[] = {
0524     SND_SOC_DAPM_SUPPLY("System Clock", SND_SOC_NOPM, 0, 0,
0525         system_clock_control, SND_SOC_DAPM_POST_PMD),
0526     SND_SOC_DAPM_SUPPLY("MICBIAS", NAU8821_R74_MIC_BIAS,
0527         NAU8821_MICBIAS_POWERUP_SFT, 0, NULL, 0),
0528     SND_SOC_DAPM_SUPPLY("DMIC Clock", SND_SOC_NOPM, 0, 0,
0529         dmic_clock_control, SND_SOC_DAPM_POST_PMU),
0530     SND_SOC_DAPM_ADC("ADCL Power", NULL, NAU8821_R72_ANALOG_ADC_2,
0531         NAU8821_POWERUP_ADCL_SFT, 0),
0532     SND_SOC_DAPM_ADC("ADCR Power", NULL, NAU8821_R72_ANALOG_ADC_2,
0533         NAU8821_POWERUP_ADCR_SFT, 0),
0534     SND_SOC_DAPM_PGA_S("Frontend PGA L", 1, NAU8821_R7F_POWER_UP_CONTROL,
0535         NAU8821_PUP_PGA_L_SFT, 0, NULL, 0),
0536     SND_SOC_DAPM_PGA_S("Frontend PGA R", 1, NAU8821_R7F_POWER_UP_CONTROL,
0537         NAU8821_PUP_PGA_R_SFT, 0, NULL, 0),
0538     SND_SOC_DAPM_PGA_S("ADCL Digital path", 0, NAU8821_R01_ENA_CTRL,
0539         NAU8821_EN_ADCL_SFT, 0, nau8821_left_adc_event,
0540         SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
0541     SND_SOC_DAPM_PGA_S("ADCR Digital path", 0, NAU8821_R01_ENA_CTRL,
0542         NAU8821_EN_ADCR_SFT, 0, nau8821_right_adc_event,
0543         SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
0544     SND_SOC_DAPM_SWITCH("DMIC Enable", SND_SOC_NOPM,
0545         0, 0, &nau8821_dmic_mode_switch),
0546     SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, NAU8821_R1D_I2S_PCM_CTRL2,
0547         NAU8821_I2S_TRISTATE_SFT, 1),
0548     SND_SOC_DAPM_AIF_IN("AIFRX", "Playback", 0, SND_SOC_NOPM, 0, 0),
0549 
0550     SND_SOC_DAPM_PGA_S("ADACL", 2, NAU8821_R73_RDAC,
0551         NAU8821_DACL_EN_SFT, 0, NULL, 0),
0552     SND_SOC_DAPM_PGA_S("ADACR", 2, NAU8821_R73_RDAC,
0553         NAU8821_DACR_EN_SFT, 0, NULL, 0),
0554     SND_SOC_DAPM_PGA_S("ADACL Clock", 3, NAU8821_R73_RDAC,
0555         NAU8821_DACL_CLK_EN_SFT, 0, NULL, 0),
0556     SND_SOC_DAPM_PGA_S("ADACR Clock", 3, NAU8821_R73_RDAC,
0557         NAU8821_DACR_CLK_EN_SFT, 0, NULL, 0),
0558     SND_SOC_DAPM_DAC("DDACR", NULL, NAU8821_R01_ENA_CTRL,
0559         NAU8821_EN_DACR_SFT, 0),
0560     SND_SOC_DAPM_DAC("DDACL", NULL, NAU8821_R01_ENA_CTRL,
0561         NAU8821_EN_DACL_SFT, 0),
0562     SND_SOC_DAPM_PGA_S("HP amp L", 0, NAU8821_R4B_CLASSG_CTRL,
0563         NAU8821_CLASSG_LDAC_EN_SFT, 0, NULL, 0),
0564     SND_SOC_DAPM_PGA_S("HP amp R", 0, NAU8821_R4B_CLASSG_CTRL,
0565         NAU8821_CLASSG_RDAC_EN_SFT, 0, NULL, 0),
0566     SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8821_R80_CHARGE_PUMP,
0567         NAU8821_CHANRGE_PUMP_EN_SFT, 0, nau8821_pump_event,
0568         SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
0569     SND_SOC_DAPM_PGA_S("Output Driver R Stage 1", 4,
0570         NAU8821_R7F_POWER_UP_CONTROL,
0571         NAU8821_PUP_INTEG_R_SFT, 0, NULL, 0),
0572     SND_SOC_DAPM_PGA_S("Output Driver L Stage 1", 4,
0573         NAU8821_R7F_POWER_UP_CONTROL,
0574         NAU8821_PUP_INTEG_L_SFT, 0, NULL, 0),
0575     SND_SOC_DAPM_PGA_S("Output Driver R Stage 2", 5,
0576         NAU8821_R7F_POWER_UP_CONTROL,
0577         NAU8821_PUP_DRV_INSTG_R_SFT, 0, NULL, 0),
0578     SND_SOC_DAPM_PGA_S("Output Driver L Stage 2", 5,
0579         NAU8821_R7F_POWER_UP_CONTROL,
0580         NAU8821_PUP_DRV_INSTG_L_SFT, 0, NULL, 0),
0581     SND_SOC_DAPM_PGA_S("Output Driver R Stage 3", 6,
0582         NAU8821_R7F_POWER_UP_CONTROL,
0583         NAU8821_PUP_MAIN_DRV_R_SFT, 0, NULL, 0),
0584     SND_SOC_DAPM_PGA_S("Output Driver L Stage 3", 6,
0585         NAU8821_R7F_POWER_UP_CONTROL,
0586         NAU8821_PUP_MAIN_DRV_L_SFT, 0, NULL, 0),
0587     SND_SOC_DAPM_PGA_S("Output DACL", 7,
0588         NAU8821_R80_CHARGE_PUMP, NAU8821_POWER_DOWN_DACL_SFT,
0589         0, nau8821_output_dac_event,
0590         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0591     SND_SOC_DAPM_PGA_S("Output DACR", 7,
0592         NAU8821_R80_CHARGE_PUMP, NAU8821_POWER_DOWN_DACR_SFT,
0593         0, nau8821_output_dac_event,
0594         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0595 
0596     /* HPOL/R are ungrounded by disabling 16 Ohm pull-downs on playback */
0597     SND_SOC_DAPM_PGA_S("HPOL Pulldown", 8,
0598         NAU8821_R0D_JACK_DET_CTRL,
0599         NAU8821_SPKR_DWN1L_SFT, 0, NULL, 0),
0600     SND_SOC_DAPM_PGA_S("HPOR Pulldown", 8,
0601         NAU8821_R0D_JACK_DET_CTRL,
0602         NAU8821_SPKR_DWN1R_SFT, 0, NULL, 0),
0603 
0604     /* High current HPOL/R boost driver */
0605     SND_SOC_DAPM_PGA_S("HP Boost Driver", 9,
0606         NAU8821_R76_BOOST, NAU8821_HP_BOOST_DIS_SFT, 1, NULL, 0),
0607     SND_SOC_DAPM_PGA("Class G", NAU8821_R4B_CLASSG_CTRL,
0608         NAU8821_CLASSG_EN_SFT, 0, NULL, 0),
0609 
0610     SND_SOC_DAPM_INPUT("MICL"),
0611     SND_SOC_DAPM_INPUT("MICR"),
0612     SND_SOC_DAPM_INPUT("DMIC"),
0613     SND_SOC_DAPM_OUTPUT("HPOL"),
0614     SND_SOC_DAPM_OUTPUT("HPOR"),
0615 };
0616 
0617 static const struct snd_soc_dapm_route nau8821_dapm_routes[] = {
0618     {"DMIC Enable", "Switch", "DMIC"},
0619     {"DMIC Enable", NULL, "DMIC Clock"},
0620 
0621     {"Frontend PGA L", NULL, "MICL"},
0622     {"Frontend PGA R", NULL, "MICR"},
0623     {"Frontend PGA L", NULL, "MICBIAS"},
0624     {"Frontend PGA R", NULL, "MICBIAS"},
0625 
0626     {"ADCL Power", NULL, "Frontend PGA L"},
0627     {"ADCR Power", NULL, "Frontend PGA R"},
0628 
0629     {"ADCL Digital path", NULL, "ADCL Power"},
0630     {"ADCR Digital path", NULL, "ADCR Power"},
0631     {"ADCL Digital path", NULL, "DMIC Enable"},
0632     {"ADCR Digital path", NULL, "DMIC Enable"},
0633 
0634     {"AIFTX", NULL, "ADCL Digital path"},
0635     {"AIFTX", NULL, "ADCR Digital path"},
0636 
0637     {"AIFTX", NULL, "System Clock"},
0638     {"AIFRX", NULL, "System Clock"},
0639 
0640     {"DDACL", NULL, "AIFRX"},
0641     {"DDACR", NULL, "AIFRX"},
0642 
0643     {"HP amp L", NULL, "DDACL"},
0644     {"HP amp R", NULL, "DDACR"},
0645 
0646     {"Charge Pump", NULL, "HP amp L"},
0647     {"Charge Pump", NULL, "HP amp R"},
0648 
0649     {"ADACL", NULL, "Charge Pump"},
0650     {"ADACR", NULL, "Charge Pump"},
0651     {"ADACL Clock", NULL, "ADACL"},
0652     {"ADACR Clock", NULL, "ADACR"},
0653 
0654     {"Output Driver L Stage 1", NULL, "ADACL Clock"},
0655     {"Output Driver R Stage 1", NULL, "ADACR Clock"},
0656     {"Output Driver L Stage 2", NULL, "Output Driver L Stage 1"},
0657     {"Output Driver R Stage 2", NULL, "Output Driver R Stage 1"},
0658     {"Output Driver L Stage 3", NULL, "Output Driver L Stage 2"},
0659     {"Output Driver R Stage 3", NULL, "Output Driver R Stage 2"},
0660     {"Output DACL", NULL, "Output Driver L Stage 3"},
0661     {"Output DACR", NULL, "Output Driver R Stage 3"},
0662 
0663     {"HPOL Pulldown", NULL, "Output DACL"},
0664     {"HPOR Pulldown", NULL, "Output DACR"},
0665     {"HP Boost Driver", NULL, "HPOL Pulldown"},
0666     {"HP Boost Driver", NULL, "HPOR Pulldown"},
0667 
0668     {"Class G", NULL, "HP Boost Driver"},
0669     {"HPOL", NULL, "Class G"},
0670     {"HPOR", NULL, "Class G"},
0671 };
0672 
0673 static const struct nau8821_osr_attr *
0674 nau8821_get_osr(struct nau8821 *nau8821, int stream)
0675 {
0676     unsigned int osr;
0677 
0678     if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
0679         regmap_read(nau8821->regmap, NAU8821_R2C_DAC_CTRL1, &osr);
0680         osr &= NAU8821_DAC_OVERSAMPLE_MASK;
0681         if (osr >= ARRAY_SIZE(osr_dac_sel))
0682             return NULL;
0683         return &osr_dac_sel[osr];
0684     } else {
0685         regmap_read(nau8821->regmap, NAU8821_R2B_ADC_RATE, &osr);
0686         osr &= NAU8821_ADC_SYNC_DOWN_MASK;
0687         if (osr >= ARRAY_SIZE(osr_adc_sel))
0688             return NULL;
0689         return &osr_adc_sel[osr];
0690     }
0691 }
0692 
0693 static int nau8821_dai_startup(struct snd_pcm_substream *substream,
0694                    struct snd_soc_dai *dai)
0695 {
0696     struct snd_soc_component *component = dai->component;
0697     struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
0698     const struct nau8821_osr_attr *osr;
0699 
0700     osr = nau8821_get_osr(nau8821, substream->stream);
0701     if (!osr || !osr->osr)
0702         return -EINVAL;
0703 
0704     return snd_pcm_hw_constraint_minmax(substream->runtime,
0705                         SNDRV_PCM_HW_PARAM_RATE,
0706                         0, CLK_DA_AD_MAX / osr->osr);
0707 }
0708 
0709 static int nau8821_hw_params(struct snd_pcm_substream *substream,
0710     struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
0711 {
0712     struct snd_soc_component *component = dai->component;
0713     struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
0714     unsigned int val_len = 0, ctrl_val, bclk_fs, clk_div;
0715     const struct nau8821_osr_attr *osr;
0716 
0717     nau8821->fs = params_rate(params);
0718     /* CLK_DAC or CLK_ADC = OSR * FS
0719      * DAC or ADC clock frequency is defined as Over Sampling Rate (OSR)
0720      * multiplied by the audio sample rate (Fs). Note that the OSR and Fs
0721      * values must be selected such that the maximum frequency is less
0722      * than 6.144 MHz.
0723      */
0724     osr = nau8821_get_osr(nau8821, substream->stream);
0725     if (!osr || !osr->osr)
0726         return -EINVAL;
0727     if (nau8821->fs * osr->osr > CLK_DA_AD_MAX)
0728         return -EINVAL;
0729     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
0730         regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER,
0731             NAU8821_CLK_DAC_SRC_MASK,
0732             osr->clk_src << NAU8821_CLK_DAC_SRC_SFT);
0733     else
0734         regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER,
0735             NAU8821_CLK_ADC_SRC_MASK,
0736             osr->clk_src << NAU8821_CLK_ADC_SRC_SFT);
0737 
0738     /* make BCLK and LRC divde configuration if the codec as master. */
0739     regmap_read(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2, &ctrl_val);
0740     if (ctrl_val & NAU8821_I2S_MS_MASTER) {
0741         /* get the bclk and fs ratio */
0742         bclk_fs = snd_soc_params_to_bclk(params) / nau8821->fs;
0743         if (bclk_fs <= 32)
0744             clk_div = 3;
0745         else if (bclk_fs <= 64)
0746             clk_div = 2;
0747         else if (bclk_fs <= 128)
0748             clk_div = 1;
0749         else {
0750             return -EINVAL;
0751         }
0752         regmap_update_bits(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2,
0753             NAU8821_I2S_LRC_DIV_MASK | NAU8821_I2S_BLK_DIV_MASK,
0754             (clk_div << NAU8821_I2S_LRC_DIV_SFT) | clk_div);
0755     }
0756 
0757     switch (params_width(params)) {
0758     case 16:
0759         val_len |= NAU8821_I2S_DL_16;
0760         break;
0761     case 20:
0762         val_len |= NAU8821_I2S_DL_20;
0763         break;
0764     case 24:
0765         val_len |= NAU8821_I2S_DL_24;
0766         break;
0767     case 32:
0768         val_len |= NAU8821_I2S_DL_32;
0769         break;
0770     default:
0771         return -EINVAL;
0772     }
0773 
0774     regmap_update_bits(nau8821->regmap, NAU8821_R1C_I2S_PCM_CTRL1,
0775         NAU8821_I2S_DL_MASK, val_len);
0776 
0777     return 0;
0778 }
0779 
0780 static int nau8821_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
0781 {
0782     struct snd_soc_component *component = codec_dai->component;
0783     struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
0784     unsigned int ctrl1_val = 0, ctrl2_val = 0;
0785 
0786     switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
0787     case SND_SOC_DAIFMT_CBP_CFP:
0788         ctrl2_val |= NAU8821_I2S_MS_MASTER;
0789         break;
0790     case SND_SOC_DAIFMT_CBC_CFC:
0791         break;
0792     default:
0793         return -EINVAL;
0794     }
0795 
0796     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0797     case SND_SOC_DAIFMT_NB_NF:
0798         break;
0799     case SND_SOC_DAIFMT_IB_NF:
0800         ctrl1_val |= NAU8821_I2S_BP_INV;
0801         break;
0802     default:
0803         return -EINVAL;
0804     }
0805 
0806     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0807     case SND_SOC_DAIFMT_I2S:
0808         ctrl1_val |= NAU8821_I2S_DF_I2S;
0809         break;
0810     case SND_SOC_DAIFMT_LEFT_J:
0811         ctrl1_val |= NAU8821_I2S_DF_LEFT;
0812         break;
0813     case SND_SOC_DAIFMT_RIGHT_J:
0814         ctrl1_val |= NAU8821_I2S_DF_RIGTH;
0815         break;
0816     case SND_SOC_DAIFMT_DSP_A:
0817         ctrl1_val |= NAU8821_I2S_DF_PCM_AB;
0818         break;
0819     case SND_SOC_DAIFMT_DSP_B:
0820         ctrl1_val |= NAU8821_I2S_DF_PCM_AB;
0821         ctrl1_val |= NAU8821_I2S_PCMB_EN;
0822         break;
0823     default:
0824         return -EINVAL;
0825     }
0826 
0827     regmap_update_bits(nau8821->regmap, NAU8821_R1C_I2S_PCM_CTRL1,
0828         NAU8821_I2S_DL_MASK | NAU8821_I2S_DF_MASK |
0829         NAU8821_I2S_BP_MASK | NAU8821_I2S_PCMB_MASK, ctrl1_val);
0830     regmap_update_bits(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2,
0831         NAU8821_I2S_MS_MASK, ctrl2_val);
0832 
0833     return 0;
0834 }
0835 
0836 static int nau8821_digital_mute(struct snd_soc_dai *dai, int mute,
0837         int direction)
0838 {
0839     struct snd_soc_component *component = dai->component;
0840     struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
0841     unsigned int val = 0;
0842 
0843     if (mute)
0844         val = NAU8821_DAC_SOFT_MUTE;
0845 
0846     return regmap_update_bits(nau8821->regmap,
0847         NAU8821_R31_MUTE_CTRL, NAU8821_DAC_SOFT_MUTE, val);
0848 }
0849 
0850 static const struct snd_soc_dai_ops nau8821_dai_ops = {
0851     .startup = nau8821_dai_startup,
0852     .hw_params = nau8821_hw_params,
0853     .set_fmt = nau8821_set_dai_fmt,
0854     .mute_stream = nau8821_digital_mute,
0855     .no_capture_mute = 1,
0856 };
0857 
0858 #define NAU8821_RATES SNDRV_PCM_RATE_8000_192000
0859 #define NAU8821_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
0860     | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
0861 
0862 static struct snd_soc_dai_driver nau8821_dai = {
0863     .name = NUVOTON_CODEC_DAI,
0864     .playback = {
0865         .stream_name = "Playback",
0866         .channels_min = 1,
0867         .channels_max = 2,
0868         .rates = NAU8821_RATES,
0869         .formats = NAU8821_FORMATS,
0870     },
0871     .capture = {
0872         .stream_name = "Capture",
0873         .channels_min = 1,
0874         .channels_max = 2,
0875         .rates = NAU8821_RATES,
0876         .formats = NAU8821_FORMATS,
0877     },
0878     .ops = &nau8821_dai_ops,
0879 };
0880 
0881 
0882 static bool nau8821_is_jack_inserted(struct regmap *regmap)
0883 {
0884     bool active_high, is_high;
0885     int status, jkdet;
0886 
0887     regmap_read(regmap, NAU8821_R0D_JACK_DET_CTRL, &jkdet);
0888     active_high = jkdet & NAU8821_JACK_POLARITY;
0889     regmap_read(regmap, NAU8821_R82_GENERAL_STATUS, &status);
0890     is_high = status & NAU8821_GPIO2_IN;
0891     /* return jack connection status according to jack insertion logic
0892      * active high or active low.
0893      */
0894     return active_high == is_high;
0895 }
0896 
0897 static void nau8821_int_status_clear_all(struct regmap *regmap)
0898 {
0899     int active_irq, clear_irq, i;
0900 
0901     /* Reset the intrruption status from rightmost bit if the corres-
0902      * ponding irq event occurs.
0903      */
0904     regmap_read(regmap, NAU8821_R10_IRQ_STATUS, &active_irq);
0905     for (i = 0; i < NAU8821_REG_DATA_LEN; i++) {
0906         clear_irq = (0x1 << i);
0907         if (active_irq & clear_irq)
0908             regmap_write(regmap,
0909                 NAU8821_R11_INT_CLR_KEY_STATUS, clear_irq);
0910     }
0911 }
0912 
0913 static void nau8821_eject_jack(struct nau8821 *nau8821)
0914 {
0915     struct snd_soc_dapm_context *dapm = nau8821->dapm;
0916     struct regmap *regmap = nau8821->regmap;
0917     struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
0918 
0919     /* Detach 2kOhm Resistors from MICBIAS to MICGND */
0920     regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS,
0921         NAU8821_MICBIAS_JKR2, 0);
0922     /* HPL/HPR short to ground */
0923     regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
0924         NAU8821_SPKR_DWN1R | NAU8821_SPKR_DWN1L, 0);
0925     snd_soc_component_disable_pin(component, "MICBIAS");
0926     snd_soc_dapm_sync(dapm);
0927 
0928     /* Clear all interruption status */
0929     nau8821_int_status_clear_all(regmap);
0930 
0931     /* Enable the insertion interruption, disable the ejection inter-
0932      * ruption, and then bypass de-bounce circuit.
0933      */
0934     regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL,
0935         NAU8821_IRQ_EJECT_DIS | NAU8821_IRQ_INSERT_DIS,
0936         NAU8821_IRQ_EJECT_DIS);
0937     /* Mask unneeded IRQs: 1 - disable, 0 - enable */
0938     regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
0939         NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN,
0940         NAU8821_IRQ_EJECT_EN);
0941 
0942     regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
0943         NAU8821_JACK_DET_DB_BYPASS, NAU8821_JACK_DET_DB_BYPASS);
0944 
0945     /* Close clock for jack type detection at manual mode */
0946     if (dapm->bias_level < SND_SOC_BIAS_PREPARE)
0947         nau8821_configure_sysclk(nau8821, NAU8821_CLK_DIS, 0);
0948 
0949     /* Recover to normal channel input */
0950     regmap_update_bits(regmap, NAU8821_R2B_ADC_RATE,
0951             NAU8821_ADC_R_SRC_EN, 0);
0952     if (nau8821->key_enable) {
0953         regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
0954             NAU8821_IRQ_KEY_RELEASE_EN |
0955             NAU8821_IRQ_KEY_PRESS_EN,
0956             NAU8821_IRQ_KEY_RELEASE_EN |
0957             NAU8821_IRQ_KEY_PRESS_EN);
0958         regmap_update_bits(regmap,
0959             NAU8821_R12_INTERRUPT_DIS_CTRL,
0960             NAU8821_IRQ_KEY_RELEASE_DIS |
0961             NAU8821_IRQ_KEY_PRESS_DIS,
0962             NAU8821_IRQ_KEY_RELEASE_DIS |
0963             NAU8821_IRQ_KEY_PRESS_DIS);
0964     }
0965 
0966 }
0967 
0968 static void nau8821_jdet_work(struct work_struct *work)
0969 {
0970     struct nau8821 *nau8821 =
0971         container_of(work, struct nau8821, jdet_work);
0972     struct snd_soc_dapm_context *dapm = nau8821->dapm;
0973     struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
0974     struct regmap *regmap = nau8821->regmap;
0975     int jack_status_reg, mic_detected, event = 0, event_mask = 0;
0976 
0977     snd_soc_component_force_enable_pin(component, "MICBIAS");
0978     snd_soc_dapm_sync(dapm);
0979     msleep(20);
0980 
0981     regmap_read(regmap, NAU8821_R58_I2C_DEVICE_ID, &jack_status_reg);
0982     mic_detected = !(jack_status_reg & NAU8821_KEYDET);
0983     if (mic_detected) {
0984         dev_dbg(nau8821->dev, "Headset connected\n");
0985         event |= SND_JACK_HEADSET;
0986 
0987         /* 2kOhm Resistor from MICBIAS to MICGND1 */
0988         regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS,
0989             NAU8821_MICBIAS_JKR2, NAU8821_MICBIAS_JKR2);
0990         /* Latch Right Channel Analog data
0991          * input into the Right Channel Filter
0992          */
0993         regmap_update_bits(regmap, NAU8821_R2B_ADC_RATE,
0994             NAU8821_ADC_R_SRC_EN, NAU8821_ADC_R_SRC_EN);
0995         if (nau8821->key_enable) {
0996             regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
0997                 NAU8821_IRQ_KEY_RELEASE_EN |
0998                 NAU8821_IRQ_KEY_PRESS_EN, 0);
0999             regmap_update_bits(regmap,
1000                 NAU8821_R12_INTERRUPT_DIS_CTRL,
1001                 NAU8821_IRQ_KEY_RELEASE_DIS |
1002                 NAU8821_IRQ_KEY_PRESS_DIS, 0);
1003         }
1004     } else {
1005         dev_dbg(nau8821->dev, "Headphone connected\n");
1006         event |= SND_JACK_HEADPHONE;
1007         snd_soc_component_disable_pin(component, "MICBIAS");
1008         snd_soc_dapm_sync(dapm);
1009     }
1010     event_mask |= SND_JACK_HEADSET;
1011     snd_soc_jack_report(nau8821->jack, event, event_mask);
1012 }
1013 
1014 /* Enable interruptions with internal clock. */
1015 static void nau8821_setup_inserted_irq(struct nau8821 *nau8821)
1016 {
1017     struct regmap *regmap = nau8821->regmap;
1018 
1019     /* Enable internal VCO needed for interruptions */
1020     if (nau8821->dapm->bias_level < SND_SOC_BIAS_PREPARE)
1021         nau8821_configure_sysclk(nau8821, NAU8821_CLK_INTERNAL, 0);
1022 
1023     /* Chip needs one FSCLK cycle in order to generate interruptions,
1024      * as we cannot guarantee one will be provided by the system. Turning
1025      * master mode on then off enables us to generate that FSCLK cycle
1026      * with a minimum of contention on the clock bus.
1027      */
1028     regmap_update_bits(regmap, NAU8821_R1D_I2S_PCM_CTRL2,
1029         NAU8821_I2S_MS_MASK, NAU8821_I2S_MS_MASTER);
1030     regmap_update_bits(regmap, NAU8821_R1D_I2S_PCM_CTRL2,
1031         NAU8821_I2S_MS_MASK, NAU8821_I2S_MS_SLAVE);
1032 
1033     /* Not bypass de-bounce circuit */
1034     regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
1035         NAU8821_JACK_DET_DB_BYPASS, 0);
1036 
1037     regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
1038         NAU8821_IRQ_EJECT_EN, 0);
1039     regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL,
1040         NAU8821_IRQ_EJECT_DIS, 0);
1041 }
1042 
1043 static irqreturn_t nau8821_interrupt(int irq, void *data)
1044 {
1045     struct nau8821 *nau8821 = (struct nau8821 *)data;
1046     struct regmap *regmap = nau8821->regmap;
1047     int active_irq, clear_irq = 0, event = 0, event_mask = 0;
1048 
1049     if (regmap_read(regmap, NAU8821_R10_IRQ_STATUS, &active_irq)) {
1050         dev_err(nau8821->dev, "failed to read irq status\n");
1051         return IRQ_NONE;
1052     }
1053 
1054     dev_dbg(nau8821->dev, "IRQ %d\n", active_irq);
1055 
1056     if ((active_irq & NAU8821_JACK_EJECT_IRQ_MASK) ==
1057         NAU8821_JACK_EJECT_DETECTED) {
1058         regmap_update_bits(regmap, NAU8821_R71_ANALOG_ADC_1,
1059             NAU8821_MICDET_MASK, NAU8821_MICDET_DIS);
1060         nau8821_eject_jack(nau8821);
1061         event_mask |= SND_JACK_HEADSET;
1062         clear_irq = NAU8821_JACK_EJECT_IRQ_MASK;
1063     } else if (active_irq & NAU8821_KEY_SHORT_PRESS_IRQ) {
1064         event |= NAU8821_BUTTON;
1065         event_mask |= NAU8821_BUTTON;
1066         clear_irq = NAU8821_KEY_SHORT_PRESS_IRQ;
1067     } else if (active_irq & NAU8821_KEY_RELEASE_IRQ) {
1068         event_mask = NAU8821_BUTTON;
1069         clear_irq = NAU8821_KEY_RELEASE_IRQ;
1070     } else if ((active_irq & NAU8821_JACK_INSERT_IRQ_MASK) ==
1071         NAU8821_JACK_INSERT_DETECTED) {
1072         regmap_update_bits(regmap, NAU8821_R71_ANALOG_ADC_1,
1073             NAU8821_MICDET_MASK, NAU8821_MICDET_EN);
1074         if (nau8821_is_jack_inserted(regmap)) {
1075             /* detect microphone and jack type */
1076             cancel_work_sync(&nau8821->jdet_work);
1077             schedule_work(&nau8821->jdet_work);
1078             /* Turn off insertion interruption at manual mode */
1079             regmap_update_bits(regmap,
1080                 NAU8821_R12_INTERRUPT_DIS_CTRL,
1081                 NAU8821_IRQ_INSERT_DIS,
1082                 NAU8821_IRQ_INSERT_DIS);
1083             regmap_update_bits(regmap,
1084                 NAU8821_R0F_INTERRUPT_MASK,
1085                 NAU8821_IRQ_INSERT_EN,
1086                 NAU8821_IRQ_INSERT_EN);
1087             nau8821_setup_inserted_irq(nau8821);
1088         } else {
1089             dev_warn(nau8821->dev,
1090                 "Inserted IRQ fired but not connected\n");
1091             nau8821_eject_jack(nau8821);
1092         }
1093     }
1094 
1095     if (!clear_irq)
1096         clear_irq = active_irq;
1097     /* clears the rightmost interruption */
1098     regmap_write(regmap, NAU8821_R11_INT_CLR_KEY_STATUS, clear_irq);
1099 
1100     if (event_mask)
1101         snd_soc_jack_report(nau8821->jack, event, event_mask);
1102 
1103     return IRQ_HANDLED;
1104 }
1105 
1106 static const struct regmap_config nau8821_regmap_config = {
1107     .val_bits = NAU8821_REG_DATA_LEN,
1108     .reg_bits = NAU8821_REG_ADDR_LEN,
1109 
1110     .max_register = NAU8821_REG_MAX,
1111     .readable_reg = nau8821_readable_reg,
1112     .writeable_reg = nau8821_writeable_reg,
1113     .volatile_reg = nau8821_volatile_reg,
1114 
1115     .cache_type = REGCACHE_RBTREE,
1116     .reg_defaults = nau8821_reg_defaults,
1117     .num_reg_defaults = ARRAY_SIZE(nau8821_reg_defaults),
1118 };
1119 
1120 static int nau8821_component_probe(struct snd_soc_component *component)
1121 {
1122     struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1123     struct snd_soc_dapm_context *dapm =
1124         snd_soc_component_get_dapm(component);
1125 
1126     nau8821->dapm = dapm;
1127 
1128     return 0;
1129 }
1130 
1131 /**
1132  * nau8821_calc_fll_param - Calculate FLL parameters.
1133  * @fll_in: external clock provided to codec.
1134  * @fs: sampling rate.
1135  * @fll_param: Pointer to structure of FLL parameters.
1136  *
1137  * Calculate FLL parameters to configure codec.
1138  *
1139  * Returns 0 for success or negative error code.
1140  */
1141 static int nau8821_calc_fll_param(unsigned int fll_in,
1142     unsigned int fs, struct nau8821_fll *fll_param)
1143 {
1144     u64 fvco, fvco_max;
1145     unsigned int fref, i, fvco_sel;
1146 
1147     /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by
1148      * dividing freq_in by 1, 2, 4, or 8 using FLL pre-scalar.
1149      * FREF = freq_in / NAU8821_FLL_REF_DIV_MASK
1150      */
1151     for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {
1152         fref = fll_in >> fll_pre_scalar[i].param;
1153         if (fref <= NAU_FREF_MAX)
1154             break;
1155     }
1156     if (i == ARRAY_SIZE(fll_pre_scalar))
1157         return -EINVAL;
1158     fll_param->clk_ref_div = fll_pre_scalar[i].val;
1159 
1160     /* Choose the FLL ratio based on FREF */
1161     for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {
1162         if (fref >= fll_ratio[i].param)
1163             break;
1164     }
1165     if (i == ARRAY_SIZE(fll_ratio))
1166         return -EINVAL;
1167     fll_param->ratio = fll_ratio[i].val;
1168 
1169     /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs.
1170      * FDCO must be within the 90MHz - 100MHz or the FFL cannot be
1171      * guaranteed across the full range of operation.
1172      * FDCO = freq_out * 2 * mclk_src_scaling
1173      */
1174     fvco_max = 0;
1175     fvco_sel = ARRAY_SIZE(mclk_src_scaling);
1176     for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {
1177         fvco = 256ULL * fs * 2 * mclk_src_scaling[i].param;
1178         if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX &&
1179             fvco_max < fvco) {
1180             fvco_max = fvco;
1181             fvco_sel = i;
1182         }
1183     }
1184     if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel)
1185         return -EINVAL;
1186     fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;
1187 
1188     /* Calculate the FLL 10-bit integer input and the FLL 24-bit fractional
1189      * input based on FDCO, FREF and FLL ratio.
1190      */
1191     fvco = div_u64(fvco_max << 24, fref * fll_param->ratio);
1192     fll_param->fll_int = (fvco >> 24) & 0x3ff;
1193     fll_param->fll_frac = fvco & 0xffffff;
1194 
1195     return 0;
1196 }
1197 
1198 static void nau8821_fll_apply(struct nau8821 *nau8821,
1199         struct nau8821_fll *fll_param)
1200 {
1201     struct regmap *regmap = nau8821->regmap;
1202 
1203     regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER,
1204         NAU8821_CLK_SRC_MASK | NAU8821_CLK_MCLK_SRC_MASK,
1205         NAU8821_CLK_SRC_MCLK | fll_param->mclk_src);
1206     /* Make DSP operate at high speed for better performance. */
1207     regmap_update_bits(regmap, NAU8821_R04_FLL1,
1208         NAU8821_FLL_RATIO_MASK | NAU8821_ICTRL_LATCH_MASK,
1209         fll_param->ratio | (0x6 << NAU8821_ICTRL_LATCH_SFT));
1210     /* FLL 24-bit fractional input */
1211     regmap_write(regmap, NAU8821_R0A_FLL7,
1212         (fll_param->fll_frac >> 16) & 0xff);
1213     regmap_write(regmap, NAU8821_R0B_FLL8, fll_param->fll_frac & 0xffff);
1214     /* FLL 10-bit integer input */
1215     regmap_update_bits(regmap, NAU8821_R06_FLL3,
1216         NAU8821_FLL_INTEGER_MASK, fll_param->fll_int);
1217     /* FLL pre-scaler */
1218     regmap_update_bits(regmap, NAU8821_R07_FLL4,
1219         NAU8821_HIGHBW_EN | NAU8821_FLL_REF_DIV_MASK,
1220         NAU8821_HIGHBW_EN |
1221         (fll_param->clk_ref_div << NAU8821_FLL_REF_DIV_SFT));
1222     /* select divided VCO input */
1223     regmap_update_bits(regmap, NAU8821_R08_FLL5,
1224         NAU8821_FLL_CLK_SW_MASK, NAU8821_FLL_CLK_SW_REF);
1225     /* Disable free-running mode */
1226     regmap_update_bits(regmap,
1227         NAU8821_R09_FLL6, NAU8821_DCO_EN, 0);
1228     if (fll_param->fll_frac) {
1229         /* set FLL loop filter enable and cutoff frequency at 500Khz */
1230         regmap_update_bits(regmap, NAU8821_R08_FLL5,
1231             NAU8821_FLL_PDB_DAC_EN | NAU8821_FLL_LOOP_FTR_EN |
1232             NAU8821_FLL_FTR_SW_MASK,
1233             NAU8821_FLL_PDB_DAC_EN | NAU8821_FLL_LOOP_FTR_EN |
1234             NAU8821_FLL_FTR_SW_FILTER);
1235         regmap_update_bits(regmap, NAU8821_R09_FLL6,
1236             NAU8821_SDM_EN | NAU8821_CUTOFF500,
1237             NAU8821_SDM_EN | NAU8821_CUTOFF500);
1238     } else {
1239         /* disable FLL loop filter and cutoff frequency */
1240         regmap_update_bits(regmap, NAU8821_R08_FLL5,
1241             NAU8821_FLL_PDB_DAC_EN | NAU8821_FLL_LOOP_FTR_EN |
1242             NAU8821_FLL_FTR_SW_MASK, NAU8821_FLL_FTR_SW_ACCU);
1243         regmap_update_bits(regmap, NAU8821_R09_FLL6,
1244             NAU8821_SDM_EN | NAU8821_CUTOFF500, 0);
1245     }
1246 }
1247 
1248 /**
1249  * nau8821_set_fll - FLL configuration of nau8821
1250  * @component:  codec component
1251  * @pll_id:  PLL requested
1252  * @source:  clock source
1253  * @freq_in:  frequency of input clock source
1254  * @freq_out:  must be 256*Fs in order to achieve the best performance
1255  *
1256  * The FLL function can select BCLK or MCLK as the input clock source.
1257  *
1258  * Returns 0 if the parameters have been applied successfully
1259  * or negative error code.
1260  */
1261 static int nau8821_set_fll(struct snd_soc_component *component,
1262     int pll_id, int source, unsigned int freq_in, unsigned int freq_out)
1263 {
1264     struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1265     struct nau8821_fll fll_set_param, *fll_param = &fll_set_param;
1266     int ret, fs;
1267 
1268     fs = freq_out >> 8;
1269     ret = nau8821_calc_fll_param(freq_in, fs, fll_param);
1270     if (ret) {
1271         dev_err(nau8821->dev,
1272             "Unsupported input clock %d to output clock %d\n",
1273             freq_in, freq_out);
1274         return ret;
1275     }
1276     dev_dbg(nau8821->dev,
1277         "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
1278         fll_param->mclk_src, fll_param->ratio, fll_param->fll_frac,
1279         fll_param->fll_int, fll_param->clk_ref_div);
1280 
1281     nau8821_fll_apply(nau8821, fll_param);
1282     mdelay(2);
1283     regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER,
1284         NAU8821_CLK_SRC_MASK, NAU8821_CLK_SRC_VCO);
1285 
1286     return 0;
1287 }
1288 
1289 static void nau8821_configure_mclk_as_sysclk(struct regmap *regmap)
1290 {
1291     regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER,
1292         NAU8821_CLK_SRC_MASK, NAU8821_CLK_SRC_MCLK);
1293     regmap_update_bits(regmap, NAU8821_R09_FLL6,
1294         NAU8821_DCO_EN, 0);
1295     /* Make DSP operate as default setting for power saving. */
1296     regmap_update_bits(regmap, NAU8821_R04_FLL1,
1297         NAU8821_ICTRL_LATCH_MASK, 0);
1298 }
1299 
1300 static int nau8821_configure_sysclk(struct nau8821 *nau8821,
1301     int clk_id, unsigned int freq)
1302 {
1303     struct regmap *regmap = nau8821->regmap;
1304 
1305     switch (clk_id) {
1306     case NAU8821_CLK_DIS:
1307         /* Clock provided externally and disable internal VCO clock */
1308         nau8821_configure_mclk_as_sysclk(regmap);
1309         break;
1310     case NAU8821_CLK_MCLK:
1311         nau8821_configure_mclk_as_sysclk(regmap);
1312         /* MCLK not changed by clock tree */
1313         regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER,
1314             NAU8821_CLK_MCLK_SRC_MASK, 0);
1315         break;
1316     case NAU8821_CLK_INTERNAL:
1317         if (nau8821_is_jack_inserted(regmap)) {
1318             regmap_update_bits(regmap, NAU8821_R09_FLL6,
1319                 NAU8821_DCO_EN, NAU8821_DCO_EN);
1320             regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER,
1321                 NAU8821_CLK_SRC_MASK, NAU8821_CLK_SRC_VCO);
1322             /* Decrease the VCO frequency and make DSP operate
1323              * as default setting for power saving.
1324              */
1325             regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER,
1326                 NAU8821_CLK_MCLK_SRC_MASK, 0xf);
1327             regmap_update_bits(regmap, NAU8821_R04_FLL1,
1328                 NAU8821_ICTRL_LATCH_MASK |
1329                 NAU8821_FLL_RATIO_MASK, 0x10);
1330             regmap_update_bits(regmap, NAU8821_R09_FLL6,
1331                 NAU8821_SDM_EN, NAU8821_SDM_EN);
1332         }
1333         break;
1334     case NAU8821_CLK_FLL_MCLK:
1335         /* Higher FLL reference input frequency can only set lower
1336          * gain error, such as 0000 for input reference from MCLK
1337          * 12.288Mhz.
1338          */
1339         regmap_update_bits(regmap, NAU8821_R06_FLL3,
1340             NAU8821_FLL_CLK_SRC_MASK | NAU8821_GAIN_ERR_MASK,
1341             NAU8821_FLL_CLK_SRC_MCLK | 0);
1342         break;
1343     case NAU8821_CLK_FLL_BLK:
1344         /* If FLL reference input is from low frequency source,
1345          * higher error gain can apply such as 0xf which has
1346          * the most sensitive gain error correction threshold,
1347          * Therefore, FLL has the most accurate DCO to
1348          * target frequency.
1349          */
1350         regmap_update_bits(regmap, NAU8821_R06_FLL3,
1351             NAU8821_FLL_CLK_SRC_MASK | NAU8821_GAIN_ERR_MASK,
1352             NAU8821_FLL_CLK_SRC_BLK |
1353             (0xf << NAU8821_GAIN_ERR_SFT));
1354         break;
1355     case NAU8821_CLK_FLL_FS:
1356         /* If FLL reference input is from low frequency source,
1357          * higher error gain can apply such as 0xf which has
1358          * the most sensitive gain error correction threshold,
1359          * Therefore, FLL has the most accurate DCO to
1360          * target frequency.
1361          */
1362         regmap_update_bits(regmap, NAU8821_R06_FLL3,
1363             NAU8821_FLL_CLK_SRC_MASK | NAU8821_GAIN_ERR_MASK,
1364             NAU8821_FLL_CLK_SRC_FS |
1365             (0xf << NAU8821_GAIN_ERR_SFT));
1366         break;
1367     default:
1368         dev_err(nau8821->dev, "Invalid clock id (%d)\n", clk_id);
1369         return -EINVAL;
1370     }
1371     nau8821->clk_id = clk_id;
1372     dev_dbg(nau8821->dev, "Sysclk is %dHz and clock id is %d\n", freq,
1373         nau8821->clk_id);
1374 
1375     return 0;
1376 }
1377 
1378 static int nau8821_set_sysclk(struct snd_soc_component *component, int clk_id,
1379     int source, unsigned int freq, int dir)
1380 {
1381     struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1382 
1383     return nau8821_configure_sysclk(nau8821, clk_id, freq);
1384 }
1385 
1386 static int nau8821_resume_setup(struct nau8821 *nau8821)
1387 {
1388     struct regmap *regmap = nau8821->regmap;
1389 
1390     /* Close clock when jack type detection at manual mode */
1391     nau8821_configure_sysclk(nau8821, NAU8821_CLK_DIS, 0);
1392     if (nau8821->irq) {
1393         /* Clear all interruption status */
1394         nau8821_int_status_clear_all(regmap);
1395 
1396         /* Enable both insertion and ejection interruptions, and then
1397          * bypass de-bounce circuit.
1398          */
1399         regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
1400             NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN, 0);
1401         regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
1402             NAU8821_JACK_DET_DB_BYPASS,
1403             NAU8821_JACK_DET_DB_BYPASS);
1404         regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL,
1405             NAU8821_IRQ_INSERT_DIS | NAU8821_IRQ_EJECT_DIS, 0);
1406     }
1407 
1408     return 0;
1409 }
1410 
1411 static int nau8821_set_bias_level(struct snd_soc_component *component,
1412         enum snd_soc_bias_level level)
1413 {
1414     struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1415     struct regmap *regmap = nau8821->regmap;
1416 
1417     switch (level) {
1418     case SND_SOC_BIAS_ON:
1419         break;
1420 
1421     case SND_SOC_BIAS_PREPARE:
1422         break;
1423 
1424     case SND_SOC_BIAS_STANDBY:
1425         /* Setup codec configuration after resume */
1426         if (snd_soc_component_get_bias_level(component) ==
1427             SND_SOC_BIAS_OFF)
1428             nau8821_resume_setup(nau8821);
1429         break;
1430 
1431     case SND_SOC_BIAS_OFF:
1432         /* HPL/HPR short to ground */
1433         regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
1434             NAU8821_SPKR_DWN1R | NAU8821_SPKR_DWN1L, 0);
1435         if (nau8821->irq) {
1436             /* Reset the configuration of jack type for detection.
1437              * Detach 2kOhm Resistors from MICBIAS to MICGND1/2.
1438              */
1439             regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS,
1440                 NAU8821_MICBIAS_JKR2, 0);
1441             /* Turn off all interruptions before system shutdown.
1442              * Keep theinterruption quiet before resume
1443              * setup completes.
1444              */
1445             regmap_write(regmap,
1446                 NAU8821_R12_INTERRUPT_DIS_CTRL, 0xffff);
1447             regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
1448                 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN,
1449                 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN);
1450         }
1451         break;
1452     default:
1453         break;
1454     }
1455 
1456     return 0;
1457 }
1458 
1459 static int __maybe_unused nau8821_suspend(struct snd_soc_component *component)
1460 {
1461     struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1462 
1463     if (nau8821->irq)
1464         disable_irq(nau8821->irq);
1465     snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
1466     /* Power down codec power; don't support button wakeup */
1467     snd_soc_component_disable_pin(component, "MICBIAS");
1468     snd_soc_dapm_sync(nau8821->dapm);
1469     regcache_cache_only(nau8821->regmap, true);
1470     regcache_mark_dirty(nau8821->regmap);
1471 
1472     return 0;
1473 }
1474 
1475 static int __maybe_unused nau8821_resume(struct snd_soc_component *component)
1476 {
1477     struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1478 
1479     regcache_cache_only(nau8821->regmap, false);
1480     regcache_sync(nau8821->regmap);
1481     if (nau8821->irq)
1482         enable_irq(nau8821->irq);
1483 
1484     return 0;
1485 }
1486 
1487 static const struct snd_soc_component_driver nau8821_component_driver = {
1488     .probe          = nau8821_component_probe,
1489     .set_sysclk     = nau8821_set_sysclk,
1490     .set_pll        = nau8821_set_fll,
1491     .set_bias_level     = nau8821_set_bias_level,
1492     .suspend        = nau8821_suspend,
1493     .resume         = nau8821_resume,
1494     .controls       = nau8821_controls,
1495     .num_controls       = ARRAY_SIZE(nau8821_controls),
1496     .dapm_widgets       = nau8821_dapm_widgets,
1497     .num_dapm_widgets   = ARRAY_SIZE(nau8821_dapm_widgets),
1498     .dapm_routes        = nau8821_dapm_routes,
1499     .num_dapm_routes    = ARRAY_SIZE(nau8821_dapm_routes),
1500     .suspend_bias_off   = 1,
1501     .idle_bias_on       = 1,
1502     .use_pmdown_time    = 1,
1503     .endianness     = 1,
1504 };
1505 
1506 /**
1507  * nau8821_enable_jack_detect - Specify a jack for event reporting
1508  *
1509  * @component:  component to register the jack with
1510  * @jack: jack to use to report headset and button events on
1511  *
1512  * After this function has been called the headset insert/remove and button
1513  * events will be routed to the given jack.  Jack can be null to stop
1514  * reporting.
1515  */
1516 int nau8821_enable_jack_detect(struct snd_soc_component *component,
1517     struct snd_soc_jack *jack)
1518 {
1519     struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1520     int ret;
1521 
1522     nau8821->jack = jack;
1523     /* Initiate jack detection work queue */
1524     INIT_WORK(&nau8821->jdet_work, nau8821_jdet_work);
1525     ret = devm_request_threaded_irq(nau8821->dev, nau8821->irq, NULL,
1526         nau8821_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1527         "nau8821", nau8821);
1528     if (ret) {
1529         dev_err(nau8821->dev, "Cannot request irq %d (%d)\n",
1530             nau8821->irq, ret);
1531         return ret;
1532     }
1533 
1534     return ret;
1535 }
1536 EXPORT_SYMBOL_GPL(nau8821_enable_jack_detect);
1537 
1538 static void nau8821_reset_chip(struct regmap *regmap)
1539 {
1540     regmap_write(regmap, NAU8821_R00_RESET, 0xffff);
1541     regmap_write(regmap, NAU8821_R00_RESET, 0xffff);
1542 }
1543 
1544 static void nau8821_print_device_properties(struct nau8821 *nau8821)
1545 {
1546     struct device *dev = nau8821->dev;
1547 
1548     dev_dbg(dev, "jkdet-enable:         %d\n", nau8821->jkdet_enable);
1549     dev_dbg(dev, "jkdet-pull-enable:    %d\n", nau8821->jkdet_pull_enable);
1550     dev_dbg(dev, "jkdet-pull-up:        %d\n", nau8821->jkdet_pull_up);
1551     dev_dbg(dev, "jkdet-polarity:       %d\n", nau8821->jkdet_polarity);
1552     dev_dbg(dev, "micbias-voltage:      %d\n", nau8821->micbias_voltage);
1553     dev_dbg(dev, "vref-impedance:       %d\n", nau8821->vref_impedance);
1554     dev_dbg(dev, "jack-insert-debounce: %d\n",
1555         nau8821->jack_insert_debounce);
1556     dev_dbg(dev, "jack-eject-debounce:  %d\n",
1557         nau8821->jack_eject_debounce);
1558     dev_dbg(dev, "dmic-clk-threshold:       %d\n",
1559         nau8821->dmic_clk_threshold);
1560     dev_dbg(dev, "key_enable:       %d\n", nau8821->key_enable);
1561 }
1562 
1563 static int nau8821_read_device_properties(struct device *dev,
1564     struct nau8821 *nau8821)
1565 {
1566     int ret;
1567 
1568     nau8821->jkdet_enable = device_property_read_bool(dev,
1569         "nuvoton,jkdet-enable");
1570     nau8821->jkdet_pull_enable = device_property_read_bool(dev,
1571         "nuvoton,jkdet-pull-enable");
1572     nau8821->jkdet_pull_up = device_property_read_bool(dev,
1573         "nuvoton,jkdet-pull-up");
1574     nau8821->key_enable = device_property_read_bool(dev,
1575         "nuvoton,key-enable");
1576     ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity",
1577         &nau8821->jkdet_polarity);
1578     if (ret)
1579         nau8821->jkdet_polarity = 1;
1580     ret = device_property_read_u32(dev, "nuvoton,micbias-voltage",
1581         &nau8821->micbias_voltage);
1582     if (ret)
1583         nau8821->micbias_voltage = 6;
1584     ret = device_property_read_u32(dev, "nuvoton,vref-impedance",
1585         &nau8821->vref_impedance);
1586     if (ret)
1587         nau8821->vref_impedance = 2;
1588     ret = device_property_read_u32(dev, "nuvoton,jack-insert-debounce",
1589         &nau8821->jack_insert_debounce);
1590     if (ret)
1591         nau8821->jack_insert_debounce = 7;
1592     ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce",
1593         &nau8821->jack_eject_debounce);
1594     if (ret)
1595         nau8821->jack_eject_debounce = 0;
1596     ret = device_property_read_u32(dev, "nuvoton,dmic-clk-threshold",
1597         &nau8821->dmic_clk_threshold);
1598     if (ret)
1599         nau8821->dmic_clk_threshold = 3072000;
1600 
1601     return 0;
1602 }
1603 
1604 static void nau8821_init_regs(struct nau8821 *nau8821)
1605 {
1606     struct regmap *regmap = nau8821->regmap;
1607 
1608     /* Enable Bias/Vmid */
1609     regmap_update_bits(regmap, NAU8821_R66_BIAS_ADJ,
1610         NAU8821_BIAS_VMID, NAU8821_BIAS_VMID);
1611     regmap_update_bits(regmap, NAU8821_R76_BOOST,
1612         NAU8821_GLOBAL_BIAS_EN, NAU8821_GLOBAL_BIAS_EN);
1613     /* VMID Tieoff setting and enable TESTDAC.
1614      * This sets the analog DAC inputs to a '0' input signal to avoid
1615      * any glitches due to power up transients in both the analog and
1616      * digital DAC circuit.
1617      */
1618     regmap_update_bits(regmap, NAU8821_R66_BIAS_ADJ,
1619         NAU8821_BIAS_VMID_SEL_MASK | NAU8821_BIAS_TESTDAC_EN,
1620         (nau8821->vref_impedance << NAU8821_BIAS_VMID_SEL_SFT) |
1621         NAU8821_BIAS_TESTDAC_EN);
1622     /* Disable short Frame Sync detection logic */
1623     regmap_update_bits(regmap, NAU8821_R1E_LEFT_TIME_SLOT,
1624         NAU8821_DIS_FS_SHORT_DET, NAU8821_DIS_FS_SHORT_DET);
1625     /* Disable Boost Driver, Automatic Short circuit protection enable */
1626     regmap_update_bits(regmap, NAU8821_R76_BOOST,
1627         NAU8821_PRECHARGE_DIS | NAU8821_HP_BOOST_DIS |
1628         NAU8821_HP_BOOST_G_DIS | NAU8821_SHORT_SHUTDOWN_EN,
1629         NAU8821_PRECHARGE_DIS | NAU8821_HP_BOOST_DIS |
1630         NAU8821_HP_BOOST_G_DIS | NAU8821_SHORT_SHUTDOWN_EN);
1631     /* Class G timer 64ms */
1632     regmap_update_bits(regmap, NAU8821_R4B_CLASSG_CTRL,
1633         NAU8821_CLASSG_TIMER_MASK,
1634         0x20 << NAU8821_CLASSG_TIMER_SFT);
1635     /* Class AB bias current to 2x, DAC Capacitor enable MSB/LSB */
1636     regmap_update_bits(regmap, NAU8821_R6A_ANALOG_CONTROL_2,
1637         NAU8821_HP_NON_CLASSG_CURRENT_2xADJ |
1638         NAU8821_DAC_CAPACITOR_MSB | NAU8821_DAC_CAPACITOR_LSB,
1639         NAU8821_HP_NON_CLASSG_CURRENT_2xADJ |
1640         NAU8821_DAC_CAPACITOR_MSB | NAU8821_DAC_CAPACITOR_LSB);
1641     /* Disable DACR/L power */
1642     regmap_update_bits(regmap, NAU8821_R80_CHARGE_PUMP,
1643         NAU8821_POWER_DOWN_DACR | NAU8821_POWER_DOWN_DACL, 0);
1644     /* DAC clock delay 2ns, VREF */
1645     regmap_update_bits(regmap, NAU8821_R73_RDAC,
1646         NAU8821_DAC_CLK_DELAY_MASK | NAU8821_DAC_VREF_MASK,
1647         (0x2 << NAU8821_DAC_CLK_DELAY_SFT) |
1648         (0x3 << NAU8821_DAC_VREF_SFT));
1649 
1650     regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS,
1651         NAU8821_MICBIAS_VOLTAGE_MASK, nau8821->micbias_voltage);
1652     /* Default oversampling/decimations settings are unusable
1653      * (audible hiss). Set it to something better.
1654      */
1655     regmap_update_bits(regmap, NAU8821_R2B_ADC_RATE,
1656         NAU8821_ADC_SYNC_DOWN_MASK, NAU8821_ADC_SYNC_DOWN_64);
1657     regmap_update_bits(regmap, NAU8821_R2C_DAC_CTRL1,
1658         NAU8821_DAC_OVERSAMPLE_MASK, NAU8821_DAC_OVERSAMPLE_64);
1659 }
1660 
1661 static int nau8821_setup_irq(struct nau8821 *nau8821)
1662 {
1663     struct regmap *regmap = nau8821->regmap;
1664 
1665     /* Jack detection */
1666     regmap_update_bits(regmap, NAU8821_R1A_GPIO12_CTRL,
1667         NAU8821_JKDET_OUTPUT_EN,
1668         nau8821->jkdet_enable ? 0 : NAU8821_JKDET_OUTPUT_EN);
1669     regmap_update_bits(regmap, NAU8821_R1A_GPIO12_CTRL,
1670         NAU8821_JKDET_PULL_EN,
1671         nau8821->jkdet_pull_enable ? 0 : NAU8821_JKDET_PULL_EN);
1672     regmap_update_bits(regmap, NAU8821_R1A_GPIO12_CTRL,
1673         NAU8821_JKDET_PULL_UP,
1674         nau8821->jkdet_pull_up ? NAU8821_JKDET_PULL_UP : 0);
1675     regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
1676         NAU8821_JACK_POLARITY,
1677         /* jkdet_polarity - 1  is for active-low */
1678         nau8821->jkdet_polarity ? 0 : NAU8821_JACK_POLARITY);
1679     regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
1680         NAU8821_JACK_INSERT_DEBOUNCE_MASK,
1681         nau8821->jack_insert_debounce <<
1682         NAU8821_JACK_INSERT_DEBOUNCE_SFT);
1683     regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
1684         NAU8821_JACK_EJECT_DEBOUNCE_MASK,
1685         nau8821->jack_eject_debounce <<
1686         NAU8821_JACK_EJECT_DEBOUNCE_SFT);
1687     /* Pull up IRQ pin */
1688     regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
1689         NAU8821_IRQ_PIN_PULL_UP | NAU8821_IRQ_PIN_PULL_EN |
1690         NAU8821_IRQ_OUTPUT_EN, NAU8821_IRQ_PIN_PULL_UP |
1691         NAU8821_IRQ_PIN_PULL_EN | NAU8821_IRQ_OUTPUT_EN);
1692     /* Disable interruption before codec initiation done */
1693     /* Mask unneeded IRQs: 1 - disable, 0 - enable */
1694     regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 0x3f5, 0x3f5);
1695 
1696     return 0;
1697 }
1698 
1699 static int nau8821_i2c_probe(struct i2c_client *i2c)
1700 {
1701     struct device *dev = &i2c->dev;
1702     struct nau8821 *nau8821 = dev_get_platdata(&i2c->dev);
1703     int ret, value;
1704 
1705     if (!nau8821) {
1706         nau8821 = devm_kzalloc(dev, sizeof(*nau8821), GFP_KERNEL);
1707         if (!nau8821)
1708             return -ENOMEM;
1709         nau8821_read_device_properties(dev, nau8821);
1710     }
1711     i2c_set_clientdata(i2c, nau8821);
1712 
1713     nau8821->regmap = devm_regmap_init_i2c(i2c, &nau8821_regmap_config);
1714     if (IS_ERR(nau8821->regmap))
1715         return PTR_ERR(nau8821->regmap);
1716 
1717     nau8821->dev = dev;
1718     nau8821->irq = i2c->irq;
1719     nau8821_print_device_properties(nau8821);
1720 
1721     nau8821_reset_chip(nau8821->regmap);
1722     ret = regmap_read(nau8821->regmap, NAU8821_R58_I2C_DEVICE_ID, &value);
1723     if (ret) {
1724         dev_err(dev, "Failed to read device id (%d)\n", ret);
1725         return ret;
1726     }
1727     nau8821_init_regs(nau8821);
1728 
1729     if (i2c->irq)
1730         nau8821_setup_irq(nau8821);
1731 
1732     ret = devm_snd_soc_register_component(&i2c->dev,
1733         &nau8821_component_driver, &nau8821_dai, 1);
1734 
1735     return ret;
1736 }
1737 
1738 static const struct i2c_device_id nau8821_i2c_ids[] = {
1739     { "nau8821", 0 },
1740     { }
1741 };
1742 MODULE_DEVICE_TABLE(i2c, nau8821_i2c_ids);
1743 
1744 #ifdef CONFIG_OF
1745 static const struct of_device_id nau8821_of_ids[] = {
1746     { .compatible = "nuvoton,nau8821", },
1747     {}
1748 };
1749 MODULE_DEVICE_TABLE(of, nau8821_of_ids);
1750 #endif
1751 
1752 #ifdef CONFIG_ACPI
1753 static const struct acpi_device_id nau8821_acpi_match[] = {
1754     { "NVTN2020", 0 },
1755     {},
1756 };
1757 MODULE_DEVICE_TABLE(acpi, nau8821_acpi_match);
1758 #endif
1759 
1760 static struct i2c_driver nau8821_driver = {
1761     .driver = {
1762         .name = "nau8821",
1763         .of_match_table = of_match_ptr(nau8821_of_ids),
1764         .acpi_match_table = ACPI_PTR(nau8821_acpi_match),
1765     },
1766     .probe_new = nau8821_i2c_probe,
1767     .id_table = nau8821_i2c_ids,
1768 };
1769 module_i2c_driver(nau8821_driver);
1770 
1771 MODULE_DESCRIPTION("ASoC nau8821 driver");
1772 MODULE_AUTHOR("John Hsu <kchsu0@nuvoton.com>");
1773 MODULE_AUTHOR("Seven Lee <wtli@nuvoton.com>");
1774 MODULE_LICENSE("GPL");
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