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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * nau8810.c  --  NAU8810 ALSA Soc Audio driver
0004  *
0005  * Copyright 2016 Nuvoton Technology Corp.
0006  *
0007  * Author: David Lin <ctlin0@nuvoton.com>
0008  *
0009  * Based on WM8974.c
0010  */
0011 
0012 #include <linux/module.h>
0013 #include <linux/moduleparam.h>
0014 #include <linux/kernel.h>
0015 #include <linux/init.h>
0016 #include <linux/delay.h>
0017 #include <linux/pm.h>
0018 #include <linux/i2c.h>
0019 #include <linux/regmap.h>
0020 #include <linux/slab.h>
0021 #include <sound/core.h>
0022 #include <sound/pcm.h>
0023 #include <sound/pcm_params.h>
0024 #include <sound/soc.h>
0025 #include <sound/initval.h>
0026 #include <sound/tlv.h>
0027 
0028 #include "nau8810.h"
0029 
0030 #define NAU_PLL_FREQ_MAX 100000000
0031 #define NAU_PLL_FREQ_MIN 90000000
0032 #define NAU_PLL_REF_MAX 33000000
0033 #define NAU_PLL_REF_MIN 8000000
0034 #define NAU_PLL_OPTOP_MIN 6
0035 
0036 
0037 static const int nau8810_mclk_scaler[] = { 10, 15, 20, 30, 40, 60, 80, 120 };
0038 
0039 static const struct reg_default nau8810_reg_defaults[] = {
0040     { NAU8810_REG_POWER1, 0x0000 },
0041     { NAU8810_REG_POWER2, 0x0000 },
0042     { NAU8810_REG_POWER3, 0x0000 },
0043     { NAU8810_REG_IFACE, 0x0050 },
0044     { NAU8810_REG_COMP, 0x0000 },
0045     { NAU8810_REG_CLOCK, 0x0140 },
0046     { NAU8810_REG_SMPLR, 0x0000 },
0047     { NAU8810_REG_DAC, 0x0000 },
0048     { NAU8810_REG_DACGAIN, 0x00FF },
0049     { NAU8810_REG_ADC, 0x0100 },
0050     { NAU8810_REG_ADCGAIN, 0x00FF },
0051     { NAU8810_REG_EQ1, 0x012C },
0052     { NAU8810_REG_EQ2, 0x002C },
0053     { NAU8810_REG_EQ3, 0x002C },
0054     { NAU8810_REG_EQ4, 0x002C },
0055     { NAU8810_REG_EQ5, 0x002C },
0056     { NAU8810_REG_DACLIM1, 0x0032 },
0057     { NAU8810_REG_DACLIM2, 0x0000 },
0058     { NAU8810_REG_NOTCH1, 0x0000 },
0059     { NAU8810_REG_NOTCH2, 0x0000 },
0060     { NAU8810_REG_NOTCH3, 0x0000 },
0061     { NAU8810_REG_NOTCH4, 0x0000 },
0062     { NAU8810_REG_ALC1, 0x0038 },
0063     { NAU8810_REG_ALC2, 0x000B },
0064     { NAU8810_REG_ALC3, 0x0032 },
0065     { NAU8810_REG_NOISEGATE, 0x0000 },
0066     { NAU8810_REG_PLLN, 0x0008 },
0067     { NAU8810_REG_PLLK1, 0x000C },
0068     { NAU8810_REG_PLLK2, 0x0093 },
0069     { NAU8810_REG_PLLK3, 0x00E9 },
0070     { NAU8810_REG_ATTEN, 0x0000 },
0071     { NAU8810_REG_INPUT_SIGNAL, 0x0003 },
0072     { NAU8810_REG_PGAGAIN, 0x0010 },
0073     { NAU8810_REG_ADCBOOST, 0x0100 },
0074     { NAU8810_REG_OUTPUT, 0x0002 },
0075     { NAU8810_REG_SPKMIX, 0x0001 },
0076     { NAU8810_REG_SPKGAIN, 0x0039 },
0077     { NAU8810_REG_MONOMIX, 0x0001 },
0078     { NAU8810_REG_POWER4, 0x0000 },
0079     { NAU8810_REG_TSLOTCTL1, 0x0000 },
0080     { NAU8810_REG_TSLOTCTL2, 0x0020 },
0081     { NAU8810_REG_DEVICE_REVID, 0x0000 },
0082     { NAU8810_REG_I2C_DEVICEID, 0x001A },
0083     { NAU8810_REG_ADDITIONID, 0x00CA },
0084     { NAU8810_REG_RESERVE, 0x0124 },
0085     { NAU8810_REG_OUTCTL, 0x0001 },
0086     { NAU8810_REG_ALC1ENHAN1, 0x0010 },
0087     { NAU8810_REG_ALC1ENHAN2, 0x0000 },
0088     { NAU8810_REG_MISCCTL, 0x0000 },
0089     { NAU8810_REG_OUTTIEOFF, 0x0000 },
0090     { NAU8810_REG_AGCP2POUT, 0x0000 },
0091     { NAU8810_REG_AGCPOUT, 0x0000 },
0092     { NAU8810_REG_AMTCTL, 0x0000 },
0093     { NAU8810_REG_OUTTIEOFFMAN, 0x0000 },
0094 };
0095 
0096 static bool nau8810_readable_reg(struct device *dev, unsigned int reg)
0097 {
0098     switch (reg) {
0099     case NAU8810_REG_RESET ... NAU8810_REG_SMPLR:
0100     case NAU8810_REG_DAC ... NAU8810_REG_DACGAIN:
0101     case NAU8810_REG_ADC ... NAU8810_REG_ADCGAIN:
0102     case NAU8810_REG_EQ1 ... NAU8810_REG_EQ5:
0103     case NAU8810_REG_DACLIM1 ... NAU8810_REG_DACLIM2:
0104     case NAU8810_REG_NOTCH1 ... NAU8810_REG_NOTCH4:
0105     case NAU8810_REG_ALC1 ... NAU8810_REG_ATTEN:
0106     case NAU8810_REG_INPUT_SIGNAL ... NAU8810_REG_PGAGAIN:
0107     case NAU8810_REG_ADCBOOST:
0108     case NAU8810_REG_OUTPUT ... NAU8810_REG_SPKMIX:
0109     case NAU8810_REG_SPKGAIN:
0110     case NAU8810_REG_MONOMIX:
0111     case NAU8810_REG_POWER4 ... NAU8810_REG_TSLOTCTL2:
0112     case NAU8810_REG_DEVICE_REVID ... NAU8810_REG_RESERVE:
0113     case NAU8810_REG_OUTCTL ... NAU8810_REG_ALC1ENHAN2:
0114     case NAU8810_REG_MISCCTL:
0115     case NAU8810_REG_OUTTIEOFF ... NAU8810_REG_OUTTIEOFFMAN:
0116         return true;
0117     default:
0118         return false;
0119     }
0120 }
0121 
0122 static bool nau8810_writeable_reg(struct device *dev, unsigned int reg)
0123 {
0124     switch (reg) {
0125     case NAU8810_REG_RESET ... NAU8810_REG_SMPLR:
0126     case NAU8810_REG_DAC ... NAU8810_REG_DACGAIN:
0127     case NAU8810_REG_ADC ... NAU8810_REG_ADCGAIN:
0128     case NAU8810_REG_EQ1 ... NAU8810_REG_EQ5:
0129     case NAU8810_REG_DACLIM1 ... NAU8810_REG_DACLIM2:
0130     case NAU8810_REG_NOTCH1 ... NAU8810_REG_NOTCH4:
0131     case NAU8810_REG_ALC1 ... NAU8810_REG_ATTEN:
0132     case NAU8810_REG_INPUT_SIGNAL ... NAU8810_REG_PGAGAIN:
0133     case NAU8810_REG_ADCBOOST:
0134     case NAU8810_REG_OUTPUT ... NAU8810_REG_SPKMIX:
0135     case NAU8810_REG_SPKGAIN:
0136     case NAU8810_REG_MONOMIX:
0137     case NAU8810_REG_POWER4 ... NAU8810_REG_TSLOTCTL2:
0138     case NAU8810_REG_OUTCTL ... NAU8810_REG_ALC1ENHAN2:
0139     case NAU8810_REG_MISCCTL:
0140     case NAU8810_REG_OUTTIEOFF ... NAU8810_REG_OUTTIEOFFMAN:
0141         return true;
0142     default:
0143         return false;
0144     }
0145 }
0146 
0147 static bool nau8810_volatile_reg(struct device *dev, unsigned int reg)
0148 {
0149     switch (reg) {
0150     case NAU8810_REG_RESET:
0151     case NAU8810_REG_DEVICE_REVID ... NAU8810_REG_RESERVE:
0152         return true;
0153     default:
0154         return false;
0155     }
0156 }
0157 
0158 /* The EQ parameters get function is to get the 5 band equalizer control.
0159  * The regmap raw read can't work here because regmap doesn't provide
0160  * value format for value width of 9 bits. Therefore, the driver reads data
0161  * from cache and makes value format according to the endianness of
0162  * bytes type control element.
0163  */
0164 static int nau8810_eq_get(struct snd_kcontrol *kcontrol,
0165     struct snd_ctl_elem_value *ucontrol)
0166 {
0167     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0168     struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
0169     struct soc_bytes_ext *params = (void *)kcontrol->private_value;
0170     int i, reg, reg_val;
0171     u16 *val;
0172 
0173     val = (u16 *)ucontrol->value.bytes.data;
0174     reg = NAU8810_REG_EQ1;
0175     for (i = 0; i < params->max / sizeof(u16); i++) {
0176         regmap_read(nau8810->regmap, reg + i, &reg_val);
0177         /* conversion of 16-bit integers between native CPU format
0178          * and big endian format
0179          */
0180         reg_val = cpu_to_be16(reg_val);
0181         memcpy(val + i, &reg_val, sizeof(reg_val));
0182     }
0183 
0184     return 0;
0185 }
0186 
0187 /* The EQ parameters put function is to make configuration of 5 band equalizer
0188  * control. These configuration includes central frequency, equalizer gain,
0189  * cut-off frequency, bandwidth control, and equalizer path.
0190  * The regmap raw write can't work here because regmap doesn't provide
0191  * register and value format for register with address 7 bits and value 9 bits.
0192  * Therefore, the driver makes value format according to the endianness of
0193  * bytes type control element and writes data to codec.
0194  */
0195 static int nau8810_eq_put(struct snd_kcontrol *kcontrol,
0196     struct snd_ctl_elem_value *ucontrol)
0197 {
0198     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0199     struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
0200     struct soc_bytes_ext *params = (void *)kcontrol->private_value;
0201     void *data;
0202     u16 *val, value;
0203     int i, reg, ret;
0204 
0205     data = kmemdup(ucontrol->value.bytes.data,
0206         params->max, GFP_KERNEL | GFP_DMA);
0207     if (!data)
0208         return -ENOMEM;
0209 
0210     val = (u16 *)data;
0211     reg = NAU8810_REG_EQ1;
0212     for (i = 0; i < params->max / sizeof(u16); i++) {
0213         /* conversion of 16-bit integers between native CPU format
0214          * and big endian format
0215          */
0216         value = be16_to_cpu(*(val + i));
0217         ret = regmap_write(nau8810->regmap, reg + i, value);
0218         if (ret) {
0219             dev_err(component->dev, "EQ configuration fail, register: %x ret: %d\n",
0220                 reg + i, ret);
0221             kfree(data);
0222             return ret;
0223         }
0224     }
0225     kfree(data);
0226 
0227     return 0;
0228 }
0229 
0230 static const char * const nau8810_companding[] = {
0231     "Off", "NC", "u-law", "A-law" };
0232 
0233 static const struct soc_enum nau8810_companding_adc_enum =
0234     SOC_ENUM_SINGLE(NAU8810_REG_COMP, NAU8810_ADCCM_SFT,
0235         ARRAY_SIZE(nau8810_companding), nau8810_companding);
0236 
0237 static const struct soc_enum nau8810_companding_dac_enum =
0238     SOC_ENUM_SINGLE(NAU8810_REG_COMP, NAU8810_DACCM_SFT,
0239         ARRAY_SIZE(nau8810_companding), nau8810_companding);
0240 
0241 static const char * const nau8810_deemp[] = {
0242     "None", "32kHz", "44.1kHz", "48kHz" };
0243 
0244 static const struct soc_enum nau8810_deemp_enum =
0245     SOC_ENUM_SINGLE(NAU8810_REG_DAC, NAU8810_DEEMP_SFT,
0246         ARRAY_SIZE(nau8810_deemp), nau8810_deemp);
0247 
0248 static const char * const nau8810_eqmode[] = {"Capture", "Playback" };
0249 
0250 static const struct soc_enum nau8810_eqmode_enum =
0251     SOC_ENUM_SINGLE(NAU8810_REG_EQ1, NAU8810_EQM_SFT,
0252         ARRAY_SIZE(nau8810_eqmode), nau8810_eqmode);
0253 
0254 static const char * const nau8810_alc[] = {"Normal", "Limiter" };
0255 
0256 static const struct soc_enum nau8810_alc_enum =
0257     SOC_ENUM_SINGLE(NAU8810_REG_ALC3, NAU8810_ALCM_SFT,
0258         ARRAY_SIZE(nau8810_alc), nau8810_alc);
0259 
0260 static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
0261 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
0262 static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1200, 75, 0);
0263 static const DECLARE_TLV_DB_SCALE(spk_tlv, -5700, 100, 0);
0264 
0265 static const struct snd_kcontrol_new nau8810_snd_controls[] = {
0266     SOC_ENUM("ADC Companding", nau8810_companding_adc_enum),
0267     SOC_ENUM("DAC Companding", nau8810_companding_dac_enum),
0268     SOC_ENUM("DAC De-emphasis", nau8810_deemp_enum),
0269 
0270     SOC_ENUM("EQ Function", nau8810_eqmode_enum),
0271     SND_SOC_BYTES_EXT("EQ Parameters", 10,
0272           nau8810_eq_get, nau8810_eq_put),
0273 
0274     SOC_SINGLE("DAC Inversion Switch", NAU8810_REG_DAC,
0275         NAU8810_DACPL_SFT, 1, 0),
0276     SOC_SINGLE_TLV("Playback Volume", NAU8810_REG_DACGAIN,
0277         NAU8810_DACGAIN_SFT, 0xff, 0, digital_tlv),
0278 
0279     SOC_SINGLE("High Pass Filter Switch", NAU8810_REG_ADC,
0280         NAU8810_HPFEN_SFT, 1, 0),
0281     SOC_SINGLE("High Pass Cut Off", NAU8810_REG_ADC,
0282         NAU8810_HPF_SFT, 0x7, 0),
0283 
0284     SOC_SINGLE("ADC Inversion Switch", NAU8810_REG_ADC,
0285         NAU8810_ADCPL_SFT, 1, 0),
0286     SOC_SINGLE_TLV("Capture Volume", NAU8810_REG_ADCGAIN,
0287         NAU8810_ADCGAIN_SFT, 0xff, 0, digital_tlv),
0288 
0289     SOC_SINGLE_TLV("EQ1 Volume", NAU8810_REG_EQ1,
0290         NAU8810_EQ1GC_SFT, 0x18, 1, eq_tlv),
0291     SOC_SINGLE_TLV("EQ2 Volume", NAU8810_REG_EQ2,
0292         NAU8810_EQ2GC_SFT, 0x18, 1, eq_tlv),
0293     SOC_SINGLE_TLV("EQ3 Volume", NAU8810_REG_EQ3,
0294         NAU8810_EQ3GC_SFT, 0x18, 1, eq_tlv),
0295     SOC_SINGLE_TLV("EQ4 Volume", NAU8810_REG_EQ4,
0296         NAU8810_EQ4GC_SFT, 0x18, 1, eq_tlv),
0297     SOC_SINGLE_TLV("EQ5 Volume", NAU8810_REG_EQ5,
0298         NAU8810_EQ5GC_SFT, 0x18, 1, eq_tlv),
0299 
0300     SOC_SINGLE("DAC Limiter Switch", NAU8810_REG_DACLIM1,
0301         NAU8810_DACLIMEN_SFT, 1, 0),
0302     SOC_SINGLE("DAC Limiter Decay", NAU8810_REG_DACLIM1,
0303         NAU8810_DACLIMDCY_SFT, 0xf, 0),
0304     SOC_SINGLE("DAC Limiter Attack", NAU8810_REG_DACLIM1,
0305         NAU8810_DACLIMATK_SFT, 0xf, 0),
0306     SOC_SINGLE("DAC Limiter Threshold", NAU8810_REG_DACLIM2,
0307         NAU8810_DACLIMTHL_SFT, 0x7, 0),
0308     SOC_SINGLE("DAC Limiter Boost", NAU8810_REG_DACLIM2,
0309         NAU8810_DACLIMBST_SFT, 0xf, 0),
0310 
0311     SOC_ENUM("ALC Mode", nau8810_alc_enum),
0312     SOC_SINGLE("ALC Enable Switch", NAU8810_REG_ALC1,
0313         NAU8810_ALCEN_SFT, 1, 0),
0314     SOC_SINGLE("ALC Max Volume", NAU8810_REG_ALC1,
0315         NAU8810_ALCMXGAIN_SFT, 0x7, 0),
0316     SOC_SINGLE("ALC Min Volume", NAU8810_REG_ALC1,
0317         NAU8810_ALCMINGAIN_SFT, 0x7, 0),
0318     SOC_SINGLE("ALC ZC Switch", NAU8810_REG_ALC2,
0319         NAU8810_ALCZC_SFT, 1, 0),
0320     SOC_SINGLE("ALC Hold", NAU8810_REG_ALC2,
0321         NAU8810_ALCHT_SFT, 0xf, 0),
0322     SOC_SINGLE("ALC Target", NAU8810_REG_ALC2,
0323         NAU8810_ALCSL_SFT, 0xf, 0),
0324     SOC_SINGLE("ALC Decay", NAU8810_REG_ALC3,
0325         NAU8810_ALCDCY_SFT, 0xf, 0),
0326     SOC_SINGLE("ALC Attack", NAU8810_REG_ALC3,
0327         NAU8810_ALCATK_SFT, 0xf, 0),
0328     SOC_SINGLE("ALC Noise Gate Switch", NAU8810_REG_NOISEGATE,
0329         NAU8810_ALCNEN_SFT, 1, 0),
0330     SOC_SINGLE("ALC Noise Gate Threshold", NAU8810_REG_NOISEGATE,
0331         NAU8810_ALCNTH_SFT, 0x7, 0),
0332 
0333     SOC_SINGLE("PGA ZC Switch", NAU8810_REG_PGAGAIN,
0334         NAU8810_PGAZC_SFT, 1, 0),
0335     SOC_SINGLE_TLV("PGA Volume", NAU8810_REG_PGAGAIN,
0336         NAU8810_PGAGAIN_SFT, 0x3f, 0, inpga_tlv),
0337 
0338     SOC_SINGLE("Speaker ZC Switch", NAU8810_REG_SPKGAIN,
0339         NAU8810_SPKZC_SFT, 1, 0),
0340     SOC_SINGLE("Speaker Mute Switch", NAU8810_REG_SPKGAIN,
0341         NAU8810_SPKMT_SFT, 1, 0),
0342     SOC_SINGLE_TLV("Speaker Volume", NAU8810_REG_SPKGAIN,
0343         NAU8810_SPKGAIN_SFT, 0x3f, 0, spk_tlv),
0344 
0345     SOC_SINGLE("Capture Boost(+20dB)", NAU8810_REG_ADCBOOST,
0346         NAU8810_PGABST_SFT, 1, 0),
0347     SOC_SINGLE("Mono Mute Switch", NAU8810_REG_MONOMIX,
0348         NAU8810_MOUTMXMT_SFT, 1, 0),
0349 
0350     SOC_SINGLE("DAC Oversampling Rate(128x) Switch", NAU8810_REG_DAC,
0351         NAU8810_DACOS_SFT, 1, 0),
0352     SOC_SINGLE("ADC Oversampling Rate(128x) Switch", NAU8810_REG_ADC,
0353         NAU8810_ADCOS_SFT, 1, 0),
0354 };
0355 
0356 /* Speaker Output Mixer */
0357 static const struct snd_kcontrol_new nau8810_speaker_mixer_controls[] = {
0358     SOC_DAPM_SINGLE("AUX Bypass Switch", NAU8810_REG_SPKMIX,
0359         NAU8810_AUXSPK_SFT, 1, 0),
0360     SOC_DAPM_SINGLE("Line Bypass Switch", NAU8810_REG_SPKMIX,
0361         NAU8810_BYPSPK_SFT, 1, 0),
0362     SOC_DAPM_SINGLE("PCM Playback Switch", NAU8810_REG_SPKMIX,
0363         NAU8810_DACSPK_SFT, 1, 0),
0364 };
0365 
0366 /* Mono Output Mixer */
0367 static const struct snd_kcontrol_new nau8810_mono_mixer_controls[] = {
0368     SOC_DAPM_SINGLE("AUX Bypass Switch", NAU8810_REG_MONOMIX,
0369         NAU8810_AUXMOUT_SFT, 1, 0),
0370     SOC_DAPM_SINGLE("Line Bypass Switch", NAU8810_REG_MONOMIX,
0371         NAU8810_BYPMOUT_SFT, 1, 0),
0372     SOC_DAPM_SINGLE("PCM Playback Switch", NAU8810_REG_MONOMIX,
0373         NAU8810_DACMOUT_SFT, 1, 0),
0374 };
0375 
0376 /* PGA Mute */
0377 static const struct snd_kcontrol_new nau8810_pgaboost_mixer_controls[] = {
0378     SOC_DAPM_SINGLE("AUX PGA Switch", NAU8810_REG_ADCBOOST,
0379         NAU8810_AUXBSTGAIN_SFT, 0x7, 0),
0380     SOC_DAPM_SINGLE("PGA Mute Switch", NAU8810_REG_PGAGAIN,
0381         NAU8810_PGAMT_SFT, 1, 1),
0382     SOC_DAPM_SINGLE("PMIC PGA Switch", NAU8810_REG_ADCBOOST,
0383         NAU8810_PMICBSTGAIN_SFT, 0x7, 0),
0384 };
0385 
0386 /* Input PGA */
0387 static const struct snd_kcontrol_new nau8810_inpga[] = {
0388     SOC_DAPM_SINGLE("AUX Switch", NAU8810_REG_INPUT_SIGNAL,
0389         NAU8810_AUXPGA_SFT, 1, 0),
0390     SOC_DAPM_SINGLE("MicN Switch", NAU8810_REG_INPUT_SIGNAL,
0391         NAU8810_NMICPGA_SFT, 1, 0),
0392     SOC_DAPM_SINGLE("MicP Switch", NAU8810_REG_INPUT_SIGNAL,
0393         NAU8810_PMICPGA_SFT, 1, 0),
0394 };
0395 
0396 /* Loopback Switch */
0397 static const struct snd_kcontrol_new nau8810_loopback =
0398     SOC_DAPM_SINGLE("Switch", NAU8810_REG_COMP,
0399         NAU8810_ADDAP_SFT, 1, 0);
0400 
0401 static int check_mclk_select_pll(struct snd_soc_dapm_widget *source,
0402              struct snd_soc_dapm_widget *sink)
0403 {
0404     struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
0405     struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
0406     unsigned int value;
0407 
0408     regmap_read(nau8810->regmap, NAU8810_REG_CLOCK, &value);
0409     return (value & NAU8810_CLKM_MASK);
0410 }
0411 
0412 static int check_mic_enabled(struct snd_soc_dapm_widget *source,
0413     struct snd_soc_dapm_widget *sink)
0414 {
0415     struct snd_soc_component *component =
0416         snd_soc_dapm_to_component(source->dapm);
0417     struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
0418     unsigned int value;
0419 
0420     regmap_read(nau8810->regmap, NAU8810_REG_INPUT_SIGNAL, &value);
0421     if (value & NAU8810_PMICPGA_EN || value & NAU8810_NMICPGA_EN)
0422         return 1;
0423     regmap_read(nau8810->regmap, NAU8810_REG_ADCBOOST, &value);
0424     if (value & NAU8810_PMICBSTGAIN_MASK)
0425         return 1;
0426     return 0;
0427 }
0428 
0429 static const struct snd_soc_dapm_widget nau8810_dapm_widgets[] = {
0430     SND_SOC_DAPM_MIXER("Speaker Mixer", NAU8810_REG_POWER3,
0431         NAU8810_SPKMX_EN_SFT, 0, &nau8810_speaker_mixer_controls[0],
0432         ARRAY_SIZE(nau8810_speaker_mixer_controls)),
0433     SND_SOC_DAPM_MIXER("Mono Mixer", NAU8810_REG_POWER3,
0434         NAU8810_MOUTMX_EN_SFT, 0, &nau8810_mono_mixer_controls[0],
0435         ARRAY_SIZE(nau8810_mono_mixer_controls)),
0436     SND_SOC_DAPM_DAC("DAC", "Playback", NAU8810_REG_POWER3,
0437         NAU8810_DAC_EN_SFT, 0),
0438     SND_SOC_DAPM_ADC("ADC", "Capture", NAU8810_REG_POWER2,
0439         NAU8810_ADC_EN_SFT, 0),
0440     SND_SOC_DAPM_PGA("SpkN Out", NAU8810_REG_POWER3,
0441         NAU8810_NSPK_EN_SFT, 0, NULL, 0),
0442     SND_SOC_DAPM_PGA("SpkP Out", NAU8810_REG_POWER3,
0443         NAU8810_PSPK_EN_SFT, 0, NULL, 0),
0444     SND_SOC_DAPM_PGA("Mono Out", NAU8810_REG_POWER3,
0445         NAU8810_MOUT_EN_SFT, 0, NULL, 0),
0446 
0447     SND_SOC_DAPM_MIXER("Input PGA", NAU8810_REG_POWER2,
0448         NAU8810_PGA_EN_SFT, 0, nau8810_inpga,
0449         ARRAY_SIZE(nau8810_inpga)),
0450     SND_SOC_DAPM_MIXER("Input Boost Stage", NAU8810_REG_POWER2,
0451         NAU8810_BST_EN_SFT, 0, nau8810_pgaboost_mixer_controls,
0452         ARRAY_SIZE(nau8810_pgaboost_mixer_controls)),
0453     SND_SOC_DAPM_PGA("AUX Input", NAU8810_REG_POWER1,
0454         NAU8810_AUX_EN_SFT, 0, NULL, 0),
0455 
0456     SND_SOC_DAPM_SUPPLY("Mic Bias", NAU8810_REG_POWER1,
0457         NAU8810_MICBIAS_EN_SFT, 0, NULL, 0),
0458     SND_SOC_DAPM_SUPPLY("PLL", NAU8810_REG_POWER1,
0459         NAU8810_PLL_EN_SFT, 0, NULL, 0),
0460 
0461     SND_SOC_DAPM_SWITCH("Digital Loopback", SND_SOC_NOPM, 0, 0,
0462         &nau8810_loopback),
0463 
0464     SND_SOC_DAPM_INPUT("AUX"),
0465     SND_SOC_DAPM_INPUT("MICN"),
0466     SND_SOC_DAPM_INPUT("MICP"),
0467     SND_SOC_DAPM_OUTPUT("MONOOUT"),
0468     SND_SOC_DAPM_OUTPUT("SPKOUTP"),
0469     SND_SOC_DAPM_OUTPUT("SPKOUTN"),
0470 };
0471 
0472 static const struct snd_soc_dapm_route nau8810_dapm_routes[] = {
0473     {"DAC", NULL, "PLL", check_mclk_select_pll},
0474 
0475     /* Mono output mixer */
0476     {"Mono Mixer", "AUX Bypass Switch", "AUX Input"},
0477     {"Mono Mixer", "PCM Playback Switch", "DAC"},
0478     {"Mono Mixer", "Line Bypass Switch", "Input Boost Stage"},
0479 
0480     /* Speaker output mixer */
0481     {"Speaker Mixer", "AUX Bypass Switch", "AUX Input"},
0482     {"Speaker Mixer", "PCM Playback Switch", "DAC"},
0483     {"Speaker Mixer", "Line Bypass Switch", "Input Boost Stage"},
0484 
0485     /* Outputs */
0486     {"Mono Out", NULL, "Mono Mixer"},
0487     {"MONOOUT", NULL, "Mono Out"},
0488     {"SpkN Out", NULL, "Speaker Mixer"},
0489     {"SpkP Out", NULL, "Speaker Mixer"},
0490     {"SPKOUTN", NULL, "SpkN Out"},
0491     {"SPKOUTP", NULL, "SpkP Out"},
0492 
0493     /* Input Boost Stage */
0494     {"ADC", NULL, "Input Boost Stage"},
0495     {"ADC", NULL, "PLL", check_mclk_select_pll},
0496     {"Input Boost Stage", "AUX PGA Switch", "AUX Input"},
0497     {"Input Boost Stage", "PGA Mute Switch", "Input PGA"},
0498     {"Input Boost Stage", "PMIC PGA Switch", "MICP"},
0499 
0500     /* Input PGA */
0501     {"Input PGA", NULL, "Mic Bias", check_mic_enabled},
0502     {"Input PGA", "AUX Switch", "AUX Input"},
0503     {"Input PGA", "MicN Switch", "MICN"},
0504     {"Input PGA", "MicP Switch", "MICP"},
0505     {"AUX Input", NULL, "AUX"},
0506 
0507     /* Digital Looptack */
0508     {"Digital Loopback", "Switch", "ADC"},
0509     {"DAC", NULL, "Digital Loopback"},
0510 };
0511 
0512 static int nau8810_set_sysclk(struct snd_soc_dai *dai,
0513                  int clk_id, unsigned int freq, int dir)
0514 {
0515     struct snd_soc_component *component = dai->component;
0516     struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
0517 
0518     nau8810->clk_id = clk_id;
0519     nau8810->sysclk = freq;
0520     dev_dbg(nau8810->dev, "master sysclk %dHz, source %s\n",
0521         freq, clk_id == NAU8810_SCLK_PLL ? "PLL" : "MCLK");
0522 
0523     return 0;
0524 }
0525 
0526 static int nau8810_calc_pll(unsigned int pll_in,
0527     unsigned int fs, struct nau8810_pll *pll_param)
0528 {
0529     u64 f2, f2_max, pll_ratio;
0530     int i, scal_sel;
0531 
0532     if (pll_in > NAU_PLL_REF_MAX || pll_in < NAU_PLL_REF_MIN)
0533         return -EINVAL;
0534 
0535     f2_max = 0;
0536     scal_sel = ARRAY_SIZE(nau8810_mclk_scaler);
0537     for (i = 0; i < ARRAY_SIZE(nau8810_mclk_scaler); i++) {
0538         f2 = 256ULL * fs * 4 * nau8810_mclk_scaler[i];
0539         f2 = div_u64(f2, 10);
0540         if (f2 > NAU_PLL_FREQ_MIN && f2 < NAU_PLL_FREQ_MAX &&
0541             f2_max < f2) {
0542             f2_max = f2;
0543             scal_sel = i;
0544         }
0545     }
0546     if (ARRAY_SIZE(nau8810_mclk_scaler) == scal_sel)
0547         return -EINVAL;
0548     pll_param->mclk_scaler = scal_sel;
0549     f2 = f2_max;
0550 
0551     /* Calculate the PLL 4-bit integer input and the PLL 24-bit fractional
0552      * input; round up the 24+4bit.
0553      */
0554     pll_ratio = div_u64(f2 << 28, pll_in);
0555     pll_param->pre_factor = 0;
0556     if (((pll_ratio >> 28) & 0xF) < NAU_PLL_OPTOP_MIN) {
0557         pll_ratio <<= 1;
0558         pll_param->pre_factor = 1;
0559     }
0560     pll_param->pll_int = (pll_ratio >> 28) & 0xF;
0561     pll_param->pll_frac = ((pll_ratio & 0xFFFFFFF) >> 4);
0562 
0563     return 0;
0564 }
0565 
0566 static int nau8810_set_pll(struct snd_soc_dai *codec_dai, int pll_id,
0567     int source, unsigned int freq_in, unsigned int freq_out)
0568 {
0569     struct snd_soc_component *component = codec_dai->component;
0570     struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
0571     struct regmap *map = nau8810->regmap;
0572     struct nau8810_pll *pll_param = &nau8810->pll;
0573     int ret, fs;
0574 
0575     fs = freq_out / 256;
0576     ret = nau8810_calc_pll(freq_in, fs, pll_param);
0577     if (ret < 0) {
0578         dev_err(nau8810->dev, "Unsupported input clock %d\n", freq_in);
0579         return ret;
0580     }
0581     dev_info(nau8810->dev, "pll_int=%x pll_frac=%x mclk_scaler=%x pre_factor=%x\n",
0582         pll_param->pll_int, pll_param->pll_frac, pll_param->mclk_scaler,
0583         pll_param->pre_factor);
0584 
0585     regmap_update_bits(map, NAU8810_REG_PLLN,
0586         NAU8810_PLLMCLK_DIV2 | NAU8810_PLLN_MASK,
0587         (pll_param->pre_factor ? NAU8810_PLLMCLK_DIV2 : 0) |
0588         pll_param->pll_int);
0589     regmap_write(map, NAU8810_REG_PLLK1,
0590         (pll_param->pll_frac >> NAU8810_PLLK1_SFT) &
0591         NAU8810_PLLK1_MASK);
0592     regmap_write(map, NAU8810_REG_PLLK2,
0593         (pll_param->pll_frac >> NAU8810_PLLK2_SFT) &
0594         NAU8810_PLLK2_MASK);
0595     regmap_write(map, NAU8810_REG_PLLK3,
0596         pll_param->pll_frac & NAU8810_PLLK3_MASK);
0597     regmap_update_bits(map, NAU8810_REG_CLOCK, NAU8810_MCLKSEL_MASK,
0598         pll_param->mclk_scaler << NAU8810_MCLKSEL_SFT);
0599     regmap_update_bits(map, NAU8810_REG_CLOCK,
0600         NAU8810_CLKM_MASK, NAU8810_CLKM_PLL);
0601 
0602     return 0;
0603 }
0604 
0605 static int nau8810_set_dai_fmt(struct snd_soc_dai *codec_dai,
0606         unsigned int fmt)
0607 {
0608     struct snd_soc_component *component = codec_dai->component;
0609     struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
0610     u16 ctrl1_val = 0, ctrl2_val = 0;
0611 
0612     switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
0613     case SND_SOC_DAIFMT_CBM_CFM:
0614         ctrl2_val |= NAU8810_CLKIO_MASTER;
0615         break;
0616     case SND_SOC_DAIFMT_CBS_CFS:
0617         break;
0618     default:
0619         return -EINVAL;
0620     }
0621 
0622     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0623     case SND_SOC_DAIFMT_I2S:
0624         ctrl1_val |= NAU8810_AIFMT_I2S;
0625         break;
0626     case SND_SOC_DAIFMT_RIGHT_J:
0627         break;
0628     case SND_SOC_DAIFMT_LEFT_J:
0629         ctrl1_val |= NAU8810_AIFMT_LEFT;
0630         break;
0631     case SND_SOC_DAIFMT_DSP_A:
0632         ctrl1_val |= NAU8810_AIFMT_PCM_A;
0633         break;
0634     default:
0635         return -EINVAL;
0636     }
0637 
0638     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0639     case SND_SOC_DAIFMT_NB_NF:
0640         break;
0641     case SND_SOC_DAIFMT_IB_IF:
0642         ctrl1_val |= NAU8810_BCLKP_IB | NAU8810_FSP_IF;
0643         break;
0644     case SND_SOC_DAIFMT_IB_NF:
0645         ctrl1_val |= NAU8810_BCLKP_IB;
0646         break;
0647     case SND_SOC_DAIFMT_NB_IF:
0648         ctrl1_val |= NAU8810_FSP_IF;
0649         break;
0650     default:
0651         return -EINVAL;
0652     }
0653 
0654     regmap_update_bits(nau8810->regmap, NAU8810_REG_IFACE,
0655         NAU8810_AIFMT_MASK | NAU8810_FSP_IF |
0656         NAU8810_BCLKP_IB, ctrl1_val);
0657     regmap_update_bits(nau8810->regmap, NAU8810_REG_CLOCK,
0658         NAU8810_CLKIO_MASK, ctrl2_val);
0659 
0660     return 0;
0661 }
0662 
0663 static int nau8810_mclk_clkdiv(struct nau8810 *nau8810, int rate)
0664 {
0665     int i, sclk, imclk = rate * 256, div = 0;
0666 
0667     if (!nau8810->sysclk) {
0668         dev_err(nau8810->dev, "Make mclk div configuration fail because of invalid system clock\n");
0669         return -EINVAL;
0670     }
0671 
0672     /* Configure the master clock prescaler div to make system
0673      * clock to approximate the internal master clock (IMCLK);
0674      * and large or equal to IMCLK.
0675      */
0676     for (i = 1; i < ARRAY_SIZE(nau8810_mclk_scaler); i++) {
0677         sclk = (nau8810->sysclk * 10) /
0678             nau8810_mclk_scaler[i];
0679         if (sclk < imclk)
0680             break;
0681         div = i;
0682     }
0683     dev_dbg(nau8810->dev,
0684         "master clock prescaler %x for fs %d\n", div, rate);
0685 
0686     /* master clock from MCLK and disable PLL */
0687     regmap_update_bits(nau8810->regmap, NAU8810_REG_CLOCK,
0688         NAU8810_MCLKSEL_MASK, (div << NAU8810_MCLKSEL_SFT));
0689     regmap_update_bits(nau8810->regmap, NAU8810_REG_CLOCK,
0690         NAU8810_CLKM_MASK, NAU8810_CLKM_MCLK);
0691 
0692     return 0;
0693 }
0694 
0695 static int nau8810_pcm_hw_params(struct snd_pcm_substream *substream,
0696     struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
0697 {
0698     struct snd_soc_component *component = dai->component;
0699     struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
0700     int val_len = 0, val_rate = 0, ret = 0;
0701     unsigned int ctrl_val, bclk_fs, bclk_div;
0702 
0703     /* Select BCLK configuration if the codec as master. */
0704     regmap_read(nau8810->regmap, NAU8810_REG_CLOCK, &ctrl_val);
0705     if (ctrl_val & NAU8810_CLKIO_MASTER) {
0706         /* get the bclk and fs ratio */
0707         bclk_fs = snd_soc_params_to_bclk(params) / params_rate(params);
0708         if (bclk_fs <= 32)
0709             bclk_div = NAU8810_BCLKDIV_8;
0710         else if (bclk_fs <= 64)
0711             bclk_div = NAU8810_BCLKDIV_4;
0712         else if (bclk_fs <= 128)
0713             bclk_div = NAU8810_BCLKDIV_2;
0714         else
0715             return -EINVAL;
0716         regmap_update_bits(nau8810->regmap, NAU8810_REG_CLOCK,
0717             NAU8810_BCLKSEL_MASK, bclk_div);
0718     }
0719 
0720     switch (params_width(params)) {
0721     case 16:
0722         break;
0723     case 20:
0724         val_len |= NAU8810_WLEN_20;
0725         break;
0726     case 24:
0727         val_len |= NAU8810_WLEN_24;
0728         break;
0729     case 32:
0730         val_len |= NAU8810_WLEN_32;
0731         break;
0732     }
0733 
0734     switch (params_rate(params)) {
0735     case 8000:
0736         val_rate |= NAU8810_SMPLR_8K;
0737         break;
0738     case 11025:
0739         val_rate |= NAU8810_SMPLR_12K;
0740         break;
0741     case 16000:
0742         val_rate |= NAU8810_SMPLR_16K;
0743         break;
0744     case 22050:
0745         val_rate |= NAU8810_SMPLR_24K;
0746         break;
0747     case 32000:
0748         val_rate |= NAU8810_SMPLR_32K;
0749         break;
0750     case 44100:
0751     case 48000:
0752         break;
0753     }
0754 
0755     regmap_update_bits(nau8810->regmap, NAU8810_REG_IFACE,
0756         NAU8810_WLEN_MASK, val_len);
0757     regmap_update_bits(nau8810->regmap, NAU8810_REG_SMPLR,
0758         NAU8810_SMPLR_MASK, val_rate);
0759 
0760     /* If the master clock is from MCLK, provide the runtime FS for driver
0761      * to get the master clock prescaler configuration.
0762      */
0763     if (nau8810->clk_id == NAU8810_SCLK_MCLK) {
0764         ret = nau8810_mclk_clkdiv(nau8810, params_rate(params));
0765         if (ret < 0)
0766             dev_err(nau8810->dev, "MCLK div configuration fail\n");
0767     }
0768 
0769     return ret;
0770 }
0771 
0772 static int nau8810_set_bias_level(struct snd_soc_component *component,
0773     enum snd_soc_bias_level level)
0774 {
0775     struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
0776     struct regmap *map = nau8810->regmap;
0777 
0778     switch (level) {
0779     case SND_SOC_BIAS_ON:
0780     case SND_SOC_BIAS_PREPARE:
0781         regmap_update_bits(map, NAU8810_REG_POWER1,
0782             NAU8810_REFIMP_MASK, NAU8810_REFIMP_80K);
0783         break;
0784 
0785     case SND_SOC_BIAS_STANDBY:
0786         regmap_update_bits(map, NAU8810_REG_POWER1,
0787             NAU8810_IOBUF_EN | NAU8810_ABIAS_EN,
0788             NAU8810_IOBUF_EN | NAU8810_ABIAS_EN);
0789 
0790         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
0791             regcache_sync(map);
0792             regmap_update_bits(map, NAU8810_REG_POWER1,
0793                 NAU8810_REFIMP_MASK, NAU8810_REFIMP_3K);
0794             mdelay(100);
0795         }
0796         regmap_update_bits(map, NAU8810_REG_POWER1,
0797             NAU8810_REFIMP_MASK, NAU8810_REFIMP_300K);
0798         break;
0799 
0800     case SND_SOC_BIAS_OFF:
0801         regmap_write(map, NAU8810_REG_POWER1, 0);
0802         regmap_write(map, NAU8810_REG_POWER2, 0);
0803         regmap_write(map, NAU8810_REG_POWER3, 0);
0804         break;
0805     }
0806 
0807     return 0;
0808 }
0809 
0810 
0811 #define NAU8810_RATES (SNDRV_PCM_RATE_8000_48000)
0812 
0813 #define NAU8810_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
0814     SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
0815 
0816 static const struct snd_soc_dai_ops nau8810_ops = {
0817     .hw_params = nau8810_pcm_hw_params,
0818     .set_fmt = nau8810_set_dai_fmt,
0819     .set_sysclk = nau8810_set_sysclk,
0820     .set_pll = nau8810_set_pll,
0821 };
0822 
0823 static struct snd_soc_dai_driver nau8810_dai = {
0824     .name = "nau8810-hifi",
0825     .playback = {
0826         .stream_name = "Playback",
0827         .channels_min = 1,
0828         .channels_max = 2,   /* Only 1 channel of data */
0829         .rates = NAU8810_RATES,
0830         .formats = NAU8810_FORMATS,
0831     },
0832     .capture = {
0833         .stream_name = "Capture",
0834         .channels_min = 1,
0835         .channels_max = 2,   /* Only 1 channel of data */
0836         .rates = NAU8810_RATES,
0837         .formats = NAU8810_FORMATS,
0838     },
0839     .ops = &nau8810_ops,
0840     .symmetric_rate = 1,
0841 };
0842 
0843 static const struct regmap_config nau8810_regmap_config = {
0844     .reg_bits = 7,
0845     .val_bits = 9,
0846 
0847     .max_register = NAU8810_REG_MAX,
0848     .readable_reg = nau8810_readable_reg,
0849     .writeable_reg = nau8810_writeable_reg,
0850     .volatile_reg = nau8810_volatile_reg,
0851 
0852     .cache_type = REGCACHE_RBTREE,
0853     .reg_defaults = nau8810_reg_defaults,
0854     .num_reg_defaults = ARRAY_SIZE(nau8810_reg_defaults),
0855 };
0856 
0857 static const struct snd_soc_component_driver nau8810_component_driver = {
0858     .set_bias_level     = nau8810_set_bias_level,
0859     .controls       = nau8810_snd_controls,
0860     .num_controls       = ARRAY_SIZE(nau8810_snd_controls),
0861     .dapm_widgets       = nau8810_dapm_widgets,
0862     .num_dapm_widgets   = ARRAY_SIZE(nau8810_dapm_widgets),
0863     .dapm_routes        = nau8810_dapm_routes,
0864     .num_dapm_routes    = ARRAY_SIZE(nau8810_dapm_routes),
0865     .suspend_bias_off   = 1,
0866     .idle_bias_on       = 1,
0867     .use_pmdown_time    = 1,
0868     .endianness     = 1,
0869 };
0870 
0871 static int nau8810_i2c_probe(struct i2c_client *i2c)
0872 {
0873     struct device *dev = &i2c->dev;
0874     struct nau8810 *nau8810 = dev_get_platdata(dev);
0875 
0876     if (!nau8810) {
0877         nau8810 = devm_kzalloc(dev, sizeof(*nau8810), GFP_KERNEL);
0878         if (!nau8810)
0879             return -ENOMEM;
0880     }
0881     i2c_set_clientdata(i2c, nau8810);
0882 
0883     nau8810->regmap = devm_regmap_init_i2c(i2c, &nau8810_regmap_config);
0884     if (IS_ERR(nau8810->regmap))
0885         return PTR_ERR(nau8810->regmap);
0886     nau8810->dev = dev;
0887 
0888     regmap_write(nau8810->regmap, NAU8810_REG_RESET, 0x00);
0889 
0890     return devm_snd_soc_register_component(dev,
0891         &nau8810_component_driver, &nau8810_dai, 1);
0892 }
0893 
0894 static const struct i2c_device_id nau8810_i2c_id[] = {
0895     { "nau8810", 0 },
0896     { "nau8812", 0 },
0897     { "nau8814", 0 },
0898     { }
0899 };
0900 MODULE_DEVICE_TABLE(i2c, nau8810_i2c_id);
0901 
0902 #ifdef CONFIG_OF
0903 static const struct of_device_id nau8810_of_match[] = {
0904     { .compatible = "nuvoton,nau8810", },
0905     { .compatible = "nuvoton,nau8812", },
0906     { .compatible = "nuvoton,nau8814", },
0907     { }
0908 };
0909 MODULE_DEVICE_TABLE(of, nau8810_of_match);
0910 #endif
0911 
0912 static struct i2c_driver nau8810_i2c_driver = {
0913     .driver = {
0914         .name = "nau8810",
0915         .of_match_table = of_match_ptr(nau8810_of_match),
0916     },
0917     .probe_new = nau8810_i2c_probe,
0918     .id_table = nau8810_i2c_id,
0919 };
0920 
0921 module_i2c_driver(nau8810_i2c_driver);
0922 
0923 MODULE_DESCRIPTION("ASoC NAU8810 driver");
0924 MODULE_AUTHOR("David Lin <ctlin0@nuvoton.com>");
0925 MODULE_LICENSE("GPL v2");
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