soc/codecs/nau8540.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * NAU85L40 ALSA SoC audio driver
0004  *
0005  * Copyright 2016 Nuvoton Technology Corp.
0006  * Author: John Hsu <KCHSU0@nuvoton.com>
0007  */
0008
0009 #ifndef __NAU8540_H__
0010 #define __NAU8540_H__
0011
0012 #define NAU8540_REG_SW_RESET            0x00
0013 #define NAU8540_REG_POWER_MANAGEMENT    0x01
0014 #define NAU8540_REG_CLOCK_CTRL      0x02
0015 #define NAU8540_REG_CLOCK_SRC           0x03
0016 #define NAU8540_REG_FLL1            0x04
0017 #define NAU8540_REG_FLL2            0x05
0018 #define NAU8540_REG_FLL3            0x06
0019 #define NAU8540_REG_FLL4            0x07
0020 #define NAU8540_REG_FLL5            0x08
0021 #define NAU8540_REG_FLL6            0x09
0022 #define NAU8540_REG_FLL_VCO_RSV     0x0A
0023 #define NAU8540_REG_PCM_CTRL0           0x10
0024 #define NAU8540_REG_PCM_CTRL1           0x11
0025 #define NAU8540_REG_PCM_CTRL2           0x12
0026 #define NAU8540_REG_PCM_CTRL3           0x13
0027 #define NAU8540_REG_PCM_CTRL4           0x14
0028 #define NAU8540_REG_ALC_CONTROL_1       0x20
0029 #define NAU8540_REG_ALC_CONTROL_2       0x21
0030 #define NAU8540_REG_ALC_CONTROL_3       0x22
0031 #define NAU8540_REG_ALC_CONTROL_4       0x23
0032 #define NAU8540_REG_ALC_CONTROL_5       0x24
0033 #define NAU8540_REG_ALC_GAIN_CH12       0x2D
0034 #define NAU8540_REG_ALC_GAIN_CH34       0x2E
0035 #define NAU8540_REG_ALC_STATUS      0x2F
0036 #define NAU8540_REG_NOTCH_FIL1_CH1      0x30
0037 #define NAU8540_REG_NOTCH_FIL2_CH1      0x31
0038 #define NAU8540_REG_NOTCH_FIL1_CH2      0x32
0039 #define NAU8540_REG_NOTCH_FIL2_CH2      0x33
0040 #define NAU8540_REG_NOTCH_FIL1_CH3      0x34
0041 #define NAU8540_REG_NOTCH_FIL2_CH3      0x35
0042 #define NAU8540_REG_NOTCH_FIL1_CH4      0x36
0043 #define NAU8540_REG_NOTCH_FIL2_CH4      0x37
0044 #define NAU8540_REG_HPF_FILTER_CH12     0x38
0045 #define NAU8540_REG_HPF_FILTER_CH34     0x39
0046 #define NAU8540_REG_ADC_SAMPLE_RATE     0x3A
0047 #define NAU8540_REG_DIGITAL_GAIN_CH1        0x40
0048 #define NAU8540_REG_DIGITAL_GAIN_CH2        0x41
0049 #define NAU8540_REG_DIGITAL_GAIN_CH3        0x42
0050 #define NAU8540_REG_DIGITAL_GAIN_CH4        0x43
0051 #define NAU8540_REG_DIGITAL_MUX     0x44
0052 #define NAU8540_REG_P2P_CH1         0x48
0053 #define NAU8540_REG_P2P_CH2         0x49
0054 #define NAU8540_REG_P2P_CH3         0x4A
0055 #define NAU8540_REG_P2P_CH4         0x4B
0056 #define NAU8540_REG_PEAK_CH1            0x4C
0057 #define NAU8540_REG_PEAK_CH2            0x4D
0058 #define NAU8540_REG_PEAK_CH3            0x4E
0059 #define NAU8540_REG_PEAK_CH4            0x4F
0060 #define NAU8540_REG_GPIO_CTRL           0x50
0061 #define NAU8540_REG_MISC_CTRL           0x51
0062 #define NAU8540_REG_I2C_CTRL            0x52
0063 #define NAU8540_REG_I2C_DEVICE_ID       0x58
0064 #define NAU8540_REG_RST         0x5A
0065 #define NAU8540_REG_VMID_CTRL           0x60
0066 #define NAU8540_REG_MUTE            0x61
0067 #define NAU8540_REG_ANALOG_ADC1     0x64
0068 #define NAU8540_REG_ANALOG_ADC2     0x65
0069 #define NAU8540_REG_ANALOG_PWR      0x66
0070 #define NAU8540_REG_MIC_BIAS            0x67
0071 #define NAU8540_REG_REFERENCE           0x68
0072 #define NAU8540_REG_FEPGA1          0x69
0073 #define NAU8540_REG_FEPGA2          0x6A
0074 #define NAU8540_REG_FEPGA3          0x6B
0075 #define NAU8540_REG_FEPGA4          0x6C
0076 #define NAU8540_REG_PWR         0x6D
0077 #define NAU8540_REG_MAX         NAU8540_REG_PWR
0078
0079
0080 /* POWER_MANAGEMENT (0x01) */
0081 #define NAU8540_ADC4_EN     (0x1 << 3)
0082 #define NAU8540_ADC3_EN     (0x1 << 2)
0083 #define NAU8540_ADC2_EN     (0x1 << 1)
0084 #define NAU8540_ADC1_EN     0x1
0085
0086 /* CLOCK_CTRL (0x02) */
0087 #define NAU8540_CLK_ADC_EN      (0x1 << 15)
0088 #define NAU8540_CLK_I2S_EN      (0x1 << 1)
0089
0090 /* CLOCK_SRC (0x03) */
0091 #define NAU8540_CLK_SRC_SFT     15
0092 #define NAU8540_CLK_SRC_MASK        (1 << NAU8540_CLK_SRC_SFT)
0093 #define NAU8540_CLK_SRC_VCO     (1 << NAU8540_CLK_SRC_SFT)
0094 #define NAU8540_CLK_SRC_MCLK        (0 << NAU8540_CLK_SRC_SFT)
0095 #define NAU8540_CLK_ADC_SRC_SFT 6
0096 #define NAU8540_CLK_ADC_SRC_MASK    (0x3 << NAU8540_CLK_ADC_SRC_SFT)
0097 #define NAU8540_CLK_MCLK_SRC_MASK   0xf
0098
0099 /* FLL1 (0x04) */
0100 #define NAU8540_ICTRL_LATCH_SFT 10
0101 #define NAU8540_ICTRL_LATCH_MASK    (0x7 << NAU8540_ICTRL_LATCH_SFT)
0102 #define NAU8540_FLL_RATIO_MASK  0x7f
0103
0104 /* FLL3 (0x06) */
0105 #define NAU8540_GAIN_ERR_SFT        12
0106 #define NAU8540_GAIN_ERR_MASK       (0xf << NAU8540_GAIN_ERR_SFT)
0107 #define NAU8540_FLL_CLK_SRC_SFT 10
0108 #define NAU8540_FLL_CLK_SRC_MASK    (0x3 << NAU8540_FLL_CLK_SRC_SFT)
0109 #define NAU8540_FLL_CLK_SRC_MCLK    (0 << NAU8540_FLL_CLK_SRC_SFT)
0110 #define NAU8540_FLL_CLK_SRC_BLK (0x2 << NAU8540_FLL_CLK_SRC_SFT)
0111 #define NAU8540_FLL_CLK_SRC_FS      (0x3 << NAU8540_FLL_CLK_SRC_SFT)
0112 #define NAU8540_FLL_INTEGER_MASK    0x3ff
0113
0114 /* FLL4 (0x07) */
0115 #define NAU8540_FLL_REF_DIV_SFT 10
0116 #define NAU8540_FLL_REF_DIV_MASK    (0x3 << NAU8540_FLL_REF_DIV_SFT)
0117
0118 /* FLL5 (0x08) */
0119 #define NAU8540_FLL_PDB_DAC_EN  (0x1 << 15)
0120 #define NAU8540_FLL_LOOP_FTR_EN (0x1 << 14)
0121 #define NAU8540_FLL_CLK_SW_MASK (0x1 << 13)
0122 #define NAU8540_FLL_CLK_SW_N2       (0x1 << 13)
0123 #define NAU8540_FLL_CLK_SW_REF  (0x0 << 13)
0124 #define NAU8540_FLL_FTR_SW_MASK (0x1 << 12)
0125 #define NAU8540_FLL_FTR_SW_ACCU (0x1 << 12)
0126 #define NAU8540_FLL_FTR_SW_FILTER   (0x0 << 12)
0127
0128 /* FLL6 (0x9) */
0129 #define NAU8540_DCO_EN          (0x1 << 15)
0130 #define NAU8540_SDM_EN          (0x1 << 14)
0131 #define NAU8540_CUTOFF500       (0x1 << 13)
0132
0133 /* PCM_CTRL0 (0x10) */
0134 #define NAU8540_I2S_BP_SFT      7
0135 #define NAU8540_I2S_BP_INV      (0x1 << NAU8540_I2S_BP_SFT)
0136 #define NAU8540_I2S_PCMB_SFT        6
0137 #define NAU8540_I2S_PCMB_EN     (0x1 << NAU8540_I2S_PCMB_SFT)
0138 #define NAU8540_I2S_DL_SFT      2
0139 #define NAU8540_I2S_DL_MASK     (0x3 << NAU8540_I2S_DL_SFT)
0140 #define NAU8540_I2S_DL_16       (0 << NAU8540_I2S_DL_SFT)
0141 #define NAU8540_I2S_DL_20       (0x1 << NAU8540_I2S_DL_SFT)
0142 #define NAU8540_I2S_DL_24       (0x2 << NAU8540_I2S_DL_SFT)
0143 #define NAU8540_I2S_DL_32       (0x3 << NAU8540_I2S_DL_SFT)
0144 #define NAU8540_I2S_DF_MASK     0x3
0145 #define NAU8540_I2S_DF_RIGTH        0
0146 #define NAU8540_I2S_DF_LEFT     0x1
0147 #define NAU8540_I2S_DF_I2S      0x2
0148 #define NAU8540_I2S_DF_PCM_AB       0x3
0149
0150 /* PCM_CTRL1 (0x11) */
0151 #define NAU8540_I2S_DO12_TRI        (0x1 << 15)
0152 #define NAU8540_I2S_LRC_DIV_SFT 12
0153 #define NAU8540_I2S_LRC_DIV_MASK    (0x3 << NAU8540_I2S_LRC_DIV_SFT)
0154 #define NAU8540_I2S_DO12_OE     (0x1 << 4)
0155 #define NAU8540_I2S_MS_SFT      3
0156 #define NAU8540_I2S_MS_MASK     (0x1 << NAU8540_I2S_MS_SFT)
0157 #define NAU8540_I2S_MS_MASTER       (0x1 << NAU8540_I2S_MS_SFT)
0158 #define NAU8540_I2S_MS_SLAVE        (0x0 << NAU8540_I2S_MS_SFT)
0159 #define NAU8540_I2S_BLK_DIV_MASK    0x7
0160
0161 /* PCM_CTRL1 (0x12) */
0162 #define NAU8540_I2S_DO34_TRI        (0x1 << 15)
0163 #define NAU8540_I2S_DO34_OE     (0x1 << 11)
0164 #define NAU8540_I2S_TSLOT_L_MASK    0x3ff
0165
0166 /* PCM_CTRL4 (0x14) */
0167 #define NAU8540_TDM_MODE        (0x1 << 15)
0168 #define NAU8540_TDM_OFFSET_EN       (0x1 << 14)
0169 #define NAU8540_TDM_TX_MASK     0xf
0170
0171 /* ADC_SAMPLE_RATE (0x3A) */
0172 #define NAU8540_CH_SYNC     (0x1 << 14)
0173 #define NAU8540_ADC_OSR_MASK        0x3
0174 #define NAU8540_ADC_OSR_256     0x3
0175 #define NAU8540_ADC_OSR_128     0x2
0176 #define NAU8540_ADC_OSR_64      0x1
0177 #define NAU8540_ADC_OSR_32      0x0
0178
0179 /* VMID_CTRL (0x60) */
0180 #define NAU8540_VMID_EN     (1 << 6)
0181 #define NAU8540_VMID_SEL_SFT        4
0182 #define NAU8540_VMID_SEL_MASK       (0x3 << NAU8540_VMID_SEL_SFT)
0183
0184 /* MIC_BIAS (0x67) */
0185 #define NAU8540_PU_PRE          (0x1 << 8)
0186
0187 /* REFERENCE (0x68) */
0188 #define NAU8540_PRECHARGE_DIS       (0x1 << 13)
0189 #define NAU8540_GLOBAL_BIAS_EN  (0x1 << 12)
0190
0191 /* FEPGA1 (0x69) */
0192 #define NAU8540_FEPGA1_MODCH2_SHT_SFT   7
0193 #define NAU8540_FEPGA1_MODCH2_SHT   (0x1 << NAU8540_FEPGA1_MODCH2_SHT_SFT)
0194 #define NAU8540_FEPGA1_MODCH1_SHT_SFT   3
0195 #define NAU8540_FEPGA1_MODCH1_SHT   (0x1 << NAU8540_FEPGA1_MODCH1_SHT_SFT)
0196
0197 /* FEPGA2 (0x6A) */
0198 #define NAU8540_FEPGA2_MODCH4_SHT_SFT   7
0199 #define NAU8540_FEPGA2_MODCH4_SHT   (0x1 << NAU8540_FEPGA2_MODCH4_SHT_SFT)
0200 #define NAU8540_FEPGA2_MODCH3_SHT_SFT   3
0201 #define NAU8540_FEPGA2_MODCH3_SHT   (0x1 << NAU8540_FEPGA2_MODCH3_SHT_SFT)
0202
0203
0204 /* System Clock Source */
0205 enum {
0206     NAU8540_CLK_DIS,
0207     NAU8540_CLK_MCLK,
0208     NAU8540_CLK_INTERNAL,
0209     NAU8540_CLK_FLL_MCLK,
0210     NAU8540_CLK_FLL_BLK,
0211     NAU8540_CLK_FLL_FS,
0212 };
0213
0214 struct nau8540 {
0215     struct device *dev;
0216     struct regmap *regmap;
0217 };
0218
0219 struct nau8540_fll {
0220     int mclk_src;
0221     int ratio;
0222     int fll_frac;
0223     int fll_int;
0224     int clk_ref_div;
0225 };
0226
0227 struct nau8540_fll_attr {
0228     unsigned int param;
0229     unsigned int val;
0230 };
0231
0232 /* over sampling rate */
0233 struct nau8540_osr_attr {
0234     unsigned int osr;
0235     unsigned int clk_src;
0236 };
0237
0238
0239 #endif  /* __NAU8540_H__ */