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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * NAU85L40 ALSA SoC audio driver
0004  *
0005  * Copyright 2016 Nuvoton Technology Corp.
0006  * Author: John Hsu <KCHSU0@nuvoton.com>
0007  */
0008 
0009 #include <linux/module.h>
0010 #include <linux/moduleparam.h>
0011 #include <linux/init.h>
0012 #include <linux/delay.h>
0013 #include <linux/pm.h>
0014 #include <linux/i2c.h>
0015 #include <linux/regmap.h>
0016 #include <linux/regulator/consumer.h>
0017 #include <linux/spi/spi.h>
0018 #include <linux/slab.h>
0019 #include <linux/of_device.h>
0020 #include <sound/core.h>
0021 #include <sound/pcm.h>
0022 #include <sound/pcm_params.h>
0023 #include <sound/soc.h>
0024 #include <sound/soc-dapm.h>
0025 #include <sound/initval.h>
0026 #include <sound/tlv.h>
0027 #include "nau8540.h"
0028 
0029 
0030 #define NAU_FREF_MAX 13500000
0031 #define NAU_FVCO_MAX 100000000
0032 #define NAU_FVCO_MIN 90000000
0033 
0034 /* the maximum frequency of CLK_ADC */
0035 #define CLK_ADC_MAX 6144000
0036 
0037 /* scaling for mclk from sysclk_src output */
0038 static const struct nau8540_fll_attr mclk_src_scaling[] = {
0039     { 1, 0x0 },
0040     { 2, 0x2 },
0041     { 4, 0x3 },
0042     { 8, 0x4 },
0043     { 16, 0x5 },
0044     { 32, 0x6 },
0045     { 3, 0x7 },
0046     { 6, 0xa },
0047     { 12, 0xb },
0048     { 24, 0xc },
0049 };
0050 
0051 /* ratio for input clk freq */
0052 static const struct nau8540_fll_attr fll_ratio[] = {
0053     { 512000, 0x01 },
0054     { 256000, 0x02 },
0055     { 128000, 0x04 },
0056     { 64000, 0x08 },
0057     { 32000, 0x10 },
0058     { 8000, 0x20 },
0059     { 4000, 0x40 },
0060 };
0061 
0062 static const struct nau8540_fll_attr fll_pre_scalar[] = {
0063     { 1, 0x0 },
0064     { 2, 0x1 },
0065     { 4, 0x2 },
0066     { 8, 0x3 },
0067 };
0068 
0069 /* over sampling rate */
0070 static const struct nau8540_osr_attr osr_adc_sel[] = {
0071     { 32, 3 },  /* OSR 32, SRC 1/8 */
0072     { 64, 2 },  /* OSR 64, SRC 1/4 */
0073     { 128, 1 }, /* OSR 128, SRC 1/2 */
0074     { 256, 0 }, /* OSR 256, SRC 1 */
0075 };
0076 
0077 static const struct reg_default nau8540_reg_defaults[] = {
0078     {NAU8540_REG_POWER_MANAGEMENT, 0x0000},
0079     {NAU8540_REG_CLOCK_CTRL, 0x0000},
0080     {NAU8540_REG_CLOCK_SRC, 0x0000},
0081     {NAU8540_REG_FLL1, 0x0001},
0082     {NAU8540_REG_FLL2, 0x3126},
0083     {NAU8540_REG_FLL3, 0x0008},
0084     {NAU8540_REG_FLL4, 0x0010},
0085     {NAU8540_REG_FLL5, 0xC000},
0086     {NAU8540_REG_FLL6, 0x6000},
0087     {NAU8540_REG_FLL_VCO_RSV, 0xF13C},
0088     {NAU8540_REG_PCM_CTRL0, 0x000B},
0089     {NAU8540_REG_PCM_CTRL1, 0x3010},
0090     {NAU8540_REG_PCM_CTRL2, 0x0800},
0091     {NAU8540_REG_PCM_CTRL3, 0x0000},
0092     {NAU8540_REG_PCM_CTRL4, 0x000F},
0093     {NAU8540_REG_ALC_CONTROL_1, 0x0000},
0094     {NAU8540_REG_ALC_CONTROL_2, 0x700B},
0095     {NAU8540_REG_ALC_CONTROL_3, 0x0022},
0096     {NAU8540_REG_ALC_CONTROL_4, 0x1010},
0097     {NAU8540_REG_ALC_CONTROL_5, 0x1010},
0098     {NAU8540_REG_NOTCH_FIL1_CH1, 0x0000},
0099     {NAU8540_REG_NOTCH_FIL2_CH1, 0x0000},
0100     {NAU8540_REG_NOTCH_FIL1_CH2, 0x0000},
0101     {NAU8540_REG_NOTCH_FIL2_CH2, 0x0000},
0102     {NAU8540_REG_NOTCH_FIL1_CH3, 0x0000},
0103     {NAU8540_REG_NOTCH_FIL2_CH3, 0x0000},
0104     {NAU8540_REG_NOTCH_FIL1_CH4, 0x0000},
0105     {NAU8540_REG_NOTCH_FIL2_CH4, 0x0000},
0106     {NAU8540_REG_HPF_FILTER_CH12, 0x0000},
0107     {NAU8540_REG_HPF_FILTER_CH34, 0x0000},
0108     {NAU8540_REG_ADC_SAMPLE_RATE, 0x0002},
0109     {NAU8540_REG_DIGITAL_GAIN_CH1, 0x0400},
0110     {NAU8540_REG_DIGITAL_GAIN_CH2, 0x0400},
0111     {NAU8540_REG_DIGITAL_GAIN_CH3, 0x0400},
0112     {NAU8540_REG_DIGITAL_GAIN_CH4, 0x0400},
0113     {NAU8540_REG_DIGITAL_MUX, 0x00E4},
0114     {NAU8540_REG_GPIO_CTRL, 0x0000},
0115     {NAU8540_REG_MISC_CTRL, 0x0000},
0116     {NAU8540_REG_I2C_CTRL, 0xEFFF},
0117     {NAU8540_REG_VMID_CTRL, 0x0000},
0118     {NAU8540_REG_MUTE, 0x0000},
0119     {NAU8540_REG_ANALOG_ADC1, 0x0011},
0120     {NAU8540_REG_ANALOG_ADC2, 0x0020},
0121     {NAU8540_REG_ANALOG_PWR, 0x0000},
0122     {NAU8540_REG_MIC_BIAS, 0x0004},
0123     {NAU8540_REG_REFERENCE, 0x0000},
0124     {NAU8540_REG_FEPGA1, 0x0000},
0125     {NAU8540_REG_FEPGA2, 0x0000},
0126     {NAU8540_REG_FEPGA3, 0x0101},
0127     {NAU8540_REG_FEPGA4, 0x0101},
0128     {NAU8540_REG_PWR, 0x0000},
0129 };
0130 
0131 static bool nau8540_readable_reg(struct device *dev, unsigned int reg)
0132 {
0133     switch (reg) {
0134     case NAU8540_REG_POWER_MANAGEMENT ... NAU8540_REG_FLL_VCO_RSV:
0135     case NAU8540_REG_PCM_CTRL0 ... NAU8540_REG_PCM_CTRL4:
0136     case NAU8540_REG_ALC_CONTROL_1 ... NAU8540_REG_ALC_CONTROL_5:
0137     case NAU8540_REG_ALC_GAIN_CH12 ... NAU8540_REG_ADC_SAMPLE_RATE:
0138     case NAU8540_REG_DIGITAL_GAIN_CH1 ... NAU8540_REG_DIGITAL_MUX:
0139     case NAU8540_REG_P2P_CH1 ... NAU8540_REG_I2C_CTRL:
0140     case NAU8540_REG_I2C_DEVICE_ID:
0141     case NAU8540_REG_VMID_CTRL ... NAU8540_REG_MUTE:
0142     case NAU8540_REG_ANALOG_ADC1 ... NAU8540_REG_PWR:
0143         return true;
0144     default:
0145         return false;
0146     }
0147 
0148 }
0149 
0150 static bool nau8540_writeable_reg(struct device *dev, unsigned int reg)
0151 {
0152     switch (reg) {
0153     case NAU8540_REG_SW_RESET ... NAU8540_REG_FLL_VCO_RSV:
0154     case NAU8540_REG_PCM_CTRL0 ... NAU8540_REG_PCM_CTRL4:
0155     case NAU8540_REG_ALC_CONTROL_1 ... NAU8540_REG_ALC_CONTROL_5:
0156     case NAU8540_REG_NOTCH_FIL1_CH1 ... NAU8540_REG_ADC_SAMPLE_RATE:
0157     case NAU8540_REG_DIGITAL_GAIN_CH1 ... NAU8540_REG_DIGITAL_MUX:
0158     case NAU8540_REG_GPIO_CTRL ... NAU8540_REG_I2C_CTRL:
0159     case NAU8540_REG_RST:
0160     case NAU8540_REG_VMID_CTRL ... NAU8540_REG_MUTE:
0161     case NAU8540_REG_ANALOG_ADC1 ... NAU8540_REG_PWR:
0162         return true;
0163     default:
0164         return false;
0165     }
0166 }
0167 
0168 static bool nau8540_volatile_reg(struct device *dev, unsigned int reg)
0169 {
0170     switch (reg) {
0171     case NAU8540_REG_SW_RESET:
0172     case NAU8540_REG_ALC_GAIN_CH12 ... NAU8540_REG_ALC_STATUS:
0173     case NAU8540_REG_P2P_CH1 ... NAU8540_REG_PEAK_CH4:
0174     case NAU8540_REG_I2C_DEVICE_ID:
0175     case NAU8540_REG_RST:
0176         return true;
0177     default:
0178         return false;
0179     }
0180 }
0181 
0182 
0183 static const DECLARE_TLV_DB_MINMAX(adc_vol_tlv, -12800, 3600);
0184 static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600);
0185 
0186 static const struct snd_kcontrol_new nau8540_snd_controls[] = {
0187     SOC_SINGLE_TLV("Mic1 Volume", NAU8540_REG_DIGITAL_GAIN_CH1,
0188         0, 0x520, 0, adc_vol_tlv),
0189     SOC_SINGLE_TLV("Mic2 Volume", NAU8540_REG_DIGITAL_GAIN_CH2,
0190         0, 0x520, 0, adc_vol_tlv),
0191     SOC_SINGLE_TLV("Mic3 Volume", NAU8540_REG_DIGITAL_GAIN_CH3,
0192         0, 0x520, 0, adc_vol_tlv),
0193     SOC_SINGLE_TLV("Mic4 Volume", NAU8540_REG_DIGITAL_GAIN_CH4,
0194         0, 0x520, 0, adc_vol_tlv),
0195 
0196     SOC_SINGLE_TLV("Frontend PGA1 Volume", NAU8540_REG_FEPGA3,
0197         0, 0x25, 0, fepga_gain_tlv),
0198     SOC_SINGLE_TLV("Frontend PGA2 Volume", NAU8540_REG_FEPGA3,
0199         8, 0x25, 0, fepga_gain_tlv),
0200     SOC_SINGLE_TLV("Frontend PGA3 Volume", NAU8540_REG_FEPGA4,
0201         0, 0x25, 0, fepga_gain_tlv),
0202     SOC_SINGLE_TLV("Frontend PGA4 Volume", NAU8540_REG_FEPGA4,
0203         8, 0x25, 0, fepga_gain_tlv),
0204 };
0205 
0206 static const char * const adc_channel[] = {
0207     "ADC channel 1", "ADC channel 2", "ADC channel 3", "ADC channel 4"
0208 };
0209 static SOC_ENUM_SINGLE_DECL(
0210     digital_ch4_enum, NAU8540_REG_DIGITAL_MUX, 6, adc_channel);
0211 
0212 static const struct snd_kcontrol_new digital_ch4_mux =
0213     SOC_DAPM_ENUM("Digital CH4 Select", digital_ch4_enum);
0214 
0215 static SOC_ENUM_SINGLE_DECL(
0216     digital_ch3_enum, NAU8540_REG_DIGITAL_MUX, 4, adc_channel);
0217 
0218 static const struct snd_kcontrol_new digital_ch3_mux =
0219     SOC_DAPM_ENUM("Digital CH3 Select", digital_ch3_enum);
0220 
0221 static SOC_ENUM_SINGLE_DECL(
0222     digital_ch2_enum, NAU8540_REG_DIGITAL_MUX, 2, adc_channel);
0223 
0224 static const struct snd_kcontrol_new digital_ch2_mux =
0225     SOC_DAPM_ENUM("Digital CH2 Select", digital_ch2_enum);
0226 
0227 static SOC_ENUM_SINGLE_DECL(
0228     digital_ch1_enum, NAU8540_REG_DIGITAL_MUX, 0, adc_channel);
0229 
0230 static const struct snd_kcontrol_new digital_ch1_mux =
0231     SOC_DAPM_ENUM("Digital CH1 Select", digital_ch1_enum);
0232 
0233 static int adc_power_control(struct snd_soc_dapm_widget *w,
0234         struct snd_kcontrol *k, int  event)
0235 {
0236     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0237     struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
0238 
0239     if (SND_SOC_DAPM_EVENT_ON(event)) {
0240         msleep(300);
0241         /* DO12 and DO34 pad output enable */
0242         regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
0243             NAU8540_I2S_DO12_TRI, 0);
0244         regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
0245             NAU8540_I2S_DO34_TRI, 0);
0246     } else if (SND_SOC_DAPM_EVENT_OFF(event)) {
0247         regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
0248             NAU8540_I2S_DO12_TRI, NAU8540_I2S_DO12_TRI);
0249         regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
0250             NAU8540_I2S_DO34_TRI, NAU8540_I2S_DO34_TRI);
0251     }
0252     return 0;
0253 }
0254 
0255 static int aiftx_power_control(struct snd_soc_dapm_widget *w,
0256         struct snd_kcontrol *k, int  event)
0257 {
0258     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0259     struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
0260 
0261     if (SND_SOC_DAPM_EVENT_OFF(event)) {
0262         regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0001);
0263         regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0000);
0264     }
0265     return 0;
0266 }
0267 
0268 static const struct snd_soc_dapm_widget nau8540_dapm_widgets[] = {
0269     SND_SOC_DAPM_SUPPLY("MICBIAS2", NAU8540_REG_MIC_BIAS, 11, 0, NULL, 0),
0270     SND_SOC_DAPM_SUPPLY("MICBIAS1", NAU8540_REG_MIC_BIAS, 10, 0, NULL, 0),
0271 
0272     SND_SOC_DAPM_INPUT("MIC1"),
0273     SND_SOC_DAPM_INPUT("MIC2"),
0274     SND_SOC_DAPM_INPUT("MIC3"),
0275     SND_SOC_DAPM_INPUT("MIC4"),
0276 
0277     SND_SOC_DAPM_PGA("Frontend PGA1", NAU8540_REG_PWR, 12, 0, NULL, 0),
0278     SND_SOC_DAPM_PGA("Frontend PGA2", NAU8540_REG_PWR, 13, 0, NULL, 0),
0279     SND_SOC_DAPM_PGA("Frontend PGA3", NAU8540_REG_PWR, 14, 0, NULL, 0),
0280     SND_SOC_DAPM_PGA("Frontend PGA4", NAU8540_REG_PWR, 15, 0, NULL, 0),
0281 
0282     SND_SOC_DAPM_ADC_E("ADC1", NULL,
0283         NAU8540_REG_POWER_MANAGEMENT, 0, 0, adc_power_control,
0284         SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
0285     SND_SOC_DAPM_ADC_E("ADC2", NULL,
0286         NAU8540_REG_POWER_MANAGEMENT, 1, 0, adc_power_control,
0287         SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
0288     SND_SOC_DAPM_ADC_E("ADC3", NULL,
0289         NAU8540_REG_POWER_MANAGEMENT, 2, 0, adc_power_control,
0290         SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
0291     SND_SOC_DAPM_ADC_E("ADC4", NULL,
0292         NAU8540_REG_POWER_MANAGEMENT, 3, 0, adc_power_control,
0293         SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
0294 
0295     SND_SOC_DAPM_PGA("ADC CH1", NAU8540_REG_ANALOG_PWR, 0, 0, NULL, 0),
0296     SND_SOC_DAPM_PGA("ADC CH2", NAU8540_REG_ANALOG_PWR, 1, 0, NULL, 0),
0297     SND_SOC_DAPM_PGA("ADC CH3", NAU8540_REG_ANALOG_PWR, 2, 0, NULL, 0),
0298     SND_SOC_DAPM_PGA("ADC CH4", NAU8540_REG_ANALOG_PWR, 3, 0, NULL, 0),
0299 
0300     SND_SOC_DAPM_MUX("Digital CH4 Mux",
0301         SND_SOC_NOPM, 0, 0, &digital_ch4_mux),
0302     SND_SOC_DAPM_MUX("Digital CH3 Mux",
0303         SND_SOC_NOPM, 0, 0, &digital_ch3_mux),
0304     SND_SOC_DAPM_MUX("Digital CH2 Mux",
0305         SND_SOC_NOPM, 0, 0, &digital_ch2_mux),
0306     SND_SOC_DAPM_MUX("Digital CH1 Mux",
0307         SND_SOC_NOPM, 0, 0, &digital_ch1_mux),
0308 
0309     SND_SOC_DAPM_AIF_OUT_E("AIFTX", "Capture", 0, SND_SOC_NOPM, 0, 0,
0310         aiftx_power_control, SND_SOC_DAPM_POST_PMD),
0311 };
0312 
0313 static const struct snd_soc_dapm_route nau8540_dapm_routes[] = {
0314     {"Frontend PGA1", NULL, "MIC1"},
0315     {"Frontend PGA2", NULL, "MIC2"},
0316     {"Frontend PGA3", NULL, "MIC3"},
0317     {"Frontend PGA4", NULL, "MIC4"},
0318 
0319     {"ADC1", NULL, "Frontend PGA1"},
0320     {"ADC2", NULL, "Frontend PGA2"},
0321     {"ADC3", NULL, "Frontend PGA3"},
0322     {"ADC4", NULL, "Frontend PGA4"},
0323 
0324     {"ADC CH1", NULL, "ADC1"},
0325     {"ADC CH2", NULL, "ADC2"},
0326     {"ADC CH3", NULL, "ADC3"},
0327     {"ADC CH4", NULL, "ADC4"},
0328 
0329     {"ADC1", NULL, "MICBIAS1"},
0330     {"ADC2", NULL, "MICBIAS1"},
0331     {"ADC3", NULL, "MICBIAS2"},
0332     {"ADC4", NULL, "MICBIAS2"},
0333 
0334     {"Digital CH1 Mux", "ADC channel 1", "ADC CH1"},
0335     {"Digital CH1 Mux", "ADC channel 2", "ADC CH2"},
0336     {"Digital CH1 Mux", "ADC channel 3", "ADC CH3"},
0337     {"Digital CH1 Mux", "ADC channel 4", "ADC CH4"},
0338 
0339     {"Digital CH2 Mux", "ADC channel 1", "ADC CH1"},
0340     {"Digital CH2 Mux", "ADC channel 2", "ADC CH2"},
0341     {"Digital CH2 Mux", "ADC channel 3", "ADC CH3"},
0342     {"Digital CH2 Mux", "ADC channel 4", "ADC CH4"},
0343 
0344     {"Digital CH3 Mux", "ADC channel 1", "ADC CH1"},
0345     {"Digital CH3 Mux", "ADC channel 2", "ADC CH2"},
0346     {"Digital CH3 Mux", "ADC channel 3", "ADC CH3"},
0347     {"Digital CH3 Mux", "ADC channel 4", "ADC CH4"},
0348 
0349     {"Digital CH4 Mux", "ADC channel 1", "ADC CH1"},
0350     {"Digital CH4 Mux", "ADC channel 2", "ADC CH2"},
0351     {"Digital CH4 Mux", "ADC channel 3", "ADC CH3"},
0352     {"Digital CH4 Mux", "ADC channel 4", "ADC CH4"},
0353 
0354     {"AIFTX", NULL, "Digital CH1 Mux"},
0355     {"AIFTX", NULL, "Digital CH2 Mux"},
0356     {"AIFTX", NULL, "Digital CH3 Mux"},
0357     {"AIFTX", NULL, "Digital CH4 Mux"},
0358 };
0359 
0360 static const struct nau8540_osr_attr *
0361 nau8540_get_osr(struct nau8540 *nau8540)
0362 {
0363     unsigned int osr;
0364 
0365     regmap_read(nau8540->regmap, NAU8540_REG_ADC_SAMPLE_RATE, &osr);
0366     osr &= NAU8540_ADC_OSR_MASK;
0367     if (osr >= ARRAY_SIZE(osr_adc_sel))
0368         return NULL;
0369     return &osr_adc_sel[osr];
0370 }
0371 
0372 static int nau8540_dai_startup(struct snd_pcm_substream *substream,
0373                    struct snd_soc_dai *dai)
0374 {
0375     struct snd_soc_component *component = dai->component;
0376     struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
0377     const struct nau8540_osr_attr *osr;
0378 
0379     osr = nau8540_get_osr(nau8540);
0380     if (!osr || !osr->osr)
0381         return -EINVAL;
0382 
0383     return snd_pcm_hw_constraint_minmax(substream->runtime,
0384                         SNDRV_PCM_HW_PARAM_RATE,
0385                         0, CLK_ADC_MAX / osr->osr);
0386 }
0387 
0388 static int nau8540_hw_params(struct snd_pcm_substream *substream,
0389     struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
0390 {
0391     struct snd_soc_component *component = dai->component;
0392     struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
0393     unsigned int val_len = 0;
0394     const struct nau8540_osr_attr *osr;
0395 
0396     /* CLK_ADC = OSR * FS
0397      * ADC clock frequency is defined as Over Sampling Rate (OSR)
0398      * multiplied by the audio sample rate (Fs). Note that the OSR and Fs
0399      * values must be selected such that the maximum frequency is less
0400      * than 6.144 MHz.
0401      */
0402     osr = nau8540_get_osr(nau8540);
0403     if (!osr || !osr->osr)
0404         return -EINVAL;
0405     if (params_rate(params) * osr->osr > CLK_ADC_MAX)
0406         return -EINVAL;
0407     regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
0408         NAU8540_CLK_ADC_SRC_MASK,
0409         osr->clk_src << NAU8540_CLK_ADC_SRC_SFT);
0410 
0411     switch (params_width(params)) {
0412     case 16:
0413         val_len |= NAU8540_I2S_DL_16;
0414         break;
0415     case 20:
0416         val_len |= NAU8540_I2S_DL_20;
0417         break;
0418     case 24:
0419         val_len |= NAU8540_I2S_DL_24;
0420         break;
0421     case 32:
0422         val_len |= NAU8540_I2S_DL_32;
0423         break;
0424     default:
0425         return -EINVAL;
0426     }
0427 
0428     regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0,
0429         NAU8540_I2S_DL_MASK, val_len);
0430 
0431     return 0;
0432 }
0433 
0434 static int nau8540_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
0435 {
0436     struct snd_soc_component *component = dai->component;
0437     struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
0438     unsigned int ctrl1_val = 0, ctrl2_val = 0;
0439 
0440     switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
0441     case SND_SOC_DAIFMT_CBM_CFM:
0442         ctrl2_val |= NAU8540_I2S_MS_MASTER;
0443         break;
0444     case SND_SOC_DAIFMT_CBS_CFS:
0445         break;
0446     default:
0447         return -EINVAL;
0448     }
0449 
0450     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0451     case SND_SOC_DAIFMT_NB_NF:
0452         break;
0453     case SND_SOC_DAIFMT_IB_NF:
0454         ctrl1_val |= NAU8540_I2S_BP_INV;
0455         break;
0456     default:
0457         return -EINVAL;
0458     }
0459 
0460     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0461     case SND_SOC_DAIFMT_I2S:
0462         ctrl1_val |= NAU8540_I2S_DF_I2S;
0463         break;
0464     case SND_SOC_DAIFMT_LEFT_J:
0465         ctrl1_val |= NAU8540_I2S_DF_LEFT;
0466         break;
0467     case SND_SOC_DAIFMT_RIGHT_J:
0468         ctrl1_val |= NAU8540_I2S_DF_RIGTH;
0469         break;
0470     case SND_SOC_DAIFMT_DSP_A:
0471         ctrl1_val |= NAU8540_I2S_DF_PCM_AB;
0472         break;
0473     case SND_SOC_DAIFMT_DSP_B:
0474         ctrl1_val |= NAU8540_I2S_DF_PCM_AB;
0475         ctrl1_val |= NAU8540_I2S_PCMB_EN;
0476         break;
0477     default:
0478         return -EINVAL;
0479     }
0480 
0481     regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0,
0482         NAU8540_I2S_DL_MASK | NAU8540_I2S_DF_MASK |
0483         NAU8540_I2S_BP_INV | NAU8540_I2S_PCMB_EN, ctrl1_val);
0484     regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
0485         NAU8540_I2S_MS_MASK | NAU8540_I2S_DO12_OE, ctrl2_val);
0486     regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
0487         NAU8540_I2S_DO34_OE, 0);
0488 
0489     return 0;
0490 }
0491 
0492 /**
0493  * nau8540_set_tdm_slot - configure DAI TX TDM.
0494  * @dai: DAI
0495  * @tx_mask: bitmask representing active TX slots. Ex.
0496  *                 0xf for normal 4 channel TDM.
0497  *                 0xf0 for shifted 4 channel TDM
0498  * @rx_mask: no used.
0499  * @slots: Number of slots in use.
0500  * @slot_width: Width in bits for each slot.
0501  *
0502  * Configures a DAI for TDM operation. Only support 4 slots TDM.
0503  */
0504 static int nau8540_set_tdm_slot(struct snd_soc_dai *dai,
0505     unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
0506 {
0507     struct snd_soc_component *component = dai->component;
0508     struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
0509     unsigned int ctrl2_val = 0, ctrl4_val = 0;
0510 
0511     if (slots > 4 || ((tx_mask & 0xf0) && (tx_mask & 0xf)))
0512         return -EINVAL;
0513 
0514     ctrl4_val |= (NAU8540_TDM_MODE | NAU8540_TDM_OFFSET_EN);
0515     if (tx_mask & 0xf0) {
0516         ctrl2_val = 4 * slot_width;
0517         ctrl4_val |= (tx_mask >> 4);
0518     } else {
0519         ctrl4_val |= tx_mask;
0520     }
0521     regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL4,
0522         NAU8540_TDM_MODE | NAU8540_TDM_OFFSET_EN |
0523         NAU8540_TDM_TX_MASK, ctrl4_val);
0524     regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
0525         NAU8540_I2S_DO12_OE, NAU8540_I2S_DO12_OE);
0526     regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
0527         NAU8540_I2S_DO34_OE | NAU8540_I2S_TSLOT_L_MASK,
0528         NAU8540_I2S_DO34_OE | ctrl2_val);
0529 
0530     return 0;
0531 }
0532 
0533 
0534 static const struct snd_soc_dai_ops nau8540_dai_ops = {
0535     .startup = nau8540_dai_startup,
0536     .hw_params = nau8540_hw_params,
0537     .set_fmt = nau8540_set_fmt,
0538     .set_tdm_slot = nau8540_set_tdm_slot,
0539 };
0540 
0541 #define NAU8540_RATES SNDRV_PCM_RATE_8000_48000
0542 #define NAU8540_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
0543      | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
0544 
0545 static struct snd_soc_dai_driver nau8540_dai = {
0546     .name = "nau8540-hifi",
0547     .capture = {
0548         .stream_name = "Capture",
0549         .channels_min = 1,
0550         .channels_max = 4,
0551         .rates = NAU8540_RATES,
0552         .formats = NAU8540_FORMATS,
0553     },
0554     .ops = &nau8540_dai_ops,
0555 };
0556 
0557 /**
0558  * nau8540_calc_fll_param - Calculate FLL parameters.
0559  * @fll_in: external clock provided to codec.
0560  * @fs: sampling rate.
0561  * @fll_param: Pointer to structure of FLL parameters.
0562  *
0563  * Calculate FLL parameters to configure codec.
0564  *
0565  * Returns 0 for success or negative error code.
0566  */
0567 static int nau8540_calc_fll_param(unsigned int fll_in,
0568     unsigned int fs, struct nau8540_fll *fll_param)
0569 {
0570     u64 fvco, fvco_max;
0571     unsigned int fref, i, fvco_sel;
0572 
0573     /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing
0574      * freq_in by 1, 2, 4, or 8 using FLL pre-scalar.
0575      * FREF = freq_in / NAU8540_FLL_REF_DIV_MASK
0576      */
0577     for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {
0578         fref = fll_in / fll_pre_scalar[i].param;
0579         if (fref <= NAU_FREF_MAX)
0580             break;
0581     }
0582     if (i == ARRAY_SIZE(fll_pre_scalar))
0583         return -EINVAL;
0584     fll_param->clk_ref_div = fll_pre_scalar[i].val;
0585 
0586     /* Choose the FLL ratio based on FREF */
0587     for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {
0588         if (fref >= fll_ratio[i].param)
0589             break;
0590     }
0591     if (i == ARRAY_SIZE(fll_ratio))
0592         return -EINVAL;
0593     fll_param->ratio = fll_ratio[i].val;
0594 
0595     /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs.
0596      * FDCO must be within the 90MHz - 124MHz or the FFL cannot be
0597      * guaranteed across the full range of operation.
0598      * FDCO = freq_out * 2 * mclk_src_scaling
0599      */
0600     fvco_max = 0;
0601     fvco_sel = ARRAY_SIZE(mclk_src_scaling);
0602     for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {
0603         fvco = 256ULL * fs * 2 * mclk_src_scaling[i].param;
0604         if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX &&
0605             fvco_max < fvco) {
0606             fvco_max = fvco;
0607             fvco_sel = i;
0608         }
0609     }
0610     if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel)
0611         return -EINVAL;
0612     fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;
0613 
0614     /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional
0615      * input based on FDCO, FREF and FLL ratio.
0616      */
0617     fvco = div_u64(fvco_max << 16, fref * fll_param->ratio);
0618     fll_param->fll_int = (fvco >> 16) & 0x3FF;
0619     fll_param->fll_frac = fvco & 0xFFFF;
0620     return 0;
0621 }
0622 
0623 static void nau8540_fll_apply(struct regmap *regmap,
0624     struct nau8540_fll *fll_param)
0625 {
0626     regmap_update_bits(regmap, NAU8540_REG_CLOCK_SRC,
0627         NAU8540_CLK_SRC_MASK | NAU8540_CLK_MCLK_SRC_MASK,
0628         NAU8540_CLK_SRC_MCLK | fll_param->mclk_src);
0629     regmap_update_bits(regmap, NAU8540_REG_FLL1,
0630         NAU8540_FLL_RATIO_MASK | NAU8540_ICTRL_LATCH_MASK,
0631         fll_param->ratio | (0x6 << NAU8540_ICTRL_LATCH_SFT));
0632     /* FLL 16-bit fractional input */
0633     regmap_write(regmap, NAU8540_REG_FLL2, fll_param->fll_frac);
0634     /* FLL 10-bit integer input */
0635     regmap_update_bits(regmap, NAU8540_REG_FLL3,
0636         NAU8540_FLL_INTEGER_MASK, fll_param->fll_int);
0637     /* FLL pre-scaler */
0638     regmap_update_bits(regmap, NAU8540_REG_FLL4,
0639         NAU8540_FLL_REF_DIV_MASK,
0640         fll_param->clk_ref_div << NAU8540_FLL_REF_DIV_SFT);
0641     regmap_update_bits(regmap, NAU8540_REG_FLL5,
0642         NAU8540_FLL_CLK_SW_MASK, NAU8540_FLL_CLK_SW_REF);
0643     regmap_update_bits(regmap,
0644         NAU8540_REG_FLL6, NAU8540_DCO_EN, 0);
0645     if (fll_param->fll_frac) {
0646         regmap_update_bits(regmap, NAU8540_REG_FLL5,
0647             NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN |
0648             NAU8540_FLL_FTR_SW_MASK,
0649             NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN |
0650             NAU8540_FLL_FTR_SW_FILTER);
0651         regmap_update_bits(regmap, NAU8540_REG_FLL6,
0652             NAU8540_SDM_EN | NAU8540_CUTOFF500,
0653             NAU8540_SDM_EN | NAU8540_CUTOFF500);
0654     } else {
0655         regmap_update_bits(regmap, NAU8540_REG_FLL5,
0656             NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN |
0657             NAU8540_FLL_FTR_SW_MASK, NAU8540_FLL_FTR_SW_ACCU);
0658         regmap_update_bits(regmap, NAU8540_REG_FLL6,
0659             NAU8540_SDM_EN | NAU8540_CUTOFF500, 0);
0660     }
0661 }
0662 
0663 /* freq_out must be 256*Fs in order to achieve the best performance */
0664 static int nau8540_set_pll(struct snd_soc_component *component, int pll_id, int source,
0665         unsigned int freq_in, unsigned int freq_out)
0666 {
0667     struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
0668     struct nau8540_fll fll_param;
0669     int ret, fs;
0670 
0671     switch (pll_id) {
0672     case NAU8540_CLK_FLL_MCLK:
0673         regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
0674             NAU8540_FLL_CLK_SRC_MASK | NAU8540_GAIN_ERR_MASK,
0675             NAU8540_FLL_CLK_SRC_MCLK | 0);
0676         break;
0677 
0678     case NAU8540_CLK_FLL_BLK:
0679         regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
0680             NAU8540_FLL_CLK_SRC_MASK | NAU8540_GAIN_ERR_MASK,
0681             NAU8540_FLL_CLK_SRC_BLK |
0682             (0xf << NAU8540_GAIN_ERR_SFT));
0683         break;
0684 
0685     case NAU8540_CLK_FLL_FS:
0686         regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
0687             NAU8540_FLL_CLK_SRC_MASK | NAU8540_GAIN_ERR_MASK,
0688             NAU8540_FLL_CLK_SRC_FS |
0689             (0xf << NAU8540_GAIN_ERR_SFT));
0690         break;
0691 
0692     default:
0693         dev_err(nau8540->dev, "Invalid clock id (%d)\n", pll_id);
0694         return -EINVAL;
0695     }
0696     dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n",
0697         freq_out, pll_id);
0698 
0699     fs = freq_out / 256;
0700     ret = nau8540_calc_fll_param(freq_in, fs, &fll_param);
0701     if (ret < 0) {
0702         dev_err(nau8540->dev, "Unsupported input clock %d\n", freq_in);
0703         return ret;
0704     }
0705     dev_dbg(nau8540->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
0706         fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac,
0707         fll_param.fll_int, fll_param.clk_ref_div);
0708 
0709     nau8540_fll_apply(nau8540->regmap, &fll_param);
0710     mdelay(2);
0711     regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
0712         NAU8540_CLK_SRC_MASK, NAU8540_CLK_SRC_VCO);
0713 
0714     return 0;
0715 }
0716 
0717 static int nau8540_set_sysclk(struct snd_soc_component *component,
0718     int clk_id, int source, unsigned int freq, int dir)
0719 {
0720     struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
0721 
0722     switch (clk_id) {
0723     case NAU8540_CLK_DIS:
0724     case NAU8540_CLK_MCLK:
0725         regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
0726             NAU8540_CLK_SRC_MASK, NAU8540_CLK_SRC_MCLK);
0727         regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6,
0728             NAU8540_DCO_EN, 0);
0729         break;
0730 
0731     case NAU8540_CLK_INTERNAL:
0732         regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6,
0733             NAU8540_DCO_EN, NAU8540_DCO_EN);
0734         regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
0735             NAU8540_CLK_SRC_MASK, NAU8540_CLK_SRC_VCO);
0736         break;
0737 
0738     default:
0739         dev_err(nau8540->dev, "Invalid clock id (%d)\n", clk_id);
0740         return -EINVAL;
0741     }
0742 
0743     dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n",
0744         freq, clk_id);
0745 
0746     return 0;
0747 }
0748 
0749 static void nau8540_reset_chip(struct regmap *regmap)
0750 {
0751     regmap_write(regmap, NAU8540_REG_SW_RESET, 0x00);
0752     regmap_write(regmap, NAU8540_REG_SW_RESET, 0x00);
0753 }
0754 
0755 static void nau8540_init_regs(struct nau8540 *nau8540)
0756 {
0757     struct regmap *regmap = nau8540->regmap;
0758 
0759     /* Enable Bias/VMID/VMID Tieoff */
0760     regmap_update_bits(regmap, NAU8540_REG_VMID_CTRL,
0761         NAU8540_VMID_EN | NAU8540_VMID_SEL_MASK,
0762         NAU8540_VMID_EN | (0x2 << NAU8540_VMID_SEL_SFT));
0763     regmap_update_bits(regmap, NAU8540_REG_REFERENCE,
0764         NAU8540_PRECHARGE_DIS | NAU8540_GLOBAL_BIAS_EN,
0765         NAU8540_PRECHARGE_DIS | NAU8540_GLOBAL_BIAS_EN);
0766     mdelay(2);
0767     regmap_update_bits(regmap, NAU8540_REG_MIC_BIAS,
0768         NAU8540_PU_PRE, NAU8540_PU_PRE);
0769     regmap_update_bits(regmap, NAU8540_REG_CLOCK_CTRL,
0770         NAU8540_CLK_ADC_EN | NAU8540_CLK_I2S_EN,
0771         NAU8540_CLK_ADC_EN | NAU8540_CLK_I2S_EN);
0772     /* ADC OSR selection, CLK_ADC = Fs * OSR;
0773      * Channel time alignment enable.
0774      */
0775     regmap_update_bits(regmap, NAU8540_REG_ADC_SAMPLE_RATE,
0776         NAU8540_CH_SYNC | NAU8540_ADC_OSR_MASK,
0777         NAU8540_CH_SYNC | NAU8540_ADC_OSR_64);
0778     /* PGA input mode selection */
0779     regmap_update_bits(regmap, NAU8540_REG_FEPGA1,
0780         NAU8540_FEPGA1_MODCH2_SHT | NAU8540_FEPGA1_MODCH1_SHT,
0781         NAU8540_FEPGA1_MODCH2_SHT | NAU8540_FEPGA1_MODCH1_SHT);
0782     regmap_update_bits(regmap, NAU8540_REG_FEPGA2,
0783         NAU8540_FEPGA2_MODCH4_SHT | NAU8540_FEPGA2_MODCH3_SHT,
0784         NAU8540_FEPGA2_MODCH4_SHT | NAU8540_FEPGA2_MODCH3_SHT);
0785     /* DO12 and DO34 pad output disable */
0786     regmap_update_bits(regmap, NAU8540_REG_PCM_CTRL1,
0787         NAU8540_I2S_DO12_TRI, NAU8540_I2S_DO12_TRI);
0788     regmap_update_bits(regmap, NAU8540_REG_PCM_CTRL2,
0789         NAU8540_I2S_DO34_TRI, NAU8540_I2S_DO34_TRI);
0790 }
0791 
0792 static int __maybe_unused nau8540_suspend(struct snd_soc_component *component)
0793 {
0794     struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
0795 
0796     regcache_cache_only(nau8540->regmap, true);
0797     regcache_mark_dirty(nau8540->regmap);
0798 
0799     return 0;
0800 }
0801 
0802 static int __maybe_unused nau8540_resume(struct snd_soc_component *component)
0803 {
0804     struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
0805 
0806     regcache_cache_only(nau8540->regmap, false);
0807     regcache_sync(nau8540->regmap);
0808 
0809     return 0;
0810 }
0811 
0812 static const struct snd_soc_component_driver nau8540_component_driver = {
0813     .set_sysclk     = nau8540_set_sysclk,
0814     .set_pll        = nau8540_set_pll,
0815     .suspend        = nau8540_suspend,
0816     .resume         = nau8540_resume,
0817     .controls       = nau8540_snd_controls,
0818     .num_controls       = ARRAY_SIZE(nau8540_snd_controls),
0819     .dapm_widgets       = nau8540_dapm_widgets,
0820     .num_dapm_widgets   = ARRAY_SIZE(nau8540_dapm_widgets),
0821     .dapm_routes        = nau8540_dapm_routes,
0822     .num_dapm_routes    = ARRAY_SIZE(nau8540_dapm_routes),
0823     .suspend_bias_off   = 1,
0824     .idle_bias_on       = 1,
0825     .use_pmdown_time    = 1,
0826     .endianness     = 1,
0827 };
0828 
0829 static const struct regmap_config nau8540_regmap_config = {
0830     .val_bits = 16,
0831     .reg_bits = 16,
0832 
0833     .max_register = NAU8540_REG_MAX,
0834     .readable_reg = nau8540_readable_reg,
0835     .writeable_reg = nau8540_writeable_reg,
0836     .volatile_reg = nau8540_volatile_reg,
0837 
0838     .cache_type = REGCACHE_RBTREE,
0839     .reg_defaults = nau8540_reg_defaults,
0840     .num_reg_defaults = ARRAY_SIZE(nau8540_reg_defaults),
0841 };
0842 
0843 static int nau8540_i2c_probe(struct i2c_client *i2c)
0844 {
0845     struct device *dev = &i2c->dev;
0846     struct nau8540 *nau8540 = dev_get_platdata(dev);
0847     int ret, value;
0848 
0849     if (!nau8540) {
0850         nau8540 = devm_kzalloc(dev, sizeof(*nau8540), GFP_KERNEL);
0851         if (!nau8540)
0852             return -ENOMEM;
0853     }
0854     i2c_set_clientdata(i2c, nau8540);
0855 
0856     nau8540->regmap = devm_regmap_init_i2c(i2c, &nau8540_regmap_config);
0857     if (IS_ERR(nau8540->regmap))
0858         return PTR_ERR(nau8540->regmap);
0859     ret = regmap_read(nau8540->regmap, NAU8540_REG_I2C_DEVICE_ID, &value);
0860     if (ret < 0) {
0861         dev_err(dev, "Failed to read device id from the NAU85L40: %d\n",
0862             ret);
0863         return ret;
0864     }
0865 
0866     nau8540->dev = dev;
0867     nau8540_reset_chip(nau8540->regmap);
0868     nau8540_init_regs(nau8540);
0869 
0870     return devm_snd_soc_register_component(dev,
0871         &nau8540_component_driver, &nau8540_dai, 1);
0872 }
0873 
0874 static const struct i2c_device_id nau8540_i2c_ids[] = {
0875     { "nau8540", 0 },
0876     { }
0877 };
0878 MODULE_DEVICE_TABLE(i2c, nau8540_i2c_ids);
0879 
0880 #ifdef CONFIG_OF
0881 static const struct of_device_id nau8540_of_ids[] = {
0882     { .compatible = "nuvoton,nau8540", },
0883     {}
0884 };
0885 MODULE_DEVICE_TABLE(of, nau8540_of_ids);
0886 #endif
0887 
0888 static struct i2c_driver nau8540_i2c_driver = {
0889     .driver = {
0890         .name = "nau8540",
0891         .of_match_table = of_match_ptr(nau8540_of_ids),
0892     },
0893     .probe_new = nau8540_i2c_probe,
0894     .id_table = nau8540_i2c_ids,
0895 };
0896 module_i2c_driver(nau8540_i2c_driver);
0897 
0898 MODULE_DESCRIPTION("ASoC NAU85L40 driver");
0899 MODULE_AUTHOR("John Hsu <KCHSU0@nuvoton.com>");
0900 MODULE_LICENSE("GPL v2");
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