soc/codecs/mt6660.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2019 MediaTek Inc.
0004  */
0005
0006 #ifndef __SND_SOC_MT6660_H
0007 #define __SND_SOC_MT6660_H
0008
0009 #include <linux/mutex.h>
0010 #include <linux/regmap.h>
0011
0012 #pragma pack(push, 1)
0013 struct mt6660_platform_data {
0014     u8 init_setting_num;
0015     u32 *init_setting_addr;
0016     u32 *init_setting_mask;
0017     u32 *init_setting_val;
0018 };
0019
0020 struct mt6660_chip {
0021     struct i2c_client *i2c;
0022     struct device *dev;
0023     struct platform_device *param_dev;
0024     struct mt6660_platform_data plat_data;
0025     struct mutex io_lock;
0026     struct regmap *regmap;
0027     u16 chip_rev;
0028 };
0029 #pragma pack(pop)
0030
0031 #define MT6660_REG_DEVID        (0x00)
0032 #define MT6660_REG_SYSTEM_CTRL      (0x03)
0033 #define MT6660_REG_IRQ_STATUS1      (0x05)
0034 #define MT6660_REG_ADDA_CLOCK       (0x07)
0035 #define MT6660_REG_SERIAL_CFG1      (0x10)
0036 #define MT6660_REG_DATAO_SEL        (0x12)
0037 #define MT6660_REG_TDM_CFG3     (0x15)
0038 #define MT6660_REG_HPF_CTRL     (0x18)
0039 #define MT6660_REG_HPF1_COEF        (0x1A)
0040 #define MT6660_REG_HPF2_COEF        (0x1B)
0041 #define MT6660_REG_PATH_BYPASS      (0x1E)
0042 #define MT6660_REG_WDT_CTRL     (0x20)
0043 #define MT6660_REG_HCLIP_CTRL       (0x24)
0044 #define MT6660_REG_VOL_CTRL     (0x29)
0045 #define MT6660_REG_SPS_CTRL     (0x30)
0046 #define MT6660_REG_SIGMAX       (0x33)
0047 #define MT6660_REG_CALI_T0      (0x3F)
0048 #define MT6660_REG_BST_CTRL     (0x40)
0049 #define MT6660_REG_PROTECTION_CFG   (0x46)
0050 #define MT6660_REG_DA_GAIN      (0x4c)
0051 #define MT6660_REG_AUDIO_IN2_SEL    (0x50)
0052 #define MT6660_REG_SIG_GAIN     (0x51)
0053 #define MT6660_REG_PLL_CFG1     (0x60)
0054 #define MT6660_REG_DRE_CTRL     (0x68)
0055 #define MT6660_REG_DRE_THDMODE      (0x69)
0056 #define MT6660_REG_DRE_CORASE       (0x6B)
0057 #define MT6660_REG_PWM_CTRL     (0x70)
0058 #define MT6660_REG_DC_PROTECT_CTRL  (0x74)
0059 #define MT6660_REG_ADC_USB_MODE     (0x7c)
0060 #define MT6660_REG_INTERNAL_CFG     (0x88)
0061 #define MT6660_REG_RESV0        (0x98)
0062 #define MT6660_REG_RESV1        (0x99)
0063 #define MT6660_REG_RESV2        (0x9A)
0064 #define MT6660_REG_RESV3        (0x9B)
0065 #define MT6660_REG_RESV6        (0xA2)
0066 #define MT6660_REG_RESV7        (0xA3)
0067 #define MT6660_REG_RESV10       (0xB0)
0068 #define MT6660_REG_RESV11       (0xB1)
0069 #define MT6660_REG_RESV16       (0xB6)
0070 #define MT6660_REG_RESV17       (0xB7)
0071 #define MT6660_REG_RESV19       (0xB9)
0072 #define MT6660_REG_RESV21       (0xBB)
0073 #define MT6660_REG_RESV23       (0xBD)
0074 #define MT6660_REG_RESV31       (0xD3)
0075 #define MT6660_REG_RESV40       (0xE0)
0076
0077 #endif /* __SND_SOC_MT6660_H */