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0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // mt6359-accdet.c  --  ALSA SoC mt6359 accdet driver
0004 //
0005 // Copyright (C) 2021 MediaTek Inc.
0006 // Author: Argus Lin <argus.lin@mediatek.com>
0007 //
0008 
0009 #include <linux/of_gpio.h>
0010 #include <linux/of.h>
0011 #include <linux/of_irq.h>
0012 #include <linux/of_device.h>
0013 #include <linux/of_address.h>
0014 #include <linux/input.h>
0015 #include <linux/kthread.h>
0016 #include <linux/io.h>
0017 #include <linux/sched/clock.h>
0018 #include <linux/workqueue.h>
0019 #include <linux/timer.h>
0020 #include <linux/delay.h>
0021 #include <linux/module.h>
0022 #include <linux/platform_device.h>
0023 #include <linux/init.h>
0024 #include <linux/irqdomain.h>
0025 #include <linux/irq.h>
0026 #include <linux/regmap.h>
0027 #include <sound/soc.h>
0028 #include <sound/jack.h>
0029 #include <linux/mfd/mt6397/core.h>
0030 
0031 #include "mt6359-accdet.h"
0032 #include "mt6359.h"
0033 
0034 /* global variable definitions */
0035 #define REGISTER_VAL(x) ((x) - 1)
0036 
0037 /* mt6359 accdet capability */
0038 #define ACCDET_PMIC_EINT_IRQ        BIT(0)
0039 #define ACCDET_AP_GPIO_EINT     BIT(1)
0040 
0041 #define ACCDET_PMIC_EINT0       BIT(2)
0042 #define ACCDET_PMIC_EINT1       BIT(3)
0043 #define ACCDET_PMIC_BI_EINT     BIT(4)
0044 
0045 #define ACCDET_PMIC_GPIO_TRIG_EINT  BIT(5)
0046 #define ACCDET_PMIC_INVERTER_TRIG_EINT  BIT(6)
0047 #define ACCDET_PMIC_RSV_EINT        BIT(7)
0048 
0049 #define ACCDET_THREE_KEY        BIT(8)
0050 #define ACCDET_FOUR_KEY         BIT(9)
0051 #define ACCDET_TRI_KEY_CDD      BIT(10)
0052 #define ACCDET_RSV_KEY          BIT(11)
0053 
0054 #define ACCDET_ANALOG_FASTDISCHARGE BIT(12)
0055 #define ACCDET_DIGITAL_FASTDISCHARGE    BIT(13)
0056 #define ACCDET_AD_FASTDISCHRAGE     BIT(14)
0057 
0058 static struct platform_driver mt6359_accdet_driver;
0059 static const struct snd_soc_component_driver mt6359_accdet_soc_driver;
0060 
0061 /* local function declaration */
0062 static void accdet_set_debounce(struct mt6359_accdet *priv, int state,
0063                 unsigned int debounce);
0064 static unsigned int adjust_eint_analog_setting(struct mt6359_accdet *priv);
0065 static void config_digital_init_by_mode(struct mt6359_accdet *priv);
0066 static void config_eint_init_by_mode(struct mt6359_accdet *priv);
0067 static inline void mt6359_accdet_init(struct mt6359_accdet *priv);
0068 static unsigned int mt6359_accdet_jd_setting(struct mt6359_accdet *priv);
0069 static void mt6359_accdet_recover_jd_setting(struct mt6359_accdet *priv);
0070 static void mt6359_accdet_jack_report(struct mt6359_accdet *priv);
0071 static void recover_eint_analog_setting(struct mt6359_accdet *priv);
0072 static void recover_eint_digital_setting(struct mt6359_accdet *priv);
0073 static void recover_eint_setting(struct mt6359_accdet *priv);
0074 
0075 static unsigned int adjust_eint_analog_setting(struct mt6359_accdet *priv)
0076 {
0077     if (priv->data->eint_detect_mode == 0x3 ||
0078         priv->data->eint_detect_mode == 0x4) {
0079         /* ESD switches off */
0080         regmap_update_bits(priv->regmap,
0081                    RG_ACCDETSPARE_ADDR, 1 << 8, 0);
0082     }
0083     if (priv->data->eint_detect_mode == 0x4) {
0084         if (priv->caps & ACCDET_PMIC_EINT0) {
0085             /* enable RG_EINT0CONFIGACCDET */
0086             regmap_update_bits(priv->regmap,
0087                        RG_EINT0CONFIGACCDET_ADDR,
0088                        RG_EINT0CONFIGACCDET_MASK_SFT,
0089                        BIT(RG_EINT0CONFIGACCDET_SFT));
0090         } else if (priv->caps & ACCDET_PMIC_EINT1) {
0091             /* enable RG_EINT1CONFIGACCDET */
0092             regmap_update_bits(priv->regmap,
0093                        RG_EINT1CONFIGACCDET_ADDR,
0094                        RG_EINT1CONFIGACCDET_MASK_SFT,
0095                        BIT(RG_EINT1CONFIGACCDET_SFT));
0096         }
0097         if (priv->data->eint_use_ext_res == 0x3 ||
0098             priv->data->eint_use_ext_res == 0x4) {
0099             /*select 500k, use internal resistor */
0100             regmap_update_bits(priv->regmap,
0101                        RG_EINT0HIRENB_ADDR,
0102                        RG_EINT0HIRENB_MASK_SFT,
0103                        BIT(RG_EINT0HIRENB_SFT));
0104         }
0105     }
0106     return 0;
0107 }
0108 
0109 static unsigned int adjust_eint_digital_setting(struct mt6359_accdet *priv)
0110 {
0111     if (priv->caps & ACCDET_PMIC_EINT0) {
0112         /* disable inverter */
0113         regmap_update_bits(priv->regmap,
0114                    ACCDET_EINT0_INVERTER_SW_EN_ADDR,
0115                    ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT, 0);
0116     } else if (priv->caps & ACCDET_PMIC_EINT1) {
0117         /* disable inverter */
0118         regmap_update_bits(priv->regmap,
0119                    ACCDET_EINT1_INVERTER_SW_EN_ADDR,
0120                    ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT, 0);
0121     }
0122 
0123     if (priv->data->eint_detect_mode == 0x4) {
0124         if (priv->caps & ACCDET_PMIC_EINT0) {
0125             /* set DA stable signal */
0126             regmap_update_bits(priv->regmap,
0127                        ACCDET_DA_STABLE_ADDR,
0128                        ACCDET_EINT0_CEN_STABLE_MASK_SFT, 0);
0129         } else if (priv->caps & ACCDET_PMIC_EINT1) {
0130             /* set DA stable signal */
0131             regmap_update_bits(priv->regmap,
0132                        ACCDET_DA_STABLE_ADDR,
0133                        ACCDET_EINT1_CEN_STABLE_MASK_SFT, 0);
0134         }
0135     }
0136     return 0;
0137 }
0138 
0139 static unsigned int mt6359_accdet_jd_setting(struct mt6359_accdet *priv)
0140 {
0141     if (priv->jd_sts == M_PLUG_IN) {
0142         /* adjust digital setting */
0143         adjust_eint_digital_setting(priv);
0144         /* adjust analog setting */
0145         adjust_eint_analog_setting(priv);
0146     } else if (priv->jd_sts == M_PLUG_OUT) {
0147         /* set debounce to 1ms */
0148         accdet_set_debounce(priv, eint_state000,
0149                     priv->data->pwm_deb->eint_debounce0);
0150     } else {
0151         dev_dbg(priv->dev, "should not be here %s()\n", __func__);
0152     }
0153 
0154     return 0;
0155 }
0156 
0157 static void recover_eint_analog_setting(struct mt6359_accdet *priv)
0158 {
0159     if (priv->data->eint_detect_mode == 0x3 ||
0160         priv->data->eint_detect_mode == 0x4) {
0161         /* ESD switches on */
0162         regmap_update_bits(priv->regmap, RG_ACCDETSPARE_ADDR,
0163                    1 << 8, 1 << 8);
0164     }
0165     if (priv->data->eint_detect_mode == 0x4) {
0166         if (priv->caps & ACCDET_PMIC_EINT0) {
0167             /* disable RG_EINT0CONFIGACCDET */
0168             regmap_update_bits(priv->regmap,
0169                        RG_EINT0CONFIGACCDET_ADDR,
0170                        RG_EINT0CONFIGACCDET_MASK_SFT, 0);
0171         } else if (priv->caps & ACCDET_PMIC_EINT1) {
0172             /* disable RG_EINT1CONFIGACCDET */
0173             regmap_update_bits(priv->regmap,
0174                        RG_EINT1CONFIGACCDET_ADDR,
0175                        RG_EINT1CONFIGACCDET_MASK_SFT, 0);
0176         }
0177         regmap_update_bits(priv->regmap, RG_EINT0HIRENB_ADDR,
0178                    RG_EINT0HIRENB_MASK_SFT, 0);
0179     }
0180 }
0181 
0182 static void recover_eint_digital_setting(struct mt6359_accdet *priv)
0183 {
0184     if (priv->caps & ACCDET_PMIC_EINT0) {
0185         regmap_update_bits(priv->regmap,
0186                    ACCDET_EINT0_M_SW_EN_ADDR,
0187                    ACCDET_EINT0_M_SW_EN_MASK_SFT, 0);
0188     } else if (priv->caps & ACCDET_PMIC_EINT1) {
0189         regmap_update_bits(priv->regmap,
0190                    ACCDET_EINT1_M_SW_EN_ADDR,
0191                    ACCDET_EINT1_M_SW_EN_MASK_SFT, 0);
0192     }
0193     if (priv->data->eint_detect_mode == 0x4) {
0194         /* enable eint0cen */
0195         if (priv->caps & ACCDET_PMIC_EINT0) {
0196             /* enable eint0cen */
0197             regmap_update_bits(priv->regmap,
0198                        ACCDET_DA_STABLE_ADDR,
0199                        ACCDET_EINT0_CEN_STABLE_MASK_SFT,
0200                        BIT(ACCDET_EINT0_CEN_STABLE_SFT));
0201         } else if (priv->caps & ACCDET_PMIC_EINT1) {
0202             /* enable eint1cen */
0203             regmap_update_bits(priv->regmap,
0204                        ACCDET_DA_STABLE_ADDR,
0205                        ACCDET_EINT1_CEN_STABLE_MASK_SFT,
0206                        BIT(ACCDET_EINT1_CEN_STABLE_SFT));
0207         }
0208     }
0209 
0210     if (priv->data->eint_detect_mode != 0x1) {
0211         if (priv->caps & ACCDET_PMIC_EINT0) {
0212             /* enable inverter */
0213             regmap_update_bits(priv->regmap,
0214                        ACCDET_EINT0_INVERTER_SW_EN_ADDR,
0215                        ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT,
0216                        BIT(ACCDET_EINT0_INVERTER_SW_EN_SFT));
0217         } else if (priv->caps & ACCDET_PMIC_EINT1) {
0218             /* enable inverter */
0219             regmap_update_bits(priv->regmap,
0220                        ACCDET_EINT1_INVERTER_SW_EN_ADDR,
0221                        ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT,
0222                        BIT(ACCDET_EINT1_INVERTER_SW_EN_SFT));
0223         }
0224     }
0225 }
0226 
0227 static void recover_eint_setting(struct mt6359_accdet *priv)
0228 {
0229     if (priv->jd_sts == M_PLUG_OUT) {
0230         recover_eint_analog_setting(priv);
0231         recover_eint_digital_setting(priv);
0232     }
0233 }
0234 
0235 static void mt6359_accdet_recover_jd_setting(struct mt6359_accdet *priv)
0236 {
0237     int ret;
0238     unsigned int value = 0;
0239 
0240     regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR,
0241                ACCDET_IRQ_CLR_MASK_SFT, BIT(ACCDET_IRQ_CLR_SFT));
0242     usleep_range(200, 300);
0243     ret = regmap_read_poll_timeout(priv->regmap,
0244                        ACCDET_IRQ_ADDR,
0245                        value,
0246                        (value & ACCDET_IRQ_MASK_SFT) == 0,
0247                        0,
0248                        1000);
0249     if (ret)
0250         dev_warn(priv->dev, "%s(), ret %d\n", __func__, ret);
0251     /* clear accdet int, modify  for fix interrupt trigger twice error */
0252     regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR,
0253                ACCDET_IRQ_CLR_MASK_SFT, 0);
0254     regmap_update_bits(priv->regmap, RG_INT_STATUS_ACCDET_ADDR,
0255                RG_INT_STATUS_ACCDET_MASK_SFT,
0256                BIT(RG_INT_STATUS_ACCDET_SFT));
0257 
0258     /* recover accdet debounce0,3 */
0259     accdet_set_debounce(priv, accdet_state000,
0260                 priv->data->pwm_deb->debounce0);
0261     accdet_set_debounce(priv, accdet_state001,
0262                 priv->data->pwm_deb->debounce1);
0263     accdet_set_debounce(priv, accdet_state011,
0264                 priv->data->pwm_deb->debounce3);
0265 
0266     priv->jack_type = 0;
0267     priv->btn_type = 0;
0268     priv->accdet_status = 0x3;
0269     mt6359_accdet_jack_report(priv);
0270 }
0271 
0272 static void accdet_set_debounce(struct mt6359_accdet *priv, int state,
0273                 unsigned int debounce)
0274 {
0275     switch (state) {
0276     case accdet_state000:
0277         regmap_write(priv->regmap, ACCDET_DEBOUNCE0_ADDR, debounce);
0278         break;
0279     case accdet_state001:
0280         regmap_write(priv->regmap, ACCDET_DEBOUNCE1_ADDR, debounce);
0281         break;
0282     case accdet_state010:
0283         regmap_write(priv->regmap, ACCDET_DEBOUNCE2_ADDR, debounce);
0284         break;
0285     case accdet_state011:
0286         regmap_write(priv->regmap, ACCDET_DEBOUNCE3_ADDR, debounce);
0287         break;
0288     case accdet_auxadc:
0289         regmap_write(priv->regmap,
0290                  ACCDET_CONNECT_AUXADC_TIME_DIG_ADDR, debounce);
0291         break;
0292     case eint_state000:
0293         regmap_update_bits(priv->regmap, ACCDET_EINT_DEBOUNCE0_ADDR,
0294                    0xF << ACCDET_EINT_DEBOUNCE0_SFT,
0295                    debounce << ACCDET_EINT_DEBOUNCE0_SFT);
0296         break;
0297     case eint_state001:
0298         regmap_update_bits(priv->regmap, ACCDET_EINT_DEBOUNCE1_ADDR,
0299                    0xF << ACCDET_EINT_DEBOUNCE1_SFT,
0300                    debounce << ACCDET_EINT_DEBOUNCE1_SFT);
0301         break;
0302     case eint_state010:
0303         regmap_update_bits(priv->regmap, ACCDET_EINT_DEBOUNCE2_ADDR,
0304                    0xF << ACCDET_EINT_DEBOUNCE2_SFT,
0305                    debounce << ACCDET_EINT_DEBOUNCE2_SFT);
0306         break;
0307     case eint_state011:
0308         regmap_update_bits(priv->regmap, ACCDET_EINT_DEBOUNCE3_ADDR,
0309                    0xF << ACCDET_EINT_DEBOUNCE3_SFT,
0310                    debounce << ACCDET_EINT_DEBOUNCE3_SFT);
0311         break;
0312     case eint_inverter_state000:
0313         regmap_write(priv->regmap, ACCDET_EINT_INVERTER_DEBOUNCE_ADDR,
0314                  debounce);
0315         break;
0316     default:
0317         dev_warn(priv->dev, "Error: %s error state (%d)\n", __func__,
0318              state);
0319         break;
0320     }
0321 }
0322 
0323 static void mt6359_accdet_jack_report(struct mt6359_accdet *priv)
0324 {
0325     int report = 0;
0326 
0327     if (!priv->jack)
0328         return;
0329 
0330     report = priv->jack_type | priv->btn_type;
0331     snd_soc_jack_report(priv->jack, report, MT6359_ACCDET_JACK_MASK);
0332 }
0333 
0334 static unsigned int check_button(struct mt6359_accdet *priv, unsigned int v)
0335 {
0336     if (priv->caps & ACCDET_FOUR_KEY) {
0337         if (v < priv->data->four_key.down &&
0338             v >= priv->data->four_key.up)
0339             priv->btn_type = SND_JACK_BTN_1;
0340         if (v < priv->data->four_key.up &&
0341             v >= priv->data->four_key.voice)
0342             priv->btn_type = SND_JACK_BTN_2;
0343         if (v < priv->data->four_key.voice &&
0344             v >= priv->data->four_key.mid)
0345             priv->btn_type = SND_JACK_BTN_3;
0346         if (v < priv->data->four_key.mid)
0347             priv->btn_type = SND_JACK_BTN_0;
0348     } else {
0349         if (v < priv->data->three_key.down &&
0350             v >= priv->data->three_key.up)
0351             priv->btn_type = SND_JACK_BTN_1;
0352         if (v < priv->data->three_key.up &&
0353             v >= priv->data->three_key.mid)
0354             priv->btn_type = SND_JACK_BTN_2;
0355         if (v < priv->data->three_key.mid)
0356             priv->btn_type = SND_JACK_BTN_0;
0357     }
0358     return 0;
0359 }
0360 
0361 static void is_key_pressed(struct mt6359_accdet *priv, bool pressed)
0362 {
0363     priv->btn_type = priv->jack_type & ~MT6359_ACCDET_BTN_MASK;
0364 
0365     if (pressed)
0366         check_button(priv, priv->cali_voltage);
0367 }
0368 
0369 static inline void check_jack_btn_type(struct mt6359_accdet *priv)
0370 {
0371     unsigned int val = 0;
0372 
0373     regmap_read(priv->regmap, ACCDET_MEM_IN_ADDR, &val);
0374 
0375     priv->accdet_status =
0376         (val >> ACCDET_STATE_MEM_IN_OFFSET) & ACCDET_STATE_AB_MASK;
0377 
0378     switch (priv->accdet_status) {
0379     case 0:
0380         if (priv->jack_type == SND_JACK_HEADSET)
0381             is_key_pressed(priv, true);
0382         else
0383             priv->jack_type = SND_JACK_HEADPHONE;
0384         break;
0385     case 1:
0386         if (priv->jack_type == SND_JACK_HEADSET) {
0387             is_key_pressed(priv, false);
0388         } else {
0389             priv->jack_type = SND_JACK_HEADSET;
0390             accdet_set_debounce(priv, eint_state011, 0x1);
0391         }
0392         break;
0393     case 3:
0394     default:
0395         priv->jack_type = 0;
0396         break;
0397     }
0398 }
0399 
0400 static void mt6359_accdet_work(struct work_struct *work)
0401 {
0402     struct mt6359_accdet *priv =
0403         container_of(work, struct mt6359_accdet, accdet_work);
0404 
0405     mutex_lock(&priv->res_lock);
0406     priv->pre_accdet_status = priv->accdet_status;
0407     check_jack_btn_type(priv);
0408 
0409     if (priv->jack_plugged &&
0410         priv->pre_accdet_status != priv->accdet_status)
0411         mt6359_accdet_jack_report(priv);
0412     mutex_unlock(&priv->res_lock);
0413 }
0414 
0415 static void mt6359_accdet_jd_work(struct work_struct *work)
0416 {
0417     int ret;
0418     unsigned int value = 0;
0419 
0420     struct mt6359_accdet *priv =
0421         container_of(work, struct mt6359_accdet, jd_work);
0422 
0423     mutex_lock(&priv->res_lock);
0424     if (priv->jd_sts == M_PLUG_IN) {
0425         priv->jack_plugged = true;
0426 
0427         /* set and clear initial bit every eint interrupt */
0428         regmap_update_bits(priv->regmap, ACCDET_SEQ_INIT_ADDR,
0429                    ACCDET_SEQ_INIT_MASK_SFT,
0430                    BIT(ACCDET_SEQ_INIT_SFT));
0431         regmap_update_bits(priv->regmap, ACCDET_SEQ_INIT_ADDR,
0432                    ACCDET_SEQ_INIT_MASK_SFT, 0);
0433         ret = regmap_read_poll_timeout(priv->regmap,
0434                            ACCDET_SEQ_INIT_ADDR,
0435                            value,
0436                            (value & ACCDET_SEQ_INIT_MASK_SFT) == 0,
0437                            0,
0438                            1000);
0439         if (ret)
0440             dev_err(priv->dev, "%s(), ret %d\n", __func__, ret);
0441 
0442         /* enable ACCDET unit */
0443         regmap_update_bits(priv->regmap, ACCDET_SW_EN_ADDR,
0444                    ACCDET_SW_EN_MASK_SFT, BIT(ACCDET_SW_EN_SFT));
0445     } else if (priv->jd_sts == M_PLUG_OUT) {
0446         priv->jack_plugged = false;
0447 
0448         accdet_set_debounce(priv, accdet_state011,
0449                     priv->data->pwm_deb->debounce3);
0450         regmap_update_bits(priv->regmap, ACCDET_SW_EN_ADDR,
0451                    ACCDET_SW_EN_MASK_SFT, 0);
0452         mt6359_accdet_recover_jd_setting(priv);
0453     }
0454 
0455     if (priv->caps & ACCDET_PMIC_EINT_IRQ)
0456         recover_eint_setting(priv);
0457     mutex_unlock(&priv->res_lock);
0458 }
0459 
0460 static irqreturn_t mt6359_accdet_irq(int irq, void *data)
0461 {
0462     struct mt6359_accdet *priv = data;
0463     unsigned int irq_val = 0, val = 0, value = 0;
0464     int ret;
0465 
0466     mutex_lock(&priv->res_lock);
0467     regmap_read(priv->regmap, ACCDET_IRQ_ADDR, &irq_val);
0468 
0469     if (irq_val & ACCDET_IRQ_MASK_SFT) {
0470         regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR,
0471                    ACCDET_IRQ_CLR_MASK_SFT,
0472                    BIT(ACCDET_IRQ_CLR_SFT));
0473         ret = regmap_read_poll_timeout(priv->regmap,
0474                            ACCDET_IRQ_ADDR,
0475                            value,
0476                            (value & ACCDET_IRQ_MASK_SFT) == 0,
0477                            0,
0478                            1000);
0479         if (ret) {
0480             dev_err(priv->dev, "%s(), ret %d\n", __func__, ret);
0481             mutex_unlock(&priv->res_lock);
0482             return IRQ_NONE;
0483         }
0484         regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR,
0485                    ACCDET_IRQ_CLR_MASK_SFT, 0);
0486         regmap_update_bits(priv->regmap, RG_INT_STATUS_ACCDET_ADDR,
0487                    RG_INT_STATUS_ACCDET_MASK_SFT,
0488                    BIT(RG_INT_STATUS_ACCDET_SFT));
0489 
0490         queue_work(priv->accdet_workqueue, &priv->accdet_work);
0491     } else {
0492         if (irq_val & ACCDET_EINT0_IRQ_MASK_SFT) {
0493             regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR,
0494                        ACCDET_EINT0_IRQ_CLR_MASK_SFT,
0495                        BIT(ACCDET_EINT0_IRQ_CLR_SFT));
0496             ret = regmap_read_poll_timeout(priv->regmap,
0497                                ACCDET_IRQ_ADDR,
0498                                value,
0499                                (value & ACCDET_EINT0_IRQ_MASK_SFT) == 0,
0500                                0,
0501                                1000);
0502             if (ret) {
0503                 dev_err(priv->dev, "%s(), ret %d\n", __func__,
0504                     ret);
0505                 mutex_unlock(&priv->res_lock);
0506                 return IRQ_NONE;
0507             }
0508             regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR,
0509                        ACCDET_EINT0_IRQ_CLR_MASK_SFT, 0);
0510             regmap_update_bits(priv->regmap,
0511                        RG_INT_STATUS_ACCDET_ADDR,
0512                        RG_INT_STATUS_ACCDET_EINT0_MASK_SFT,
0513                        BIT(RG_INT_STATUS_ACCDET_EINT0_SFT));
0514         }
0515         if (irq_val & ACCDET_EINT1_IRQ_MASK_SFT) {
0516             regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR,
0517                        ACCDET_EINT1_IRQ_CLR_MASK_SFT,
0518                        BIT(ACCDET_EINT1_IRQ_CLR_SFT));
0519             ret = regmap_read_poll_timeout(priv->regmap,
0520                                ACCDET_IRQ_ADDR,
0521                                value,
0522                                (value & ACCDET_EINT1_IRQ_MASK_SFT) == 0,
0523                                0,
0524                                1000);
0525             if (ret) {
0526                 dev_err(priv->dev, "%s(), ret %d\n", __func__,
0527                     ret);
0528                 mutex_unlock(&priv->res_lock);
0529                 return IRQ_NONE;
0530             }
0531             regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR,
0532                        ACCDET_EINT1_IRQ_CLR_MASK_SFT, 0);
0533             regmap_update_bits(priv->regmap,
0534                        RG_INT_STATUS_ACCDET_ADDR,
0535                        RG_INT_STATUS_ACCDET_EINT1_MASK_SFT,
0536                        BIT(RG_INT_STATUS_ACCDET_EINT1_SFT));
0537         }
0538         /* get jack detection status */
0539         regmap_read(priv->regmap, ACCDET_EINT0_MEM_IN_ADDR, &val);
0540         priv->jd_sts = ((val >> ACCDET_EINT0_MEM_IN_SFT) &
0541                    ACCDET_EINT0_MEM_IN_MASK);
0542         /* adjust eint digital/analog setting */
0543         mt6359_accdet_jd_setting(priv);
0544 
0545         queue_work(priv->jd_workqueue, &priv->jd_work);
0546     }
0547     mutex_unlock(&priv->res_lock);
0548 
0549     return IRQ_HANDLED;
0550 }
0551 
0552 static int mt6359_accdet_parse_dt(struct mt6359_accdet *priv)
0553 {
0554     int ret;
0555     struct device *dev = priv->dev;
0556     struct device_node *node = NULL;
0557     int pwm_deb[15] = {0};
0558     unsigned int tmp = 0;
0559 
0560     node = of_get_child_by_name(dev->parent->of_node, "accdet");
0561     if (!node)
0562         return -EINVAL;
0563 
0564     ret = of_property_read_u32(node, "mediatek,mic-vol",
0565                    &priv->data->mic_vol);
0566     if (ret)
0567         priv->data->mic_vol = 8;
0568 
0569     ret = of_property_read_u32(node, "mediatek,plugout-debounce",
0570                    &priv->data->plugout_deb);
0571     if (ret)
0572         priv->data->plugout_deb = 1;
0573 
0574     ret = of_property_read_u32(node, "mediatek,mic-mode",
0575                    &priv->data->mic_mode);
0576     if (ret)
0577         priv->data->mic_mode = 2;
0578 
0579     ret = of_property_read_u32_array(node, "mediatek,pwm-deb-setting",
0580                      pwm_deb, ARRAY_SIZE(pwm_deb));
0581     /* debounce8(auxadc debounce) is default, needn't get from dts */
0582     if (!ret)
0583         memcpy(priv->data->pwm_deb, pwm_deb, sizeof(pwm_deb));
0584 
0585     ret = of_property_read_u32(node, "mediatek,eint-level-pol",
0586                    &priv->data->eint_pol);
0587     if (ret)
0588         priv->data->eint_pol = 8;
0589 
0590     ret = of_property_read_u32(node, "mediatek,eint-use-ap", &tmp);
0591     if (ret)
0592         tmp = 0;
0593     if (tmp == 0)
0594         priv->caps |= ACCDET_PMIC_EINT_IRQ;
0595     else if (tmp == 1)
0596         priv->caps |= ACCDET_AP_GPIO_EINT;
0597 
0598     ret = of_property_read_u32(node, "mediatek,eint-detect-mode",
0599                    &priv->data->eint_detect_mode);
0600     if (ret) {
0601         /* eint detection mode equals to EINT HW Mode */
0602         priv->data->eint_detect_mode = 0x4;
0603     }
0604 
0605     ret = of_property_read_u32(node, "mediatek,eint-num", &tmp);
0606     if (ret)
0607         tmp = 0;
0608     if (tmp == 0)
0609         priv->caps |= ACCDET_PMIC_EINT0;
0610     else if (tmp == 1)
0611         priv->caps |= ACCDET_PMIC_EINT1;
0612     else if (tmp == 2)
0613         priv->caps |= ACCDET_PMIC_BI_EINT;
0614 
0615     ret = of_property_read_u32(node, "mediatek,eint-trig-mode",
0616                    &tmp);
0617     if (ret)
0618         tmp = 0;
0619     if (tmp == 0)
0620         priv->caps |= ACCDET_PMIC_GPIO_TRIG_EINT;
0621     else if (tmp == 1)
0622         priv->caps |= ACCDET_PMIC_INVERTER_TRIG_EINT;
0623 
0624     ret = of_property_read_u32(node, "mediatek,eint-use-ext-res",
0625                    &priv->data->eint_use_ext_res);
0626     if (ret) {
0627         /* eint use internal resister */
0628         priv->data->eint_use_ext_res = 0x0;
0629     }
0630 
0631     ret = of_property_read_u32(node, "mediatek,eint-comp-vth",
0632                    &priv->data->eint_comp_vth);
0633     if (ret)
0634         priv->data->eint_comp_vth = 0x0;
0635 
0636     ret = of_property_read_u32(node, "mediatek,key-mode", &tmp);
0637     if (ret)
0638         tmp = 0;
0639     if (tmp == 0) {
0640         int three_key[4];
0641 
0642         priv->caps |= ACCDET_THREE_KEY;
0643         ret = of_property_read_u32_array(node,
0644                          "mediatek,three-key-thr",
0645                          three_key,
0646                          ARRAY_SIZE(three_key));
0647         if (!ret)
0648             memcpy(&priv->data->three_key, three_key + 1,
0649                    sizeof(struct three_key_threshold));
0650     } else if (tmp == 1) {
0651         int four_key[5];
0652 
0653         priv->caps |= ACCDET_FOUR_KEY;
0654         ret = of_property_read_u32_array(node,
0655                          "mediatek,four-key-thr",
0656                          four_key,
0657                          ARRAY_SIZE(four_key));
0658         if (!ret) {
0659             memcpy(&priv->data->four_key, four_key + 1,
0660                    sizeof(struct four_key_threshold));
0661         } else {
0662             dev_warn(priv->dev,
0663                  "accdet no 4-key-thrsh dts, use efuse\n");
0664         }
0665     } else if (tmp == 2) {
0666         int three_key[4];
0667 
0668         priv->caps |= ACCDET_TRI_KEY_CDD;
0669         ret = of_property_read_u32_array(node,
0670                          "mediatek,tri-key-cdd-thr",
0671                          three_key,
0672                          ARRAY_SIZE(three_key));
0673         if (!ret)
0674             memcpy(&priv->data->three_key, three_key + 1,
0675                    sizeof(struct three_key_threshold));
0676     }
0677 
0678     of_node_put(node);
0679     dev_warn(priv->dev, "accdet caps=%x\n", priv->caps);
0680 
0681     return 0;
0682 }
0683 
0684 static void config_digital_init_by_mode(struct mt6359_accdet *priv)
0685 {
0686     /* enable eint cmpmem pwm */
0687     regmap_write(priv->regmap, ACCDET_EINT_CMPMEN_PWM_THRESH_ADDR,
0688              (priv->data->pwm_deb->eint_pwm_width << 4 |
0689              priv->data->pwm_deb->eint_pwm_thresh));
0690     /* DA signal stable */
0691     if (priv->caps & ACCDET_PMIC_EINT0) {
0692         regmap_write(priv->regmap, ACCDET_DA_STABLE_ADDR,
0693                  ACCDET_EINT0_STABLE_VAL);
0694     } else if (priv->caps & ACCDET_PMIC_EINT1) {
0695         regmap_write(priv->regmap, ACCDET_DA_STABLE_ADDR,
0696                  ACCDET_EINT1_STABLE_VAL);
0697     }
0698     /* after receive n+1 number, interrupt issued. */
0699     regmap_update_bits(priv->regmap, ACCDET_EINT_M_PLUG_IN_NUM_ADDR,
0700                ACCDET_EINT_M_PLUG_IN_NUM_MASK_SFT,
0701                BIT(ACCDET_EINT_M_PLUG_IN_NUM_SFT));
0702     /* setting HW mode, enable digital fast discharge
0703      * if use EINT0 & EINT1 detection, please modify
0704      * ACCDET_HWMODE_EN_ADDR[2:1]
0705      */
0706     regmap_write(priv->regmap, ACCDET_HWMODE_EN_ADDR, 0x100);
0707 
0708     regmap_update_bits(priv->regmap, ACCDET_EINT_M_DETECT_EN_ADDR,
0709                ACCDET_EINT_M_DETECT_EN_MASK_SFT, 0);
0710 
0711     /* enable PWM */
0712     regmap_write(priv->regmap, ACCDET_CMP_PWM_EN_ADDR, 0x67);
0713     /* enable inverter detection */
0714     if (priv->data->eint_detect_mode == 0x1) {
0715         /* disable inverter detection */
0716         if (priv->caps & ACCDET_PMIC_EINT0) {
0717             regmap_update_bits(priv->regmap,
0718                        ACCDET_EINT0_INVERTER_SW_EN_ADDR,
0719                        ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT,
0720                        0);
0721         } else if (priv->caps & ACCDET_PMIC_EINT1) {
0722             regmap_update_bits(priv->regmap,
0723                        ACCDET_EINT1_INVERTER_SW_EN_ADDR,
0724                        ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT,
0725                        0);
0726         }
0727     } else {
0728         if (priv->caps & ACCDET_PMIC_EINT0) {
0729             regmap_update_bits(priv->regmap,
0730                        ACCDET_EINT0_INVERTER_SW_EN_ADDR,
0731                        ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT,
0732                        BIT(ACCDET_EINT0_INVERTER_SW_EN_SFT));
0733         } else if (priv->caps & ACCDET_PMIC_EINT1) {
0734             regmap_update_bits(priv->regmap,
0735                        ACCDET_EINT1_INVERTER_SW_EN_ADDR,
0736                        ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT,
0737                        BIT(ACCDET_EINT1_INVERTER_SW_EN_SFT));
0738         }
0739     }
0740 }
0741 
0742 static void config_eint_init_by_mode(struct mt6359_accdet *priv)
0743 {
0744     unsigned int val = 0;
0745 
0746     if (priv->caps & ACCDET_PMIC_EINT0) {
0747         regmap_update_bits(priv->regmap, RG_EINT0EN_ADDR,
0748                    RG_EINT0EN_MASK_SFT, BIT(RG_EINT0EN_SFT));
0749     } else if (priv->caps & ACCDET_PMIC_EINT1) {
0750         regmap_update_bits(priv->regmap, RG_EINT1EN_ADDR,
0751                    RG_EINT1EN_MASK_SFT, BIT(RG_EINT1EN_SFT));
0752     }
0753     /* ESD switches on */
0754     regmap_update_bits(priv->regmap, RG_ACCDETSPARE_ADDR,
0755                1 << 8, 1 << 8);
0756     /* before playback, set NCP pull low before nagative voltage */
0757     regmap_update_bits(priv->regmap, RG_NCP_PDDIS_EN_ADDR,
0758                RG_NCP_PDDIS_EN_MASK_SFT, BIT(RG_NCP_PDDIS_EN_SFT));
0759 
0760     if (priv->data->eint_detect_mode == 0x1 ||
0761         priv->data->eint_detect_mode == 0x2 ||
0762         priv->data->eint_detect_mode == 0x3) {
0763         if (priv->data->eint_use_ext_res == 0x1) {
0764             if (priv->caps & ACCDET_PMIC_EINT0) {
0765                 regmap_update_bits(priv->regmap,
0766                            RG_EINT0CONFIGACCDET_ADDR,
0767                            RG_EINT0CONFIGACCDET_MASK_SFT,
0768                            0);
0769             } else if (priv->caps & ACCDET_PMIC_EINT1) {
0770                 regmap_update_bits(priv->regmap,
0771                            RG_EINT1CONFIGACCDET_ADDR,
0772                            RG_EINT1CONFIGACCDET_MASK_SFT,
0773                            0);
0774             }
0775         } else {
0776             if (priv->caps & ACCDET_PMIC_EINT0) {
0777                 regmap_update_bits(priv->regmap,
0778                            RG_EINT0CONFIGACCDET_ADDR,
0779                            RG_EINT0CONFIGACCDET_MASK_SFT,
0780                            BIT(RG_EINT0CONFIGACCDET_SFT));
0781             } else if (priv->caps & ACCDET_PMIC_EINT1) {
0782                 regmap_update_bits(priv->regmap,
0783                            RG_EINT1CONFIGACCDET_ADDR,
0784                            RG_EINT1CONFIGACCDET_MASK_SFT,
0785                            BIT(RG_EINT1CONFIGACCDET_SFT));
0786             }
0787         }
0788     }
0789 
0790     if (priv->data->eint_detect_mode != 0x1) {
0791         /* current detect set 0.25uA */
0792         regmap_update_bits(priv->regmap, RG_ACCDETSPARE_ADDR,
0793                    0x3 << RG_ACCDETSPARE_SFT,
0794                    0x3 << RG_ACCDETSPARE_SFT);
0795     }
0796     regmap_write(priv->regmap, RG_EINTCOMPVTH_ADDR,
0797              val | priv->data->eint_comp_vth << RG_EINTCOMPVTH_SFT);
0798 }
0799 
0800 static void mt6359_accdet_init(struct mt6359_accdet *priv)
0801 {
0802     unsigned int reg = 0;
0803 
0804     regmap_update_bits(priv->regmap, ACCDET_SEQ_INIT_ADDR,
0805                ACCDET_SEQ_INIT_MASK_SFT, BIT(ACCDET_SEQ_INIT_SFT));
0806     mdelay(2);
0807     regmap_update_bits(priv->regmap, ACCDET_SEQ_INIT_ADDR,
0808                ACCDET_SEQ_INIT_MASK_SFT, 0);
0809     mdelay(1);
0810     /* init the debounce time (debounce/32768)sec */
0811     accdet_set_debounce(priv, accdet_state000,
0812                 priv->data->pwm_deb->debounce0);
0813     accdet_set_debounce(priv, accdet_state001,
0814                 priv->data->pwm_deb->debounce1);
0815     accdet_set_debounce(priv, accdet_state011,
0816                 priv->data->pwm_deb->debounce3);
0817     accdet_set_debounce(priv, accdet_auxadc,
0818                 priv->data->pwm_deb->debounce4);
0819 
0820     accdet_set_debounce(priv, eint_state000,
0821                 priv->data->pwm_deb->eint_debounce0);
0822     accdet_set_debounce(priv, eint_state001,
0823                 priv->data->pwm_deb->eint_debounce1);
0824     accdet_set_debounce(priv, eint_state011,
0825                 priv->data->pwm_deb->eint_debounce3);
0826     accdet_set_debounce(priv, eint_inverter_state000,
0827                 priv->data->pwm_deb->eint_inverter_debounce);
0828 
0829     regmap_update_bits(priv->regmap, RG_ACCDET_RST_ADDR,
0830                RG_ACCDET_RST_MASK_SFT, BIT(RG_ACCDET_RST_SFT));
0831     regmap_update_bits(priv->regmap, RG_ACCDET_RST_ADDR,
0832                RG_ACCDET_RST_MASK_SFT, 0);
0833 
0834     /* clear high micbias1 voltage setting */
0835     regmap_update_bits(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR,
0836                0x3 << RG_AUDMICBIAS1HVEN_SFT, 0);
0837     regmap_update_bits(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR,
0838                0x7 << RG_AUDMICBIAS1VREF_SFT, 0);
0839 
0840     /* init pwm frequency, duty & rise/falling delay */
0841     regmap_write(priv->regmap, ACCDET_PWM_WIDTH_ADDR,
0842              REGISTER_VAL(priv->data->pwm_deb->pwm_width));
0843     regmap_write(priv->regmap, ACCDET_PWM_THRESH_ADDR,
0844              REGISTER_VAL(priv->data->pwm_deb->pwm_thresh));
0845     regmap_write(priv->regmap, ACCDET_RISE_DELAY_ADDR,
0846              (priv->data->pwm_deb->fall_delay << 15 |
0847               priv->data->pwm_deb->rise_delay));
0848 
0849     regmap_read(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR, &reg);
0850     if (priv->data->mic_vol <= 7) {
0851         /* micbias1 <= 2.7V */
0852         regmap_write(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR,
0853                  reg | (priv->data->mic_vol << RG_AUDMICBIAS1VREF_SFT) |
0854                  RG_AUDMICBIAS1LOWPEN_MASK_SFT);
0855     } else if (priv->data->mic_vol == 8) {
0856         /* micbias1 = 2.8v */
0857         regmap_write(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR,
0858                  reg | (3 << RG_AUDMICBIAS1HVEN_SFT) |
0859                  RG_AUDMICBIAS1LOWPEN_MASK_SFT);
0860     } else if (priv->data->mic_vol == 9) {
0861         /* micbias1 = 2.85v */
0862         regmap_write(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR,
0863                  reg | (1 << RG_AUDMICBIAS1HVEN_SFT) |
0864                  RG_AUDMICBIAS1LOWPEN_MASK_SFT);
0865     }
0866     /* mic mode setting */
0867     regmap_read(priv->regmap, RG_AUDACCDETMICBIAS0PULLLOW_ADDR, &reg);
0868     if (priv->data->mic_mode == HEADSET_MODE_1) {
0869         /* ACC mode*/
0870         regmap_write(priv->regmap, RG_AUDACCDETMICBIAS0PULLLOW_ADDR,
0871                  reg | RG_ACCDET_MODE_ANA11_MODE1);
0872         /* enable analog fast discharge */
0873         regmap_update_bits(priv->regmap, RG_ANALOGFDEN_ADDR,
0874                    RG_ANALOGFDEN_MASK_SFT,
0875                    BIT(RG_ANALOGFDEN_SFT));
0876         regmap_update_bits(priv->regmap, RG_ACCDETSPARE_ADDR,
0877                    0x3 << 11, 0x3 << 11);
0878     } else if (priv->data->mic_mode == HEADSET_MODE_2) {
0879         /* DCC mode Low cost mode without internal bias */
0880         regmap_write(priv->regmap, RG_AUDACCDETMICBIAS0PULLLOW_ADDR,
0881                  reg | RG_ACCDET_MODE_ANA11_MODE2);
0882         /* enable analog fast discharge */
0883         regmap_update_bits(priv->regmap, RG_ANALOGFDEN_ADDR,
0884                    0x3 << RG_ANALOGFDEN_SFT,
0885                    0x3 << RG_ANALOGFDEN_SFT);
0886     } else if (priv->data->mic_mode == HEADSET_MODE_6) {
0887         /* DCC mode Low cost mode with internal bias,
0888          * bit8 = 1 to use internal bias
0889          */
0890         regmap_write(priv->regmap, RG_AUDACCDETMICBIAS0PULLLOW_ADDR,
0891                  reg | RG_ACCDET_MODE_ANA11_MODE6);
0892         regmap_update_bits(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR,
0893                    RG_AUDMICBIAS1DCSW1PEN_MASK_SFT,
0894                    BIT(RG_AUDMICBIAS1DCSW1PEN_SFT));
0895         /* enable analog fast discharge */
0896         regmap_update_bits(priv->regmap, RG_ANALOGFDEN_ADDR,
0897                    0x3 << RG_ANALOGFDEN_SFT,
0898                    0x3 << RG_ANALOGFDEN_SFT);
0899     }
0900 
0901     if (priv->caps & ACCDET_PMIC_EINT_IRQ) {
0902         config_eint_init_by_mode(priv);
0903         config_digital_init_by_mode(priv);
0904     }
0905 }
0906 
0907 int mt6359_accdet_enable_jack_detect(struct snd_soc_component *component,
0908                      struct snd_soc_jack *jack)
0909 {
0910     struct mt6359_accdet *priv =
0911         snd_soc_component_get_drvdata(component);
0912 
0913     snd_jack_set_key(jack->jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
0914     snd_jack_set_key(jack->jack, SND_JACK_BTN_1, KEY_VOLUMEDOWN);
0915     snd_jack_set_key(jack->jack, SND_JACK_BTN_2, KEY_VOLUMEUP);
0916     snd_jack_set_key(jack->jack, SND_JACK_BTN_3, KEY_VOICECOMMAND);
0917 
0918     priv->jack = jack;
0919 
0920     mt6359_accdet_jack_report(priv);
0921 
0922     return 0;
0923 }
0924 EXPORT_SYMBOL_GPL(mt6359_accdet_enable_jack_detect);
0925 
0926 static int mt6359_accdet_probe(struct platform_device *pdev)
0927 {
0928     struct mt6359_accdet *priv;
0929     struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
0930     int ret;
0931 
0932     dev_dbg(&pdev->dev, "%s(), dev name %s\n",
0933         __func__, dev_name(&pdev->dev));
0934 
0935     priv = devm_kzalloc(&pdev->dev, sizeof(struct mt6359_accdet),
0936                 GFP_KERNEL);
0937     if (!priv)
0938         return -ENOMEM;
0939 
0940     priv->data = devm_kzalloc(&pdev->dev, sizeof(struct dts_data),
0941                   GFP_KERNEL);
0942     if (!priv->data)
0943         return -ENOMEM;
0944 
0945     priv->data->pwm_deb = devm_kzalloc(&pdev->dev,
0946                        sizeof(struct pwm_deb_settings),
0947                        GFP_KERNEL);
0948     if (!priv->data->pwm_deb)
0949         return -ENOMEM;
0950 
0951     priv->regmap = mt6397->regmap;
0952     if (IS_ERR(priv->regmap)) {
0953         ret = PTR_ERR(priv->regmap);
0954         dev_err(&pdev->dev, "Failed to allocate register map: %d\n",
0955             ret);
0956         return ret;
0957     }
0958     priv->dev = &pdev->dev;
0959 
0960     ret = mt6359_accdet_parse_dt(priv);
0961     if (ret) {
0962         dev_err(&pdev->dev, "Failed to parse dts\n");
0963         return ret;
0964     }
0965     mutex_init(&priv->res_lock);
0966 
0967     priv->accdet_irq = platform_get_irq(pdev, 0);
0968     if (priv->accdet_irq) {
0969         ret = devm_request_threaded_irq(&pdev->dev, priv->accdet_irq,
0970                         NULL, mt6359_accdet_irq,
0971                         IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
0972                         "ACCDET_IRQ", priv);
0973         if (ret) {
0974             dev_err(&pdev->dev,
0975                 "Failed to request IRQ: (%d)\n", ret);
0976             return ret;
0977         }
0978     }
0979 
0980     if (priv->caps & ACCDET_PMIC_EINT0) {
0981         priv->accdet_eint0 = platform_get_irq(pdev, 1);
0982         if (priv->accdet_eint0) {
0983             ret = devm_request_threaded_irq(&pdev->dev,
0984                             priv->accdet_eint0,
0985                             NULL, mt6359_accdet_irq,
0986                             IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
0987                             "ACCDET_EINT0", priv);
0988             if (ret) {
0989                 dev_err(&pdev->dev,
0990                     "Failed to request eint0 IRQ (%d)\n",
0991                     ret);
0992                 return ret;
0993             }
0994         }
0995     } else if (priv->caps & ACCDET_PMIC_EINT1) {
0996         priv->accdet_eint1 = platform_get_irq(pdev, 2);
0997         if (priv->accdet_eint1) {
0998             ret = devm_request_threaded_irq(&pdev->dev,
0999                             priv->accdet_eint1,
1000                             NULL, mt6359_accdet_irq,
1001                             IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1002                             "ACCDET_EINT1", priv);
1003             if (ret) {
1004                 dev_err(&pdev->dev,
1005                     "Failed to request eint1 IRQ (%d)\n",
1006                     ret);
1007                 return ret;
1008             }
1009         }
1010     }
1011 
1012     priv->accdet_workqueue = create_singlethread_workqueue("accdet");
1013     INIT_WORK(&priv->accdet_work, mt6359_accdet_work);
1014     if (!priv->accdet_workqueue) {
1015         dev_err(&pdev->dev, "Failed to create accdet workqueue\n");
1016         ret = -1;
1017         goto err_accdet_wq;
1018     }
1019 
1020     priv->jd_workqueue = create_singlethread_workqueue("mt6359_accdet_jd");
1021     INIT_WORK(&priv->jd_work, mt6359_accdet_jd_work);
1022     if (!priv->jd_workqueue) {
1023         dev_err(&pdev->dev, "Failed to create jack detect workqueue\n");
1024         ret = -1;
1025         goto err_eint_wq;
1026     }
1027 
1028     platform_set_drvdata(pdev, priv);
1029     ret = devm_snd_soc_register_component(&pdev->dev,
1030                           &mt6359_accdet_soc_driver,
1031                           NULL, 0);
1032     if (ret) {
1033         dev_err(&pdev->dev, "Failed to register component\n");
1034         return ret;
1035     }
1036 
1037     priv->jd_sts = M_PLUG_OUT;
1038     priv->jack_type = 0;
1039     priv->btn_type = 0;
1040     priv->accdet_status = 0x3;
1041     mt6359_accdet_init(priv);
1042 
1043     mt6359_accdet_jack_report(priv);
1044 
1045     return 0;
1046 
1047 err_eint_wq:
1048     destroy_workqueue(priv->accdet_workqueue);
1049 err_accdet_wq:
1050     dev_err(&pdev->dev, "%s error. now exit.!\n", __func__);
1051     return ret;
1052 }
1053 
1054 static struct platform_driver mt6359_accdet_driver = {
1055     .driver = {
1056         .name = "pmic-codec-accdet",
1057     },
1058     .probe = mt6359_accdet_probe,
1059 };
1060 
1061 module_platform_driver(mt6359_accdet_driver)
1062 
1063 /* Module information */
1064 MODULE_DESCRIPTION("MT6359 ALSA SoC codec jack driver");
1065 MODULE_AUTHOR("Argus Lin <argus.lin@mediatek.com>");
1066 MODULE_LICENSE("GPL v2");
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