soc/codecs/mt6358.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // mt6358.c  --  mt6358 ALSA SoC audio codec driver
0004 //
0005 // Copyright (c) 2018 MediaTek Inc.
0006 // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
0007
0008 #include <linux/platform_device.h>
0009 #include <linux/module.h>
0010 #include <linux/of_device.h>
0011 #include <linux/delay.h>
0012 #include <linux/kthread.h>
0013 #include <linux/sched.h>
0014 #include <linux/mfd/mt6397/core.h>
0015 #include <linux/regulator/consumer.h>
0016
0017 #include <sound/soc.h>
0018 #include <sound/tlv.h>
0019
0020 #include "mt6358.h"
0021
0022 enum {
0023     AUDIO_ANALOG_VOLUME_HSOUTL,
0024     AUDIO_ANALOG_VOLUME_HSOUTR,
0025     AUDIO_ANALOG_VOLUME_HPOUTL,
0026     AUDIO_ANALOG_VOLUME_HPOUTR,
0027     AUDIO_ANALOG_VOLUME_LINEOUTL,
0028     AUDIO_ANALOG_VOLUME_LINEOUTR,
0029     AUDIO_ANALOG_VOLUME_MICAMP1,
0030     AUDIO_ANALOG_VOLUME_MICAMP2,
0031     AUDIO_ANALOG_VOLUME_TYPE_MAX
0032 };
0033
0034 enum {
0035     MUX_ADC_L,
0036     MUX_ADC_R,
0037     MUX_PGA_L,
0038     MUX_PGA_R,
0039     MUX_MIC_TYPE,
0040     MUX_HP_L,
0041     MUX_HP_R,
0042     MUX_NUM,
0043 };
0044
0045 enum {
0046     DEVICE_HP,
0047     DEVICE_LO,
0048     DEVICE_RCV,
0049     DEVICE_MIC1,
0050     DEVICE_MIC2,
0051     DEVICE_NUM
0052 };
0053
0054 /* Supply widget subseq */
0055 enum {
0056     /* common */
0057     SUPPLY_SEQ_CLK_BUF,
0058     SUPPLY_SEQ_AUD_GLB,
0059     SUPPLY_SEQ_CLKSQ,
0060     SUPPLY_SEQ_VOW_AUD_LPW,
0061     SUPPLY_SEQ_AUD_VOW,
0062     SUPPLY_SEQ_VOW_CLK,
0063     SUPPLY_SEQ_VOW_LDO,
0064     SUPPLY_SEQ_TOP_CK,
0065     SUPPLY_SEQ_TOP_CK_LAST,
0066     SUPPLY_SEQ_AUD_TOP,
0067     SUPPLY_SEQ_AUD_TOP_LAST,
0068     SUPPLY_SEQ_AFE,
0069     /* capture */
0070     SUPPLY_SEQ_ADC_SUPPLY,
0071 };
0072
0073 enum {
0074     CH_L = 0,
0075     CH_R,
0076     NUM_CH,
0077 };
0078
0079 #define REG_STRIDE 2
0080
0081 struct mt6358_priv {
0082     struct device *dev;
0083     struct regmap *regmap;
0084
0085     unsigned int dl_rate;
0086     unsigned int ul_rate;
0087
0088     int ana_gain[AUDIO_ANALOG_VOLUME_TYPE_MAX];
0089     unsigned int mux_select[MUX_NUM];
0090
0091     int dev_counter[DEVICE_NUM];
0092
0093     int mtkaif_protocol;
0094
0095     struct regulator *avdd_reg;
0096
0097     int wov_enabled;
0098
0099     unsigned int dmic_one_wire_mode;
0100 };
0101
0102 int mt6358_set_mtkaif_protocol(struct snd_soc_component *cmpnt,
0103                    int mtkaif_protocol)
0104 {
0105     struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
0106
0107     priv->mtkaif_protocol = mtkaif_protocol;
0108     return 0;
0109 }
0110 EXPORT_SYMBOL_GPL(mt6358_set_mtkaif_protocol);
0111
0112 static void playback_gpio_set(struct mt6358_priv *priv)
0113 {
0114     /* set gpio mosi mode */
0115     regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR,
0116                0x01f8, 0x01f8);
0117     regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_SET,
0118                0xffff, 0x0249);
0119     regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2,
0120                0xffff, 0x0249);
0121 }
0122
0123 static void playback_gpio_reset(struct mt6358_priv *priv)
0124 {
0125     /* set pad_aud_*_mosi to GPIO mode and dir input
0126      * reason:
0127      * pad_aud_dat_mosi*, because the pin is used as boot strap
0128      * don't clean clk/sync, for mtkaif protocol 2
0129      */
0130     regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR,
0131                0x01f8, 0x01f8);
0132     regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2,
0133                0x01f8, 0x0000);
0134     regmap_update_bits(priv->regmap, MT6358_GPIO_DIR0,
0135                0xf << 8, 0x0);
0136 }
0137
0138 static void capture_gpio_set(struct mt6358_priv *priv)
0139 {
0140     /* set gpio miso mode */
0141     regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_CLR,
0142                0xffff, 0xffff);
0143     regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_SET,
0144                0xffff, 0x0249);
0145     regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3,
0146                0xffff, 0x0249);
0147 }
0148
0149 static void capture_gpio_reset(struct mt6358_priv *priv)
0150 {
0151     /* set pad_aud_*_miso to GPIO mode and dir input
0152      * reason:
0153      * pad_aud_clk_miso, because when playback only the miso_clk
0154      * will also have 26m, so will have power leak
0155      * pad_aud_dat_miso*, because the pin is used as boot strap
0156      */
0157     regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_CLR,
0158                0xffff, 0xffff);
0159     regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3,
0160                0xffff, 0x0000);
0161     regmap_update_bits(priv->regmap, MT6358_GPIO_DIR0,
0162                0xf << 12, 0x0);
0163 }
0164
0165 /* use only when not govern by DAPM */
0166 static int mt6358_set_dcxo(struct mt6358_priv *priv, bool enable)
0167 {
0168     regmap_update_bits(priv->regmap, MT6358_DCXO_CW14,
0169                0x1 << RG_XO_AUDIO_EN_M_SFT,
0170                (enable ? 1 : 0) << RG_XO_AUDIO_EN_M_SFT);
0171     return 0;
0172 }
0173
0174 /* use only when not govern by DAPM */
0175 static int mt6358_set_clksq(struct mt6358_priv *priv, bool enable)
0176 {
0177     /* audio clk source from internal dcxo */
0178     regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6,
0179                RG_CLKSQ_IN_SEL_TEST_MASK_SFT,
0180                0x0);
0181
0182     /* Enable/disable CLKSQ 26MHz */
0183     regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6,
0184                RG_CLKSQ_EN_MASK_SFT,
0185                (enable ? 1 : 0) << RG_CLKSQ_EN_SFT);
0186     return 0;
0187 }
0188
0189 /* use only when not govern by DAPM */
0190 static int mt6358_set_aud_global_bias(struct mt6358_priv *priv, bool enable)
0191 {
0192     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
0193                RG_AUDGLB_PWRDN_VA28_MASK_SFT,
0194                (enable ? 0 : 1) << RG_AUDGLB_PWRDN_VA28_SFT);
0195     return 0;
0196 }
0197
0198 /* use only when not govern by DAPM */
0199 static int mt6358_set_topck(struct mt6358_priv *priv, bool enable)
0200 {
0201     regmap_update_bits(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0,
0202                0x0066, enable ? 0x0 : 0x66);
0203     return 0;
0204 }
0205
0206 static int mt6358_mtkaif_tx_enable(struct mt6358_priv *priv)
0207 {
0208     switch (priv->mtkaif_protocol) {
0209     case MT6358_MTKAIF_PROTOCOL_2_CLK_P2:
0210         /* MTKAIF TX format setting */
0211         regmap_update_bits(priv->regmap,
0212                    MT6358_AFE_ADDA_MTKAIF_CFG0,
0213                    0xffff, 0x0010);
0214         /* enable aud_pad TX fifos */
0215         regmap_update_bits(priv->regmap,
0216                    MT6358_AFE_AUD_PAD_TOP,
0217                    0xff00, 0x3800);
0218         regmap_update_bits(priv->regmap,
0219                    MT6358_AFE_AUD_PAD_TOP,
0220                    0xff00, 0x3900);
0221         break;
0222     case MT6358_MTKAIF_PROTOCOL_2:
0223         /* MTKAIF TX format setting */
0224         regmap_update_bits(priv->regmap,
0225                    MT6358_AFE_ADDA_MTKAIF_CFG0,
0226                    0xffff, 0x0010);
0227         /* enable aud_pad TX fifos */
0228         regmap_update_bits(priv->regmap,
0229                    MT6358_AFE_AUD_PAD_TOP,
0230                    0xff00, 0x3100);
0231         break;
0232     case MT6358_MTKAIF_PROTOCOL_1:
0233     default:
0234         /* MTKAIF TX format setting */
0235         regmap_update_bits(priv->regmap,
0236                    MT6358_AFE_ADDA_MTKAIF_CFG0,
0237                    0xffff, 0x0000);
0238         /* enable aud_pad TX fifos */
0239         regmap_update_bits(priv->regmap,
0240                    MT6358_AFE_AUD_PAD_TOP,
0241                    0xff00, 0x3100);
0242         break;
0243     }
0244     return 0;
0245 }
0246
0247 static int mt6358_mtkaif_tx_disable(struct mt6358_priv *priv)
0248 {
0249     /* disable aud_pad TX fifos */
0250     regmap_update_bits(priv->regmap, MT6358_AFE_AUD_PAD_TOP,
0251                0xff00, 0x3000);
0252     return 0;
0253 }
0254
0255 int mt6358_mtkaif_calibration_enable(struct snd_soc_component *cmpnt)
0256 {
0257     struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
0258
0259     playback_gpio_set(priv);
0260     capture_gpio_set(priv);
0261     mt6358_mtkaif_tx_enable(priv);
0262
0263     mt6358_set_dcxo(priv, true);
0264     mt6358_set_aud_global_bias(priv, true);
0265     mt6358_set_clksq(priv, true);
0266     mt6358_set_topck(priv, true);
0267
0268     /* set dat_miso_loopback on */
0269     regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
0270                RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT,
0271                1 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT);
0272     regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
0273                RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT,
0274                1 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT);
0275     return 0;
0276 }
0277 EXPORT_SYMBOL_GPL(mt6358_mtkaif_calibration_enable);
0278
0279 int mt6358_mtkaif_calibration_disable(struct snd_soc_component *cmpnt)
0280 {
0281     struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
0282
0283     /* set dat_miso_loopback off */
0284     regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
0285                RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT,
0286                0 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT);
0287     regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
0288                RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT,
0289                0 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT);
0290
0291     mt6358_set_topck(priv, false);
0292     mt6358_set_clksq(priv, false);
0293     mt6358_set_aud_global_bias(priv, false);
0294     mt6358_set_dcxo(priv, false);
0295
0296     mt6358_mtkaif_tx_disable(priv);
0297     playback_gpio_reset(priv);
0298     capture_gpio_reset(priv);
0299     return 0;
0300 }
0301 EXPORT_SYMBOL_GPL(mt6358_mtkaif_calibration_disable);
0302
0303 int mt6358_set_mtkaif_calibration_phase(struct snd_soc_component *cmpnt,
0304                     int phase_1, int phase_2)
0305 {
0306     struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
0307
0308     regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
0309                RG_AUD_PAD_TOP_PHASE_MODE_MASK_SFT,
0310                phase_1 << RG_AUD_PAD_TOP_PHASE_MODE_SFT);
0311     regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
0312                RG_AUD_PAD_TOP_PHASE_MODE2_MASK_SFT,
0313                phase_2 << RG_AUD_PAD_TOP_PHASE_MODE2_SFT);
0314     return 0;
0315 }
0316 EXPORT_SYMBOL_GPL(mt6358_set_mtkaif_calibration_phase);
0317
0318 /* dl pga gain */
0319 enum {
0320     DL_GAIN_8DB = 0,
0321     DL_GAIN_0DB = 8,
0322     DL_GAIN_N_1DB = 9,
0323     DL_GAIN_N_10DB = 18,
0324     DL_GAIN_N_40DB = 0x1f,
0325 };
0326
0327 #define DL_GAIN_N_10DB_REG (DL_GAIN_N_10DB << 7 | DL_GAIN_N_10DB)
0328 #define DL_GAIN_N_40DB_REG (DL_GAIN_N_40DB << 7 | DL_GAIN_N_40DB)
0329 #define DL_GAIN_REG_MASK 0x0f9f
0330
0331 static void hp_zcd_disable(struct mt6358_priv *priv)
0332 {
0333     regmap_write(priv->regmap, MT6358_ZCD_CON0, 0x0000);
0334 }
0335
0336 static void hp_main_output_ramp(struct mt6358_priv *priv, bool up)
0337 {
0338     int i, stage;
0339     int target = 7;
0340
0341     /* Enable/Reduce HPL/R main output stage step by step */
0342     for (i = 0; i <= target; i++) {
0343         stage = up ? i : target - i;
0344         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
0345                    0x7 << 8, stage << 8);
0346         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
0347                    0x7 << 11, stage << 11);
0348         usleep_range(100, 150);
0349     }
0350 }
0351
0352 static void hp_aux_feedback_loop_gain_ramp(struct mt6358_priv *priv, bool up)
0353 {
0354     int i, stage;
0355
0356     /* Reduce HP aux feedback loop gain step by step */
0357     for (i = 0; i <= 0xf; i++) {
0358         stage = up ? i : 0xf - i;
0359         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
0360                    0xf << 12, stage << 12);
0361         usleep_range(100, 150);
0362     }
0363 }
0364
0365 static void hp_pull_down(struct mt6358_priv *priv, bool enable)
0366 {
0367     int i;
0368
0369     if (enable) {
0370         for (i = 0x0; i <= 0x6; i++) {
0371             regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
0372                        0x7, i);
0373             usleep_range(600, 700);
0374         }
0375     } else {
0376         for (i = 0x6; i >= 0x1; i--) {
0377             regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
0378                        0x7, i);
0379             usleep_range(600, 700);
0380         }
0381     }
0382 }
0383
0384 static bool is_valid_hp_pga_idx(int reg_idx)
0385 {
0386     return (reg_idx >= DL_GAIN_8DB && reg_idx <= DL_GAIN_N_10DB) ||
0387            reg_idx == DL_GAIN_N_40DB;
0388 }
0389
0390 static void headset_volume_ramp(struct mt6358_priv *priv, int from, int to)
0391 {
0392     int offset = 0, count = 0, reg_idx;
0393
0394     if (!is_valid_hp_pga_idx(from) || !is_valid_hp_pga_idx(to))
0395         dev_warn(priv->dev, "%s(), volume index is not valid, from %d, to %d\n",
0396              __func__, from, to);
0397
0398     dev_info(priv->dev, "%s(), from %d, to %d\n",
0399          __func__, from, to);
0400
0401     if (to > from)
0402         offset = to - from;
0403     else
0404         offset = from - to;
0405
0406     while (offset >= 0) {
0407         if (to > from)
0408             reg_idx = from + count;
0409         else
0410             reg_idx = from - count;
0411
0412         if (is_valid_hp_pga_idx(reg_idx)) {
0413             regmap_update_bits(priv->regmap,
0414                        MT6358_ZCD_CON2,
0415                        DL_GAIN_REG_MASK,
0416                        (reg_idx << 7) | reg_idx);
0417             usleep_range(200, 300);
0418         }
0419         offset--;
0420         count++;
0421     }
0422 }
0423
0424 static int mt6358_put_volsw(struct snd_kcontrol *kcontrol,
0425                 struct snd_ctl_elem_value *ucontrol)
0426 {
0427     struct snd_soc_component *component =
0428             snd_soc_kcontrol_component(kcontrol);
0429     struct mt6358_priv *priv = snd_soc_component_get_drvdata(component);
0430     struct soc_mixer_control *mc =
0431             (struct soc_mixer_control *)kcontrol->private_value;
0432     unsigned int reg;
0433     int ret;
0434
0435     ret = snd_soc_put_volsw(kcontrol, ucontrol);
0436     if (ret < 0)
0437         return ret;
0438
0439     switch (mc->reg) {
0440     case MT6358_ZCD_CON2:
0441         regmap_read(priv->regmap, MT6358_ZCD_CON2, &reg);
0442         priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL] =
0443             (reg >> RG_AUDHPLGAIN_SFT) & RG_AUDHPLGAIN_MASK;
0444         priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR] =
0445             (reg >> RG_AUDHPRGAIN_SFT) & RG_AUDHPRGAIN_MASK;
0446         break;
0447     case MT6358_ZCD_CON1:
0448         regmap_read(priv->regmap, MT6358_ZCD_CON1, &reg);
0449         priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] =
0450             (reg >> RG_AUDLOLGAIN_SFT) & RG_AUDLOLGAIN_MASK;
0451         priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] =
0452             (reg >> RG_AUDLORGAIN_SFT) & RG_AUDLORGAIN_MASK;
0453         break;
0454     case MT6358_ZCD_CON3:
0455         regmap_read(priv->regmap, MT6358_ZCD_CON3, &reg);
0456         priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL] =
0457             (reg >> RG_AUDHSGAIN_SFT) & RG_AUDHSGAIN_MASK;
0458         priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTR] =
0459             (reg >> RG_AUDHSGAIN_SFT) & RG_AUDHSGAIN_MASK;
0460         break;
0461     case MT6358_AUDENC_ANA_CON0:
0462     case MT6358_AUDENC_ANA_CON1:
0463         regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON0, &reg);
0464         priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1] =
0465             (reg >> RG_AUDPREAMPLGAIN_SFT) & RG_AUDPREAMPLGAIN_MASK;
0466         regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON1, &reg);
0467         priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2] =
0468             (reg >> RG_AUDPREAMPRGAIN_SFT) & RG_AUDPREAMPRGAIN_MASK;
0469         break;
0470     }
0471
0472     return ret;
0473 }
0474
0475 static void mt6358_restore_pga(struct mt6358_priv *priv);
0476
0477 static int mt6358_enable_wov_phase2(struct mt6358_priv *priv)
0478 {
0479     /* analog */
0480     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
0481                0xffff, 0x0000);
0482     regmap_update_bits(priv->regmap, MT6358_DCXO_CW14, 0xffff, 0xa2b5);
0483     regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
0484                0xffff, 0x0800);
0485     mt6358_restore_pga(priv);
0486
0487     regmap_update_bits(priv->regmap, MT6358_DCXO_CW13, 0xffff, 0x9929);
0488     regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
0489                0xffff, 0x0025);
0490     regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON8,
0491                0xffff, 0x0005);
0492
0493     /* digital */
0494     regmap_update_bits(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0,
0495                0xffff, 0x0000);
0496     regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 0xffff, 0x0120);
0497     regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG0, 0xffff, 0xffff);
0498     regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG1, 0xffff, 0x0200);
0499     regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG2, 0xffff, 0x2424);
0500     regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG3, 0xffff, 0xdbac);
0501     regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG4, 0xffff, 0x029e);
0502     regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG5, 0xffff, 0x0000);
0503     regmap_update_bits(priv->regmap, MT6358_AFE_VOW_POSDIV_CFG0,
0504                0xffff, 0x0000);
0505     regmap_update_bits(priv->regmap, MT6358_AFE_VOW_HPF_CFG0,
0506                0xffff, 0x0451);
0507     regmap_update_bits(priv->regmap, MT6358_AFE_VOW_TOP, 0xffff, 0x68d1);
0508
0509     return 0;
0510 }
0511
0512 static int mt6358_disable_wov_phase2(struct mt6358_priv *priv)
0513 {
0514     /* digital */
0515     regmap_update_bits(priv->regmap, MT6358_AFE_VOW_TOP, 0xffff, 0xc000);
0516     regmap_update_bits(priv->regmap, MT6358_AFE_VOW_HPF_CFG0,
0517                0xffff, 0x0450);
0518     regmap_update_bits(priv->regmap, MT6358_AFE_VOW_POSDIV_CFG0,
0519                0xffff, 0x0c00);
0520     regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG5, 0xffff, 0x0100);
0521     regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG4, 0xffff, 0x006c);
0522     regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG3, 0xffff, 0xa879);
0523     regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG2, 0xffff, 0x2323);
0524     regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG1, 0xffff, 0x0400);
0525     regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG0, 0xffff, 0x0000);
0526     regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 0xffff, 0x02d8);
0527     regmap_update_bits(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0,
0528                0xffff, 0x0000);
0529
0530     /* analog */
0531     regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON8,
0532                0xffff, 0x0004);
0533     regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
0534                0xffff, 0x0000);
0535     regmap_update_bits(priv->regmap, MT6358_DCXO_CW13, 0xffff, 0x9829);
0536     regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
0537                0xffff, 0x0000);
0538     mt6358_restore_pga(priv);
0539     regmap_update_bits(priv->regmap, MT6358_DCXO_CW14, 0xffff, 0xa2b5);
0540     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
0541                0xffff, 0x0010);
0542
0543     return 0;
0544 }
0545
0546 static int mt6358_get_wov(struct snd_kcontrol *kcontrol,
0547               struct snd_ctl_elem_value *ucontrol)
0548 {
0549     struct snd_soc_component *c = snd_soc_kcontrol_component(kcontrol);
0550     struct mt6358_priv *priv = snd_soc_component_get_drvdata(c);
0551
0552     ucontrol->value.integer.value[0] = priv->wov_enabled;
0553     return 0;
0554 }
0555
0556 static int mt6358_put_wov(struct snd_kcontrol *kcontrol,
0557               struct snd_ctl_elem_value *ucontrol)
0558 {
0559     struct snd_soc_component *c = snd_soc_kcontrol_component(kcontrol);
0560     struct mt6358_priv *priv = snd_soc_component_get_drvdata(c);
0561     int enabled = ucontrol->value.integer.value[0];
0562
0563     if (priv->wov_enabled != enabled) {
0564         if (enabled)
0565             mt6358_enable_wov_phase2(priv);
0566         else
0567             mt6358_disable_wov_phase2(priv);
0568
0569         priv->wov_enabled = enabled;
0570     }
0571
0572     return 0;
0573 }
0574
0575 static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0);
0576 static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 600, 0);
0577
0578 static const struct snd_kcontrol_new mt6358_snd_controls[] = {
0579     /* dl pga gain */
0580     SOC_DOUBLE_EXT_TLV("Headphone Volume",
0581                MT6358_ZCD_CON2, 0, 7, 0x12, 1,
0582                snd_soc_get_volsw, mt6358_put_volsw, playback_tlv),
0583     SOC_DOUBLE_EXT_TLV("Lineout Volume",
0584                MT6358_ZCD_CON1, 0, 7, 0x12, 1,
0585                snd_soc_get_volsw, mt6358_put_volsw, playback_tlv),
0586     SOC_SINGLE_EXT_TLV("Handset Volume",
0587                MT6358_ZCD_CON3, 0, 0x12, 1,
0588                snd_soc_get_volsw, mt6358_put_volsw, playback_tlv),
0589     /* ul pga gain */
0590     SOC_DOUBLE_R_EXT_TLV("PGA Volume",
0591                  MT6358_AUDENC_ANA_CON0, MT6358_AUDENC_ANA_CON1,
0592                  8, 4, 0,
0593                  snd_soc_get_volsw, mt6358_put_volsw, pga_tlv),
0594
0595     SOC_SINGLE_BOOL_EXT("Wake-on-Voice Phase2 Switch", 0,
0596                 mt6358_get_wov, mt6358_put_wov),
0597 };
0598
0599 /* MUX */
0600 /* LOL MUX */
0601 static const char * const lo_in_mux_map[] = {
0602     "Open", "Mute", "Playback", "Test Mode"
0603 };
0604
0605 static int lo_in_mux_map_value[] = {
0606     0x0, 0x1, 0x2, 0x3,
0607 };
0608
0609 static SOC_VALUE_ENUM_SINGLE_DECL(lo_in_mux_map_enum,
0610                   MT6358_AUDDEC_ANA_CON7,
0611                   RG_AUDLOLMUXINPUTSEL_VAUDP15_SFT,
0612                   RG_AUDLOLMUXINPUTSEL_VAUDP15_MASK,
0613                   lo_in_mux_map,
0614                   lo_in_mux_map_value);
0615
0616 static const struct snd_kcontrol_new lo_in_mux_control =
0617     SOC_DAPM_ENUM("In Select", lo_in_mux_map_enum);
0618
0619 /*HP MUX */
0620 enum {
0621     HP_MUX_OPEN = 0,
0622     HP_MUX_HPSPK,
0623     HP_MUX_HP,
0624     HP_MUX_TEST_MODE,
0625     HP_MUX_HP_IMPEDANCE,
0626     HP_MUX_MASK = 0x7,
0627 };
0628
0629 static const char * const hp_in_mux_map[] = {
0630     "Open",
0631     "LoudSPK Playback",
0632     "Audio Playback",
0633     "Test Mode",
0634     "HP Impedance",
0635     "undefined1",
0636     "undefined2",
0637     "undefined3",
0638 };
0639
0640 static int hp_in_mux_map_value[] = {
0641     HP_MUX_OPEN,
0642     HP_MUX_HPSPK,
0643     HP_MUX_HP,
0644     HP_MUX_TEST_MODE,
0645     HP_MUX_HP_IMPEDANCE,
0646     HP_MUX_OPEN,
0647     HP_MUX_OPEN,
0648     HP_MUX_OPEN,
0649 };
0650
0651 static SOC_VALUE_ENUM_SINGLE_DECL(hpl_in_mux_map_enum,
0652                   SND_SOC_NOPM,
0653                   0,
0654                   HP_MUX_MASK,
0655                   hp_in_mux_map,
0656                   hp_in_mux_map_value);
0657
0658 static const struct snd_kcontrol_new hpl_in_mux_control =
0659     SOC_DAPM_ENUM("HPL Select", hpl_in_mux_map_enum);
0660
0661 static SOC_VALUE_ENUM_SINGLE_DECL(hpr_in_mux_map_enum,
0662                   SND_SOC_NOPM,
0663                   0,
0664                   HP_MUX_MASK,
0665                   hp_in_mux_map,
0666                   hp_in_mux_map_value);
0667
0668 static const struct snd_kcontrol_new hpr_in_mux_control =
0669     SOC_DAPM_ENUM("HPR Select", hpr_in_mux_map_enum);
0670
0671 /* RCV MUX */
0672 enum {
0673     RCV_MUX_OPEN = 0,
0674     RCV_MUX_MUTE,
0675     RCV_MUX_VOICE_PLAYBACK,
0676     RCV_MUX_TEST_MODE,
0677     RCV_MUX_MASK = 0x3,
0678 };
0679
0680 static const char * const rcv_in_mux_map[] = {
0681     "Open", "Mute", "Voice Playback", "Test Mode"
0682 };
0683
0684 static int rcv_in_mux_map_value[] = {
0685     RCV_MUX_OPEN,
0686     RCV_MUX_MUTE,
0687     RCV_MUX_VOICE_PLAYBACK,
0688     RCV_MUX_TEST_MODE,
0689 };
0690
0691 static SOC_VALUE_ENUM_SINGLE_DECL(rcv_in_mux_map_enum,
0692                   SND_SOC_NOPM,
0693                   0,
0694                   RCV_MUX_MASK,
0695                   rcv_in_mux_map,
0696                   rcv_in_mux_map_value);
0697
0698 static const struct snd_kcontrol_new rcv_in_mux_control =
0699     SOC_DAPM_ENUM("RCV Select", rcv_in_mux_map_enum);
0700
0701 /* DAC In MUX */
0702 static const char * const dac_in_mux_map[] = {
0703     "Normal Path", "Sgen"
0704 };
0705
0706 static int dac_in_mux_map_value[] = {
0707     0x0, 0x1,
0708 };
0709
0710 static SOC_VALUE_ENUM_SINGLE_DECL(dac_in_mux_map_enum,
0711                   MT6358_AFE_TOP_CON0,
0712                   DL_SINE_ON_SFT,
0713                   DL_SINE_ON_MASK,
0714                   dac_in_mux_map,
0715                   dac_in_mux_map_value);
0716
0717 static const struct snd_kcontrol_new dac_in_mux_control =
0718     SOC_DAPM_ENUM("DAC Select", dac_in_mux_map_enum);
0719
0720 /* AIF Out MUX */
0721 static SOC_VALUE_ENUM_SINGLE_DECL(aif_out_mux_map_enum,
0722                   MT6358_AFE_TOP_CON0,
0723                   UL_SINE_ON_SFT,
0724                   UL_SINE_ON_MASK,
0725                   dac_in_mux_map,
0726                   dac_in_mux_map_value);
0727
0728 static const struct snd_kcontrol_new aif_out_mux_control =
0729     SOC_DAPM_ENUM("AIF Out Select", aif_out_mux_map_enum);
0730
0731 /* Mic Type MUX */
0732 enum {
0733     MIC_TYPE_MUX_IDLE = 0,
0734     MIC_TYPE_MUX_ACC,
0735     MIC_TYPE_MUX_DMIC,
0736     MIC_TYPE_MUX_DCC,
0737     MIC_TYPE_MUX_DCC_ECM_DIFF,
0738     MIC_TYPE_MUX_DCC_ECM_SINGLE,
0739     MIC_TYPE_MUX_MASK = 0x7,
0740 };
0741
0742 #define IS_DCC_BASE(type) ((type) == MIC_TYPE_MUX_DCC || \
0743             (type) == MIC_TYPE_MUX_DCC_ECM_DIFF || \
0744             (type) == MIC_TYPE_MUX_DCC_ECM_SINGLE)
0745
0746 static const char * const mic_type_mux_map[] = {
0747     "Idle",
0748     "ACC",
0749     "DMIC",
0750     "DCC",
0751     "DCC_ECM_DIFF",
0752     "DCC_ECM_SINGLE",
0753 };
0754
0755 static int mic_type_mux_map_value[] = {
0756     MIC_TYPE_MUX_IDLE,
0757     MIC_TYPE_MUX_ACC,
0758     MIC_TYPE_MUX_DMIC,
0759     MIC_TYPE_MUX_DCC,
0760     MIC_TYPE_MUX_DCC_ECM_DIFF,
0761     MIC_TYPE_MUX_DCC_ECM_SINGLE,
0762 };
0763
0764 static SOC_VALUE_ENUM_SINGLE_DECL(mic_type_mux_map_enum,
0765                   SND_SOC_NOPM,
0766                   0,
0767                   MIC_TYPE_MUX_MASK,
0768                   mic_type_mux_map,
0769                   mic_type_mux_map_value);
0770
0771 static const struct snd_kcontrol_new mic_type_mux_control =
0772     SOC_DAPM_ENUM("Mic Type Select", mic_type_mux_map_enum);
0773
0774 /* ADC L MUX */
0775 enum {
0776     ADC_MUX_IDLE = 0,
0777     ADC_MUX_AIN0,
0778     ADC_MUX_PREAMPLIFIER,
0779     ADC_MUX_IDLE1,
0780     ADC_MUX_MASK = 0x3,
0781 };
0782
0783 static const char * const adc_left_mux_map[] = {
0784     "Idle", "AIN0", "Left Preamplifier", "Idle_1"
0785 };
0786
0787 static int adc_mux_map_value[] = {
0788     ADC_MUX_IDLE,
0789     ADC_MUX_AIN0,
0790     ADC_MUX_PREAMPLIFIER,
0791     ADC_MUX_IDLE1,
0792 };
0793
0794 static SOC_VALUE_ENUM_SINGLE_DECL(adc_left_mux_map_enum,
0795                   SND_SOC_NOPM,
0796                   0,
0797                   ADC_MUX_MASK,
0798                   adc_left_mux_map,
0799                   adc_mux_map_value);
0800
0801 static const struct snd_kcontrol_new adc_left_mux_control =
0802     SOC_DAPM_ENUM("ADC L Select", adc_left_mux_map_enum);
0803
0804 /* ADC R MUX */
0805 static const char * const adc_right_mux_map[] = {
0806     "Idle", "AIN0", "Right Preamplifier", "Idle_1"
0807 };
0808
0809 static SOC_VALUE_ENUM_SINGLE_DECL(adc_right_mux_map_enum,
0810                   SND_SOC_NOPM,
0811                   0,
0812                   ADC_MUX_MASK,
0813                   adc_right_mux_map,
0814                   adc_mux_map_value);
0815
0816 static const struct snd_kcontrol_new adc_right_mux_control =
0817     SOC_DAPM_ENUM("ADC R Select", adc_right_mux_map_enum);
0818
0819 /* PGA L MUX */
0820 enum {
0821     PGA_MUX_NONE = 0,
0822     PGA_MUX_AIN0,
0823     PGA_MUX_AIN1,
0824     PGA_MUX_AIN2,
0825     PGA_MUX_MASK = 0x3,
0826 };
0827
0828 static const char * const pga_mux_map[] = {
0829     "None", "AIN0", "AIN1", "AIN2"
0830 };
0831
0832 static int pga_mux_map_value[] = {
0833     PGA_MUX_NONE,
0834     PGA_MUX_AIN0,
0835     PGA_MUX_AIN1,
0836     PGA_MUX_AIN2,
0837 };
0838
0839 static SOC_VALUE_ENUM_SINGLE_DECL(pga_left_mux_map_enum,
0840                   SND_SOC_NOPM,
0841                   0,
0842                   PGA_MUX_MASK,
0843                   pga_mux_map,
0844                   pga_mux_map_value);
0845
0846 static const struct snd_kcontrol_new pga_left_mux_control =
0847     SOC_DAPM_ENUM("PGA L Select", pga_left_mux_map_enum);
0848
0849 /* PGA R MUX */
0850 static SOC_VALUE_ENUM_SINGLE_DECL(pga_right_mux_map_enum,
0851                   SND_SOC_NOPM,
0852                   0,
0853                   PGA_MUX_MASK,
0854                   pga_mux_map,
0855                   pga_mux_map_value);
0856
0857 static const struct snd_kcontrol_new pga_right_mux_control =
0858     SOC_DAPM_ENUM("PGA R Select", pga_right_mux_map_enum);
0859
0860 static int mt_clksq_event(struct snd_soc_dapm_widget *w,
0861               struct snd_kcontrol *kcontrol,
0862               int event)
0863 {
0864     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0865     struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
0866
0867     dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
0868
0869     switch (event) {
0870     case SND_SOC_DAPM_PRE_PMU:
0871         /* audio clk source from internal dcxo */
0872         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6,
0873                    RG_CLKSQ_IN_SEL_TEST_MASK_SFT,
0874                    0x0);
0875         break;
0876     default:
0877         break;
0878     }
0879
0880     return 0;
0881 }
0882
0883 static int mt_sgen_event(struct snd_soc_dapm_widget *w,
0884              struct snd_kcontrol *kcontrol,
0885              int event)
0886 {
0887     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0888     struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
0889
0890     dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
0891
0892     switch (event) {
0893     case SND_SOC_DAPM_PRE_PMU:
0894         /* sdm audio fifo clock power on */
0895         regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006);
0896         /* scrambler clock on enable */
0897         regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1);
0898         /* sdm power on */
0899         regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003);
0900         /* sdm fifo enable */
0901         regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B);
0902
0903         regmap_update_bits(priv->regmap, MT6358_AFE_SGEN_CFG0,
0904                    0xff3f,
0905                    0x0000);
0906         regmap_update_bits(priv->regmap, MT6358_AFE_SGEN_CFG1,
0907                    0xffff,
0908                    0x0001);
0909         break;
0910     case SND_SOC_DAPM_POST_PMD:
0911         /* DL scrambler disabling sequence */
0912         regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000);
0913         regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0);
0914         break;
0915     default:
0916         break;
0917     }
0918
0919     return 0;
0920 }
0921
0922 static int mt_aif_in_event(struct snd_soc_dapm_widget *w,
0923                struct snd_kcontrol *kcontrol,
0924                int event)
0925 {
0926     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0927     struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
0928
0929     dev_info(priv->dev, "%s(), event 0x%x, rate %d\n",
0930          __func__, event, priv->dl_rate);
0931
0932     switch (event) {
0933     case SND_SOC_DAPM_PRE_PMU:
0934         playback_gpio_set(priv);
0935
0936         /* sdm audio fifo clock power on */
0937         regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006);
0938         /* scrambler clock on enable */
0939         regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1);
0940         /* sdm power on */
0941         regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003);
0942         /* sdm fifo enable */
0943         regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B);
0944         break;
0945     case SND_SOC_DAPM_POST_PMD:
0946         /* DL scrambler disabling sequence */
0947         regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000);
0948         regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0);
0949
0950         playback_gpio_reset(priv);
0951         break;
0952     default:
0953         break;
0954     }
0955
0956     return 0;
0957 }
0958
0959 static int mtk_hp_enable(struct mt6358_priv *priv)
0960 {
0961     /* Pull-down HPL/R to AVSS28_AUD */
0962     hp_pull_down(priv, true);
0963     /* release HP CMFB gate rstb */
0964     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
0965                0x1 << 6, 0x1 << 6);
0966
0967     /* Reduce ESD resistance of AU_REFN */
0968     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000);
0969
0970     /* Set HPR/HPL gain as minimum (~ -40dB) */
0971     regmap_write(priv->regmap, MT6358_ZCD_CON2, DL_GAIN_N_40DB_REG);
0972
0973     /* Turn on DA_600K_NCP_VA18 */
0974     regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001);
0975     /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */
0976     regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c);
0977     /* Toggle RG_DIVCKS_CHG */
0978     regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001);
0979     /* Set NCP soft start mode as default mode: 100us */
0980     regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003);
0981     /* Enable NCP */
0982     regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000);
0983     usleep_range(250, 270);
0984
0985     /* Enable cap-less LDOs (1.5V) */
0986     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
0987                0x1055, 0x1055);
0988     /* Enable NV regulator (-1.2V) */
0989     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001);
0990     usleep_range(100, 120);
0991
0992     /* Disable AUD_ZCD */
0993     hp_zcd_disable(priv);
0994
0995     /* Disable headphone short-circuit protection */
0996     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000);
0997
0998     /* Enable IBIST */
0999     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
1000
1001     /* Set HP DR bias current optimization, 010: 6uA */
1002     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900);
1003     /* Set HP & ZCD bias current optimization */
1004     /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
1005     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
1006     /* Set HPP/N STB enhance circuits */
1007     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033);
1008
1009     /* Enable HP aux output stage */
1010     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x000c);
1011     /* Enable HP aux feedback loop */
1012     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x003c);
1013     /* Enable HP aux CMFB loop */
1014     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00);
1015     /* Enable HP driver bias circuits */
1016     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0);
1017     /* Enable HP driver core circuits */
1018     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0);
1019     /* Short HP main output to HP aux output stage */
1020     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00fc);
1021
1022     /* Enable HP main CMFB loop */
1023     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00);
1024     /* Disable HP aux CMFB loop */
1025     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200);
1026
1027     /* Select CMFB resistor bulk to AC mode */
1028     /* Selec HS/LO cap size (6.5pF default) */
1029     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000);
1030
1031     /* Enable HP main output stage */
1032     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00ff);
1033     /* Enable HPR/L main output stage step by step */
1034     hp_main_output_ramp(priv, true);
1035
1036     /* Reduce HP aux feedback loop gain */
1037     hp_aux_feedback_loop_gain_ramp(priv, true);
1038     /* Disable HP aux feedback loop */
1039     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf);
1040
1041     /* apply volume setting */
1042     headset_volume_ramp(priv,
1043                 DL_GAIN_N_10DB,
1044                 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]);
1045
1046     /* Disable HP aux output stage */
1047     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3);
1048     /* Unshort HP main output to HP aux output stage */
1049     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3f03);
1050     usleep_range(100, 120);
1051
1052     /* Enable AUD_CLK */
1053     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1);
1054     /* Enable Audio DAC  */
1055     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30ff);
1056     /* Enable low-noise mode of DAC */
1057     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0xf201);
1058     usleep_range(100, 120);
1059
1060     /* Switch HPL MUX to audio DAC */
1061     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x32ff);
1062     /* Switch HPR MUX to audio DAC */
1063     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3aff);
1064
1065     /* Disable Pull-down HPL/R to AVSS28_AUD */
1066     hp_pull_down(priv, false);
1067
1068     return 0;
1069 }
1070
1071 static int mtk_hp_disable(struct mt6358_priv *priv)
1072 {
1073     /* Pull-down HPL/R to AVSS28_AUD */
1074     hp_pull_down(priv, true);
1075
1076     /* HPR/HPL mux to open */
1077     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1078                0x0f00, 0x0000);
1079
1080     /* Disable low-noise mode of DAC */
1081     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
1082                0x0001, 0x0000);
1083
1084     /* Disable Audio DAC */
1085     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1086                0x000f, 0x0000);
1087
1088     /* Disable AUD_CLK */
1089     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0);
1090
1091     /* Short HP main output to HP aux output stage */
1092     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3);
1093     /* Enable HP aux output stage */
1094     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf);
1095
1096     /* decrease HPL/R gain to normal gain step by step */
1097     headset_volume_ramp(priv,
1098                 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL],
1099                 DL_GAIN_N_40DB);
1100
1101     /* Enable HP aux feedback loop */
1102     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff);
1103
1104     /* Reduce HP aux feedback loop gain */
1105     hp_aux_feedback_loop_gain_ramp(priv, false);
1106
1107     /* decrease HPR/L main output stage step by step */
1108     hp_main_output_ramp(priv, false);
1109
1110     /* Disable HP main output stage */
1111     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0);
1112
1113     /* Enable HP aux CMFB loop */
1114     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00);
1115
1116     /* Disable HP main CMFB loop */
1117     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00);
1118
1119     /* Unshort HP main output to HP aux output stage */
1120     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
1121                0x3 << 6, 0x0);
1122
1123     /* Disable HP driver core circuits */
1124     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1125                0x3 << 4, 0x0);
1126
1127     /* Disable HP driver bias circuits */
1128     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1129                0x3 << 6, 0x0);
1130
1131     /* Disable HP aux CMFB loop */
1132     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000);
1133
1134     /* Disable HP aux feedback loop */
1135     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
1136                0x3 << 4, 0x0);
1137
1138     /* Disable HP aux output stage */
1139     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
1140                0x3 << 2, 0x0);
1141
1142     /* Disable IBIST */
1143     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12,
1144                0x1 << 8, 0x1 << 8);
1145
1146     /* Disable NV regulator (-1.2V) */
1147     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0);
1148     /* Disable cap-less LDOs (1.5V) */
1149     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1150                0x1055, 0x0);
1151     /* Disable NCP */
1152     regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3,
1153                0x1, 0x1);
1154
1155     /* Increase ESD resistance of AU_REFN */
1156     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON2,
1157                0x1 << 14, 0x0);
1158
1159     /* Set HP CMFB gate rstb */
1160     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
1161                0x1 << 6, 0x0);
1162     /* disable Pull-down HPL/R to AVSS28_AUD */
1163     hp_pull_down(priv, false);
1164
1165     return 0;
1166 }
1167
1168 static int mtk_hp_spk_enable(struct mt6358_priv *priv)
1169 {
1170     /* Pull-down HPL/R to AVSS28_AUD */
1171     hp_pull_down(priv, true);
1172     /* release HP CMFB gate rstb */
1173     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
1174                0x1 << 6, 0x1 << 6);
1175
1176     /* Reduce ESD resistance of AU_REFN */
1177     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000);
1178
1179     /* Set HPR/HPL gain to -10dB */
1180     regmap_write(priv->regmap, MT6358_ZCD_CON2, DL_GAIN_N_10DB_REG);
1181
1182     /* Turn on DA_600K_NCP_VA18 */
1183     regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001);
1184     /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */
1185     regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c);
1186     /* Toggle RG_DIVCKS_CHG */
1187     regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001);
1188     /* Set NCP soft start mode as default mode: 100us */
1189     regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003);
1190     /* Enable NCP */
1191     regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000);
1192     usleep_range(250, 270);
1193
1194     /* Enable cap-less LDOs (1.5V) */
1195     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1196                0x1055, 0x1055);
1197     /* Enable NV regulator (-1.2V) */
1198     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001);
1199     usleep_range(100, 120);
1200
1201     /* Disable AUD_ZCD */
1202     hp_zcd_disable(priv);
1203
1204     /* Disable headphone short-circuit protection */
1205     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000);
1206
1207     /* Enable IBIST */
1208     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
1209
1210     /* Set HP DR bias current optimization, 010: 6uA */
1211     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900);
1212     /* Set HP & ZCD bias current optimization */
1213     /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
1214     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
1215     /* Set HPP/N STB enhance circuits */
1216     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033);
1217
1218     /* Disable Pull-down HPL/R to AVSS28_AUD */
1219     hp_pull_down(priv, false);
1220
1221     /* Enable HP driver bias circuits */
1222     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0);
1223     /* Enable HP driver core circuits */
1224     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0);
1225     /* Enable HP main CMFB loop */
1226     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200);
1227
1228     /* Select CMFB resistor bulk to AC mode */
1229     /* Selec HS/LO cap size (6.5pF default) */
1230     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000);
1231
1232     /* Enable HP main output stage */
1233     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x0003);
1234     /* Enable HPR/L main output stage step by step */
1235     hp_main_output_ramp(priv, true);
1236
1237     /* Set LO gain as minimum (~ -40dB) */
1238     regmap_write(priv->regmap, MT6358_ZCD_CON1, DL_GAIN_N_40DB_REG);
1239     /* apply volume setting */
1240     headset_volume_ramp(priv,
1241                 DL_GAIN_N_10DB,
1242                 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]);
1243
1244     /* Set LO STB enhance circuits */
1245     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0110);
1246     /* Enable LO driver bias circuits */
1247     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0112);
1248     /* Enable LO driver core circuits */
1249     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0113);
1250
1251     /* Set LOL gain to normal gain step by step */
1252     regmap_update_bits(priv->regmap, MT6358_ZCD_CON1,
1253                RG_AUDLOLGAIN_MASK_SFT,
1254                priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] <<
1255                RG_AUDLOLGAIN_SFT);
1256     regmap_update_bits(priv->regmap, MT6358_ZCD_CON1,
1257                RG_AUDLORGAIN_MASK_SFT,
1258                priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] <<
1259                RG_AUDLORGAIN_SFT);
1260
1261     /* Enable AUD_CLK */
1262     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1);
1263     /* Enable Audio DAC  */
1264     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f9);
1265     /* Enable low-noise mode of DAC */
1266     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0201);
1267     /* Switch LOL MUX to audio DAC */
1268     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x011b);
1269     /* Switch HPL/R MUX to Line-out */
1270     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x35f9);
1271
1272     return 0;
1273 }
1274
1275 static int mtk_hp_spk_disable(struct mt6358_priv *priv)
1276 {
1277     /* HPR/HPL mux to open */
1278     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1279                0x0f00, 0x0000);
1280     /* LOL mux to open */
1281     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
1282                0x3 << 2, 0x0000);
1283
1284     /* Disable Audio DAC */
1285     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1286                0x000f, 0x0000);
1287
1288     /* Disable AUD_CLK */
1289     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0);
1290
1291     /* decrease HPL/R gain to normal gain step by step */
1292     headset_volume_ramp(priv,
1293                 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL],
1294                 DL_GAIN_N_40DB);
1295
1296     /* decrease LOL gain to minimum gain step by step */
1297     regmap_update_bits(priv->regmap, MT6358_ZCD_CON1,
1298                DL_GAIN_REG_MASK, DL_GAIN_N_40DB_REG);
1299
1300     /* decrease HPR/L main output stage step by step */
1301     hp_main_output_ramp(priv, false);
1302
1303     /* Disable HP main output stage */
1304     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0);
1305
1306     /* Short HP main output to HP aux output stage */
1307     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3);
1308     /* Enable HP aux output stage */
1309     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf);
1310
1311     /* Enable HP aux feedback loop */
1312     regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff);
1313
1314     /* Reduce HP aux feedback loop gain */
1315     hp_aux_feedback_loop_gain_ramp(priv, false);
1316
1317     /* Disable HP driver core circuits */
1318     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1319                0x3 << 4, 0x0);
1320     /* Disable LO driver core circuits */
1321     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
1322                0x1, 0x0);
1323
1324     /* Disable HP driver bias circuits */
1325     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1326                0x3 << 6, 0x0);
1327     /* Disable LO driver bias circuits */
1328     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
1329                0x1 << 1, 0x0);
1330
1331     /* Disable HP aux CMFB loop */
1332     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
1333                0xff << 8, 0x0000);
1334
1335     /* Disable IBIST */
1336     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12,
1337                0x1 << 8, 0x1 << 8);
1338     /* Disable NV regulator (-1.2V) */
1339     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0);
1340     /* Disable cap-less LDOs (1.5V) */
1341     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 0x1055, 0x0);
1342     /* Disable NCP */
1343     regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x1, 0x1);
1344
1345     /* Set HP CMFB gate rstb */
1346     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
1347                0x1 << 6, 0x0);
1348     /* disable Pull-down HPL/R to AVSS28_AUD */
1349     hp_pull_down(priv, false);
1350
1351     return 0;
1352 }
1353
1354 static int mt_hp_event(struct snd_soc_dapm_widget *w,
1355                struct snd_kcontrol *kcontrol,
1356                int event)
1357 {
1358     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1359     struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1360     unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1361     int device = DEVICE_HP;
1362
1363     dev_info(priv->dev, "%s(), event 0x%x, dev_counter[DEV_HP] %d, mux %u\n",
1364          __func__,
1365          event,
1366          priv->dev_counter[device],
1367          mux);
1368
1369     switch (event) {
1370     case SND_SOC_DAPM_PRE_PMU:
1371         priv->dev_counter[device]++;
1372         if (priv->dev_counter[device] > 1)
1373             break;  /* already enabled, do nothing */
1374         else if (priv->dev_counter[device] <= 0)
1375             dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d <= 0\n",
1376                  __func__,
1377                  priv->dev_counter[device]);
1378
1379         priv->mux_select[MUX_HP_L] = mux;
1380
1381         if (mux == HP_MUX_HP)
1382             mtk_hp_enable(priv);
1383         else if (mux == HP_MUX_HPSPK)
1384             mtk_hp_spk_enable(priv);
1385         break;
1386     case SND_SOC_DAPM_PRE_PMD:
1387         priv->dev_counter[device]--;
1388         if (priv->dev_counter[device] > 0) {
1389             break;  /* still being used, don't close */
1390         } else if (priv->dev_counter[device] < 0) {
1391             dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d < 0\n",
1392                  __func__,
1393                  priv->dev_counter[device]);
1394             priv->dev_counter[device] = 0;
1395             break;
1396         }
1397
1398         if (priv->mux_select[MUX_HP_L] == HP_MUX_HP)
1399             mtk_hp_disable(priv);
1400         else if (priv->mux_select[MUX_HP_L] == HP_MUX_HPSPK)
1401             mtk_hp_spk_disable(priv);
1402
1403         priv->mux_select[MUX_HP_L] = mux;
1404         break;
1405     default:
1406         break;
1407     }
1408
1409     return 0;
1410 }
1411
1412 static int mt_rcv_event(struct snd_soc_dapm_widget *w,
1413             struct snd_kcontrol *kcontrol,
1414             int event)
1415 {
1416     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1417     struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1418
1419     dev_info(priv->dev, "%s(), event 0x%x, mux %u\n",
1420          __func__,
1421          event,
1422          dapm_kcontrol_get_value(w->kcontrols[0]));
1423
1424     switch (event) {
1425     case SND_SOC_DAPM_PRE_PMU:
1426         /* Reduce ESD resistance of AU_REFN */
1427         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000);
1428
1429         /* Turn on DA_600K_NCP_VA18 */
1430         regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001);
1431         /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */
1432         regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c);
1433         /* Toggle RG_DIVCKS_CHG */
1434         regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001);
1435         /* Set NCP soft start mode as default mode: 100us */
1436         regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003);
1437         /* Enable NCP */
1438         regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000);
1439         usleep_range(250, 270);
1440
1441         /* Enable cap-less LDOs (1.5V) */
1442         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1443                    0x1055, 0x1055);
1444         /* Enable NV regulator (-1.2V) */
1445         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001);
1446         usleep_range(100, 120);
1447
1448         /* Disable AUD_ZCD */
1449         hp_zcd_disable(priv);
1450
1451         /* Disable handset short-circuit protection */
1452         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0010);
1453
1454         /* Enable IBIST */
1455         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
1456         /* Set HP DR bias current optimization, 010: 6uA */
1457         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900);
1458         /* Set HP & ZCD bias current optimization */
1459         /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
1460         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
1461         /* Set HS STB enhance circuits */
1462         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0090);
1463
1464         /* Disable HP main CMFB loop */
1465         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000);
1466         /* Select CMFB resistor bulk to AC mode */
1467         /* Selec HS/LO cap size (6.5pF default) */
1468         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000);
1469
1470         /* Enable HS driver bias circuits */
1471         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0092);
1472         /* Enable HS driver core circuits */
1473         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0093);
1474
1475         /* Enable AUD_CLK */
1476         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
1477                    0x1, 0x1);
1478
1479         /* Enable Audio DAC  */
1480         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x0009);
1481         /* Enable low-noise mode of DAC */
1482         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0001);
1483         /* Switch HS MUX to audio DAC */
1484         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x009b);
1485         break;
1486     case SND_SOC_DAPM_PRE_PMD:
1487         /* HS mux to open */
1488         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
1489                    RG_AUDHSMUXINPUTSEL_VAUDP15_MASK_SFT,
1490                    RCV_MUX_OPEN);
1491
1492         /* Disable Audio DAC */
1493         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1494                    0x000f, 0x0000);
1495
1496         /* Disable AUD_CLK */
1497         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
1498                    0x1, 0x0);
1499
1500         /* decrease HS gain to minimum gain step by step */
1501         regmap_write(priv->regmap, MT6358_ZCD_CON3, DL_GAIN_N_40DB);
1502
1503         /* Disable HS driver core circuits */
1504         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
1505                    0x1, 0x0);
1506
1507         /* Disable HS driver bias circuits */
1508         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
1509                    0x1 << 1, 0x0000);
1510
1511         /* Disable HP aux CMFB loop */
1512         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
1513                    0xff << 8, 0x0);
1514
1515         /* Enable HP main CMFB Switch */
1516         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
1517                    0xff << 8, 0x2 << 8);
1518
1519         /* Disable IBIST */
1520         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12,
1521                    0x1 << 8, 0x1 << 8);
1522
1523         /* Disable NV regulator (-1.2V) */
1524         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15,
1525                    0x1, 0x0);
1526         /* Disable cap-less LDOs (1.5V) */
1527         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1528                    0x1055, 0x0);
1529         /* Disable NCP */
1530         regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3,
1531                    0x1, 0x1);
1532         break;
1533     default:
1534         break;
1535     }
1536
1537     return 0;
1538 }
1539
1540 static int mt_aif_out_event(struct snd_soc_dapm_widget *w,
1541                 struct snd_kcontrol *kcontrol,
1542                 int event)
1543 {
1544     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1545     struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1546
1547     dev_dbg(priv->dev, "%s(), event 0x%x, rate %d\n",
1548         __func__, event, priv->ul_rate);
1549
1550     switch (event) {
1551     case SND_SOC_DAPM_PRE_PMU:
1552         capture_gpio_set(priv);
1553         break;
1554     case SND_SOC_DAPM_POST_PMD:
1555         capture_gpio_reset(priv);
1556         break;
1557     default:
1558         break;
1559     }
1560
1561     return 0;
1562 }
1563
1564 static int mt_adc_supply_event(struct snd_soc_dapm_widget *w,
1565                    struct snd_kcontrol *kcontrol,
1566                    int event)
1567 {
1568     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1569     struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1570
1571     dev_dbg(priv->dev, "%s(), event 0x%x\n",
1572         __func__, event);
1573
1574     switch (event) {
1575     case SND_SOC_DAPM_PRE_PMU:
1576         /* Enable audio ADC CLKGEN  */
1577         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
1578                    0x1 << 5, 0x1 << 5);
1579         /* ADC CLK from CLKGEN (13MHz) */
1580         regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON3,
1581                  0x0000);
1582         /* Enable  LCLDO_ENC 1P8V */
1583         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1584                    0x2500, 0x0100);
1585         /* LCLDO_ENC remote sense */
1586         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1587                    0x2500, 0x2500);
1588         break;
1589     case SND_SOC_DAPM_POST_PMD:
1590         /* LCLDO_ENC remote sense off */
1591         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1592                    0x2500, 0x0100);
1593         /* disable LCLDO_ENC 1P8V */
1594         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1595                    0x2500, 0x0000);
1596
1597         /* ADC CLK from CLKGEN (13MHz) */
1598         regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON3, 0x0000);
1599         /* disable audio ADC CLKGEN  */
1600         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
1601                    0x1 << 5, 0x0 << 5);
1602         break;
1603     default:
1604         break;
1605     }
1606
1607     return 0;
1608 }
1609
1610 static int mt6358_amic_enable(struct mt6358_priv *priv)
1611 {
1612     unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE];
1613     unsigned int mux_pga_l = priv->mux_select[MUX_PGA_L];
1614     unsigned int mux_pga_r = priv->mux_select[MUX_PGA_R];
1615
1616     dev_info(priv->dev, "%s(), mux, mic %u, pga l %u, pga r %u\n",
1617          __func__, mic_type, mux_pga_l, mux_pga_r);
1618
1619     if (IS_DCC_BASE(mic_type)) {
1620         /* DCC 50k CLK (from 26M) */
1621         regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1622         regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1623         regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060);
1624         regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2061);
1625         regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG1, 0x0100);
1626     }
1627
1628     /* mic bias 0 */
1629     if (mux_pga_l == PGA_MUX_AIN0 || mux_pga_l == PGA_MUX_AIN2 ||
1630         mux_pga_r == PGA_MUX_AIN0 || mux_pga_r == PGA_MUX_AIN2) {
1631         switch (mic_type) {
1632         case MIC_TYPE_MUX_DCC_ECM_DIFF:
1633             regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
1634                        0xff00, 0x7700);
1635             break;
1636         case MIC_TYPE_MUX_DCC_ECM_SINGLE:
1637             regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
1638                        0xff00, 0x1100);
1639             break;
1640         default:
1641             regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
1642                        0xff00, 0x0000);
1643             break;
1644         }
1645         /* Enable MICBIAS0, MISBIAS0 = 1P9V */
1646         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
1647                    0xff, 0x21);
1648     }
1649
1650     /* mic bias 1 */
1651     if (mux_pga_l == PGA_MUX_AIN1 || mux_pga_r == PGA_MUX_AIN1) {
1652         /* Enable MICBIAS1, MISBIAS1 = 2P6V */
1653         if (mic_type == MIC_TYPE_MUX_DCC_ECM_SINGLE)
1654             regmap_write(priv->regmap,
1655                      MT6358_AUDENC_ANA_CON10, 0x0161);
1656         else
1657             regmap_write(priv->regmap,
1658                      MT6358_AUDENC_ANA_CON10, 0x0061);
1659     }
1660
1661     if (IS_DCC_BASE(mic_type)) {
1662         /* Audio L/R preamplifier DCC precharge */
1663         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1664                    0xf8ff, 0x0004);
1665         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1666                    0xf8ff, 0x0004);
1667     } else {
1668         /* reset reg */
1669         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1670                    0xf8ff, 0x0000);
1671         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1672                    0xf8ff, 0x0000);
1673     }
1674
1675     if (mux_pga_l != PGA_MUX_NONE) {
1676         /* L preamplifier input sel */
1677         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1678                    RG_AUDPREAMPLINPUTSEL_MASK_SFT,
1679                    mux_pga_l << RG_AUDPREAMPLINPUTSEL_SFT);
1680
1681         /* L preamplifier enable */
1682         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1683                    RG_AUDPREAMPLON_MASK_SFT,
1684                    0x1 << RG_AUDPREAMPLON_SFT);
1685
1686         if (IS_DCC_BASE(mic_type)) {
1687             /* L preamplifier DCCEN */
1688             regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1689                        RG_AUDPREAMPLDCCEN_MASK_SFT,
1690                        0x1 << RG_AUDPREAMPLDCCEN_SFT);
1691         }
1692
1693         /* L ADC input sel : L PGA. Enable audio L ADC */
1694         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1695                    RG_AUDADCLINPUTSEL_MASK_SFT,
1696                    ADC_MUX_PREAMPLIFIER <<
1697                    RG_AUDADCLINPUTSEL_SFT);
1698         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1699                    RG_AUDADCLPWRUP_MASK_SFT,
1700                    0x1 << RG_AUDADCLPWRUP_SFT);
1701     }
1702
1703     if (mux_pga_r != PGA_MUX_NONE) {
1704         /* R preamplifier input sel */
1705         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1706                    RG_AUDPREAMPRINPUTSEL_MASK_SFT,
1707                    mux_pga_r << RG_AUDPREAMPRINPUTSEL_SFT);
1708
1709         /* R preamplifier enable */
1710         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1711                    RG_AUDPREAMPRON_MASK_SFT,
1712                    0x1 << RG_AUDPREAMPRON_SFT);
1713
1714         if (IS_DCC_BASE(mic_type)) {
1715             /* R preamplifier DCCEN */
1716             regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1717                        RG_AUDPREAMPRDCCEN_MASK_SFT,
1718                        0x1 << RG_AUDPREAMPRDCCEN_SFT);
1719         }
1720
1721         /* R ADC input sel : R PGA. Enable audio R ADC */
1722         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1723                    RG_AUDADCRINPUTSEL_MASK_SFT,
1724                    ADC_MUX_PREAMPLIFIER <<
1725                    RG_AUDADCRINPUTSEL_SFT);
1726         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1727                    RG_AUDADCRPWRUP_MASK_SFT,
1728                    0x1 << RG_AUDADCRPWRUP_SFT);
1729     }
1730
1731     if (IS_DCC_BASE(mic_type)) {
1732         usleep_range(100, 150);
1733         /* Audio L preamplifier DCC precharge off */
1734         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1735                    RG_AUDPREAMPLDCPRECHARGE_MASK_SFT, 0x0);
1736         /* Audio R preamplifier DCC precharge off */
1737         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1738                    RG_AUDPREAMPRDCPRECHARGE_MASK_SFT, 0x0);
1739
1740         /* Short body to ground in PGA */
1741         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON3,
1742                    0x1 << 12, 0x0);
1743     }
1744
1745     /* here to set digital part */
1746     mt6358_mtkaif_tx_enable(priv);
1747
1748     /* UL dmic setting off */
1749     regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0000);
1750
1751     /* UL turn on */
1752     regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0001);
1753
1754     return 0;
1755 }
1756
1757 static void mt6358_amic_disable(struct mt6358_priv *priv)
1758 {
1759     unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE];
1760     unsigned int mux_pga_l = priv->mux_select[MUX_PGA_L];
1761     unsigned int mux_pga_r = priv->mux_select[MUX_PGA_R];
1762
1763     dev_info(priv->dev, "%s(), mux, mic %u, pga l %u, pga r %u\n",
1764          __func__, mic_type, mux_pga_l, mux_pga_r);
1765
1766     /* UL turn off */
1767     regmap_update_bits(priv->regmap, MT6358_AFE_UL_SRC_CON0_L,
1768                0x0001, 0x0000);
1769
1770     /* disable aud_pad TX fifos */
1771     mt6358_mtkaif_tx_disable(priv);
1772
1773     /* L ADC input sel : off, disable L ADC */
1774     regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1775                0xf000, 0x0000);
1776     /* L preamplifier DCCEN */
1777     regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1778                0x1 << 1, 0x0);
1779     /* L preamplifier input sel : off, L PGA 0 dB gain */
1780     regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1781                0xfffb, 0x0000);
1782
1783     /* disable L preamplifier DCC precharge */
1784     regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1785                0x1 << 2, 0x0);
1786
1787     /* R ADC input sel : off, disable R ADC */
1788     regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1789                0xf000, 0x0000);
1790     /* R preamplifier DCCEN */
1791     regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1792                0x1 << 1, 0x0);
1793     /* R preamplifier input sel : off, R PGA 0 dB gain */
1794     regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1795                0x0ffb, 0x0000);
1796
1797     /* disable R preamplifier DCC precharge */
1798     regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1799                0x1 << 2, 0x0);
1800
1801     /* mic bias */
1802     /* Disable MICBIAS0, MISBIAS0 = 1P7V */
1803     regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000);
1804
1805     /* Disable MICBIAS1 */
1806     regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10,
1807                0x0001, 0x0000);
1808
1809     if (IS_DCC_BASE(mic_type)) {
1810         /* dcclk_gen_on=1'b0 */
1811         regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060);
1812         /* dcclk_pdn=1'b1 */
1813         regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1814         /* dcclk_ref_ck_sel=2'b00 */
1815         regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1816         /* dcclk_div=11'b00100000011 */
1817         regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1818     }
1819 }
1820
1821 static int mt6358_dmic_enable(struct mt6358_priv *priv)
1822 {
1823     dev_info(priv->dev, "%s()\n", __func__);
1824
1825     /* mic bias */
1826     /* Enable MICBIAS0, MISBIAS0 = 1P9V */
1827     regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0021);
1828
1829     /* RG_BANDGAPGEN=1'b0 */
1830     regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10,
1831                0x1 << 12, 0x0);
1832
1833     /* DMIC enable */
1834     regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0005);
1835
1836     /* here to set digital part */
1837     mt6358_mtkaif_tx_enable(priv);
1838
1839     /* UL dmic setting */
1840     if (priv->dmic_one_wire_mode)
1841         regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0400);
1842     else
1843         regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0080);
1844
1845     /* UL turn on */
1846     regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0003);
1847
1848     /* Prevent pop noise form dmic hw */
1849     msleep(100);
1850
1851     return 0;
1852 }
1853
1854 static void mt6358_dmic_disable(struct mt6358_priv *priv)
1855 {
1856     dev_info(priv->dev, "%s()\n", __func__);
1857
1858     /* UL turn off */
1859     regmap_update_bits(priv->regmap, MT6358_AFE_UL_SRC_CON0_L,
1860                0x0003, 0x0000);
1861
1862     /* disable aud_pad TX fifos */
1863     mt6358_mtkaif_tx_disable(priv);
1864
1865     /* DMIC disable */
1866     regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0000);
1867
1868     /* mic bias */
1869     /* MISBIAS0 = 1P7V */
1870     regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0001);
1871
1872     /* RG_BANDGAPGEN=1'b0 */
1873     regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10,
1874                0x1 << 12, 0x0);
1875
1876     /* MICBIA0 disable */
1877     regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000);
1878 }
1879
1880 static void mt6358_restore_pga(struct mt6358_priv *priv)
1881 {
1882     unsigned int gain_l, gain_r;
1883
1884     gain_l = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1];
1885     gain_r = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2];
1886
1887     regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1888                RG_AUDPREAMPLGAIN_MASK_SFT,
1889                gain_l << RG_AUDPREAMPLGAIN_SFT);
1890     regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1891                RG_AUDPREAMPRGAIN_MASK_SFT,
1892                gain_r << RG_AUDPREAMPRGAIN_SFT);
1893 }
1894
1895 static int mt_mic_type_event(struct snd_soc_dapm_widget *w,
1896                  struct snd_kcontrol *kcontrol,
1897                  int event)
1898 {
1899     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1900     struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1901     unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1902
1903     dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n",
1904         __func__, event, mux);
1905
1906     switch (event) {
1907     case SND_SOC_DAPM_WILL_PMU:
1908         priv->mux_select[MUX_MIC_TYPE] = mux;
1909         break;
1910     case SND_SOC_DAPM_PRE_PMU:
1911         switch (mux) {
1912         case MIC_TYPE_MUX_DMIC:
1913             mt6358_dmic_enable(priv);
1914             break;
1915         default:
1916             mt6358_amic_enable(priv);
1917             break;
1918         }
1919         mt6358_restore_pga(priv);
1920
1921         break;
1922     case SND_SOC_DAPM_POST_PMD:
1923         switch (priv->mux_select[MUX_MIC_TYPE]) {
1924         case MIC_TYPE_MUX_DMIC:
1925             mt6358_dmic_disable(priv);
1926             break;
1927         default:
1928             mt6358_amic_disable(priv);
1929             break;
1930         }
1931
1932         priv->mux_select[MUX_MIC_TYPE] = mux;
1933         break;
1934     default:
1935         break;
1936     }
1937
1938     return 0;
1939 }
1940
1941 static int mt_adc_l_event(struct snd_soc_dapm_widget *w,
1942               struct snd_kcontrol *kcontrol,
1943               int event)
1944 {
1945     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1946     struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1947     unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1948
1949     dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
1950         __func__, event, mux);
1951
1952     priv->mux_select[MUX_ADC_L] = mux;
1953
1954     return 0;
1955 }
1956
1957 static int mt_adc_r_event(struct snd_soc_dapm_widget *w,
1958               struct snd_kcontrol *kcontrol,
1959               int event)
1960 {
1961     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1962     struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1963     unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1964
1965     dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
1966         __func__, event, mux);
1967
1968     priv->mux_select[MUX_ADC_R] = mux;
1969
1970     return 0;
1971 }
1972
1973 static int mt_pga_left_event(struct snd_soc_dapm_widget *w,
1974                  struct snd_kcontrol *kcontrol,
1975                  int event)
1976 {
1977     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1978     struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1979     unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1980
1981     dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
1982         __func__, event, mux);
1983
1984     priv->mux_select[MUX_PGA_L] = mux;
1985
1986     return 0;
1987 }
1988
1989 static int mt_pga_right_event(struct snd_soc_dapm_widget *w,
1990                   struct snd_kcontrol *kcontrol,
1991                   int event)
1992 {
1993     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1994     struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1995     unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1996
1997     dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
1998         __func__, event, mux);
1999
2000     priv->mux_select[MUX_PGA_R] = mux;
2001
2002     return 0;
2003 }
2004
2005 static int mt_delay_250_event(struct snd_soc_dapm_widget *w,
2006                   struct snd_kcontrol *kcontrol,
2007                   int event)
2008 {
2009     switch (event) {
2010     case SND_SOC_DAPM_POST_PMU:
2011         usleep_range(250, 270);
2012         break;
2013     case SND_SOC_DAPM_PRE_PMD:
2014         usleep_range(250, 270);
2015         break;
2016     default:
2017         break;
2018     }
2019
2020     return 0;
2021 }
2022
2023 /* DAPM Widgets */
2024 static const struct snd_soc_dapm_widget mt6358_dapm_widgets[] = {
2025     /* Global Supply*/
2026     SND_SOC_DAPM_SUPPLY_S("CLK_BUF", SUPPLY_SEQ_CLK_BUF,
2027                   MT6358_DCXO_CW14,
2028                   RG_XO_AUDIO_EN_M_SFT, 0, NULL, 0),
2029     SND_SOC_DAPM_SUPPLY_S("AUDGLB", SUPPLY_SEQ_AUD_GLB,
2030                   MT6358_AUDDEC_ANA_CON13,
2031                   RG_AUDGLB_PWRDN_VA28_SFT, 1, NULL, 0),
2032     SND_SOC_DAPM_SUPPLY_S("CLKSQ Audio", SUPPLY_SEQ_CLKSQ,
2033                   MT6358_AUDENC_ANA_CON6,
2034                   RG_CLKSQ_EN_SFT, 0,
2035                   mt_clksq_event,
2036                   SND_SOC_DAPM_PRE_PMU),
2037     SND_SOC_DAPM_SUPPLY_S("AUDNCP_CK", SUPPLY_SEQ_TOP_CK,
2038                   MT6358_AUD_TOP_CKPDN_CON0,
2039                   RG_AUDNCP_CK_PDN_SFT, 1, NULL, 0),
2040     SND_SOC_DAPM_SUPPLY_S("ZCD13M_CK", SUPPLY_SEQ_TOP_CK,
2041                   MT6358_AUD_TOP_CKPDN_CON0,
2042                   RG_ZCD13M_CK_PDN_SFT, 1, NULL, 0),
2043     SND_SOC_DAPM_SUPPLY_S("AUD_CK", SUPPLY_SEQ_TOP_CK_LAST,
2044                   MT6358_AUD_TOP_CKPDN_CON0,
2045                   RG_AUD_CK_PDN_SFT, 1,
2046                   mt_delay_250_event,
2047                   SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2048     SND_SOC_DAPM_SUPPLY_S("AUDIF_CK", SUPPLY_SEQ_TOP_CK,
2049                   MT6358_AUD_TOP_CKPDN_CON0,
2050                   RG_AUDIF_CK_PDN_SFT, 1, NULL, 0),
2051
2052     /* Digital Clock */
2053     SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_AFE_CTL", SUPPLY_SEQ_AUD_TOP_LAST,
2054                   MT6358_AUDIO_TOP_CON0,
2055                   PDN_AFE_CTL_SFT, 1,
2056                   mt_delay_250_event,
2057                   SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2058     SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_DAC_CTL", SUPPLY_SEQ_AUD_TOP,
2059                   MT6358_AUDIO_TOP_CON0,
2060                   PDN_DAC_CTL_SFT, 1, NULL, 0),
2061     SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_ADC_CTL", SUPPLY_SEQ_AUD_TOP,
2062                   MT6358_AUDIO_TOP_CON0,
2063                   PDN_ADC_CTL_SFT, 1, NULL, 0),
2064     SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_I2S_DL", SUPPLY_SEQ_AUD_TOP,
2065                   MT6358_AUDIO_TOP_CON0,
2066                   PDN_I2S_DL_CTL_SFT, 1, NULL, 0),
2067     SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PWR_CLK", SUPPLY_SEQ_AUD_TOP,
2068                   MT6358_AUDIO_TOP_CON0,
2069                   PWR_CLK_DIS_CTL_SFT, 1, NULL, 0),
2070     SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_AFE_TESTMODEL", SUPPLY_SEQ_AUD_TOP,
2071                   MT6358_AUDIO_TOP_CON0,
2072                   PDN_AFE_TESTMODEL_CTL_SFT, 1, NULL, 0),
2073     SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_RESERVED", SUPPLY_SEQ_AUD_TOP,
2074                   MT6358_AUDIO_TOP_CON0,
2075                   PDN_RESERVED_SFT, 1, NULL, 0),
2076
2077     SND_SOC_DAPM_SUPPLY("DL Digital Clock", SND_SOC_NOPM,
2078                 0, 0, NULL, 0),
2079
2080     /* AFE ON */
2081     SND_SOC_DAPM_SUPPLY_S("AFE_ON", SUPPLY_SEQ_AFE,
2082                   MT6358_AFE_UL_DL_CON0, AFE_ON_SFT, 0,
2083                   NULL, 0),
2084
2085     /* AIF Rx*/
2086     SND_SOC_DAPM_AIF_IN_E("AIF_RX", "AIF1 Playback", 0,
2087                   MT6358_AFE_DL_SRC2_CON0_L,
2088                   DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
2089                   mt_aif_in_event,
2090                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2091
2092     /* DL Supply */
2093     SND_SOC_DAPM_SUPPLY("DL Power Supply", SND_SOC_NOPM,
2094                 0, 0, NULL, 0),
2095
2096     /* DAC */
2097     SND_SOC_DAPM_MUX("DAC In Mux", SND_SOC_NOPM, 0, 0, &dac_in_mux_control),
2098
2099     SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0),
2100
2101     SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0),
2102
2103     /* LOL */
2104     SND_SOC_DAPM_MUX("LOL Mux", SND_SOC_NOPM, 0, 0, &lo_in_mux_control),
2105
2106     SND_SOC_DAPM_SUPPLY("LO Stability Enh", MT6358_AUDDEC_ANA_CON7,
2107                 RG_LOOUTPUTSTBENH_VAUDP15_SFT, 0, NULL, 0),
2108
2109     SND_SOC_DAPM_OUT_DRV("LOL Buffer", MT6358_AUDDEC_ANA_CON7,
2110                  RG_AUDLOLPWRUP_VAUDP15_SFT, 0, NULL, 0),
2111
2112     /* Headphone */
2113     SND_SOC_DAPM_MUX_E("HPL Mux", SND_SOC_NOPM, 0, 0,
2114                &hpl_in_mux_control,
2115                mt_hp_event,
2116                SND_SOC_DAPM_PRE_PMU |
2117                SND_SOC_DAPM_PRE_PMD),
2118
2119     SND_SOC_DAPM_MUX_E("HPR Mux", SND_SOC_NOPM, 0, 0,
2120                &hpr_in_mux_control,
2121                mt_hp_event,
2122                SND_SOC_DAPM_PRE_PMU |
2123                SND_SOC_DAPM_PRE_PMD),
2124
2125     /* Receiver */
2126     SND_SOC_DAPM_MUX_E("RCV Mux", SND_SOC_NOPM, 0, 0,
2127                &rcv_in_mux_control,
2128                mt_rcv_event,
2129                SND_SOC_DAPM_PRE_PMU |
2130                SND_SOC_DAPM_PRE_PMD),
2131
2132     /* Outputs */
2133     SND_SOC_DAPM_OUTPUT("Receiver"),
2134     SND_SOC_DAPM_OUTPUT("Headphone L"),
2135     SND_SOC_DAPM_OUTPUT("Headphone R"),
2136     SND_SOC_DAPM_OUTPUT("Headphone L Ext Spk Amp"),
2137     SND_SOC_DAPM_OUTPUT("Headphone R Ext Spk Amp"),
2138     SND_SOC_DAPM_OUTPUT("LINEOUT L"),
2139     SND_SOC_DAPM_OUTPUT("LINEOUT L HSSPK"),
2140
2141     /* SGEN */
2142     SND_SOC_DAPM_SUPPLY("SGEN DL Enable", MT6358_AFE_SGEN_CFG0,
2143                 SGEN_DAC_EN_CTL_SFT, 0, NULL, 0),
2144     SND_SOC_DAPM_SUPPLY("SGEN MUTE", MT6358_AFE_SGEN_CFG0,
2145                 SGEN_MUTE_SW_CTL_SFT, 1,
2146                 mt_sgen_event,
2147                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2148     SND_SOC_DAPM_SUPPLY("SGEN DL SRC", MT6358_AFE_DL_SRC2_CON0_L,
2149                 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, NULL, 0),
2150
2151     SND_SOC_DAPM_INPUT("SGEN DL"),
2152
2153     /* Uplinks */
2154     SND_SOC_DAPM_AIF_OUT_E("AIF1TX", "AIF1 Capture", 0,
2155                    SND_SOC_NOPM, 0, 0,
2156                    mt_aif_out_event,
2157                    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2158
2159     SND_SOC_DAPM_SUPPLY_S("ADC Supply", SUPPLY_SEQ_ADC_SUPPLY,
2160                   SND_SOC_NOPM, 0, 0,
2161                   mt_adc_supply_event,
2162                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2163
2164     /* Uplinks MUX */
2165     SND_SOC_DAPM_MUX("AIF Out Mux", SND_SOC_NOPM, 0, 0,
2166              &aif_out_mux_control),
2167
2168     SND_SOC_DAPM_MUX_E("Mic Type Mux", SND_SOC_NOPM, 0, 0,
2169                &mic_type_mux_control,
2170                mt_mic_type_event,
2171                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD |
2172                SND_SOC_DAPM_WILL_PMU),
2173
2174     SND_SOC_DAPM_MUX_E("ADC L Mux", SND_SOC_NOPM, 0, 0,
2175                &adc_left_mux_control,
2176                mt_adc_l_event,
2177                SND_SOC_DAPM_WILL_PMU),
2178     SND_SOC_DAPM_MUX_E("ADC R Mux", SND_SOC_NOPM, 0, 0,
2179                &adc_right_mux_control,
2180                mt_adc_r_event,
2181                SND_SOC_DAPM_WILL_PMU),
2182
2183     SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
2184     SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
2185
2186     SND_SOC_DAPM_MUX_E("PGA L Mux", SND_SOC_NOPM, 0, 0,
2187                &pga_left_mux_control,
2188                mt_pga_left_event,
2189                SND_SOC_DAPM_WILL_PMU),
2190     SND_SOC_DAPM_MUX_E("PGA R Mux", SND_SOC_NOPM, 0, 0,
2191                &pga_right_mux_control,
2192                mt_pga_right_event,
2193                SND_SOC_DAPM_WILL_PMU),
2194
2195     SND_SOC_DAPM_PGA("PGA L", SND_SOC_NOPM, 0, 0, NULL, 0),
2196     SND_SOC_DAPM_PGA("PGA R", SND_SOC_NOPM, 0, 0, NULL, 0),
2197
2198     /* UL input */
2199     SND_SOC_DAPM_INPUT("AIN0"),
2200     SND_SOC_DAPM_INPUT("AIN1"),
2201     SND_SOC_DAPM_INPUT("AIN2"),
2202 };
2203
2204 static const struct snd_soc_dapm_route mt6358_dapm_routes[] = {
2205     /* Capture */
2206     {"AIF1TX", NULL, "AIF Out Mux"},
2207     {"AIF1TX", NULL, "CLK_BUF"},
2208     {"AIF1TX", NULL, "AUDGLB"},
2209     {"AIF1TX", NULL, "CLKSQ Audio"},
2210
2211     {"AIF1TX", NULL, "AUD_CK"},
2212     {"AIF1TX", NULL, "AUDIF_CK"},
2213
2214     {"AIF1TX", NULL, "AUDIO_TOP_AFE_CTL"},
2215     {"AIF1TX", NULL, "AUDIO_TOP_ADC_CTL"},
2216     {"AIF1TX", NULL, "AUDIO_TOP_PWR_CLK"},
2217     {"AIF1TX", NULL, "AUDIO_TOP_PDN_RESERVED"},
2218     {"AIF1TX", NULL, "AUDIO_TOP_I2S_DL"},
2219
2220     {"AIF1TX", NULL, "AFE_ON"},
2221
2222     {"AIF Out Mux", NULL, "Mic Type Mux"},
2223
2224     {"Mic Type Mux", "ACC", "ADC L"},
2225     {"Mic Type Mux", "ACC", "ADC R"},
2226     {"Mic Type Mux", "DCC", "ADC L"},
2227     {"Mic Type Mux", "DCC", "ADC R"},
2228     {"Mic Type Mux", "DCC_ECM_DIFF", "ADC L"},
2229     {"Mic Type Mux", "DCC_ECM_DIFF", "ADC R"},
2230     {"Mic Type Mux", "DCC_ECM_SINGLE", "ADC L"},
2231     {"Mic Type Mux", "DCC_ECM_SINGLE", "ADC R"},
2232     {"Mic Type Mux", "DMIC", "AIN0"},
2233     {"Mic Type Mux", "DMIC", "AIN2"},
2234
2235     {"ADC L", NULL, "ADC L Mux"},
2236     {"ADC L", NULL, "ADC Supply"},
2237     {"ADC R", NULL, "ADC R Mux"},
2238     {"ADC R", NULL, "ADC Supply"},
2239
2240     {"ADC L Mux", "Left Preamplifier", "PGA L"},
2241
2242     {"ADC R Mux", "Right Preamplifier", "PGA R"},
2243
2244     {"PGA L", NULL, "PGA L Mux"},
2245     {"PGA R", NULL, "PGA R Mux"},
2246
2247     {"PGA L Mux", "AIN0", "AIN0"},
2248     {"PGA L Mux", "AIN1", "AIN1"},
2249     {"PGA L Mux", "AIN2", "AIN2"},
2250
2251     {"PGA R Mux", "AIN0", "AIN0"},
2252     {"PGA R Mux", "AIN1", "AIN1"},
2253     {"PGA R Mux", "AIN2", "AIN2"},
2254
2255     /* DL Supply */
2256     {"DL Power Supply", NULL, "CLK_BUF"},
2257     {"DL Power Supply", NULL, "AUDGLB"},
2258     {"DL Power Supply", NULL, "CLKSQ Audio"},
2259
2260     {"DL Power Supply", NULL, "AUDNCP_CK"},
2261     {"DL Power Supply", NULL, "ZCD13M_CK"},
2262     {"DL Power Supply", NULL, "AUD_CK"},
2263     {"DL Power Supply", NULL, "AUDIF_CK"},
2264
2265     /* DL Digital Supply */
2266     {"DL Digital Clock", NULL, "AUDIO_TOP_AFE_CTL"},
2267     {"DL Digital Clock", NULL, "AUDIO_TOP_DAC_CTL"},
2268     {"DL Digital Clock", NULL, "AUDIO_TOP_PWR_CLK"},
2269
2270     {"DL Digital Clock", NULL, "AFE_ON"},
2271
2272     {"AIF_RX", NULL, "DL Digital Clock"},
2273
2274     /* DL Path */
2275     {"DAC In Mux", "Normal Path", "AIF_RX"},
2276
2277     {"DAC In Mux", "Sgen", "SGEN DL"},
2278     {"SGEN DL", NULL, "SGEN DL SRC"},
2279     {"SGEN DL", NULL, "SGEN MUTE"},
2280     {"SGEN DL", NULL, "SGEN DL Enable"},
2281     {"SGEN DL", NULL, "DL Digital Clock"},
2282     {"SGEN DL", NULL, "AUDIO_TOP_PDN_AFE_TESTMODEL"},
2283
2284     {"DACL", NULL, "DAC In Mux"},
2285     {"DACL", NULL, "DL Power Supply"},
2286
2287     {"DACR", NULL, "DAC In Mux"},
2288     {"DACR", NULL, "DL Power Supply"},
2289
2290     /* Lineout Path */
2291     {"LOL Mux", "Playback", "DACL"},
2292
2293     {"LOL Buffer", NULL, "LOL Mux"},
2294     {"LOL Buffer", NULL, "LO Stability Enh"},
2295
2296     {"LINEOUT L", NULL, "LOL Buffer"},
2297
2298     /* Headphone Path */
2299     {"HPL Mux", "Audio Playback", "DACL"},
2300     {"HPR Mux", "Audio Playback", "DACR"},
2301     {"HPL Mux", "HP Impedance", "DACL"},
2302     {"HPR Mux", "HP Impedance", "DACR"},
2303     {"HPL Mux", "LoudSPK Playback", "DACL"},
2304     {"HPR Mux", "LoudSPK Playback", "DACR"},
2305
2306     {"Headphone L", NULL, "HPL Mux"},
2307     {"Headphone R", NULL, "HPR Mux"},
2308     {"Headphone L Ext Spk Amp", NULL, "HPL Mux"},
2309     {"Headphone R Ext Spk Amp", NULL, "HPR Mux"},
2310     {"LINEOUT L HSSPK", NULL, "HPL Mux"},
2311
2312     /* Receiver Path */
2313     {"RCV Mux", "Voice Playback", "DACL"},
2314     {"Receiver", NULL, "RCV Mux"},
2315 };
2316
2317 static int mt6358_codec_dai_hw_params(struct snd_pcm_substream *substream,
2318                       struct snd_pcm_hw_params *params,
2319                       struct snd_soc_dai *dai)
2320 {
2321     struct snd_soc_component *cmpnt = dai->component;
2322     struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2323     unsigned int rate = params_rate(params);
2324
2325     dev_info(priv->dev, "%s(), substream->stream %d, rate %d, number %d\n",
2326          __func__,
2327          substream->stream,
2328          rate,
2329          substream->number);
2330
2331     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2332         priv->dl_rate = rate;
2333     else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2334         priv->ul_rate = rate;
2335
2336     return 0;
2337 }
2338
2339 static const struct snd_soc_dai_ops mt6358_codec_dai_ops = {
2340     .hw_params = mt6358_codec_dai_hw_params,
2341 };
2342
2343 #define MT6358_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE |\
2344             SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_U24_LE |\
2345             SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_U32_LE)
2346
2347 static struct snd_soc_dai_driver mt6358_dai_driver[] = {
2348     {
2349         .name = "mt6358-snd-codec-aif1",
2350         .playback = {
2351             .stream_name = "AIF1 Playback",
2352             .channels_min = 1,
2353             .channels_max = 2,
2354             .rates = SNDRV_PCM_RATE_8000_48000 |
2355                  SNDRV_PCM_RATE_96000 |
2356                  SNDRV_PCM_RATE_192000,
2357             .formats = MT6358_FORMATS,
2358         },
2359         .capture = {
2360             .stream_name = "AIF1 Capture",
2361             .channels_min = 1,
2362             .channels_max = 2,
2363             .rates = SNDRV_PCM_RATE_8000 |
2364                  SNDRV_PCM_RATE_16000 |
2365                  SNDRV_PCM_RATE_32000 |
2366                  SNDRV_PCM_RATE_48000,
2367             .formats = MT6358_FORMATS,
2368         },
2369         .ops = &mt6358_codec_dai_ops,
2370     },
2371 };
2372
2373 static void mt6358_codec_init_reg(struct mt6358_priv *priv)
2374 {
2375     /* Disable HeadphoneL/HeadphoneR short circuit protection */
2376     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
2377                RG_AUDHPLSCDISABLE_VAUDP15_MASK_SFT,
2378                0x1 << RG_AUDHPLSCDISABLE_VAUDP15_SFT);
2379     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
2380                RG_AUDHPRSCDISABLE_VAUDP15_MASK_SFT,
2381                0x1 << RG_AUDHPRSCDISABLE_VAUDP15_SFT);
2382     /* Disable voice short circuit protection */
2383     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
2384                RG_AUDHSSCDISABLE_VAUDP15_MASK_SFT,
2385                0x1 << RG_AUDHSSCDISABLE_VAUDP15_SFT);
2386     /* disable LO buffer left short circuit protection */
2387     regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
2388                RG_AUDLOLSCDISABLE_VAUDP15_MASK_SFT,
2389                0x1 << RG_AUDLOLSCDISABLE_VAUDP15_SFT);
2390
2391     /* accdet s/w enable */
2392     regmap_update_bits(priv->regmap, MT6358_ACCDET_CON13,
2393                0xFFFF, 0x700E);
2394
2395     /* gpio miso driving set to 4mA */
2396     regmap_write(priv->regmap, MT6358_DRV_CON3, 0x8888);
2397
2398     /* set gpio */
2399     playback_gpio_reset(priv);
2400     capture_gpio_reset(priv);
2401 }
2402
2403 static int mt6358_codec_probe(struct snd_soc_component *cmpnt)
2404 {
2405     struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2406     int ret;
2407
2408     snd_soc_component_init_regmap(cmpnt, priv->regmap);
2409
2410     mt6358_codec_init_reg(priv);
2411
2412     priv->avdd_reg = devm_regulator_get(priv->dev, "Avdd");
2413     if (IS_ERR(priv->avdd_reg)) {
2414         dev_err(priv->dev, "%s() have no Avdd supply", __func__);
2415         return PTR_ERR(priv->avdd_reg);
2416     }
2417
2418     ret = regulator_enable(priv->avdd_reg);
2419     if (ret)
2420         return  ret;
2421
2422     return 0;
2423 }
2424
2425 static const struct snd_soc_component_driver mt6358_soc_component_driver = {
2426     .probe = mt6358_codec_probe,
2427     .controls = mt6358_snd_controls,
2428     .num_controls = ARRAY_SIZE(mt6358_snd_controls),
2429     .dapm_widgets = mt6358_dapm_widgets,
2430     .num_dapm_widgets = ARRAY_SIZE(mt6358_dapm_widgets),
2431     .dapm_routes = mt6358_dapm_routes,
2432     .num_dapm_routes = ARRAY_SIZE(mt6358_dapm_routes),
2433     .endianness = 1,
2434 };
2435
2436 static void mt6358_parse_dt(struct mt6358_priv *priv)
2437 {
2438     int ret;
2439     struct device *dev = priv->dev;
2440
2441     ret = of_property_read_u32(dev->of_node, "mediatek,dmic-mode",
2442                    &priv->dmic_one_wire_mode);
2443     if (ret) {
2444         dev_warn(priv->dev, "%s() failed to read dmic-mode\n",
2445              __func__);
2446         priv->dmic_one_wire_mode = 0;
2447     }
2448 }
2449
2450 static int mt6358_platform_driver_probe(struct platform_device *pdev)
2451 {
2452     struct mt6358_priv *priv;
2453     struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
2454
2455     priv = devm_kzalloc(&pdev->dev,
2456                 sizeof(struct mt6358_priv),
2457                 GFP_KERNEL);
2458     if (!priv)
2459         return -ENOMEM;
2460
2461     dev_set_drvdata(&pdev->dev, priv);
2462
2463     priv->dev = &pdev->dev;
2464
2465     priv->regmap = mt6397->regmap;
2466     if (IS_ERR(priv->regmap))
2467         return PTR_ERR(priv->regmap);
2468
2469     mt6358_parse_dt(priv);
2470
2471     dev_info(priv->dev, "%s(), dev name %s\n",
2472          __func__, dev_name(&pdev->dev));
2473
2474     return devm_snd_soc_register_component(&pdev->dev,
2475                       &mt6358_soc_component_driver,
2476                       mt6358_dai_driver,
2477                       ARRAY_SIZE(mt6358_dai_driver));
2478 }
2479
2480 static const struct of_device_id mt6358_of_match[] = {
2481     {.compatible = "mediatek,mt6358-sound",},
2482     {.compatible = "mediatek,mt6366-sound",},
2483     {}
2484 };
2485 MODULE_DEVICE_TABLE(of, mt6358_of_match);
2486
2487 static struct platform_driver mt6358_platform_driver = {
2488     .driver = {
2489         .name = "mt6358-sound",
2490         .of_match_table = mt6358_of_match,
2491     },
2492     .probe = mt6358_platform_driver_probe,
2493 };
2494
2495 module_platform_driver(mt6358_platform_driver)
2496
2497 /* Module information */
2498 MODULE_DESCRIPTION("MT6358 ALSA SoC codec driver");
2499 MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>");
2500 MODULE_LICENSE("GPL v2");