soc/codecs/mt6351.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * mt6351.h  --  mt6351 ALSA SoC audio codec driver
0004  *
0005  * Copyright (c) 2018 MediaTek Inc.
0006  * Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
0007  */
0008
0009 #ifndef __MT6351_H__
0010 #define __MT6351_H__
0011
0012 #define MT6351_AFE_UL_DL_CON0               (0x2000 + 0x0000)
0013 #define MT6351_AFE_DL_SRC2_CON0_H           (0x2000 + 0x0002)
0014 #define MT6351_AFE_DL_SRC2_CON0_L           (0x2000 + 0x0004)
0015 #define MT6351_AFE_DL_SDM_CON0              (0x2000 + 0x0006)
0016 #define MT6351_AFE_DL_SDM_CON1              (0x2000 + 0x0008)
0017 #define MT6351_AFE_UL_SRC_CON0_H            (0x2000 + 0x000a)
0018 #define MT6351_AFE_UL_SRC_CON0_L            (0x2000 + 0x000c)
0019 #define MT6351_AFE_UL_SRC_CON1_H            (0x2000 + 0x000e)
0020 #define MT6351_AFE_UL_SRC_CON1_L            (0x2000 + 0x0010)
0021 #define MT6351_AFE_TOP_CON0                 (0x2000 + 0x0012)
0022 #define MT6351_AUDIO_TOP_CON0               (0x2000 + 0x0014)
0023 #define MT6351_AFE_DL_SRC_MON0              (0x2000 + 0x0016)
0024 #define MT6351_AFE_DL_SDM_TEST0             (0x2000 + 0x0018)
0025 #define MT6351_AFE_MON_DEBUG0               (0x2000 + 0x001a)
0026 #define MT6351_AFUNC_AUD_CON0               (0x2000 + 0x001c)
0027 #define MT6351_AFUNC_AUD_CON1               (0x2000 + 0x001e)
0028 #define MT6351_AFUNC_AUD_CON2               (0x2000 + 0x0020)
0029 #define MT6351_AFUNC_AUD_CON3               (0x2000 + 0x0022)
0030 #define MT6351_AFUNC_AUD_CON4               (0x2000 + 0x0024)
0031 #define MT6351_AFUNC_AUD_MON0               (0x2000 + 0x0026)
0032 #define MT6351_AFUNC_AUD_MON1               (0x2000 + 0x0028)
0033 #define MT6351_AFE_UP8X_FIFO_CFG0           (0x2000 + 0x002c)
0034 #define MT6351_AFE_UP8X_FIFO_LOG_MON0       (0x2000 + 0x002e)
0035 #define MT6351_AFE_UP8X_FIFO_LOG_MON1       (0x2000 + 0x0030)
0036 #define MT6351_AFE_DL_DC_COMP_CFG0          (0x2000 + 0x0032)
0037 #define MT6351_AFE_DL_DC_COMP_CFG1          (0x2000 + 0x0034)
0038 #define MT6351_AFE_DL_DC_COMP_CFG2          (0x2000 + 0x0036)
0039 #define MT6351_AFE_PMIC_NEWIF_CFG0          (0x2000 + 0x0038)
0040 #define MT6351_AFE_PMIC_NEWIF_CFG1          (0x2000 + 0x003a)
0041 #define MT6351_AFE_PMIC_NEWIF_CFG2          (0x2000 + 0x003c)
0042 #define MT6351_AFE_PMIC_NEWIF_CFG3          (0x2000 + 0x003e)
0043 #define MT6351_AFE_SGEN_CFG0                (0x2000 + 0x0040)
0044 #define MT6351_AFE_SGEN_CFG1                (0x2000 + 0x0042)
0045 #define MT6351_AFE_ADDA2_UP8X_FIFO_LOG_MON0 (0x2000 + 0x004c)
0046 #define MT6351_AFE_ADDA2_UP8X_FIFO_LOG_MON1 (0x2000 + 0x004e)
0047 #define MT6351_AFE_ADDA2_PMIC_NEWIF_CFG0    (0x2000 + 0x0050)
0048 #define MT6351_AFE_ADDA2_PMIC_NEWIF_CFG1    (0x2000 + 0x0052)
0049 #define MT6351_AFE_ADDA2_PMIC_NEWIF_CFG2    (0x2000 + 0x0054)
0050 #define MT6351_AFE_DCCLK_CFG0               (0x2000 + 0x0090)
0051 #define MT6351_AFE_DCCLK_CFG1               (0x2000 + 0x0092)
0052 #define MT6351_AFE_HPANC_CFG0               (0x2000 + 0x0094)
0053 #define MT6351_AFE_NCP_CFG0                 (0x2000 + 0x0096)
0054 #define MT6351_AFE_NCP_CFG1                 (0x2000 + 0x0098)
0055
0056 #define MT6351_TOP_CKPDN_CON0      0x023A
0057 #define MT6351_TOP_CKPDN_CON0_SET  0x023C
0058 #define MT6351_TOP_CKPDN_CON0_CLR  0x023E
0059
0060 #define MT6351_TOP_CLKSQ           0x029A
0061 #define MT6351_TOP_CLKSQ_SET       0x029C
0062 #define MT6351_TOP_CLKSQ_CLR       0x029E
0063
0064 #define MT6351_ZCD_CON0            0x0800
0065 #define MT6351_ZCD_CON1            0x0802
0066 #define MT6351_ZCD_CON2            0x0804
0067 #define MT6351_ZCD_CON3            0x0806
0068 #define MT6351_ZCD_CON4            0x0808
0069 #define MT6351_ZCD_CON5            0x080A
0070
0071 #define MT6351_LDO_VA18_CON0       0x0A00
0072 #define MT6351_LDO_VA18_CON1       0x0A02
0073 #define MT6351_LDO_VUSB33_CON0     0x0A16
0074 #define MT6351_LDO_VUSB33_CON1     0x0A18
0075
0076 #define MT6351_AUDDEC_ANA_CON0     0x0CF2
0077 #define MT6351_AUDDEC_ANA_CON1     0x0CF4
0078 #define MT6351_AUDDEC_ANA_CON2     0x0CF6
0079 #define MT6351_AUDDEC_ANA_CON3     0x0CF8
0080 #define MT6351_AUDDEC_ANA_CON4     0x0CFA
0081 #define MT6351_AUDDEC_ANA_CON5     0x0CFC
0082 #define MT6351_AUDDEC_ANA_CON6     0x0CFE
0083 #define MT6351_AUDDEC_ANA_CON7     0x0D00
0084 #define MT6351_AUDDEC_ANA_CON8     0x0D02
0085 #define MT6351_AUDDEC_ANA_CON9     0x0D04
0086 #define MT6351_AUDDEC_ANA_CON10    0x0D06
0087
0088 #define MT6351_AUDENC_ANA_CON0     0x0D08
0089 #define MT6351_AUDENC_ANA_CON1     0x0D0A
0090 #define MT6351_AUDENC_ANA_CON2     0x0D0C
0091 #define MT6351_AUDENC_ANA_CON3     0x0D0E
0092 #define MT6351_AUDENC_ANA_CON4     0x0D10
0093 #define MT6351_AUDENC_ANA_CON5     0x0D12
0094 #define MT6351_AUDENC_ANA_CON6     0x0D14
0095 #define MT6351_AUDENC_ANA_CON7     0x0D16
0096 #define MT6351_AUDENC_ANA_CON8     0x0D18
0097 #define MT6351_AUDENC_ANA_CON9     0x0D1A
0098 #define MT6351_AUDENC_ANA_CON10    0x0D1C
0099 #define MT6351_AUDENC_ANA_CON11    0x0D1E
0100 #define MT6351_AUDENC_ANA_CON12    0x0D20
0101 #define MT6351_AUDENC_ANA_CON13    0x0D22
0102 #define MT6351_AUDENC_ANA_CON14    0x0D24
0103 #define MT6351_AUDENC_ANA_CON15    0x0D26
0104 #define MT6351_AUDENC_ANA_CON16    0x0D28
0105 #endif