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0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // mt6351.c  --  mt6351 ALSA SoC audio codec driver
0004 //
0005 // Copyright (c) 2018 MediaTek Inc.
0006 // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
0007 
0008 #include <linux/dma-mapping.h>
0009 #include <linux/platform_device.h>
0010 #include <linux/slab.h>
0011 #include <linux/module.h>
0012 #include <linux/of_device.h>
0013 #include <linux/delay.h>
0014 
0015 #include <sound/core.h>
0016 #include <sound/pcm.h>
0017 #include <sound/soc.h>
0018 #include <sound/tlv.h>
0019 
0020 #include "mt6351.h"
0021 
0022 /* MT6351_TOP_CLKSQ */
0023 #define RG_CLKSQ_EN_AUD_BIT (0)
0024 
0025 /* MT6351_TOP_CKPDN_CON0 */
0026 #define RG_AUDNCP_CK_PDN_BIT (12)
0027 #define RG_AUDIF_CK_PDN_BIT (13)
0028 #define RG_AUD_CK_PDN_BIT (14)
0029 #define RG_ZCD13M_CK_PDN_BIT (15)
0030 
0031 /* MT6351_AUDDEC_ANA_CON0 */
0032 #define RG_AUDDACLPWRUP_VAUDP32_BIT (0)
0033 #define RG_AUDDACRPWRUP_VAUDP32_BIT (1)
0034 #define RG_AUD_DAC_PWR_UP_VA32_BIT (2)
0035 #define RG_AUD_DAC_PWL_UP_VA32_BIT (3)
0036 
0037 #define RG_AUDHSPWRUP_VAUDP32_BIT (4)
0038 
0039 #define RG_AUDHPLPWRUP_VAUDP32_BIT (5)
0040 #define RG_AUDHPRPWRUP_VAUDP32_BIT (6)
0041 
0042 #define RG_AUDHSMUXINPUTSEL_VAUDP32_SFT (7)
0043 #define RG_AUDHSMUXINPUTSEL_VAUDP32_MASK (0x3)
0044 
0045 #define RG_AUDHPLMUXINPUTSEL_VAUDP32_SFT (9)
0046 #define RG_AUDHPLMUXINPUTSEL_VAUDP32_MASK (0x3)
0047 
0048 #define RG_AUDHPRMUXINPUTSEL_VAUDP32_SFT (11)
0049 #define RG_AUDHPRMUXINPUTSEL_VAUDP32_MASK (0x3)
0050 
0051 #define RG_AUDHSSCDISABLE_VAUDP32 (13)
0052 #define RG_AUDHPLSCDISABLE_VAUDP32_BIT (14)
0053 #define RG_AUDHPRSCDISABLE_VAUDP32_BIT (15)
0054 
0055 /* MT6351_AUDDEC_ANA_CON1 */
0056 #define RG_HSOUTPUTSTBENH_VAUDP32_BIT (8)
0057 
0058 /* MT6351_AUDDEC_ANA_CON3 */
0059 #define RG_AUDLOLPWRUP_VAUDP32_BIT (2)
0060 
0061 #define RG_AUDLOLMUXINPUTSEL_VAUDP32_SFT (3)
0062 #define RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK (0x3)
0063 
0064 #define RG_AUDLOLSCDISABLE_VAUDP32_BIT (5)
0065 #define RG_LOOUTPUTSTBENH_VAUDP32_BIT (9)
0066 
0067 /* MT6351_AUDDEC_ANA_CON6 */
0068 #define RG_ABIDEC_RSVD0_VAUDP32_HPL_BIT (8)
0069 #define RG_ABIDEC_RSVD0_VAUDP32_HPR_BIT (9)
0070 #define RG_ABIDEC_RSVD0_VAUDP32_HS_BIT (10)
0071 #define RG_ABIDEC_RSVD0_VAUDP32_LOL_BIT (11)
0072 
0073 /* MT6351_AUDDEC_ANA_CON9 */
0074 #define RG_AUDIBIASPWRDN_VAUDP32_BIT (8)
0075 #define RG_RSTB_DECODER_VA32_BIT (9)
0076 #define RG_AUDGLB_PWRDN_VA32_BIT (12)
0077 
0078 #define RG_LCLDO_DEC_EN_VA32_BIT (13)
0079 #define RG_LCLDO_DEC_REMOTE_SENSE_VA18_BIT (15)
0080 /* MT6351_AUDDEC_ANA_CON10 */
0081 #define RG_NVREG_EN_VAUDP32_BIT (8)
0082 
0083 #define RG_AUDGLB_LP2_VOW_EN_VA32 10
0084 
0085 /* MT6351_AFE_UL_DL_CON0 */
0086 #define RG_AFE_ON_BIT (0)
0087 
0088 /* MT6351_AFE_DL_SRC2_CON0_L */
0089 #define RG_DL_2_SRC_ON_TMP_CTL_PRE_BIT (0)
0090 
0091 /* MT6351_AFE_UL_SRC_CON0_L */
0092 #define UL_SRC_ON_TMP_CTL (0)
0093 
0094 /* MT6351_AFE_TOP_CON0 */
0095 #define RG_DL_SINE_ON_SFT (0)
0096 #define RG_DL_SINE_ON_MASK (0x1)
0097 
0098 #define RG_UL_SINE_ON_SFT (1)
0099 #define RG_UL_SINE_ON_MASK (0x1)
0100 
0101 /* MT6351_AUDIO_TOP_CON0 */
0102 #define AUD_TOP_PDN_RESERVED_BIT 0
0103 #define AUD_TOP_PWR_CLK_DIS_CTL_BIT 2
0104 #define AUD_TOP_PDN_ADC_CTL_BIT 5
0105 #define AUD_TOP_PDN_DAC_CTL_BIT 6
0106 #define AUD_TOP_PDN_AFE_CTL_BIT 7
0107 
0108 /* MT6351_AFE_SGEN_CFG0 */
0109 #define SGEN_C_MUTE_SW_CTL_BIT 6
0110 #define SGEN_C_DAC_EN_CTL_BIT 7
0111 
0112 /* MT6351_AFE_NCP_CFG0 */
0113 #define RG_NCP_ON_BIT 0
0114 
0115 /* MT6351_LDO_VUSB33_CON0 */
0116 #define RG_VUSB33_EN 1
0117 #define RG_VUSB33_ON_CTRL 3
0118 
0119 /* MT6351_LDO_VA18_CON0 */
0120 #define RG_VA18_EN 1
0121 #define RG_VA18_ON_CTRL 3
0122 
0123 /* MT6351_AUDENC_ANA_CON0 */
0124 #define RG_AUDPREAMPLON 0
0125 #define RG_AUDPREAMPLDCCEN 1
0126 #define RG_AUDPREAMPLDCPRECHARGE 2
0127 
0128 #define RG_AUDPREAMPLINPUTSEL_SFT (4)
0129 #define RG_AUDPREAMPLINPUTSEL_MASK (0x3)
0130 
0131 #define RG_AUDADCLPWRUP 12
0132 
0133 #define RG_AUDADCLINPUTSEL_SFT (13)
0134 #define RG_AUDADCLINPUTSEL_MASK (0x3)
0135 
0136 /* MT6351_AUDENC_ANA_CON1 */
0137 #define RG_AUDPREAMPRON 0
0138 #define RG_AUDPREAMPRDCCEN 1
0139 #define RG_AUDPREAMPRDCPRECHARGE 2
0140 
0141 #define RG_AUDPREAMPRINPUTSEL_SFT (4)
0142 #define RG_AUDPREAMPRINPUTSEL_MASK (0x3)
0143 
0144 #define RG_AUDADCRPWRUP 12
0145 
0146 #define RG_AUDADCRINPUTSEL_SFT (13)
0147 #define RG_AUDADCRINPUTSEL_MASK (0x3)
0148 
0149 /* MT6351_AUDENC_ANA_CON3 */
0150 #define RG_AUDADCCLKRSTB 6
0151 
0152 /* MT6351_AUDENC_ANA_CON9 */
0153 #define RG_AUDPWDBMICBIAS0 0
0154 #define RG_AUDMICBIAS0VREF 4
0155 #define RG_AUDMICBIAS0LOWPEN 7
0156 
0157 #define RG_AUDPWDBMICBIAS2 8
0158 #define RG_AUDMICBIAS2VREF 12
0159 #define RG_AUDMICBIAS2LOWPEN 15
0160 
0161 /* MT6351_AUDENC_ANA_CON10 */
0162 #define RG_AUDPWDBMICBIAS1 0
0163 #define RG_AUDMICBIAS1DCSW1NEN 2
0164 #define RG_AUDMICBIAS1VREF 4
0165 #define RG_AUDMICBIAS1LOWPEN 7
0166 
0167 enum {
0168     AUDIO_ANALOG_VOLUME_HSOUTL,
0169     AUDIO_ANALOG_VOLUME_HSOUTR,
0170     AUDIO_ANALOG_VOLUME_HPOUTL,
0171     AUDIO_ANALOG_VOLUME_HPOUTR,
0172     AUDIO_ANALOG_VOLUME_LINEOUTL,
0173     AUDIO_ANALOG_VOLUME_LINEOUTR,
0174     AUDIO_ANALOG_VOLUME_MICAMP1,
0175     AUDIO_ANALOG_VOLUME_MICAMP2,
0176     AUDIO_ANALOG_VOLUME_TYPE_MAX
0177 };
0178 
0179 /* Supply subseq */
0180 enum {
0181     SUPPLY_SUBSEQ_SETTING,
0182     SUPPLY_SUBSEQ_ENABLE,
0183     SUPPLY_SUBSEQ_MICBIAS,
0184 };
0185 
0186 #define REG_STRIDE 2
0187 
0188 struct mt6351_priv {
0189     struct device *dev;
0190     struct regmap *regmap;
0191 
0192     unsigned int dl_rate;
0193     unsigned int ul_rate;
0194 
0195     int ana_gain[AUDIO_ANALOG_VOLUME_TYPE_MAX];
0196 
0197     int hp_en_counter;
0198 };
0199 
0200 static void set_hp_gain_zero(struct snd_soc_component *cmpnt)
0201 {
0202     regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON2,
0203                0x1f << 7, 0x8 << 7);
0204     regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON2,
0205                0x1f << 0, 0x8 << 0);
0206 }
0207 
0208 static unsigned int get_cap_reg_val(struct snd_soc_component *cmpnt,
0209                     unsigned int rate)
0210 {
0211     switch (rate) {
0212     case 8000:
0213         return 0;
0214     case 16000:
0215         return 1;
0216     case 32000:
0217         return 2;
0218     case 48000:
0219         return 3;
0220     case 96000:
0221         return 4;
0222     case 192000:
0223         return 5;
0224     default:
0225         dev_warn(cmpnt->dev, "%s(), error rate %d, return 3",
0226              __func__, rate);
0227         return 3;
0228     }
0229 }
0230 
0231 static unsigned int get_play_reg_val(struct snd_soc_component *cmpnt,
0232                      unsigned int rate)
0233 {
0234     switch (rate) {
0235     case 8000:
0236         return 0;
0237     case 11025:
0238         return 1;
0239     case 12000:
0240         return 2;
0241     case 16000:
0242         return 3;
0243     case 22050:
0244         return 4;
0245     case 24000:
0246         return 5;
0247     case 32000:
0248         return 6;
0249     case 44100:
0250         return 7;
0251     case 48000:
0252     case 96000:
0253     case 192000:
0254         return 8;
0255     default:
0256         dev_warn(cmpnt->dev, "%s(), error rate %d, return 8",
0257              __func__, rate);
0258         return 8;
0259     }
0260 }
0261 
0262 static int mt6351_codec_dai_hw_params(struct snd_pcm_substream *substream,
0263                       struct snd_pcm_hw_params *params,
0264                       struct snd_soc_dai *dai)
0265 {
0266     struct snd_soc_component *cmpnt = dai->component;
0267     struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt);
0268     unsigned int rate = params_rate(params);
0269 
0270     dev_dbg(priv->dev, "%s(), substream->stream %d, rate %d\n",
0271         __func__, substream->stream, rate);
0272 
0273     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
0274         priv->dl_rate = rate;
0275     else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
0276         priv->ul_rate = rate;
0277 
0278     return 0;
0279 }
0280 
0281 static const struct snd_soc_dai_ops mt6351_codec_dai_ops = {
0282     .hw_params = mt6351_codec_dai_hw_params,
0283 };
0284 
0285 #define MT6351_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE |\
0286             SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_U24_LE |\
0287             SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_U32_LE)
0288 
0289 static struct snd_soc_dai_driver mt6351_dai_driver[] = {
0290     {
0291         .name = "mt6351-snd-codec-aif1",
0292         .playback = {
0293             .stream_name = "AIF1 Playback",
0294             .channels_min = 1,
0295             .channels_max = 2,
0296             .rates = SNDRV_PCM_RATE_8000_48000 |
0297                  SNDRV_PCM_RATE_96000 |
0298                  SNDRV_PCM_RATE_192000,
0299             .formats = MT6351_FORMATS,
0300         },
0301         .capture = {
0302             .stream_name = "AIF1 Capture",
0303             .channels_min = 1,
0304             .channels_max = 2,
0305             .rates = SNDRV_PCM_RATE_8000 |
0306                  SNDRV_PCM_RATE_16000 |
0307                  SNDRV_PCM_RATE_32000 |
0308                  SNDRV_PCM_RATE_48000 |
0309                  SNDRV_PCM_RATE_96000 |
0310                  SNDRV_PCM_RATE_192000,
0311             .formats = MT6351_FORMATS,
0312         },
0313         .ops = &mt6351_codec_dai_ops,
0314     },
0315 };
0316 
0317 enum {
0318     HP_GAIN_SET_ZERO,
0319     HP_GAIN_RESTORE,
0320 };
0321 
0322 static void hp_gain_ramp_set(struct snd_soc_component *cmpnt, int hp_gain_ctl)
0323 {
0324     struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt);
0325     int idx, old_idx, offset, reg_idx;
0326 
0327     if (hp_gain_ctl == HP_GAIN_SET_ZERO) {
0328         idx = 8;    /* 0dB */
0329         old_idx = priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL];
0330     } else {
0331         idx = priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL];
0332         old_idx = 8;    /* 0dB */
0333     }
0334     dev_dbg(priv->dev, "%s(), idx %d, old_idx %d\n",
0335         __func__, idx, old_idx);
0336 
0337     if (idx > old_idx)
0338         offset = idx - old_idx;
0339     else
0340         offset = old_idx - idx;
0341 
0342     reg_idx = old_idx;
0343 
0344     while (offset > 0) {
0345         reg_idx = idx > old_idx ? reg_idx + 1 : reg_idx - 1;
0346 
0347         /* check valid range, and set value */
0348         if ((reg_idx >= 0 && reg_idx <= 0x12) || reg_idx == 0x1f) {
0349             regmap_update_bits(cmpnt->regmap,
0350                        MT6351_ZCD_CON2,
0351                        0xf9f,
0352                        (reg_idx << 7) | reg_idx);
0353             usleep_range(100, 120);
0354         }
0355         offset--;
0356     }
0357 }
0358 
0359 static void hp_zcd_enable(struct snd_soc_component *cmpnt)
0360 {
0361     /* Enable ZCD, for minimize pop noise */
0362     /* when adjust gain during HP buffer on */
0363     regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x7 << 8, 0x1 << 8);
0364     regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x1 << 7, 0x0 << 7);
0365 
0366     /* timeout, 1=5ms, 0=30ms */
0367     regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x1 << 6, 0x1 << 6);
0368 
0369     regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x3 << 4, 0x0 << 4);
0370     regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x7 << 1, 0x5 << 1);
0371     regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x1 << 0, 0x1 << 0);
0372 }
0373 
0374 static void hp_zcd_disable(struct snd_soc_component *cmpnt)
0375 {
0376     regmap_write(cmpnt->regmap, MT6351_ZCD_CON0, 0x0000);
0377 }
0378 
0379 static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0);
0380 static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 600, 0);
0381 
0382 static const struct snd_kcontrol_new mt6351_snd_controls[] = {
0383     /* dl pga gain */
0384     SOC_DOUBLE_TLV("Headphone Volume",
0385                MT6351_ZCD_CON2, 0, 7, 0x12, 1,
0386                playback_tlv),
0387     SOC_DOUBLE_TLV("Lineout Volume",
0388                MT6351_ZCD_CON1, 0, 7, 0x12, 1,
0389                playback_tlv),
0390     SOC_SINGLE_TLV("Handset Volume",
0391                MT6351_ZCD_CON3, 0, 0x12, 1,
0392                playback_tlv),
0393        /* ul pga gain */
0394     SOC_DOUBLE_R_TLV("PGA Volume",
0395              MT6351_AUDENC_ANA_CON0, MT6351_AUDENC_ANA_CON1,
0396              8, 4, 0,
0397              pga_tlv),
0398 };
0399 
0400 /* MUX */
0401 
0402 /* LOL MUX */
0403 static const char *const lo_in_mux_map[] = {
0404     "Open", "Mute", "Playback", "Test Mode",
0405 };
0406 
0407 static int lo_in_mux_map_value[] = {
0408     0x0, 0x1, 0x2, 0x3,
0409 };
0410 
0411 static SOC_VALUE_ENUM_SINGLE_DECL(lo_in_mux_map_enum,
0412                   MT6351_AUDDEC_ANA_CON3,
0413                   RG_AUDLOLMUXINPUTSEL_VAUDP32_SFT,
0414                   RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK,
0415                   lo_in_mux_map,
0416                   lo_in_mux_map_value);
0417 
0418 static const struct snd_kcontrol_new lo_in_mux_control =
0419     SOC_DAPM_ENUM("In Select", lo_in_mux_map_enum);
0420 
0421 /*HP MUX */
0422 static const char *const hp_in_mux_map[] = {
0423     "Open", "LoudSPK Playback", "Audio Playback", "Test Mode",
0424 };
0425 
0426 static int hp_in_mux_map_value[] = {
0427     0x0, 0x1, 0x2, 0x3,
0428 };
0429 
0430 static SOC_VALUE_ENUM_SINGLE_DECL(hpl_in_mux_map_enum,
0431                   MT6351_AUDDEC_ANA_CON0,
0432                   RG_AUDHPLMUXINPUTSEL_VAUDP32_SFT,
0433                   RG_AUDHPLMUXINPUTSEL_VAUDP32_MASK,
0434                   hp_in_mux_map,
0435                   hp_in_mux_map_value);
0436 
0437 static const struct snd_kcontrol_new hpl_in_mux_control =
0438     SOC_DAPM_ENUM("HPL Select", hpl_in_mux_map_enum);
0439 
0440 static SOC_VALUE_ENUM_SINGLE_DECL(hpr_in_mux_map_enum,
0441                   MT6351_AUDDEC_ANA_CON0,
0442                   RG_AUDHPRMUXINPUTSEL_VAUDP32_SFT,
0443                   RG_AUDHPRMUXINPUTSEL_VAUDP32_MASK,
0444                   hp_in_mux_map,
0445                   hp_in_mux_map_value);
0446 
0447 static const struct snd_kcontrol_new hpr_in_mux_control =
0448     SOC_DAPM_ENUM("HPR Select", hpr_in_mux_map_enum);
0449 
0450 /* RCV MUX */
0451 static const char *const rcv_in_mux_map[] = {
0452     "Open", "Mute", "Voice Playback", "Test Mode",
0453 };
0454 
0455 static int rcv_in_mux_map_value[] = {
0456     0x0, 0x1, 0x2, 0x3,
0457 };
0458 
0459 static SOC_VALUE_ENUM_SINGLE_DECL(rcv_in_mux_map_enum,
0460                   MT6351_AUDDEC_ANA_CON0,
0461                   RG_AUDHSMUXINPUTSEL_VAUDP32_SFT,
0462                   RG_AUDHSMUXINPUTSEL_VAUDP32_MASK,
0463                   rcv_in_mux_map,
0464                   rcv_in_mux_map_value);
0465 
0466 static const struct snd_kcontrol_new rcv_in_mux_control =
0467     SOC_DAPM_ENUM("RCV Select", rcv_in_mux_map_enum);
0468 
0469 /* DAC In MUX */
0470 static const char *const dac_in_mux_map[] = {
0471     "Normal Path", "Sgen",
0472 };
0473 
0474 static int dac_in_mux_map_value[] = {
0475     0x0, 0x1,
0476 };
0477 
0478 static SOC_VALUE_ENUM_SINGLE_DECL(dac_in_mux_map_enum,
0479                   MT6351_AFE_TOP_CON0,
0480                   RG_DL_SINE_ON_SFT,
0481                   RG_DL_SINE_ON_MASK,
0482                   dac_in_mux_map,
0483                   dac_in_mux_map_value);
0484 
0485 static const struct snd_kcontrol_new dac_in_mux_control =
0486     SOC_DAPM_ENUM("DAC Select", dac_in_mux_map_enum);
0487 
0488 /* AIF Out MUX */
0489 static SOC_VALUE_ENUM_SINGLE_DECL(aif_out_mux_map_enum,
0490                   MT6351_AFE_TOP_CON0,
0491                   RG_UL_SINE_ON_SFT,
0492                   RG_UL_SINE_ON_MASK,
0493                   dac_in_mux_map,
0494                   dac_in_mux_map_value);
0495 
0496 static const struct snd_kcontrol_new aif_out_mux_control =
0497     SOC_DAPM_ENUM("AIF Out Select", aif_out_mux_map_enum);
0498 
0499 /* ADC L MUX */
0500 static const char *const adc_left_mux_map[] = {
0501     "Idle", "AIN0", "Left Preamplifier", "Idle_1",
0502 };
0503 
0504 static int adc_left_mux_map_value[] = {
0505     0x0, 0x1, 0x2, 0x3,
0506 };
0507 
0508 static SOC_VALUE_ENUM_SINGLE_DECL(adc_left_mux_map_enum,
0509                   MT6351_AUDENC_ANA_CON0,
0510                   RG_AUDADCLINPUTSEL_SFT,
0511                   RG_AUDADCLINPUTSEL_MASK,
0512                   adc_left_mux_map,
0513                   adc_left_mux_map_value);
0514 
0515 static const struct snd_kcontrol_new adc_left_mux_control =
0516     SOC_DAPM_ENUM("ADC L Select", adc_left_mux_map_enum);
0517 
0518 /* ADC R MUX */
0519 static const char *const adc_right_mux_map[] = {
0520     "Idle", "AIN0", "Right Preamplifier", "Idle_1",
0521 };
0522 
0523 static int adc_right_mux_map_value[] = {
0524     0x0, 0x1, 0x2, 0x3,
0525 };
0526 
0527 static SOC_VALUE_ENUM_SINGLE_DECL(adc_right_mux_map_enum,
0528                   MT6351_AUDENC_ANA_CON1,
0529                   RG_AUDADCRINPUTSEL_SFT,
0530                   RG_AUDADCRINPUTSEL_MASK,
0531                   adc_right_mux_map,
0532                   adc_right_mux_map_value);
0533 
0534 static const struct snd_kcontrol_new adc_right_mux_control =
0535     SOC_DAPM_ENUM("ADC R Select", adc_right_mux_map_enum);
0536 
0537 /* PGA L MUX */
0538 static const char *const pga_left_mux_map[] = {
0539     "None", "AIN0", "AIN1", "AIN2",
0540 };
0541 
0542 static int pga_left_mux_map_value[] = {
0543     0x0, 0x1, 0x2, 0x3,
0544 };
0545 
0546 static SOC_VALUE_ENUM_SINGLE_DECL(pga_left_mux_map_enum,
0547                   MT6351_AUDENC_ANA_CON0,
0548                   RG_AUDPREAMPLINPUTSEL_SFT,
0549                   RG_AUDPREAMPLINPUTSEL_MASK,
0550                   pga_left_mux_map,
0551                   pga_left_mux_map_value);
0552 
0553 static const struct snd_kcontrol_new pga_left_mux_control =
0554     SOC_DAPM_ENUM("PGA L Select", pga_left_mux_map_enum);
0555 
0556 /* PGA R MUX */
0557 static const char *const pga_right_mux_map[] = {
0558     "None", "AIN0", "AIN3", "AIN2",
0559 };
0560 
0561 static int pga_right_mux_map_value[] = {
0562     0x0, 0x1, 0x2, 0x3,
0563 };
0564 
0565 static SOC_VALUE_ENUM_SINGLE_DECL(pga_right_mux_map_enum,
0566                   MT6351_AUDENC_ANA_CON1,
0567                   RG_AUDPREAMPRINPUTSEL_SFT,
0568                   RG_AUDPREAMPRINPUTSEL_MASK,
0569                   pga_right_mux_map,
0570                   pga_right_mux_map_value);
0571 
0572 static const struct snd_kcontrol_new pga_right_mux_control =
0573     SOC_DAPM_ENUM("PGA R Select", pga_right_mux_map_enum);
0574 
0575 static int mt_reg_set_clr_event(struct snd_soc_dapm_widget *w,
0576                 struct snd_kcontrol *kcontrol,
0577                 int event)
0578 {
0579     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0580 
0581     switch (event) {
0582     case SND_SOC_DAPM_POST_PMU:
0583         if (w->on_val) {
0584             /* SET REG */
0585             regmap_update_bits(cmpnt->regmap,
0586                        w->reg + REG_STRIDE,
0587                        0x1 << w->shift,
0588                        0x1 << w->shift);
0589         } else {
0590             /* CLR REG */
0591             regmap_update_bits(cmpnt->regmap,
0592                        w->reg + REG_STRIDE * 2,
0593                        0x1 << w->shift,
0594                        0x1 << w->shift);
0595         }
0596         break;
0597     case SND_SOC_DAPM_PRE_PMD:
0598         if (w->off_val) {
0599             /* SET REG */
0600             regmap_update_bits(cmpnt->regmap,
0601                        w->reg + REG_STRIDE,
0602                        0x1 << w->shift,
0603                        0x1 << w->shift);
0604         } else {
0605             /* CLR REG */
0606             regmap_update_bits(cmpnt->regmap,
0607                        w->reg + REG_STRIDE * 2,
0608                        0x1 << w->shift,
0609                        0x1 << w->shift);
0610         }
0611         break;
0612     default:
0613         break;
0614     }
0615 
0616     return 0;
0617 }
0618 
0619 static int mt_ncp_event(struct snd_soc_dapm_widget *w,
0620             struct snd_kcontrol *kcontrol,
0621             int event)
0622 {
0623     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0624 
0625     switch (event) {
0626     case SND_SOC_DAPM_PRE_PMU:
0627         regmap_update_bits(cmpnt->regmap, MT6351_AFE_NCP_CFG1,
0628                    0xffff, 0x1515);
0629         /* NCP: ck1 and ck2 clock frequecy adjust configure */
0630         regmap_update_bits(cmpnt->regmap, MT6351_AFE_NCP_CFG0,
0631                    0xfffe, 0x8C00);
0632         break;
0633     case SND_SOC_DAPM_POST_PMU:
0634         usleep_range(250, 270);
0635         break;
0636     default:
0637         break;
0638     }
0639 
0640     return 0;
0641 }
0642 
0643 static int mt_sgen_event(struct snd_soc_dapm_widget *w,
0644              struct snd_kcontrol *kcontrol,
0645              int event)
0646 {
0647     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0648 
0649     switch (event) {
0650     case SND_SOC_DAPM_PRE_PMU:
0651         regmap_update_bits(cmpnt->regmap, MT6351_AFE_SGEN_CFG0,
0652                    0xffef, 0x0008);
0653         regmap_update_bits(cmpnt->regmap, MT6351_AFE_SGEN_CFG1,
0654                    0xffff, 0x0101);
0655         break;
0656     default:
0657         break;
0658     }
0659 
0660     return 0;
0661 }
0662 
0663 static int mt_aif_in_event(struct snd_soc_dapm_widget *w,
0664                struct snd_kcontrol *kcontrol,
0665                int event)
0666 {
0667     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0668     struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt);
0669 
0670     dev_dbg(priv->dev, "%s(), event 0x%x, rate %d\n",
0671         __func__, event, priv->dl_rate);
0672 
0673     switch (event) {
0674     case SND_SOC_DAPM_PRE_PMU:
0675         /* sdm audio fifo clock power on */
0676         regmap_update_bits(cmpnt->regmap, MT6351_AFUNC_AUD_CON2,
0677                    0xffff, 0x0006);
0678         /* scrambler clock on enable */
0679         regmap_update_bits(cmpnt->regmap, MT6351_AFUNC_AUD_CON0,
0680                    0xffff, 0xC3A1);
0681         /* sdm power on */
0682         regmap_update_bits(cmpnt->regmap, MT6351_AFUNC_AUD_CON2,
0683                    0xffff, 0x0003);
0684         /* sdm fifo enable */
0685         regmap_update_bits(cmpnt->regmap, MT6351_AFUNC_AUD_CON2,
0686                    0xffff, 0x000B);
0687         /* set attenuation gain */
0688         regmap_update_bits(cmpnt->regmap, MT6351_AFE_DL_SDM_CON1,
0689                    0xffff, 0x001E);
0690 
0691         regmap_write(cmpnt->regmap, MT6351_AFE_PMIC_NEWIF_CFG0,
0692                  (get_play_reg_val(cmpnt, priv->dl_rate) << 12) |
0693                  0x330);
0694         regmap_write(cmpnt->regmap, MT6351_AFE_DL_SRC2_CON0_H,
0695                  (get_play_reg_val(cmpnt, priv->dl_rate) << 12) |
0696                  0x300);
0697 
0698         regmap_update_bits(cmpnt->regmap, MT6351_AFE_PMIC_NEWIF_CFG2,
0699                    0x8000, 0x8000);
0700         break;
0701     default:
0702         break;
0703     }
0704 
0705     return 0;
0706 }
0707 
0708 static int mt_hp_event(struct snd_soc_dapm_widget *w,
0709                struct snd_kcontrol *kcontrol,
0710                int event)
0711 {
0712     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0713     struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt);
0714     int reg;
0715 
0716     dev_dbg(priv->dev, "%s(), event 0x%x, hp_en_counter %d\n",
0717         __func__, event, priv->hp_en_counter);
0718 
0719     switch (event) {
0720     case SND_SOC_DAPM_PRE_PMU:
0721         priv->hp_en_counter++;
0722         if (priv->hp_en_counter > 1)
0723             break;  /* already enabled, do nothing */
0724         else if (priv->hp_en_counter <= 0)
0725             dev_err(priv->dev, "%s(), hp_en_counter %d <= 0\n",
0726                 __func__,
0727                 priv->hp_en_counter);
0728 
0729         hp_zcd_disable(cmpnt);
0730 
0731         /* from yoyo HQA script */
0732         regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON6,
0733                    0x0700, 0x0700);
0734 
0735         /* save target gain to restore after hardware open complete */
0736         regmap_read(cmpnt->regmap, MT6351_ZCD_CON2, &reg);
0737         priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL] = reg & 0x1f;
0738         priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR] = (reg >> 7) & 0x1f;
0739 
0740         /* Set HPR/HPL gain as minimum (~ -40dB) */
0741         regmap_update_bits(cmpnt->regmap,
0742                    MT6351_ZCD_CON2, 0xffff, 0x0F9F);
0743         /* Set HS gain as minimum (~ -40dB) */
0744         regmap_update_bits(cmpnt->regmap,
0745                    MT6351_ZCD_CON3, 0xffff, 0x001F);
0746         /* De_OSC of HP */
0747         regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON2,
0748                    0x0001, 0x0001);
0749         /* enable output STBENH */
0750         regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON1,
0751                    0xffff, 0x2000);
0752         /* De_OSC of voice, enable output STBENH */
0753         regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON1,
0754                    0xffff, 0x2100);
0755         /* Enable voice driver */
0756         regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON0,
0757                    0x0010, 0xE090);
0758         /* Enable pre-charge buffer  */
0759         regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON1,
0760                    0xffff, 0x2140);
0761 
0762         usleep_range(50, 60);
0763 
0764         /* Apply digital DC compensation value to DAC */
0765         set_hp_gain_zero(cmpnt);
0766 
0767         /* Enable HPR/HPL */
0768         regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON1,
0769                    0xffff, 0x2100);
0770         /* Disable pre-charge buffer */
0771         regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON1,
0772                    0xffff, 0x2000);
0773         /* Disable De_OSC of voice */
0774         regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON0,
0775                    0x0010, 0xF4EF);
0776         /* Disable voice buffer */
0777 
0778         /* from yoyo HQ */
0779         regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON6,
0780                    0x0700, 0x0300);
0781 
0782         /* Enable ZCD, for minimize pop noise */
0783         /* when adjust gain during HP buffer on */
0784         hp_zcd_enable(cmpnt);
0785 
0786         /* apply volume setting */
0787         hp_gain_ramp_set(cmpnt, HP_GAIN_RESTORE);
0788 
0789         break;
0790     case SND_SOC_DAPM_PRE_PMD:
0791         priv->hp_en_counter--;
0792         if (priv->hp_en_counter > 0)
0793             break;  /* still being used, don't close */
0794         else if (priv->hp_en_counter < 0)
0795             dev_err(priv->dev, "%s(), hp_en_counter %d <= 0\n",
0796                 __func__,
0797                 priv->hp_en_counter);
0798 
0799         /* Disable AUD_ZCD */
0800         hp_zcd_disable(cmpnt);
0801 
0802         /* Set HPR/HPL gain as -1dB, step by step */
0803         hp_gain_ramp_set(cmpnt, HP_GAIN_SET_ZERO);
0804 
0805         set_hp_gain_zero(cmpnt);
0806         break;
0807     case SND_SOC_DAPM_POST_PMD:
0808         if (priv->hp_en_counter > 0)
0809             break;  /* still being used, don't close */
0810         else if (priv->hp_en_counter < 0)
0811             dev_err(priv->dev, "%s(), hp_en_counter %d <= 0\n",
0812                 __func__,
0813                 priv->hp_en_counter);
0814 
0815         /* reset*/
0816         regmap_update_bits(cmpnt->regmap,
0817                    MT6351_AUDDEC_ANA_CON6,
0818                    0x0700,
0819                    0x0000);
0820         /* De_OSC of HP */
0821         regmap_update_bits(cmpnt->regmap,
0822                    MT6351_AUDDEC_ANA_CON2,
0823                    0x0001,
0824                    0x0000);
0825 
0826         /* apply volume setting */
0827         hp_gain_ramp_set(cmpnt, HP_GAIN_RESTORE);
0828         break;
0829     default:
0830         break;
0831     }
0832 
0833     return 0;
0834 }
0835 
0836 static int mt_aif_out_event(struct snd_soc_dapm_widget *w,
0837                 struct snd_kcontrol *kcontrol,
0838                 int event)
0839 {
0840     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0841     struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt);
0842 
0843     dev_dbg(priv->dev, "%s(), event 0x%x, rate %d\n",
0844         __func__, event, priv->ul_rate);
0845 
0846     switch (event) {
0847     case SND_SOC_DAPM_PRE_PMU:
0848         /* dcclk_div=11'b00100000011, dcclk_ref_ck_sel=2'b00 */
0849         regmap_update_bits(cmpnt->regmap, MT6351_AFE_DCCLK_CFG0,
0850                    0xffff, 0x2062);
0851         /* dcclk_pdn=1'b0 */
0852         regmap_update_bits(cmpnt->regmap, MT6351_AFE_DCCLK_CFG0,
0853                    0xffff, 0x2060);
0854         /* dcclk_gen_on=1'b1 */
0855         regmap_update_bits(cmpnt->regmap, MT6351_AFE_DCCLK_CFG0,
0856                    0xffff, 0x2061);
0857 
0858         /* UL sample rate and mode configure */
0859         regmap_update_bits(cmpnt->regmap, MT6351_AFE_UL_SRC_CON0_H,
0860                    0x000E,
0861                    get_cap_reg_val(cmpnt, priv->ul_rate) << 1);
0862 
0863         /* fixed 260k path for 8/16/32/48 */
0864         if (priv->ul_rate <= 48000) {
0865             /* anc ul path src on */
0866             regmap_update_bits(cmpnt->regmap,
0867                        MT6351_AFE_HPANC_CFG0,
0868                        0x1 << 1,
0869                        0x1 << 1);
0870             /* ANC clk pdn release */
0871             regmap_update_bits(cmpnt->regmap,
0872                        MT6351_AFE_HPANC_CFG0,
0873                        0x1 << 0,
0874                        0x0 << 0);
0875         }
0876         break;
0877     case SND_SOC_DAPM_PRE_PMD:
0878         /* fixed 260k path for 8/16/32/48 */
0879         if (priv->ul_rate <= 48000) {
0880             /* anc ul path src on */
0881             regmap_update_bits(cmpnt->regmap,
0882                        MT6351_AFE_HPANC_CFG0,
0883                        0x1 << 1,
0884                        0x0 << 1);
0885             /* ANC clk pdn release */
0886             regmap_update_bits(cmpnt->regmap,
0887                        MT6351_AFE_HPANC_CFG0,
0888                        0x1 << 0,
0889                        0x1 << 0);
0890         }
0891         break;
0892     default:
0893         break;
0894     }
0895 
0896     return 0;
0897 }
0898 
0899 static int mt_adc_clkgen_event(struct snd_soc_dapm_widget *w,
0900                    struct snd_kcontrol *kcontrol,
0901                    int event)
0902 {
0903     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0904 
0905     switch (event) {
0906     case SND_SOC_DAPM_PRE_PMU:
0907         /* Audio ADC clock gen. mode: 00_divided by 2 (Normal) */
0908         regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON3,
0909                    0x3 << 4, 0x0);
0910         break;
0911     case SND_SOC_DAPM_POST_PMU:
0912         /* ADC CLK from: 00_13MHz from CLKSQ (Default) */
0913         regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON3,
0914                    0x3 << 2, 0x0);
0915         break;
0916     default:
0917         break;
0918     }
0919     return 0;
0920 }
0921 
0922 static int mt_pga_left_event(struct snd_soc_dapm_widget *w,
0923                  struct snd_kcontrol *kcontrol,
0924                  int event)
0925 {
0926     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0927 
0928     switch (event) {
0929     case SND_SOC_DAPM_PRE_PMU:
0930         /* Audio L PGA precharge on */
0931         regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON0,
0932                    0x3 << RG_AUDPREAMPLDCPRECHARGE,
0933                    0x1 << RG_AUDPREAMPLDCPRECHARGE);
0934         /* Audio L PGA mode: 1_DCC */
0935         regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON0,
0936                    0x3 << RG_AUDPREAMPLDCCEN,
0937                    0x1 << RG_AUDPREAMPLDCCEN);
0938         break;
0939     case SND_SOC_DAPM_POST_PMU:
0940         usleep_range(100, 120);
0941         /* Audio L PGA precharge off */
0942         regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON0,
0943                    0x3 << RG_AUDPREAMPLDCPRECHARGE,
0944                    0x0 << RG_AUDPREAMPLDCPRECHARGE);
0945         break;
0946     default:
0947         break;
0948     }
0949     return 0;
0950 }
0951 
0952 static int mt_pga_right_event(struct snd_soc_dapm_widget *w,
0953                   struct snd_kcontrol *kcontrol,
0954                   int event)
0955 {
0956     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0957 
0958     switch (event) {
0959     case SND_SOC_DAPM_PRE_PMU:
0960         /* Audio R PGA precharge on */
0961         regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON1,
0962                    0x3 << RG_AUDPREAMPRDCPRECHARGE,
0963                    0x1 << RG_AUDPREAMPRDCPRECHARGE);
0964         /* Audio R PGA mode: 1_DCC */
0965         regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON1,
0966                    0x3 << RG_AUDPREAMPRDCCEN,
0967                    0x1 << RG_AUDPREAMPRDCCEN);
0968         break;
0969     case SND_SOC_DAPM_POST_PMU:
0970         usleep_range(100, 120);
0971         /* Audio R PGA precharge off */
0972         regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON1,
0973                    0x3 << RG_AUDPREAMPRDCPRECHARGE,
0974                    0x0 << RG_AUDPREAMPRDCPRECHARGE);
0975         break;
0976     default:
0977         break;
0978     }
0979     return 0;
0980 }
0981 
0982 static int mt_mic_bias_0_event(struct snd_soc_dapm_widget *w,
0983                    struct snd_kcontrol *kcontrol,
0984                    int event)
0985 {
0986     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
0987 
0988     switch (event) {
0989     case SND_SOC_DAPM_PRE_PMU:
0990         /* MIC Bias 0 LowPower: 0_Normal */
0991         regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9,
0992                    0x3 << RG_AUDMICBIAS0LOWPEN, 0x0);
0993         /* MISBIAS0 = 1P9V */
0994         regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9,
0995                    0x7 << RG_AUDMICBIAS0VREF,
0996                    0x2 << RG_AUDMICBIAS0VREF);
0997         break;
0998     case SND_SOC_DAPM_POST_PMD:
0999         /* MISBIAS0 = 1P97 */
1000         regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9,
1001                    0x7 << RG_AUDMICBIAS0VREF,
1002                    0x0 << RG_AUDMICBIAS0VREF);
1003         break;
1004     default:
1005         break;
1006     }
1007     return 0;
1008 }
1009 
1010 static int mt_mic_bias_1_event(struct snd_soc_dapm_widget *w,
1011                    struct snd_kcontrol *kcontrol,
1012                    int event)
1013 {
1014     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1015 
1016     switch (event) {
1017     case SND_SOC_DAPM_PRE_PMU:
1018         /* MIC Bias 1 LowPower: 0_Normal */
1019         regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON10,
1020                    0x3 << RG_AUDMICBIAS1LOWPEN, 0x0);
1021         /* MISBIAS1 = 2P7V */
1022         regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON10,
1023                    0x7 << RG_AUDMICBIAS1VREF,
1024                    0x7 << RG_AUDMICBIAS1VREF);
1025         break;
1026     case SND_SOC_DAPM_POST_PMD:
1027         /* MISBIAS1 = 1P7V */
1028         regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON10,
1029                    0x7 << RG_AUDMICBIAS1VREF,
1030                    0x0 << RG_AUDMICBIAS1VREF);
1031         break;
1032     default:
1033         break;
1034     }
1035     return 0;
1036 }
1037 
1038 static int mt_mic_bias_2_event(struct snd_soc_dapm_widget *w,
1039                    struct snd_kcontrol *kcontrol,
1040                    int event)
1041 {
1042     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1043 
1044     switch (event) {
1045     case SND_SOC_DAPM_PRE_PMU:
1046         /* MIC Bias 2 LowPower: 0_Normal */
1047         regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9,
1048                    0x3 << RG_AUDMICBIAS2LOWPEN, 0x0);
1049         /* MISBIAS2 = 1P9V */
1050         regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9,
1051                    0x7 << RG_AUDMICBIAS2VREF,
1052                    0x2 << RG_AUDMICBIAS2VREF);
1053         break;
1054     case SND_SOC_DAPM_POST_PMD:
1055         /* MISBIAS2 = 1P97 */
1056         regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9,
1057                    0x7 << RG_AUDMICBIAS2VREF,
1058                    0x0 << RG_AUDMICBIAS2VREF);
1059         break;
1060     default:
1061         break;
1062     }
1063     return 0;
1064 }
1065 
1066 /* DAPM Widgets */
1067 static const struct snd_soc_dapm_widget mt6351_dapm_widgets[] = {
1068     /* Digital Clock */
1069     SND_SOC_DAPM_SUPPLY("AUDIO_TOP_AFE_CTL", MT6351_AUDIO_TOP_CON0,
1070                 AUD_TOP_PDN_AFE_CTL_BIT, 1, NULL, 0),
1071     SND_SOC_DAPM_SUPPLY("AUDIO_TOP_DAC_CTL", MT6351_AUDIO_TOP_CON0,
1072                 AUD_TOP_PDN_DAC_CTL_BIT, 1, NULL, 0),
1073     SND_SOC_DAPM_SUPPLY("AUDIO_TOP_ADC_CTL", MT6351_AUDIO_TOP_CON0,
1074                 AUD_TOP_PDN_ADC_CTL_BIT, 1, NULL, 0),
1075     SND_SOC_DAPM_SUPPLY("AUDIO_TOP_PWR_CLK", MT6351_AUDIO_TOP_CON0,
1076                 AUD_TOP_PWR_CLK_DIS_CTL_BIT, 1, NULL, 0),
1077     SND_SOC_DAPM_SUPPLY("AUDIO_TOP_PDN_RESERVED", MT6351_AUDIO_TOP_CON0,
1078                 AUD_TOP_PDN_RESERVED_BIT, 1, NULL, 0),
1079 
1080     SND_SOC_DAPM_SUPPLY("NCP", MT6351_AFE_NCP_CFG0,
1081                 RG_NCP_ON_BIT, 0,
1082                 mt_ncp_event,
1083                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1084 
1085     SND_SOC_DAPM_SUPPLY("DL Digital Clock", SND_SOC_NOPM,
1086                 0, 0, NULL, 0),
1087 
1088     /* Global Supply*/
1089     SND_SOC_DAPM_SUPPLY("AUDGLB", MT6351_AUDDEC_ANA_CON9,
1090                 RG_AUDGLB_PWRDN_VA32_BIT, 1, NULL, 0),
1091     SND_SOC_DAPM_SUPPLY("CLKSQ Audio", MT6351_TOP_CLKSQ,
1092                 RG_CLKSQ_EN_AUD_BIT, 0,
1093                 mt_reg_set_clr_event,
1094                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1095     SND_SOC_DAPM_SUPPLY("ZCD13M_CK", MT6351_TOP_CKPDN_CON0,
1096                 RG_ZCD13M_CK_PDN_BIT, 1,
1097                 mt_reg_set_clr_event,
1098                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1099     SND_SOC_DAPM_SUPPLY("AUD_CK", MT6351_TOP_CKPDN_CON0,
1100                 RG_AUD_CK_PDN_BIT, 1,
1101                 mt_reg_set_clr_event,
1102                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1103     SND_SOC_DAPM_SUPPLY("AUDIF_CK", MT6351_TOP_CKPDN_CON0,
1104                 RG_AUDIF_CK_PDN_BIT, 1,
1105                 mt_reg_set_clr_event,
1106                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1107     SND_SOC_DAPM_SUPPLY("AUDNCP_CK", MT6351_TOP_CKPDN_CON0,
1108                 RG_AUDNCP_CK_PDN_BIT, 1,
1109                 mt_reg_set_clr_event,
1110                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1111 
1112     SND_SOC_DAPM_SUPPLY("AFE_ON", MT6351_AFE_UL_DL_CON0, RG_AFE_ON_BIT, 0,
1113                 NULL, 0),
1114 
1115     /* AIF Rx*/
1116     SND_SOC_DAPM_AIF_IN_E("AIF_RX", "AIF1 Playback", 0,
1117                   MT6351_AFE_DL_SRC2_CON0_L,
1118                   RG_DL_2_SRC_ON_TMP_CTL_PRE_BIT, 0,
1119                   mt_aif_in_event, SND_SOC_DAPM_PRE_PMU),
1120 
1121     /* DL Supply */
1122     SND_SOC_DAPM_SUPPLY("DL Power Supply", SND_SOC_NOPM,
1123                 0, 0, NULL, 0),
1124     SND_SOC_DAPM_SUPPLY("NV Regulator", MT6351_AUDDEC_ANA_CON10,
1125                 RG_NVREG_EN_VAUDP32_BIT, 0, NULL, 0),
1126     SND_SOC_DAPM_SUPPLY("AUD_CLK", MT6351_AUDDEC_ANA_CON9,
1127                 RG_RSTB_DECODER_VA32_BIT, 0, NULL, 0),
1128     SND_SOC_DAPM_SUPPLY("IBIST", MT6351_AUDDEC_ANA_CON9,
1129                 RG_AUDIBIASPWRDN_VAUDP32_BIT, 1, NULL, 0),
1130     SND_SOC_DAPM_SUPPLY("LDO", MT6351_AUDDEC_ANA_CON9,
1131                 RG_LCLDO_DEC_EN_VA32_BIT, 0, NULL, 0),
1132     SND_SOC_DAPM_SUPPLY("LDO_REMOTE_SENSE", MT6351_AUDDEC_ANA_CON9,
1133                 RG_LCLDO_DEC_REMOTE_SENSE_VA18_BIT, 0, NULL, 0),
1134 
1135     /* DAC */
1136     SND_SOC_DAPM_MUX("DAC In Mux", SND_SOC_NOPM, 0, 0, &dac_in_mux_control),
1137 
1138     SND_SOC_DAPM_DAC("DACL", NULL, MT6351_AUDDEC_ANA_CON0,
1139              RG_AUDDACLPWRUP_VAUDP32_BIT, 0),
1140     SND_SOC_DAPM_SUPPLY("DACL_BIASGEN", MT6351_AUDDEC_ANA_CON0,
1141                 RG_AUD_DAC_PWL_UP_VA32_BIT, 0, NULL, 0),
1142 
1143     SND_SOC_DAPM_DAC("DACR", NULL, MT6351_AUDDEC_ANA_CON0,
1144              RG_AUDDACRPWRUP_VAUDP32_BIT, 0),
1145     SND_SOC_DAPM_SUPPLY("DACR_BIASGEN", MT6351_AUDDEC_ANA_CON0,
1146                 RG_AUD_DAC_PWR_UP_VA32_BIT, 0, NULL, 0),
1147     /* LOL */
1148     SND_SOC_DAPM_MUX("LOL Mux", SND_SOC_NOPM, 0, 0, &lo_in_mux_control),
1149 
1150     SND_SOC_DAPM_SUPPLY("LO Stability Enh", MT6351_AUDDEC_ANA_CON3,
1151                 RG_LOOUTPUTSTBENH_VAUDP32_BIT, 0, NULL, 0),
1152     SND_SOC_DAPM_SUPPLY("LOL Bias Gen", MT6351_AUDDEC_ANA_CON6,
1153                 RG_ABIDEC_RSVD0_VAUDP32_LOL_BIT, 0, NULL, 0),
1154 
1155     SND_SOC_DAPM_OUT_DRV("LOL Buffer", MT6351_AUDDEC_ANA_CON3,
1156                  RG_AUDLOLPWRUP_VAUDP32_BIT, 0, NULL, 0),
1157 
1158     /* Headphone */
1159     SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0, &hpl_in_mux_control),
1160     SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0, &hpr_in_mux_control),
1161 
1162     SND_SOC_DAPM_OUT_DRV_E("HPL Power", MT6351_AUDDEC_ANA_CON0,
1163                    RG_AUDHPLPWRUP_VAUDP32_BIT, 0, NULL, 0,
1164                    mt_hp_event,
1165                    SND_SOC_DAPM_PRE_PMU |
1166                    SND_SOC_DAPM_PRE_PMD |
1167                    SND_SOC_DAPM_POST_PMD),
1168     SND_SOC_DAPM_OUT_DRV_E("HPR Power", MT6351_AUDDEC_ANA_CON0,
1169                    RG_AUDHPRPWRUP_VAUDP32_BIT, 0, NULL, 0,
1170                    mt_hp_event,
1171                    SND_SOC_DAPM_PRE_PMU |
1172                    SND_SOC_DAPM_PRE_PMD |
1173                    SND_SOC_DAPM_POST_PMD),
1174 
1175     /* Receiver */
1176     SND_SOC_DAPM_MUX("RCV Mux", SND_SOC_NOPM, 0, 0, &rcv_in_mux_control),
1177 
1178     SND_SOC_DAPM_SUPPLY("RCV Stability Enh", MT6351_AUDDEC_ANA_CON1,
1179                 RG_HSOUTPUTSTBENH_VAUDP32_BIT, 0, NULL, 0),
1180     SND_SOC_DAPM_SUPPLY("RCV Bias Gen", MT6351_AUDDEC_ANA_CON6,
1181                 RG_ABIDEC_RSVD0_VAUDP32_HS_BIT, 0, NULL, 0),
1182 
1183     SND_SOC_DAPM_OUT_DRV("RCV Buffer", MT6351_AUDDEC_ANA_CON0,
1184                  RG_AUDHSPWRUP_VAUDP32_BIT, 0, NULL, 0),
1185 
1186     /* Outputs */
1187     SND_SOC_DAPM_OUTPUT("Receiver"),
1188     SND_SOC_DAPM_OUTPUT("Headphone L"),
1189     SND_SOC_DAPM_OUTPUT("Headphone R"),
1190     SND_SOC_DAPM_OUTPUT("LINEOUT L"),
1191 
1192     /* SGEN */
1193     SND_SOC_DAPM_SUPPLY("SGEN DL Enable", MT6351_AFE_SGEN_CFG0,
1194                 SGEN_C_DAC_EN_CTL_BIT, 0, NULL, 0),
1195     SND_SOC_DAPM_SUPPLY("SGEN MUTE", MT6351_AFE_SGEN_CFG0,
1196                 SGEN_C_MUTE_SW_CTL_BIT, 1,
1197                 mt_sgen_event, SND_SOC_DAPM_PRE_PMU),
1198     SND_SOC_DAPM_SUPPLY("SGEN DL SRC", MT6351_AFE_DL_SRC2_CON0_L,
1199                 RG_DL_2_SRC_ON_TMP_CTL_PRE_BIT, 0, NULL, 0),
1200 
1201     SND_SOC_DAPM_INPUT("SGEN DL"),
1202 
1203     /* Uplinks */
1204     SND_SOC_DAPM_AIF_OUT_E("AIF1TX", "AIF1 Capture", 0,
1205                    MT6351_AFE_UL_SRC_CON0_L,
1206                    UL_SRC_ON_TMP_CTL, 0,
1207                    mt_aif_out_event,
1208                    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1209 
1210     SND_SOC_DAPM_SUPPLY_S("VUSB33_LDO", SUPPLY_SUBSEQ_ENABLE,
1211                   MT6351_LDO_VUSB33_CON0, RG_VUSB33_EN, 0,
1212                   NULL, 0),
1213     SND_SOC_DAPM_SUPPLY_S("VUSB33_LDO_CTRL", SUPPLY_SUBSEQ_SETTING,
1214                   MT6351_LDO_VUSB33_CON0, RG_VUSB33_ON_CTRL, 1,
1215                   NULL, 0),
1216 
1217     SND_SOC_DAPM_SUPPLY_S("VA18_LDO", SUPPLY_SUBSEQ_ENABLE,
1218                   MT6351_LDO_VA18_CON0, RG_VA18_EN, 0, NULL, 0),
1219     SND_SOC_DAPM_SUPPLY_S("VA18_LDO_CTRL", SUPPLY_SUBSEQ_SETTING,
1220                   MT6351_LDO_VA18_CON0, RG_VA18_ON_CTRL, 1,
1221                   NULL, 0),
1222 
1223     SND_SOC_DAPM_SUPPLY_S("ADC CLKGEN", SUPPLY_SUBSEQ_ENABLE,
1224                   MT6351_AUDENC_ANA_CON3, RG_AUDADCCLKRSTB, 0,
1225                   mt_adc_clkgen_event,
1226                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1227 
1228     /* Uplinks MUX */
1229     SND_SOC_DAPM_MUX("AIF Out Mux", SND_SOC_NOPM, 0, 0,
1230              &aif_out_mux_control),
1231 
1232     SND_SOC_DAPM_MUX("ADC L Mux", SND_SOC_NOPM, 0, 0,
1233              &adc_left_mux_control),
1234     SND_SOC_DAPM_MUX("ADC R Mux", SND_SOC_NOPM, 0, 0,
1235              &adc_right_mux_control),
1236 
1237     SND_SOC_DAPM_ADC("ADC L", NULL,
1238              MT6351_AUDENC_ANA_CON0, RG_AUDADCLPWRUP, 0),
1239     SND_SOC_DAPM_ADC("ADC R", NULL,
1240              MT6351_AUDENC_ANA_CON1, RG_AUDADCRPWRUP, 0),
1241 
1242     SND_SOC_DAPM_MUX("PGA L Mux", SND_SOC_NOPM, 0, 0,
1243              &pga_left_mux_control),
1244     SND_SOC_DAPM_MUX("PGA R Mux", SND_SOC_NOPM, 0, 0,
1245              &pga_right_mux_control),
1246 
1247     SND_SOC_DAPM_PGA_E("PGA L", MT6351_AUDENC_ANA_CON0, RG_AUDPREAMPLON, 0,
1248                NULL, 0,
1249                mt_pga_left_event,
1250                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1251     SND_SOC_DAPM_PGA_E("PGA R", MT6351_AUDENC_ANA_CON1, RG_AUDPREAMPRON, 0,
1252                NULL, 0,
1253                mt_pga_right_event,
1254                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1255 
1256     /* main mic mic bias */
1257     SND_SOC_DAPM_SUPPLY_S("Mic Bias 0", SUPPLY_SUBSEQ_MICBIAS,
1258                   MT6351_AUDENC_ANA_CON9, RG_AUDPWDBMICBIAS0, 0,
1259                   mt_mic_bias_0_event,
1260                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1261     /* ref mic mic bias */
1262     SND_SOC_DAPM_SUPPLY_S("Mic Bias 2", SUPPLY_SUBSEQ_MICBIAS,
1263                   MT6351_AUDENC_ANA_CON9, RG_AUDPWDBMICBIAS2, 0,
1264                   mt_mic_bias_2_event,
1265                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1266     /* headset mic1/2 mic bias */
1267     SND_SOC_DAPM_SUPPLY_S("Mic Bias 1", SUPPLY_SUBSEQ_MICBIAS,
1268                   MT6351_AUDENC_ANA_CON10, RG_AUDPWDBMICBIAS1, 0,
1269                   mt_mic_bias_1_event,
1270                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1271     SND_SOC_DAPM_SUPPLY_S("Mic Bias 1 DCC pull high", SUPPLY_SUBSEQ_MICBIAS,
1272                   MT6351_AUDENC_ANA_CON10,
1273                   RG_AUDMICBIAS1DCSW1NEN, 0,
1274                   NULL, 0),
1275 
1276     /* UL input */
1277     SND_SOC_DAPM_INPUT("AIN0"),
1278     SND_SOC_DAPM_INPUT("AIN1"),
1279     SND_SOC_DAPM_INPUT("AIN2"),
1280     SND_SOC_DAPM_INPUT("AIN3"),
1281 };
1282 
1283 static const struct snd_soc_dapm_route mt6351_dapm_routes[] = {
1284     /* Capture */
1285     {"AIF1TX", NULL, "AIF Out Mux"},
1286     {"AIF1TX", NULL, "VUSB33_LDO"},
1287     {"VUSB33_LDO", NULL, "VUSB33_LDO_CTRL"},
1288     {"AIF1TX", NULL, "VA18_LDO"},
1289     {"VA18_LDO", NULL, "VA18_LDO_CTRL"},
1290 
1291     {"AIF1TX", NULL, "AUDGLB"},
1292     {"AIF1TX", NULL, "CLKSQ Audio"},
1293 
1294     {"AIF1TX", NULL, "AFE_ON"},
1295 
1296     {"AIF1TX", NULL, "AUDIO_TOP_AFE_CTL"},
1297     {"AIF1TX", NULL, "AUDIO_TOP_ADC_CTL"},
1298     {"AIF1TX", NULL, "AUDIO_TOP_PWR_CLK"},
1299     {"AIF1TX", NULL, "AUDIO_TOP_PDN_RESERVED"},
1300 
1301     {"AIF Out Mux", "Normal Path", "ADC L"},
1302     {"AIF Out Mux", "Normal Path", "ADC R"},
1303 
1304     {"ADC L", NULL, "ADC L Mux"},
1305     {"ADC L", NULL, "AUD_CK"},
1306     {"ADC L", NULL, "AUDIF_CK"},
1307     {"ADC L", NULL, "ADC CLKGEN"},
1308     {"ADC R", NULL, "ADC R Mux"},
1309     {"ADC R", NULL, "AUD_CK"},
1310     {"ADC R", NULL, "AUDIF_CK"},
1311     {"ADC R", NULL, "ADC CLKGEN"},
1312 
1313     {"ADC L Mux", "AIN0", "AIN0"},
1314     {"ADC L Mux", "Left Preamplifier", "PGA L"},
1315 
1316     {"ADC R Mux", "AIN0", "AIN0"},
1317     {"ADC R Mux", "Right Preamplifier", "PGA R"},
1318 
1319     {"PGA L", NULL, "PGA L Mux"},
1320     {"PGA R", NULL, "PGA R Mux"},
1321 
1322     {"PGA L Mux", "AIN0", "AIN0"},
1323     {"PGA L Mux", "AIN1", "AIN1"},
1324     {"PGA L Mux", "AIN2", "AIN2"},
1325 
1326     {"PGA R Mux", "AIN0", "AIN0"},
1327     {"PGA R Mux", "AIN3", "AIN3"},
1328     {"PGA R Mux", "AIN2", "AIN2"},
1329 
1330     {"AIN0", NULL, "Mic Bias 0"},
1331     {"AIN2", NULL, "Mic Bias 2"},
1332 
1333     {"AIN1", NULL, "Mic Bias 1"},
1334     {"AIN1", NULL, "Mic Bias 1 DCC pull high"},
1335 
1336     /* DL Supply */
1337     {"DL Power Supply", NULL, "AUDGLB"},
1338     {"DL Power Supply", NULL, "CLKSQ Audio"},
1339     {"DL Power Supply", NULL, "ZCD13M_CK"},
1340     {"DL Power Supply", NULL, "AUD_CK"},
1341     {"DL Power Supply", NULL, "AUDIF_CK"},
1342     {"DL Power Supply", NULL, "AUDNCP_CK"},
1343 
1344     {"DL Power Supply", NULL, "NV Regulator"},
1345     {"DL Power Supply", NULL, "AUD_CLK"},
1346     {"DL Power Supply", NULL, "IBIST"},
1347     {"DL Power Supply", NULL, "LDO"},
1348     {"LDO", NULL, "LDO_REMOTE_SENSE"},
1349 
1350     /* DL Digital Supply */
1351     {"DL Digital Clock", NULL, "AUDIO_TOP_AFE_CTL"},
1352     {"DL Digital Clock", NULL, "AUDIO_TOP_DAC_CTL"},
1353     {"DL Digital Clock", NULL, "AUDIO_TOP_PWR_CLK"},
1354     {"DL Digital Clock", NULL, "AUDIO_TOP_PDN_RESERVED"},
1355     {"DL Digital Clock", NULL, "NCP"},
1356     {"DL Digital Clock", NULL, "AFE_ON"},
1357 
1358     {"AIF_RX", NULL, "DL Digital Clock"},
1359 
1360     /* DL Path */
1361     {"DAC In Mux", "Normal Path", "AIF_RX"},
1362 
1363     {"DAC In Mux", "Sgen", "SGEN DL"},
1364     {"SGEN DL", NULL, "SGEN DL SRC"},
1365     {"SGEN DL", NULL, "SGEN MUTE"},
1366     {"SGEN DL", NULL, "SGEN DL Enable"},
1367     {"SGEN DL", NULL, "DL Digital Clock"},
1368 
1369     {"DACL", NULL, "DAC In Mux"},
1370     {"DACL", NULL, "DL Power Supply"},
1371     {"DACL", NULL, "DACL_BIASGEN"},
1372 
1373     {"DACR", NULL, "DAC In Mux"},
1374     {"DACR", NULL, "DL Power Supply"},
1375     {"DACR", NULL, "DACR_BIASGEN"},
1376 
1377     {"LOL Mux", "Playback", "DACL"},
1378 
1379     {"LOL Buffer", NULL, "LOL Mux"},
1380     {"LOL Buffer", NULL, "LO Stability Enh"},
1381     {"LOL Buffer", NULL, "LOL Bias Gen"},
1382 
1383     {"LINEOUT L", NULL, "LOL Buffer"},
1384 
1385     /* Headphone Path */
1386     {"HPL Mux", "Audio Playback", "DACL"},
1387     {"HPR Mux", "Audio Playback", "DACR"},
1388 
1389     {"HPL Mux", "LoudSPK Playback", "DACL"},
1390     {"HPR Mux", "LoudSPK Playback", "DACR"},
1391 
1392     {"HPL Power", NULL, "HPL Mux"},
1393     {"HPR Power", NULL, "HPR Mux"},
1394 
1395     {"Headphone L", NULL, "HPL Power"},
1396     {"Headphone R", NULL, "HPR Power"},
1397 
1398     /* Receiver Path */
1399     {"RCV Mux", "Voice Playback", "DACL"},
1400 
1401     {"RCV Buffer", NULL, "RCV Mux"},
1402     {"RCV Buffer", NULL, "RCV Stability Enh"},
1403     {"RCV Buffer", NULL, "RCV Bias Gen"},
1404 
1405     {"Receiver", NULL, "RCV Buffer"},
1406 };
1407 
1408 static int mt6351_codec_init_reg(struct snd_soc_component *cmpnt)
1409 {
1410     /* Disable CLKSQ 26MHz */
1411     regmap_update_bits(cmpnt->regmap, MT6351_TOP_CLKSQ, 0x0001, 0x0);
1412     /* disable AUDGLB */
1413     regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON9,
1414                0x1000, 0x1000);
1415     /* Turn off AUDNCP_CLKDIV engine clock,Turn off AUD 26M */
1416     regmap_update_bits(cmpnt->regmap, MT6351_TOP_CKPDN_CON0_SET,
1417                0x3800, 0x3800);
1418     /* Disable HeadphoneL/HeadphoneR/voice short circuit protection */
1419     regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON0,
1420                0xe000, 0xe000);
1421     /* [5] = 1, disable LO buffer left short circuit protection */
1422     regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON3,
1423                0x20, 0x20);
1424     /* Reverse the PMIC clock*/
1425     regmap_update_bits(cmpnt->regmap, MT6351_AFE_PMIC_NEWIF_CFG2,
1426                0x8000, 0x8000);
1427     return 0;
1428 }
1429 
1430 static int mt6351_codec_probe(struct snd_soc_component *cmpnt)
1431 {
1432     struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1433 
1434     snd_soc_component_init_regmap(cmpnt, priv->regmap);
1435 
1436     mt6351_codec_init_reg(cmpnt);
1437     return 0;
1438 }
1439 
1440 static const struct snd_soc_component_driver mt6351_soc_component_driver = {
1441     .probe = mt6351_codec_probe,
1442     .controls = mt6351_snd_controls,
1443     .num_controls = ARRAY_SIZE(mt6351_snd_controls),
1444     .dapm_widgets = mt6351_dapm_widgets,
1445     .num_dapm_widgets = ARRAY_SIZE(mt6351_dapm_widgets),
1446     .dapm_routes = mt6351_dapm_routes,
1447     .num_dapm_routes = ARRAY_SIZE(mt6351_dapm_routes),
1448     .endianness = 1,
1449 };
1450 
1451 static int mt6351_codec_driver_probe(struct platform_device *pdev)
1452 {
1453     struct mt6351_priv *priv;
1454 
1455     priv = devm_kzalloc(&pdev->dev,
1456                 sizeof(struct mt6351_priv),
1457                 GFP_KERNEL);
1458     if (!priv)
1459         return -ENOMEM;
1460 
1461     dev_set_drvdata(&pdev->dev, priv);
1462 
1463     priv->dev = &pdev->dev;
1464 
1465     priv->regmap = dev_get_regmap(pdev->dev.parent, NULL);
1466     if (!priv->regmap)
1467         return -ENODEV;
1468 
1469     dev_dbg(priv->dev, "%s(), dev name %s\n",
1470         __func__, dev_name(&pdev->dev));
1471 
1472     return devm_snd_soc_register_component(&pdev->dev,
1473                            &mt6351_soc_component_driver,
1474                            mt6351_dai_driver,
1475                            ARRAY_SIZE(mt6351_dai_driver));
1476 }
1477 
1478 static const struct of_device_id mt6351_of_match[] = {
1479     {.compatible = "mediatek,mt6351-sound",},
1480     {}
1481 };
1482 
1483 static struct platform_driver mt6351_codec_driver = {
1484     .driver = {
1485         .name = "mt6351-sound",
1486         .of_match_table = mt6351_of_match,
1487     },
1488     .probe = mt6351_codec_driver_probe,
1489 };
1490 
1491 module_platform_driver(mt6351_codec_driver)
1492 
1493 /* Module information */
1494 MODULE_DESCRIPTION("MT6351 ALSA SoC codec driver");
1495 MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>");
1496 MODULE_LICENSE("GPL v2");
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