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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (c) 2016, The Linux Foundation. All rights reserved.
0003 
0004 #include <linux/module.h>
0005 #include <linux/err.h>
0006 #include <linux/kernel.h>
0007 #include <linux/delay.h>
0008 #include <linux/types.h>
0009 #include <linux/clk.h>
0010 #include <linux/of.h>
0011 #include <linux/platform_device.h>
0012 #include <linux/regmap.h>
0013 #include <linux/mfd/syscon.h>
0014 #include <sound/soc.h>
0015 #include <sound/pcm.h>
0016 #include <sound/pcm_params.h>
0017 #include <sound/tlv.h>
0018 
0019 #define LPASS_CDC_CLK_RX_RESET_CTL      (0x000)
0020 #define LPASS_CDC_CLK_TX_RESET_B1_CTL       (0x004)
0021 #define CLK_RX_RESET_B1_CTL_TX1_RESET_MASK  BIT(0)
0022 #define CLK_RX_RESET_B1_CTL_TX2_RESET_MASK  BIT(1)
0023 #define LPASS_CDC_CLK_DMIC_B1_CTL       (0x008)
0024 #define DMIC_B1_CTL_DMIC0_CLK_SEL_MASK      GENMASK(3, 1)
0025 #define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV2      (0x0 << 1)
0026 #define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV3      (0x1 << 1)
0027 #define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV4      (0x2 << 1)
0028 #define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV6      (0x3 << 1)
0029 #define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV16     (0x4 << 1)
0030 #define DMIC_B1_CTL_DMIC0_CLK_EN_MASK       BIT(0)
0031 #define DMIC_B1_CTL_DMIC0_CLK_EN_ENABLE     BIT(0)
0032 
0033 #define LPASS_CDC_CLK_RX_I2S_CTL        (0x00C)
0034 #define RX_I2S_CTL_RX_I2S_MODE_MASK     BIT(5)
0035 #define RX_I2S_CTL_RX_I2S_MODE_16       BIT(5)
0036 #define RX_I2S_CTL_RX_I2S_MODE_32       0
0037 #define RX_I2S_CTL_RX_I2S_FS_RATE_MASK      GENMASK(2, 0)
0038 #define RX_I2S_CTL_RX_I2S_FS_RATE_F_8_KHZ   0x0
0039 #define RX_I2S_CTL_RX_I2S_FS_RATE_F_16_KHZ  0x1
0040 #define RX_I2S_CTL_RX_I2S_FS_RATE_F_32_KHZ  0x2
0041 #define RX_I2S_CTL_RX_I2S_FS_RATE_F_48_KHZ  0x3
0042 #define RX_I2S_CTL_RX_I2S_FS_RATE_F_96_KHZ  0x4
0043 #define RX_I2S_CTL_RX_I2S_FS_RATE_F_192_KHZ 0x5
0044 #define LPASS_CDC_CLK_TX_I2S_CTL        (0x010)
0045 #define TX_I2S_CTL_TX_I2S_MODE_MASK     BIT(5)
0046 #define TX_I2S_CTL_TX_I2S_MODE_16       BIT(5)
0047 #define TX_I2S_CTL_TX_I2S_MODE_32       0
0048 #define TX_I2S_CTL_TX_I2S_FS_RATE_MASK      GENMASK(2, 0)
0049 #define TX_I2S_CTL_TX_I2S_FS_RATE_F_8_KHZ   0x0
0050 #define TX_I2S_CTL_TX_I2S_FS_RATE_F_16_KHZ  0x1
0051 #define TX_I2S_CTL_TX_I2S_FS_RATE_F_32_KHZ  0x2
0052 #define TX_I2S_CTL_TX_I2S_FS_RATE_F_48_KHZ  0x3
0053 #define TX_I2S_CTL_TX_I2S_FS_RATE_F_96_KHZ  0x4
0054 #define TX_I2S_CTL_TX_I2S_FS_RATE_F_192_KHZ 0x5
0055 
0056 #define LPASS_CDC_CLK_OTHR_RESET_B1_CTL     (0x014)
0057 #define LPASS_CDC_CLK_TX_CLK_EN_B1_CTL      (0x018)
0058 #define LPASS_CDC_CLK_OTHR_CTL          (0x01C)
0059 #define LPASS_CDC_CLK_RX_B1_CTL         (0x020)
0060 #define LPASS_CDC_CLK_MCLK_CTL          (0x024)
0061 #define MCLK_CTL_MCLK_EN_MASK           BIT(0)
0062 #define MCLK_CTL_MCLK_EN_ENABLE         BIT(0)
0063 #define MCLK_CTL_MCLK_EN_DISABLE        0
0064 #define LPASS_CDC_CLK_PDM_CTL           (0x028)
0065 #define LPASS_CDC_CLK_PDM_CTL_PDM_EN_MASK   BIT(0)
0066 #define LPASS_CDC_CLK_PDM_CTL_PDM_EN        BIT(0)
0067 #define LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_MASK  BIT(1)
0068 #define LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_FB    BIT(1)
0069 #define LPASS_CDC_CLK_PDM_CTL_PDM_CLK_PDM_CLK   0
0070 
0071 #define LPASS_CDC_CLK_SD_CTL            (0x02C)
0072 #define LPASS_CDC_RX1_B1_CTL            (0x040)
0073 #define LPASS_CDC_RX2_B1_CTL            (0x060)
0074 #define LPASS_CDC_RX3_B1_CTL            (0x080)
0075 #define LPASS_CDC_RX1_B2_CTL            (0x044)
0076 #define LPASS_CDC_RX2_B2_CTL            (0x064)
0077 #define LPASS_CDC_RX3_B2_CTL            (0x084)
0078 #define LPASS_CDC_RX1_B3_CTL            (0x048)
0079 #define LPASS_CDC_RX2_B3_CTL            (0x068)
0080 #define LPASS_CDC_RX3_B3_CTL            (0x088)
0081 #define LPASS_CDC_RX1_B4_CTL            (0x04C)
0082 #define LPASS_CDC_RX2_B4_CTL            (0x06C)
0083 #define LPASS_CDC_RX3_B4_CTL            (0x08C)
0084 #define LPASS_CDC_RX1_B5_CTL            (0x050)
0085 #define LPASS_CDC_RX2_B5_CTL            (0x070)
0086 #define LPASS_CDC_RX3_B5_CTL            (0x090)
0087 #define LPASS_CDC_RX1_B6_CTL            (0x054)
0088 #define RXn_B6_CTL_MUTE_MASK            BIT(0)
0089 #define RXn_B6_CTL_MUTE_ENABLE          BIT(0)
0090 #define RXn_B6_CTL_MUTE_DISABLE         0
0091 #define LPASS_CDC_RX2_B6_CTL            (0x074)
0092 #define LPASS_CDC_RX3_B6_CTL            (0x094)
0093 #define LPASS_CDC_RX1_VOL_CTL_B1_CTL        (0x058)
0094 #define LPASS_CDC_RX2_VOL_CTL_B1_CTL        (0x078)
0095 #define LPASS_CDC_RX3_VOL_CTL_B1_CTL        (0x098)
0096 #define LPASS_CDC_RX1_VOL_CTL_B2_CTL        (0x05C)
0097 #define LPASS_CDC_RX2_VOL_CTL_B2_CTL        (0x07C)
0098 #define LPASS_CDC_RX3_VOL_CTL_B2_CTL        (0x09C)
0099 #define LPASS_CDC_TOP_GAIN_UPDATE       (0x0A0)
0100 #define LPASS_CDC_TOP_CTL           (0x0A4)
0101 #define TOP_CTL_DIG_MCLK_FREQ_MASK      BIT(0)
0102 #define TOP_CTL_DIG_MCLK_FREQ_F_12_288MHZ   0
0103 #define TOP_CTL_DIG_MCLK_FREQ_F_9_6MHZ      BIT(0)
0104 
0105 #define LPASS_CDC_DEBUG_DESER1_CTL      (0x0E0)
0106 #define LPASS_CDC_DEBUG_DESER2_CTL      (0x0E4)
0107 #define LPASS_CDC_DEBUG_B1_CTL_CFG      (0x0E8)
0108 #define LPASS_CDC_DEBUG_B2_CTL_CFG      (0x0EC)
0109 #define LPASS_CDC_DEBUG_B3_CTL_CFG      (0x0F0)
0110 #define LPASS_CDC_IIR1_GAIN_B1_CTL      (0x100)
0111 #define LPASS_CDC_IIR2_GAIN_B1_CTL      (0x140)
0112 #define LPASS_CDC_IIR1_GAIN_B2_CTL      (0x104)
0113 #define LPASS_CDC_IIR2_GAIN_B2_CTL      (0x144)
0114 #define LPASS_CDC_IIR1_GAIN_B3_CTL      (0x108)
0115 #define LPASS_CDC_IIR2_GAIN_B3_CTL      (0x148)
0116 #define LPASS_CDC_IIR1_GAIN_B4_CTL      (0x10C)
0117 #define LPASS_CDC_IIR2_GAIN_B4_CTL      (0x14C)
0118 #define LPASS_CDC_IIR1_GAIN_B5_CTL      (0x110)
0119 #define LPASS_CDC_IIR2_GAIN_B5_CTL      (0x150)
0120 #define LPASS_CDC_IIR1_GAIN_B6_CTL      (0x114)
0121 #define LPASS_CDC_IIR2_GAIN_B6_CTL      (0x154)
0122 #define LPASS_CDC_IIR1_GAIN_B7_CTL      (0x118)
0123 #define LPASS_CDC_IIR2_GAIN_B7_CTL      (0x158)
0124 #define LPASS_CDC_IIR1_GAIN_B8_CTL      (0x11C)
0125 #define LPASS_CDC_IIR2_GAIN_B8_CTL      (0x15C)
0126 #define LPASS_CDC_IIR1_CTL          (0x120)
0127 #define LPASS_CDC_IIR2_CTL          (0x160)
0128 #define LPASS_CDC_IIR1_GAIN_TIMER_CTL       (0x124)
0129 #define LPASS_CDC_IIR2_GAIN_TIMER_CTL       (0x164)
0130 #define LPASS_CDC_IIR1_COEF_B1_CTL      (0x128)
0131 #define LPASS_CDC_IIR2_COEF_B1_CTL      (0x168)
0132 #define LPASS_CDC_IIR1_COEF_B2_CTL      (0x12C)
0133 #define LPASS_CDC_IIR2_COEF_B2_CTL      (0x16C)
0134 #define LPASS_CDC_CONN_RX1_B1_CTL       (0x180)
0135 #define LPASS_CDC_CONN_RX1_B2_CTL       (0x184)
0136 #define LPASS_CDC_CONN_RX1_B3_CTL       (0x188)
0137 #define LPASS_CDC_CONN_RX2_B1_CTL       (0x18C)
0138 #define LPASS_CDC_CONN_RX2_B2_CTL       (0x190)
0139 #define LPASS_CDC_CONN_RX2_B3_CTL       (0x194)
0140 #define LPASS_CDC_CONN_RX3_B1_CTL       (0x198)
0141 #define LPASS_CDC_CONN_RX3_B2_CTL       (0x19C)
0142 #define LPASS_CDC_CONN_TX_B1_CTL        (0x1A0)
0143 #define LPASS_CDC_CONN_EQ1_B1_CTL       (0x1A8)
0144 #define LPASS_CDC_CONN_EQ1_B2_CTL       (0x1AC)
0145 #define LPASS_CDC_CONN_EQ1_B3_CTL       (0x1B0)
0146 #define LPASS_CDC_CONN_EQ1_B4_CTL       (0x1B4)
0147 #define LPASS_CDC_CONN_EQ2_B1_CTL       (0x1B8)
0148 #define LPASS_CDC_CONN_EQ2_B2_CTL       (0x1BC)
0149 #define LPASS_CDC_CONN_EQ2_B3_CTL       (0x1C0)
0150 #define LPASS_CDC_CONN_EQ2_B4_CTL       (0x1C4)
0151 #define LPASS_CDC_CONN_TX_I2S_SD1_CTL       (0x1C8)
0152 #define LPASS_CDC_TX1_VOL_CTL_TIMER     (0x280)
0153 #define LPASS_CDC_TX2_VOL_CTL_TIMER     (0x2A0)
0154 #define LPASS_CDC_TX1_VOL_CTL_GAIN      (0x284)
0155 #define LPASS_CDC_TX2_VOL_CTL_GAIN      (0x2A4)
0156 #define LPASS_CDC_TX1_VOL_CTL_CFG       (0x288)
0157 #define TX_VOL_CTL_CFG_MUTE_EN_MASK     BIT(0)
0158 #define TX_VOL_CTL_CFG_MUTE_EN_ENABLE       BIT(0)
0159 
0160 #define LPASS_CDC_TX2_VOL_CTL_CFG       (0x2A8)
0161 #define LPASS_CDC_TX1_MUX_CTL           (0x28C)
0162 #define TX_MUX_CTL_CUT_OFF_FREQ_MASK        GENMASK(5, 4)
0163 #define TX_MUX_CTL_CUT_OFF_FREQ_SHIFT       4
0164 #define TX_MUX_CTL_CF_NEG_3DB_4HZ       (0x0 << 4)
0165 #define TX_MUX_CTL_CF_NEG_3DB_75HZ      (0x1 << 4)
0166 #define TX_MUX_CTL_CF_NEG_3DB_150HZ     (0x2 << 4)
0167 #define TX_MUX_CTL_HPF_BP_SEL_MASK      BIT(3)
0168 #define TX_MUX_CTL_HPF_BP_SEL_BYPASS        BIT(3)
0169 #define TX_MUX_CTL_HPF_BP_SEL_NO_BYPASS     0
0170 
0171 #define LPASS_CDC_TX2_MUX_CTL           (0x2AC)
0172 #define LPASS_CDC_TX1_CLK_FS_CTL        (0x290)
0173 #define LPASS_CDC_TX2_CLK_FS_CTL        (0x2B0)
0174 #define LPASS_CDC_TX1_DMIC_CTL          (0x294)
0175 #define LPASS_CDC_TX2_DMIC_CTL          (0x2B4)
0176 #define TXN_DMIC_CTL_CLK_SEL_MASK       GENMASK(2, 0)
0177 #define TXN_DMIC_CTL_CLK_SEL_DIV2       0x0
0178 #define TXN_DMIC_CTL_CLK_SEL_DIV3       0x1
0179 #define TXN_DMIC_CTL_CLK_SEL_DIV4       0x2
0180 #define TXN_DMIC_CTL_CLK_SEL_DIV6       0x3
0181 #define TXN_DMIC_CTL_CLK_SEL_DIV16      0x4
0182 
0183 #define MSM8916_WCD_DIGITAL_RATES (SNDRV_PCM_RATE_8000 | \
0184                    SNDRV_PCM_RATE_16000 | \
0185                    SNDRV_PCM_RATE_32000 | \
0186                    SNDRV_PCM_RATE_48000)
0187 #define MSM8916_WCD_DIGITAL_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
0188                      SNDRV_PCM_FMTBIT_S32_LE)
0189 
0190 /* Codec supports 2 IIR filters */
0191 enum {
0192     IIR1 = 0,
0193     IIR2,
0194     IIR_MAX,
0195 };
0196 
0197 /* Codec supports 5 bands */
0198 enum {
0199     BAND1 = 0,
0200     BAND2,
0201     BAND3,
0202     BAND4,
0203     BAND5,
0204     BAND_MAX,
0205 };
0206 
0207 #define WCD_IIR_FILTER_SIZE (sizeof(u32)*BAND_MAX)
0208 
0209 #define WCD_IIR_FILTER_CTL(xname, iidx, bidx) \
0210 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
0211     .info = wcd_iir_filter_info, \
0212     .get = msm8x16_wcd_get_iir_band_audio_mixer, \
0213     .put = msm8x16_wcd_put_iir_band_audio_mixer, \
0214     .private_value = (unsigned long)&(struct wcd_iir_filter_ctl) { \
0215         .iir_idx = iidx, \
0216         .band_idx = bidx, \
0217         .bytes_ext = {.max = WCD_IIR_FILTER_SIZE, }, \
0218     } \
0219 }
0220 
0221 struct wcd_iir_filter_ctl {
0222     unsigned int iir_idx;
0223     unsigned int band_idx;
0224     struct soc_bytes_ext bytes_ext;
0225 };
0226 
0227 struct msm8916_wcd_digital_priv {
0228     struct clk *ahbclk, *mclk;
0229 };
0230 
0231 static const unsigned long rx_gain_reg[] = {
0232     LPASS_CDC_RX1_VOL_CTL_B2_CTL,
0233     LPASS_CDC_RX2_VOL_CTL_B2_CTL,
0234     LPASS_CDC_RX3_VOL_CTL_B2_CTL,
0235 };
0236 
0237 static const unsigned long tx_gain_reg[] = {
0238     LPASS_CDC_TX1_VOL_CTL_GAIN,
0239     LPASS_CDC_TX2_VOL_CTL_GAIN,
0240 };
0241 
0242 static const char *const rx_mix1_text[] = {
0243     "ZERO", "IIR1", "IIR2", "RX1", "RX2", "RX3"
0244 };
0245 
0246 static const char * const rx_mix2_text[] = {
0247     "ZERO", "IIR1", "IIR2"
0248 };
0249 
0250 static const char *const dec_mux_text[] = {
0251     "ZERO", "ADC1", "ADC2", "ADC3", "DMIC1", "DMIC2"
0252 };
0253 
0254 static const char *const cic_mux_text[] = { "AMIC", "DMIC" };
0255 
0256 /* RX1 MIX1 */
0257 static const struct soc_enum rx_mix1_inp_enum[] = {
0258     SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX1_B1_CTL, 0, 6, rx_mix1_text),
0259     SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX1_B1_CTL, 3, 6, rx_mix1_text),
0260     SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX1_B2_CTL, 0, 6, rx_mix1_text),
0261 };
0262 
0263 /* RX2 MIX1 */
0264 static const struct soc_enum rx2_mix1_inp_enum[] = {
0265     SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX2_B1_CTL, 0, 6, rx_mix1_text),
0266     SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX2_B1_CTL, 3, 6, rx_mix1_text),
0267     SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX2_B2_CTL, 0, 6, rx_mix1_text),
0268 };
0269 
0270 /* RX3 MIX1 */
0271 static const struct soc_enum rx3_mix1_inp_enum[] = {
0272     SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX3_B1_CTL, 0, 6, rx_mix1_text),
0273     SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX3_B1_CTL, 3, 6, rx_mix1_text),
0274     SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX3_B2_CTL, 0, 6, rx_mix1_text),
0275 };
0276 
0277 /* RX1 MIX2 */
0278 static const struct soc_enum rx_mix2_inp1_chain_enum =
0279     SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX1_B3_CTL,
0280         0, 3, rx_mix2_text);
0281 
0282 /* RX2 MIX2 */
0283 static const struct soc_enum rx2_mix2_inp1_chain_enum =
0284     SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX2_B3_CTL,
0285         0, 3, rx_mix2_text);
0286 
0287 /* DEC */
0288 static const struct soc_enum dec1_mux_enum = SOC_ENUM_SINGLE(
0289                 LPASS_CDC_CONN_TX_B1_CTL, 0, 6, dec_mux_text);
0290 static const struct soc_enum dec2_mux_enum = SOC_ENUM_SINGLE(
0291                 LPASS_CDC_CONN_TX_B1_CTL, 3, 6, dec_mux_text);
0292 
0293 /* CIC */
0294 static const struct soc_enum cic1_mux_enum = SOC_ENUM_SINGLE(
0295                 LPASS_CDC_TX1_MUX_CTL, 0, 2, cic_mux_text);
0296 static const struct soc_enum cic2_mux_enum = SOC_ENUM_SINGLE(
0297                 LPASS_CDC_TX2_MUX_CTL, 0, 2, cic_mux_text);
0298 
0299 /* RDAC2 MUX */
0300 static const struct snd_kcontrol_new dec1_mux = SOC_DAPM_ENUM(
0301                 "DEC1 MUX Mux", dec1_mux_enum);
0302 static const struct snd_kcontrol_new dec2_mux = SOC_DAPM_ENUM(
0303                 "DEC2 MUX Mux", dec2_mux_enum);
0304 static const struct snd_kcontrol_new cic1_mux = SOC_DAPM_ENUM(
0305                 "CIC1 MUX Mux", cic1_mux_enum);
0306 static const struct snd_kcontrol_new cic2_mux = SOC_DAPM_ENUM(
0307                 "CIC2 MUX Mux", cic2_mux_enum);
0308 static const struct snd_kcontrol_new rx_mix1_inp1_mux = SOC_DAPM_ENUM(
0309                 "RX1 MIX1 INP1 Mux", rx_mix1_inp_enum[0]);
0310 static const struct snd_kcontrol_new rx_mix1_inp2_mux = SOC_DAPM_ENUM(
0311                 "RX1 MIX1 INP2 Mux", rx_mix1_inp_enum[1]);
0312 static const struct snd_kcontrol_new rx_mix1_inp3_mux = SOC_DAPM_ENUM(
0313                 "RX1 MIX1 INP3 Mux", rx_mix1_inp_enum[2]);
0314 static const struct snd_kcontrol_new rx2_mix1_inp1_mux = SOC_DAPM_ENUM(
0315                 "RX2 MIX1 INP1 Mux", rx2_mix1_inp_enum[0]);
0316 static const struct snd_kcontrol_new rx2_mix1_inp2_mux = SOC_DAPM_ENUM(
0317                 "RX2 MIX1 INP2 Mux", rx2_mix1_inp_enum[1]);
0318 static const struct snd_kcontrol_new rx2_mix1_inp3_mux = SOC_DAPM_ENUM(
0319                 "RX2 MIX1 INP3 Mux", rx2_mix1_inp_enum[2]);
0320 static const struct snd_kcontrol_new rx3_mix1_inp1_mux = SOC_DAPM_ENUM(
0321                 "RX3 MIX1 INP1 Mux", rx3_mix1_inp_enum[0]);
0322 static const struct snd_kcontrol_new rx3_mix1_inp2_mux = SOC_DAPM_ENUM(
0323                 "RX3 MIX1 INP2 Mux", rx3_mix1_inp_enum[1]);
0324 static const struct snd_kcontrol_new rx3_mix1_inp3_mux = SOC_DAPM_ENUM(
0325                 "RX3 MIX1 INP3 Mux", rx3_mix1_inp_enum[2]);
0326 static const struct snd_kcontrol_new rx1_mix2_inp1_mux = SOC_DAPM_ENUM(
0327                 "RX1 MIX2 INP1 Mux", rx_mix2_inp1_chain_enum);
0328 static const struct snd_kcontrol_new rx2_mix2_inp1_mux = SOC_DAPM_ENUM(
0329                 "RX2 MIX2 INP1 Mux", rx2_mix2_inp1_chain_enum);
0330 
0331 /* Digital Gain control -84 dB to +40 dB in 1 dB steps */
0332 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
0333 
0334 /* Cutoff Freq for High Pass Filter at -3dB */
0335 static const char * const hpf_cutoff_text[] = {
0336     "4Hz", "75Hz", "150Hz",
0337 };
0338 
0339 static SOC_ENUM_SINGLE_DECL(tx1_hpf_cutoff_enum, LPASS_CDC_TX1_MUX_CTL, 4,
0340                 hpf_cutoff_text);
0341 static SOC_ENUM_SINGLE_DECL(tx2_hpf_cutoff_enum, LPASS_CDC_TX2_MUX_CTL, 4,
0342                 hpf_cutoff_text);
0343 
0344 /* cut off for dc blocker inside rx chain */
0345 static const char * const dc_blocker_cutoff_text[] = {
0346     "4Hz", "75Hz", "150Hz",
0347 };
0348 
0349 static SOC_ENUM_SINGLE_DECL(rx1_dcb_cutoff_enum, LPASS_CDC_RX1_B4_CTL, 0,
0350                 dc_blocker_cutoff_text);
0351 static SOC_ENUM_SINGLE_DECL(rx2_dcb_cutoff_enum, LPASS_CDC_RX2_B4_CTL, 0,
0352                 dc_blocker_cutoff_text);
0353 static SOC_ENUM_SINGLE_DECL(rx3_dcb_cutoff_enum, LPASS_CDC_RX3_B4_CTL, 0,
0354                 dc_blocker_cutoff_text);
0355 
0356 static int msm8x16_wcd_codec_set_iir_gain(struct snd_soc_dapm_widget *w,
0357         struct snd_kcontrol *kcontrol, int event)
0358 {
0359     struct snd_soc_component *component =
0360             snd_soc_dapm_to_component(w->dapm);
0361     int value = 0, reg = 0;
0362 
0363     switch (event) {
0364     case SND_SOC_DAPM_POST_PMU:
0365         if (w->shift == 0)
0366             reg = LPASS_CDC_IIR1_GAIN_B1_CTL;
0367         else if (w->shift == 1)
0368             reg = LPASS_CDC_IIR2_GAIN_B1_CTL;
0369         value = snd_soc_component_read(component, reg);
0370         snd_soc_component_write(component, reg, value);
0371         break;
0372     default:
0373         break;
0374     }
0375     return 0;
0376 }
0377 
0378 static uint32_t get_iir_band_coeff(struct snd_soc_component *component,
0379                    int iir_idx, int band_idx,
0380                    int coeff_idx)
0381 {
0382     uint32_t value = 0;
0383 
0384     /* Address does not automatically update if reading */
0385     snd_soc_component_write(component,
0386         (LPASS_CDC_IIR1_COEF_B1_CTL + 64 * iir_idx),
0387         ((band_idx * BAND_MAX + coeff_idx)
0388         * sizeof(uint32_t)) & 0x7F);
0389 
0390     value |= snd_soc_component_read(component,
0391         (LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx));
0392 
0393     snd_soc_component_write(component,
0394         (LPASS_CDC_IIR1_COEF_B1_CTL + 64 * iir_idx),
0395         ((band_idx * BAND_MAX + coeff_idx)
0396         * sizeof(uint32_t) + 1) & 0x7F);
0397 
0398     value |= (snd_soc_component_read(component,
0399         (LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx)) << 8);
0400 
0401     snd_soc_component_write(component,
0402         (LPASS_CDC_IIR1_COEF_B1_CTL + 64 * iir_idx),
0403         ((band_idx * BAND_MAX + coeff_idx)
0404         * sizeof(uint32_t) + 2) & 0x7F);
0405 
0406     value |= (snd_soc_component_read(component,
0407         (LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx)) << 16);
0408 
0409     snd_soc_component_write(component,
0410         (LPASS_CDC_IIR1_COEF_B1_CTL + 64 * iir_idx),
0411         ((band_idx * BAND_MAX + coeff_idx)
0412         * sizeof(uint32_t) + 3) & 0x7F);
0413 
0414     /* Mask bits top 2 bits since they are reserved */
0415     value |= ((snd_soc_component_read(component,
0416          (LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx)) & 0x3f) << 24);
0417     return value;
0418 
0419 }
0420 
0421 static int msm8x16_wcd_get_iir_band_audio_mixer(
0422                     struct snd_kcontrol *kcontrol,
0423                     struct snd_ctl_elem_value *ucontrol)
0424 {
0425 
0426     struct snd_soc_component *component =
0427             snd_soc_kcontrol_component(kcontrol);
0428     struct wcd_iir_filter_ctl *ctl =
0429             (struct wcd_iir_filter_ctl *)kcontrol->private_value;
0430     struct soc_bytes_ext *params = &ctl->bytes_ext;
0431     int iir_idx = ctl->iir_idx;
0432     int band_idx = ctl->band_idx;
0433     u32 coeff[BAND_MAX];
0434 
0435     coeff[0] = get_iir_band_coeff(component, iir_idx, band_idx, 0);
0436     coeff[1] = get_iir_band_coeff(component, iir_idx, band_idx, 1);
0437     coeff[2] = get_iir_band_coeff(component, iir_idx, band_idx, 2);
0438     coeff[3] = get_iir_band_coeff(component, iir_idx, band_idx, 3);
0439     coeff[4] = get_iir_band_coeff(component, iir_idx, band_idx, 4);
0440 
0441     memcpy(ucontrol->value.bytes.data, &coeff[0], params->max);
0442 
0443     return 0;
0444 }
0445 
0446 static void set_iir_band_coeff(struct snd_soc_component *component,
0447                 int iir_idx, int band_idx,
0448                 uint32_t value)
0449 {
0450     snd_soc_component_write(component,
0451         (LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx),
0452         (value & 0xFF));
0453 
0454     snd_soc_component_write(component,
0455         (LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx),
0456         (value >> 8) & 0xFF);
0457 
0458     snd_soc_component_write(component,
0459         (LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx),
0460         (value >> 16) & 0xFF);
0461 
0462     /* Mask top 2 bits, 7-8 are reserved */
0463     snd_soc_component_write(component,
0464         (LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx),
0465         (value >> 24) & 0x3F);
0466 }
0467 
0468 static int msm8x16_wcd_put_iir_band_audio_mixer(
0469                     struct snd_kcontrol *kcontrol,
0470                     struct snd_ctl_elem_value *ucontrol)
0471 {
0472     struct snd_soc_component *component =
0473             snd_soc_kcontrol_component(kcontrol);
0474     struct wcd_iir_filter_ctl *ctl =
0475             (struct wcd_iir_filter_ctl *)kcontrol->private_value;
0476     struct soc_bytes_ext *params = &ctl->bytes_ext;
0477     int iir_idx = ctl->iir_idx;
0478     int band_idx = ctl->band_idx;
0479     u32 coeff[BAND_MAX];
0480 
0481     memcpy(&coeff[0], ucontrol->value.bytes.data, params->max);
0482 
0483     /* Mask top bit it is reserved */
0484     /* Updates addr automatically for each B2 write */
0485     snd_soc_component_write(component,
0486         (LPASS_CDC_IIR1_COEF_B1_CTL + 64 * iir_idx),
0487         (band_idx * BAND_MAX * sizeof(uint32_t)) & 0x7F);
0488 
0489     set_iir_band_coeff(component, iir_idx, band_idx, coeff[0]);
0490     set_iir_band_coeff(component, iir_idx, band_idx, coeff[1]);
0491     set_iir_band_coeff(component, iir_idx, band_idx, coeff[2]);
0492     set_iir_band_coeff(component, iir_idx, band_idx, coeff[3]);
0493     set_iir_band_coeff(component, iir_idx, band_idx, coeff[4]);
0494 
0495     return 0;
0496 }
0497 
0498 static int wcd_iir_filter_info(struct snd_kcontrol *kcontrol,
0499                 struct snd_ctl_elem_info *ucontrol)
0500 {
0501     struct wcd_iir_filter_ctl *ctl =
0502         (struct wcd_iir_filter_ctl *)kcontrol->private_value;
0503     struct soc_bytes_ext *params = &ctl->bytes_ext;
0504 
0505     ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES;
0506     ucontrol->count = params->max;
0507 
0508     return 0;
0509 }
0510 
0511 static const struct snd_kcontrol_new msm8916_wcd_digital_snd_controls[] = {
0512     SOC_SINGLE_S8_TLV("RX1 Digital Volume", LPASS_CDC_RX1_VOL_CTL_B2_CTL,
0513             -84, 40, digital_gain),
0514     SOC_SINGLE_S8_TLV("RX2 Digital Volume", LPASS_CDC_RX2_VOL_CTL_B2_CTL,
0515             -84, 40, digital_gain),
0516     SOC_SINGLE_S8_TLV("RX3 Digital Volume", LPASS_CDC_RX3_VOL_CTL_B2_CTL,
0517             -84, 40, digital_gain),
0518     SOC_SINGLE_S8_TLV("TX1 Digital Volume", LPASS_CDC_TX1_VOL_CTL_GAIN,
0519             -84, 40, digital_gain),
0520     SOC_SINGLE_S8_TLV("TX2 Digital Volume", LPASS_CDC_TX2_VOL_CTL_GAIN,
0521             -84, 40, digital_gain),
0522     SOC_ENUM("TX1 HPF Cutoff", tx1_hpf_cutoff_enum),
0523     SOC_ENUM("TX2 HPF Cutoff", tx2_hpf_cutoff_enum),
0524     SOC_SINGLE("TX1 HPF Switch", LPASS_CDC_TX1_MUX_CTL, 3, 1, 0),
0525     SOC_SINGLE("TX2 HPF Switch", LPASS_CDC_TX2_MUX_CTL, 3, 1, 0),
0526     SOC_ENUM("RX1 DCB Cutoff", rx1_dcb_cutoff_enum),
0527     SOC_ENUM("RX2 DCB Cutoff", rx2_dcb_cutoff_enum),
0528     SOC_ENUM("RX3 DCB Cutoff", rx3_dcb_cutoff_enum),
0529     SOC_SINGLE("RX1 DCB Switch", LPASS_CDC_RX1_B5_CTL, 2, 1, 0),
0530     SOC_SINGLE("RX2 DCB Switch", LPASS_CDC_RX2_B5_CTL, 2, 1, 0),
0531     SOC_SINGLE("RX3 DCB Switch", LPASS_CDC_RX3_B5_CTL, 2, 1, 0),
0532     SOC_SINGLE("RX1 Mute Switch", LPASS_CDC_RX1_B6_CTL, 0, 1, 0),
0533     SOC_SINGLE("RX2 Mute Switch", LPASS_CDC_RX2_B6_CTL, 0, 1, 0),
0534     SOC_SINGLE("RX3 Mute Switch", LPASS_CDC_RX3_B6_CTL, 0, 1, 0),
0535 
0536     SOC_SINGLE("IIR1 Band1 Switch", LPASS_CDC_IIR1_CTL, 0, 1, 0),
0537     SOC_SINGLE("IIR1 Band2 Switch", LPASS_CDC_IIR1_CTL, 1, 1, 0),
0538     SOC_SINGLE("IIR1 Band3 Switch", LPASS_CDC_IIR1_CTL, 2, 1, 0),
0539     SOC_SINGLE("IIR1 Band4 Switch", LPASS_CDC_IIR1_CTL, 3, 1, 0),
0540     SOC_SINGLE("IIR1 Band5 Switch", LPASS_CDC_IIR1_CTL, 4, 1, 0),
0541     SOC_SINGLE("IIR2 Band1 Switch", LPASS_CDC_IIR2_CTL, 0, 1, 0),
0542     SOC_SINGLE("IIR2 Band2 Switch", LPASS_CDC_IIR2_CTL, 1, 1, 0),
0543     SOC_SINGLE("IIR2 Band3 Switch", LPASS_CDC_IIR2_CTL, 2, 1, 0),
0544     SOC_SINGLE("IIR2 Band4 Switch", LPASS_CDC_IIR2_CTL, 3, 1, 0),
0545     SOC_SINGLE("IIR2 Band5 Switch", LPASS_CDC_IIR2_CTL, 4, 1, 0),
0546     WCD_IIR_FILTER_CTL("IIR1 Band1", IIR1, BAND1),
0547     WCD_IIR_FILTER_CTL("IIR1 Band2", IIR1, BAND2),
0548     WCD_IIR_FILTER_CTL("IIR1 Band3", IIR1, BAND3),
0549     WCD_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4),
0550     WCD_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5),
0551     WCD_IIR_FILTER_CTL("IIR2 Band1", IIR2, BAND1),
0552     WCD_IIR_FILTER_CTL("IIR2 Band2", IIR2, BAND2),
0553     WCD_IIR_FILTER_CTL("IIR2 Band3", IIR2, BAND3),
0554     WCD_IIR_FILTER_CTL("IIR2 Band4", IIR2, BAND4),
0555     WCD_IIR_FILTER_CTL("IIR2 Band5", IIR2, BAND5),
0556     SOC_SINGLE_S8_TLV("IIR1 INP1 Volume", LPASS_CDC_IIR1_GAIN_B1_CTL,
0557             -84, 40, digital_gain),
0558     SOC_SINGLE_S8_TLV("IIR1 INP2 Volume", LPASS_CDC_IIR1_GAIN_B2_CTL,
0559             -84, 40, digital_gain),
0560     SOC_SINGLE_S8_TLV("IIR1 INP3 Volume", LPASS_CDC_IIR1_GAIN_B3_CTL,
0561             -84, 40, digital_gain),
0562     SOC_SINGLE_S8_TLV("IIR1 INP4 Volume", LPASS_CDC_IIR1_GAIN_B4_CTL,
0563             -84, 40, digital_gain),
0564     SOC_SINGLE_S8_TLV("IIR2 INP1 Volume", LPASS_CDC_IIR2_GAIN_B1_CTL,
0565             -84, 40, digital_gain),
0566     SOC_SINGLE_S8_TLV("IIR2 INP2 Volume", LPASS_CDC_IIR2_GAIN_B2_CTL,
0567             -84, 40, digital_gain),
0568     SOC_SINGLE_S8_TLV("IIR2 INP3 Volume", LPASS_CDC_IIR2_GAIN_B3_CTL,
0569             -84, 40, digital_gain),
0570     SOC_SINGLE_S8_TLV("IIR2 INP4 Volume", LPASS_CDC_IIR2_GAIN_B4_CTL,
0571             -84, 40, digital_gain),
0572 
0573 };
0574 
0575 static int msm8916_wcd_digital_enable_interpolator(
0576                         struct snd_soc_dapm_widget *w,
0577                         struct snd_kcontrol *kcontrol,
0578                         int event)
0579 {
0580     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0581 
0582     switch (event) {
0583     case SND_SOC_DAPM_POST_PMU:
0584         /* apply the digital gain after the interpolator is enabled */
0585         usleep_range(10000, 10100);
0586         snd_soc_component_write(component, rx_gain_reg[w->shift],
0587                   snd_soc_component_read(component, rx_gain_reg[w->shift]));
0588         break;
0589     case SND_SOC_DAPM_POST_PMD:
0590         snd_soc_component_update_bits(component, LPASS_CDC_CLK_RX_RESET_CTL,
0591                           1 << w->shift, 1 << w->shift);
0592         snd_soc_component_update_bits(component, LPASS_CDC_CLK_RX_RESET_CTL,
0593                           1 << w->shift, 0x0);
0594         break;
0595     }
0596     return 0;
0597 }
0598 
0599 static int msm8916_wcd_digital_enable_dec(struct snd_soc_dapm_widget *w,
0600                       struct snd_kcontrol *kcontrol,
0601                       int event)
0602 {
0603     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0604     unsigned int decimator = w->shift + 1;
0605     u16 dec_reset_reg, tx_vol_ctl_reg, tx_mux_ctl_reg;
0606     u8 dec_hpf_cut_of_freq;
0607 
0608     dec_reset_reg = LPASS_CDC_CLK_TX_RESET_B1_CTL;
0609     tx_vol_ctl_reg = LPASS_CDC_TX1_VOL_CTL_CFG + 32 * (decimator - 1);
0610     tx_mux_ctl_reg = LPASS_CDC_TX1_MUX_CTL + 32 * (decimator - 1);
0611 
0612     switch (event) {
0613     case SND_SOC_DAPM_PRE_PMU:
0614         /* Enable TX digital mute */
0615         snd_soc_component_update_bits(component, tx_vol_ctl_reg,
0616                     TX_VOL_CTL_CFG_MUTE_EN_MASK,
0617                     TX_VOL_CTL_CFG_MUTE_EN_ENABLE);
0618         dec_hpf_cut_of_freq = snd_soc_component_read(component, tx_mux_ctl_reg) &
0619                     TX_MUX_CTL_CUT_OFF_FREQ_MASK;
0620         dec_hpf_cut_of_freq >>= TX_MUX_CTL_CUT_OFF_FREQ_SHIFT;
0621         if (dec_hpf_cut_of_freq != TX_MUX_CTL_CF_NEG_3DB_150HZ) {
0622             /* set cut of freq to CF_MIN_3DB_150HZ (0x1) */
0623             snd_soc_component_update_bits(component, tx_mux_ctl_reg,
0624                         TX_MUX_CTL_CUT_OFF_FREQ_MASK,
0625                         TX_MUX_CTL_CF_NEG_3DB_150HZ);
0626         }
0627         break;
0628     case SND_SOC_DAPM_POST_PMU:
0629         /* enable HPF */
0630         snd_soc_component_update_bits(component, tx_mux_ctl_reg,
0631                     TX_MUX_CTL_HPF_BP_SEL_MASK,
0632                     TX_MUX_CTL_HPF_BP_SEL_NO_BYPASS);
0633         /* apply the digital gain after the decimator is enabled */
0634         snd_soc_component_write(component, tx_gain_reg[w->shift],
0635                   snd_soc_component_read(component, tx_gain_reg[w->shift]));
0636         snd_soc_component_update_bits(component, tx_vol_ctl_reg,
0637                     TX_VOL_CTL_CFG_MUTE_EN_MASK, 0);
0638         break;
0639     case SND_SOC_DAPM_PRE_PMD:
0640         snd_soc_component_update_bits(component, tx_vol_ctl_reg,
0641                     TX_VOL_CTL_CFG_MUTE_EN_MASK,
0642                     TX_VOL_CTL_CFG_MUTE_EN_ENABLE);
0643         snd_soc_component_update_bits(component, tx_mux_ctl_reg,
0644                     TX_MUX_CTL_HPF_BP_SEL_MASK,
0645                     TX_MUX_CTL_HPF_BP_SEL_BYPASS);
0646         break;
0647     case SND_SOC_DAPM_POST_PMD:
0648         snd_soc_component_update_bits(component, dec_reset_reg, 1 << w->shift,
0649                     1 << w->shift);
0650         snd_soc_component_update_bits(component, dec_reset_reg, 1 << w->shift, 0x0);
0651         snd_soc_component_update_bits(component, tx_mux_ctl_reg,
0652                     TX_MUX_CTL_HPF_BP_SEL_MASK,
0653                     TX_MUX_CTL_HPF_BP_SEL_BYPASS);
0654         snd_soc_component_update_bits(component, tx_vol_ctl_reg,
0655                     TX_VOL_CTL_CFG_MUTE_EN_MASK, 0);
0656         break;
0657     }
0658 
0659     return 0;
0660 }
0661 
0662 static int msm8916_wcd_digital_enable_dmic(struct snd_soc_dapm_widget *w,
0663                        struct snd_kcontrol *kcontrol,
0664                        int event)
0665 {
0666     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0667     unsigned int dmic;
0668     int ret;
0669     /* get dmic number out of widget name */
0670     char *dmic_num = strpbrk(w->name, "12");
0671 
0672     if (dmic_num == NULL) {
0673         dev_err(component->dev, "Invalid DMIC\n");
0674         return -EINVAL;
0675     }
0676     ret = kstrtouint(dmic_num, 10, &dmic);
0677     if (ret < 0 || dmic > 2) {
0678         dev_err(component->dev, "Invalid DMIC line on the component\n");
0679         return -EINVAL;
0680     }
0681 
0682     switch (event) {
0683     case SND_SOC_DAPM_PRE_PMU:
0684         snd_soc_component_update_bits(component, LPASS_CDC_CLK_DMIC_B1_CTL,
0685                     DMIC_B1_CTL_DMIC0_CLK_SEL_MASK,
0686                     DMIC_B1_CTL_DMIC0_CLK_SEL_DIV3);
0687         switch (dmic) {
0688         case 1:
0689             snd_soc_component_update_bits(component, LPASS_CDC_TX1_DMIC_CTL,
0690                         TXN_DMIC_CTL_CLK_SEL_MASK,
0691                         TXN_DMIC_CTL_CLK_SEL_DIV3);
0692             break;
0693         case 2:
0694             snd_soc_component_update_bits(component, LPASS_CDC_TX2_DMIC_CTL,
0695                         TXN_DMIC_CTL_CLK_SEL_MASK,
0696                         TXN_DMIC_CTL_CLK_SEL_DIV3);
0697             break;
0698         }
0699         break;
0700     }
0701 
0702     return 0;
0703 }
0704 
0705 static const char * const iir_inp1_text[] = {
0706     "ZERO", "DEC1", "DEC2", "RX1", "RX2", "RX3"
0707 };
0708 
0709 static const struct soc_enum iir1_inp1_mux_enum =
0710     SOC_ENUM_SINGLE(LPASS_CDC_CONN_EQ1_B1_CTL,
0711         0, 6, iir_inp1_text);
0712 
0713 static const struct soc_enum iir2_inp1_mux_enum =
0714     SOC_ENUM_SINGLE(LPASS_CDC_CONN_EQ2_B1_CTL,
0715         0, 6, iir_inp1_text);
0716 
0717 static const struct snd_kcontrol_new iir1_inp1_mux =
0718     SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum);
0719 
0720 static const struct snd_kcontrol_new iir2_inp1_mux =
0721     SOC_DAPM_ENUM("IIR2 INP1 Mux", iir2_inp1_mux_enum);
0722 
0723 static const struct snd_soc_dapm_widget msm8916_wcd_digital_dapm_widgets[] = {
0724     /*RX stuff */
0725     SND_SOC_DAPM_AIF_IN("I2S RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
0726     SND_SOC_DAPM_AIF_IN("I2S RX2", NULL, 0, SND_SOC_NOPM, 0, 0),
0727     SND_SOC_DAPM_AIF_IN("I2S RX3", NULL, 0, SND_SOC_NOPM, 0, 0),
0728 
0729     SND_SOC_DAPM_OUTPUT("PDM_RX1"),
0730     SND_SOC_DAPM_OUTPUT("PDM_RX2"),
0731     SND_SOC_DAPM_OUTPUT("PDM_RX3"),
0732 
0733     SND_SOC_DAPM_INPUT("LPASS_PDM_TX"),
0734 
0735     SND_SOC_DAPM_MIXER("RX1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
0736     SND_SOC_DAPM_MIXER("RX2 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
0737     SND_SOC_DAPM_MIXER("RX3 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
0738 
0739     /* Interpolator */
0740     SND_SOC_DAPM_MIXER_E("RX1 INT", LPASS_CDC_CLK_RX_B1_CTL, 0, 0, NULL,
0741                  0, msm8916_wcd_digital_enable_interpolator,
0742                  SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
0743     SND_SOC_DAPM_MIXER_E("RX2 INT", LPASS_CDC_CLK_RX_B1_CTL, 1, 0, NULL,
0744                  0, msm8916_wcd_digital_enable_interpolator,
0745                  SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
0746     SND_SOC_DAPM_MIXER_E("RX3 INT", LPASS_CDC_CLK_RX_B1_CTL, 2, 0, NULL,
0747                  0, msm8916_wcd_digital_enable_interpolator,
0748                  SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
0749     SND_SOC_DAPM_MUX("RX1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
0750              &rx_mix1_inp1_mux),
0751     SND_SOC_DAPM_MUX("RX1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
0752              &rx_mix1_inp2_mux),
0753     SND_SOC_DAPM_MUX("RX1 MIX1 INP3", SND_SOC_NOPM, 0, 0,
0754              &rx_mix1_inp3_mux),
0755     SND_SOC_DAPM_MUX("RX2 MIX1 INP1", SND_SOC_NOPM, 0, 0,
0756              &rx2_mix1_inp1_mux),
0757     SND_SOC_DAPM_MUX("RX2 MIX1 INP2", SND_SOC_NOPM, 0, 0,
0758              &rx2_mix1_inp2_mux),
0759     SND_SOC_DAPM_MUX("RX2 MIX1 INP3", SND_SOC_NOPM, 0, 0,
0760              &rx2_mix1_inp3_mux),
0761     SND_SOC_DAPM_MUX("RX3 MIX1 INP1", SND_SOC_NOPM, 0, 0,
0762              &rx3_mix1_inp1_mux),
0763     SND_SOC_DAPM_MUX("RX3 MIX1 INP2", SND_SOC_NOPM, 0, 0,
0764              &rx3_mix1_inp2_mux),
0765     SND_SOC_DAPM_MUX("RX3 MIX1 INP3", SND_SOC_NOPM, 0, 0,
0766              &rx3_mix1_inp3_mux),
0767     SND_SOC_DAPM_MUX("RX1 MIX2 INP1", SND_SOC_NOPM, 0, 0,
0768              &rx1_mix2_inp1_mux),
0769     SND_SOC_DAPM_MUX("RX2 MIX2 INP1", SND_SOC_NOPM, 0, 0,
0770              &rx2_mix2_inp1_mux),
0771 
0772     SND_SOC_DAPM_MUX("CIC1 MUX", SND_SOC_NOPM, 0, 0, &cic1_mux),
0773     SND_SOC_DAPM_MUX("CIC2 MUX", SND_SOC_NOPM, 0, 0, &cic2_mux),
0774     /* TX */
0775     SND_SOC_DAPM_MIXER("ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
0776     SND_SOC_DAPM_MIXER("ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
0777     SND_SOC_DAPM_MIXER("ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
0778 
0779     SND_SOC_DAPM_MUX_E("DEC1 MUX", LPASS_CDC_CLK_TX_CLK_EN_B1_CTL, 0, 0,
0780                &dec1_mux, msm8916_wcd_digital_enable_dec,
0781                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
0782                SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
0783     SND_SOC_DAPM_MUX_E("DEC2 MUX", LPASS_CDC_CLK_TX_CLK_EN_B1_CTL, 1, 0,
0784                &dec2_mux, msm8916_wcd_digital_enable_dec,
0785                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
0786                SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
0787     SND_SOC_DAPM_AIF_OUT("I2S TX1", NULL, 0, SND_SOC_NOPM, 0, 0),
0788     SND_SOC_DAPM_AIF_OUT("I2S TX2", NULL, 0, SND_SOC_NOPM, 0, 0),
0789     SND_SOC_DAPM_AIF_OUT("I2S TX3", NULL, 0, SND_SOC_NOPM, 0, 0),
0790 
0791     /* Digital Mic Inputs */
0792     SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
0793                msm8916_wcd_digital_enable_dmic,
0794                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0795     SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
0796                msm8916_wcd_digital_enable_dmic,
0797                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0798     SND_SOC_DAPM_SUPPLY("DMIC_CLK", LPASS_CDC_CLK_DMIC_B1_CTL, 0, 0,
0799                 NULL, 0),
0800     SND_SOC_DAPM_SUPPLY("RX_I2S_CLK", LPASS_CDC_CLK_RX_I2S_CTL,
0801                 4, 0, NULL, 0),
0802     SND_SOC_DAPM_SUPPLY("TX_I2S_CLK", LPASS_CDC_CLK_TX_I2S_CTL, 4, 0,
0803                 NULL, 0),
0804 
0805     SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0, NULL, 0),
0806     SND_SOC_DAPM_SUPPLY("PDM_CLK", LPASS_CDC_CLK_PDM_CTL, 0, 0, NULL, 0),
0807     /* Connectivity Clock */
0808     SND_SOC_DAPM_SUPPLY_S("CDC_CONN", -2, LPASS_CDC_CLK_OTHR_CTL, 2, 0,
0809                   NULL, 0),
0810     SND_SOC_DAPM_MIC("Digital Mic1", NULL),
0811     SND_SOC_DAPM_MIC("Digital Mic2", NULL),
0812 
0813     /* Sidetone */
0814     SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux),
0815     SND_SOC_DAPM_PGA_E("IIR1", LPASS_CDC_CLK_SD_CTL, 0, 0, NULL, 0,
0816         msm8x16_wcd_codec_set_iir_gain, SND_SOC_DAPM_POST_PMU),
0817 
0818     SND_SOC_DAPM_MUX("IIR2 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir2_inp1_mux),
0819     SND_SOC_DAPM_PGA_E("IIR2", LPASS_CDC_CLK_SD_CTL, 1, 0, NULL, 0,
0820         msm8x16_wcd_codec_set_iir_gain, SND_SOC_DAPM_POST_PMU),
0821 
0822 };
0823 
0824 static int msm8916_wcd_digital_get_clks(struct platform_device *pdev,
0825                     struct msm8916_wcd_digital_priv *priv)
0826 {
0827     struct device *dev = &pdev->dev;
0828 
0829     priv->ahbclk = devm_clk_get(dev, "ahbix-clk");
0830     if (IS_ERR(priv->ahbclk)) {
0831         dev_err(dev, "failed to get ahbix clk\n");
0832         return PTR_ERR(priv->ahbclk);
0833     }
0834 
0835     priv->mclk = devm_clk_get(dev, "mclk");
0836     if (IS_ERR(priv->mclk)) {
0837         dev_err(dev, "failed to get mclk\n");
0838         return PTR_ERR(priv->mclk);
0839     }
0840 
0841     return 0;
0842 }
0843 
0844 static int msm8916_wcd_digital_component_probe(struct snd_soc_component *component)
0845 {
0846     struct msm8916_wcd_digital_priv *priv = dev_get_drvdata(component->dev);
0847 
0848     snd_soc_component_set_drvdata(component, priv);
0849 
0850     return 0;
0851 }
0852 
0853 static int msm8916_wcd_digital_component_set_sysclk(struct snd_soc_component *component,
0854                         int clk_id, int source,
0855                         unsigned int freq, int dir)
0856 {
0857     struct msm8916_wcd_digital_priv *p = dev_get_drvdata(component->dev);
0858 
0859     return clk_set_rate(p->mclk, freq);
0860 }
0861 
0862 static int msm8916_wcd_digital_hw_params(struct snd_pcm_substream *substream,
0863                      struct snd_pcm_hw_params *params,
0864                      struct snd_soc_dai *dai)
0865 {
0866     u8 tx_fs_rate;
0867     u8 rx_fs_rate;
0868 
0869     switch (params_rate(params)) {
0870     case 8000:
0871         tx_fs_rate = TX_I2S_CTL_TX_I2S_FS_RATE_F_8_KHZ;
0872         rx_fs_rate = RX_I2S_CTL_RX_I2S_FS_RATE_F_8_KHZ;
0873         break;
0874     case 16000:
0875         tx_fs_rate = TX_I2S_CTL_TX_I2S_FS_RATE_F_16_KHZ;
0876         rx_fs_rate = RX_I2S_CTL_RX_I2S_FS_RATE_F_16_KHZ;
0877         break;
0878     case 32000:
0879         tx_fs_rate = TX_I2S_CTL_TX_I2S_FS_RATE_F_32_KHZ;
0880         rx_fs_rate = RX_I2S_CTL_RX_I2S_FS_RATE_F_32_KHZ;
0881         break;
0882     case 48000:
0883         tx_fs_rate = TX_I2S_CTL_TX_I2S_FS_RATE_F_48_KHZ;
0884         rx_fs_rate = RX_I2S_CTL_RX_I2S_FS_RATE_F_48_KHZ;
0885         break;
0886     default:
0887         dev_err(dai->component->dev, "Invalid sampling rate %d\n",
0888             params_rate(params));
0889         return -EINVAL;
0890     }
0891 
0892     switch (substream->stream) {
0893     case SNDRV_PCM_STREAM_CAPTURE:
0894         snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_TX_I2S_CTL,
0895                     TX_I2S_CTL_TX_I2S_FS_RATE_MASK, tx_fs_rate);
0896         break;
0897     case SNDRV_PCM_STREAM_PLAYBACK:
0898         snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_RX_I2S_CTL,
0899                     RX_I2S_CTL_RX_I2S_FS_RATE_MASK, rx_fs_rate);
0900         break;
0901     default:
0902         return -EINVAL;
0903     }
0904 
0905     switch (params_format(params)) {
0906     case SNDRV_PCM_FORMAT_S16_LE:
0907         snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_TX_I2S_CTL,
0908                     TX_I2S_CTL_TX_I2S_MODE_MASK,
0909                     TX_I2S_CTL_TX_I2S_MODE_16);
0910         snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_RX_I2S_CTL,
0911                     RX_I2S_CTL_RX_I2S_MODE_MASK,
0912                     RX_I2S_CTL_RX_I2S_MODE_16);
0913         break;
0914 
0915     case SNDRV_PCM_FORMAT_S32_LE:
0916         snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_TX_I2S_CTL,
0917                     TX_I2S_CTL_TX_I2S_MODE_MASK,
0918                     TX_I2S_CTL_TX_I2S_MODE_32);
0919         snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_RX_I2S_CTL,
0920                     RX_I2S_CTL_RX_I2S_MODE_MASK,
0921                     RX_I2S_CTL_RX_I2S_MODE_32);
0922         break;
0923     default:
0924         dev_err(dai->dev, "%s: wrong format selected\n", __func__);
0925         return -EINVAL;
0926     }
0927 
0928     return 0;
0929 }
0930 
0931 static const struct snd_soc_dapm_route msm8916_wcd_digital_audio_map[] = {
0932 
0933     {"I2S RX1",  NULL, "AIF1 Playback"},
0934     {"I2S RX2",  NULL, "AIF1 Playback"},
0935     {"I2S RX3",  NULL, "AIF1 Playback"},
0936 
0937     {"AIF1 Capture", NULL, "I2S TX1"},
0938     {"AIF1 Capture", NULL, "I2S TX2"},
0939     {"AIF1 Capture", NULL, "I2S TX3"},
0940 
0941     {"CIC1 MUX", "DMIC", "DEC1 MUX"},
0942     {"CIC1 MUX", "AMIC", "DEC1 MUX"},
0943     {"CIC2 MUX", "DMIC", "DEC2 MUX"},
0944     {"CIC2 MUX", "AMIC", "DEC2 MUX"},
0945 
0946     /* Decimator Inputs */
0947     {"DEC1 MUX", "DMIC1", "DMIC1"},
0948     {"DEC1 MUX", "DMIC2", "DMIC2"},
0949     {"DEC1 MUX", "ADC1", "ADC1"},
0950     {"DEC1 MUX", "ADC2", "ADC2"},
0951     {"DEC1 MUX", "ADC3", "ADC3"},
0952     {"DEC1 MUX", NULL, "CDC_CONN"},
0953 
0954     {"DEC2 MUX", "DMIC1", "DMIC1"},
0955     {"DEC2 MUX", "DMIC2", "DMIC2"},
0956     {"DEC2 MUX", "ADC1", "ADC1"},
0957     {"DEC2 MUX", "ADC2", "ADC2"},
0958     {"DEC2 MUX", "ADC3", "ADC3"},
0959     {"DEC2 MUX", NULL, "CDC_CONN"},
0960 
0961     {"DMIC1", NULL, "DMIC_CLK"},
0962     {"DMIC2", NULL, "DMIC_CLK"},
0963 
0964     {"I2S TX1", NULL, "CIC1 MUX"},
0965     {"I2S TX2", NULL, "CIC2 MUX"},
0966 
0967     {"I2S TX1", NULL, "TX_I2S_CLK"},
0968     {"I2S TX2", NULL, "TX_I2S_CLK"},
0969 
0970     {"TX_I2S_CLK", NULL, "MCLK"},
0971     {"TX_I2S_CLK", NULL, "PDM_CLK"},
0972 
0973     {"ADC1", NULL, "LPASS_PDM_TX"},
0974     {"ADC2", NULL, "LPASS_PDM_TX"},
0975     {"ADC3", NULL, "LPASS_PDM_TX"},
0976 
0977     {"I2S RX1", NULL, "RX_I2S_CLK"},
0978     {"I2S RX2", NULL, "RX_I2S_CLK"},
0979     {"I2S RX3", NULL, "RX_I2S_CLK"},
0980 
0981     {"RX_I2S_CLK", NULL, "PDM_CLK"},
0982     {"RX_I2S_CLK", NULL, "MCLK"},
0983     {"RX_I2S_CLK", NULL, "CDC_CONN"},
0984 
0985     /* RX1 PATH.. */
0986     {"PDM_RX1", NULL, "RX1 INT"},
0987     {"RX1 INT", NULL, "RX1 MIX1"},
0988 
0989     {"RX1 MIX1", NULL, "RX1 MIX1 INP1"},
0990     {"RX1 MIX1", NULL, "RX1 MIX1 INP2"},
0991     {"RX1 MIX1", NULL, "RX1 MIX1 INP3"},
0992 
0993     {"RX1 MIX1 INP1", "RX1", "I2S RX1"},
0994     {"RX1 MIX1 INP1", "RX2", "I2S RX2"},
0995     {"RX1 MIX1 INP1", "RX3", "I2S RX3"},
0996     {"RX1 MIX1 INP1", "IIR1", "IIR1"},
0997     {"RX1 MIX1 INP1", "IIR2", "IIR2"},
0998 
0999     {"RX1 MIX1 INP2", "RX1", "I2S RX1"},
1000     {"RX1 MIX1 INP2", "RX2", "I2S RX2"},
1001     {"RX1 MIX1 INP2", "RX3", "I2S RX3"},
1002     {"RX1 MIX1 INP2", "IIR1", "IIR1"},
1003     {"RX1 MIX1 INP2", "IIR2", "IIR2"},
1004 
1005     {"RX1 MIX1 INP3", "RX1", "I2S RX1"},
1006     {"RX1 MIX1 INP3", "RX2", "I2S RX2"},
1007     {"RX1 MIX1 INP3", "RX3", "I2S RX3"},
1008 
1009     /* RX2 PATH */
1010     {"PDM_RX2", NULL, "RX2 INT"},
1011     {"RX2 INT", NULL, "RX2 MIX1"},
1012 
1013     {"RX2 MIX1", NULL, "RX2 MIX1 INP1"},
1014     {"RX2 MIX1", NULL, "RX2 MIX1 INP2"},
1015     {"RX2 MIX1", NULL, "RX2 MIX1 INP3"},
1016 
1017     {"RX2 MIX1 INP1", "RX1", "I2S RX1"},
1018     {"RX2 MIX1 INP1", "RX2", "I2S RX2"},
1019     {"RX2 MIX1 INP1", "RX3", "I2S RX3"},
1020     {"RX2 MIX1 INP1", "IIR1", "IIR1"},
1021     {"RX2 MIX1 INP1", "IIR2", "IIR2"},
1022 
1023     {"RX2 MIX1 INP2", "RX1", "I2S RX1"},
1024     {"RX2 MIX1 INP2", "RX2", "I2S RX2"},
1025     {"RX2 MIX1 INP2", "RX3", "I2S RX3"},
1026     {"RX2 MIX1 INP1", "IIR1", "IIR1"},
1027     {"RX2 MIX1 INP1", "IIR2", "IIR2"},
1028 
1029     {"RX2 MIX1 INP3", "RX1", "I2S RX1"},
1030     {"RX2 MIX1 INP3", "RX2", "I2S RX2"},
1031     {"RX2 MIX1 INP3", "RX3", "I2S RX3"},
1032 
1033     /* RX3 PATH */
1034     {"PDM_RX3", NULL, "RX3 INT"},
1035     {"RX3 INT", NULL, "RX3 MIX1"},
1036 
1037     {"RX3 MIX1", NULL, "RX3 MIX1 INP1"},
1038     {"RX3 MIX1", NULL, "RX3 MIX1 INP2"},
1039     {"RX3 MIX1", NULL, "RX3 MIX1 INP3"},
1040 
1041     {"RX3 MIX1 INP1", "RX1", "I2S RX1"},
1042     {"RX3 MIX1 INP1", "RX2", "I2S RX2"},
1043     {"RX3 MIX1 INP1", "RX3", "I2S RX3"},
1044     {"RX3 MIX1 INP1", "IIR1", "IIR1"},
1045     {"RX3 MIX1 INP1", "IIR2", "IIR2"},
1046 
1047     {"RX3 MIX1 INP2", "RX1", "I2S RX1"},
1048     {"RX3 MIX1 INP2", "RX2", "I2S RX2"},
1049     {"RX3 MIX1 INP2", "RX3", "I2S RX3"},
1050     {"RX3 MIX1 INP2", "IIR1", "IIR1"},
1051     {"RX3 MIX1 INP2", "IIR2", "IIR2"},
1052 
1053     {"RX1 MIX2 INP1", "IIR1", "IIR1"},
1054     {"RX2 MIX2 INP1", "IIR1", "IIR1"},
1055     {"RX1 MIX2 INP1", "IIR2", "IIR2"},
1056     {"RX2 MIX2 INP1", "IIR2", "IIR2"},
1057 
1058     {"IIR1", NULL, "IIR1 INP1 MUX"},
1059     {"IIR1 INP1 MUX", "DEC1", "DEC1 MUX"},
1060     {"IIR1 INP1 MUX", "DEC2", "DEC2 MUX"},
1061 
1062     {"IIR2", NULL, "IIR2 INP1 MUX"},
1063     {"IIR2 INP1 MUX", "DEC1", "DEC1 MUX"},
1064     {"IIR2 INP1 MUX", "DEC2", "DEC2 MUX"},
1065 
1066     {"RX3 MIX1 INP3", "RX1", "I2S RX1"},
1067     {"RX3 MIX1 INP3", "RX2", "I2S RX2"},
1068     {"RX3 MIX1 INP3", "RX3", "I2S RX3"},
1069 
1070 };
1071 
1072 static int msm8916_wcd_digital_startup(struct snd_pcm_substream *substream,
1073                        struct snd_soc_dai *dai)
1074 {
1075     struct snd_soc_component *component = dai->component;
1076     struct msm8916_wcd_digital_priv *msm8916_wcd;
1077     unsigned long mclk_rate;
1078 
1079     msm8916_wcd = snd_soc_component_get_drvdata(component);
1080     snd_soc_component_update_bits(component, LPASS_CDC_CLK_MCLK_CTL,
1081                 MCLK_CTL_MCLK_EN_MASK,
1082                 MCLK_CTL_MCLK_EN_ENABLE);
1083     snd_soc_component_update_bits(component, LPASS_CDC_CLK_PDM_CTL,
1084                 LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_MASK,
1085                 LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_FB);
1086 
1087     mclk_rate = clk_get_rate(msm8916_wcd->mclk);
1088     switch (mclk_rate) {
1089     case 12288000:
1090         snd_soc_component_update_bits(component, LPASS_CDC_TOP_CTL,
1091                     TOP_CTL_DIG_MCLK_FREQ_MASK,
1092                     TOP_CTL_DIG_MCLK_FREQ_F_12_288MHZ);
1093         break;
1094     case 9600000:
1095         snd_soc_component_update_bits(component, LPASS_CDC_TOP_CTL,
1096                     TOP_CTL_DIG_MCLK_FREQ_MASK,
1097                     TOP_CTL_DIG_MCLK_FREQ_F_9_6MHZ);
1098         break;
1099     default:
1100         dev_err(component->dev, "Invalid mclk rate %ld\n", mclk_rate);
1101         break;
1102     }
1103     return 0;
1104 }
1105 
1106 static void msm8916_wcd_digital_shutdown(struct snd_pcm_substream *substream,
1107                      struct snd_soc_dai *dai)
1108 {
1109     snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_PDM_CTL,
1110                 LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_MASK, 0);
1111 }
1112 
1113 static const struct snd_soc_dai_ops msm8916_wcd_digital_dai_ops = {
1114     .startup = msm8916_wcd_digital_startup,
1115     .shutdown = msm8916_wcd_digital_shutdown,
1116     .hw_params = msm8916_wcd_digital_hw_params,
1117 };
1118 
1119 static struct snd_soc_dai_driver msm8916_wcd_digital_dai[] = {
1120     [0] = {
1121            .name = "msm8916_wcd_digital_i2s_rx1",
1122            .id = 0,
1123            .playback = {
1124                 .stream_name = "AIF1 Playback",
1125                 .rates = MSM8916_WCD_DIGITAL_RATES,
1126                 .formats = MSM8916_WCD_DIGITAL_FORMATS,
1127                 .channels_min = 1,
1128                 .channels_max = 3,
1129                 },
1130            .ops = &msm8916_wcd_digital_dai_ops,
1131            },
1132     [1] = {
1133            .name = "msm8916_wcd_digital_i2s_tx1",
1134            .id = 1,
1135            .capture = {
1136                .stream_name = "AIF1 Capture",
1137                .rates = MSM8916_WCD_DIGITAL_RATES,
1138                .formats = MSM8916_WCD_DIGITAL_FORMATS,
1139                .channels_min = 1,
1140                .channels_max = 4,
1141                },
1142            .ops = &msm8916_wcd_digital_dai_ops,
1143            },
1144 };
1145 
1146 static const struct snd_soc_component_driver msm8916_wcd_digital = {
1147     .probe          = msm8916_wcd_digital_component_probe,
1148     .set_sysclk     = msm8916_wcd_digital_component_set_sysclk,
1149     .controls       = msm8916_wcd_digital_snd_controls,
1150     .num_controls       = ARRAY_SIZE(msm8916_wcd_digital_snd_controls),
1151     .dapm_widgets       = msm8916_wcd_digital_dapm_widgets,
1152     .num_dapm_widgets   = ARRAY_SIZE(msm8916_wcd_digital_dapm_widgets),
1153     .dapm_routes        = msm8916_wcd_digital_audio_map,
1154     .num_dapm_routes    = ARRAY_SIZE(msm8916_wcd_digital_audio_map),
1155     .idle_bias_on       = 1,
1156     .use_pmdown_time    = 1,
1157     .endianness     = 1,
1158 };
1159 
1160 static const struct regmap_config msm8916_codec_regmap_config = {
1161     .reg_bits = 32,
1162     .reg_stride = 4,
1163     .val_bits = 32,
1164     .max_register = LPASS_CDC_TX2_DMIC_CTL,
1165     .cache_type = REGCACHE_FLAT,
1166 };
1167 
1168 static int msm8916_wcd_digital_probe(struct platform_device *pdev)
1169 {
1170     struct msm8916_wcd_digital_priv *priv;
1171     struct device *dev = &pdev->dev;
1172     void __iomem *base;
1173     struct regmap *digital_map;
1174     int ret;
1175 
1176     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1177     if (!priv)
1178         return -ENOMEM;
1179 
1180     base = devm_platform_ioremap_resource(pdev, 0);
1181     if (IS_ERR(base))
1182         return PTR_ERR(base);
1183 
1184     digital_map =
1185         devm_regmap_init_mmio(&pdev->dev, base,
1186                   &msm8916_codec_regmap_config);
1187     if (IS_ERR(digital_map))
1188         return PTR_ERR(digital_map);
1189 
1190     ret = msm8916_wcd_digital_get_clks(pdev, priv);
1191     if (ret < 0)
1192         return ret;
1193 
1194     ret = clk_prepare_enable(priv->ahbclk);
1195     if (ret < 0) {
1196         dev_err(dev, "failed to enable ahbclk %d\n", ret);
1197         return ret;
1198     }
1199 
1200     ret = clk_prepare_enable(priv->mclk);
1201     if (ret < 0) {
1202         dev_err(dev, "failed to enable mclk %d\n", ret);
1203         goto err_clk;
1204     }
1205 
1206     dev_set_drvdata(dev, priv);
1207 
1208     ret = devm_snd_soc_register_component(dev, &msm8916_wcd_digital,
1209                       msm8916_wcd_digital_dai,
1210                       ARRAY_SIZE(msm8916_wcd_digital_dai));
1211     if (ret)
1212         goto err_mclk;
1213 
1214     return 0;
1215 
1216 err_mclk:
1217     clk_disable_unprepare(priv->mclk);
1218 err_clk:
1219     clk_disable_unprepare(priv->ahbclk);
1220     return ret;
1221 }
1222 
1223 static int msm8916_wcd_digital_remove(struct platform_device *pdev)
1224 {
1225     struct msm8916_wcd_digital_priv *priv = dev_get_drvdata(&pdev->dev);
1226 
1227     clk_disable_unprepare(priv->mclk);
1228     clk_disable_unprepare(priv->ahbclk);
1229 
1230     return 0;
1231 }
1232 
1233 static const struct of_device_id msm8916_wcd_digital_match_table[] = {
1234     { .compatible = "qcom,msm8916-wcd-digital-codec" },
1235     { }
1236 };
1237 
1238 MODULE_DEVICE_TABLE(of, msm8916_wcd_digital_match_table);
1239 
1240 static struct platform_driver msm8916_wcd_digital_driver = {
1241     .driver = {
1242            .name = "msm8916-wcd-digital-codec",
1243            .of_match_table = msm8916_wcd_digital_match_table,
1244     },
1245     .probe = msm8916_wcd_digital_probe,
1246     .remove = msm8916_wcd_digital_remove,
1247 };
1248 
1249 module_platform_driver(msm8916_wcd_digital_driver);
1250 
1251 MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>");
1252 MODULE_DESCRIPTION("MSM8916 WCD Digital Codec driver");
1253 MODULE_LICENSE("GPL v2");
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