0001
0002
0003
0004 #include <linux/module.h>
0005 #include <linux/err.h>
0006 #include <linux/kernel.h>
0007 #include <linux/delay.h>
0008 #include <linux/regulator/consumer.h>
0009 #include <linux/types.h>
0010 #include <linux/clk.h>
0011 #include <linux/of.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/regmap.h>
0014 #include <sound/soc.h>
0015 #include <sound/pcm.h>
0016 #include <sound/pcm_params.h>
0017 #include <sound/tlv.h>
0018 #include <sound/jack.h>
0019
0020 #define CDC_D_REVISION1 (0xf000)
0021 #define CDC_D_PERPH_SUBTYPE (0xf005)
0022 #define CDC_D_INT_EN_SET (0xf015)
0023 #define CDC_D_INT_EN_CLR (0xf016)
0024 #define MBHC_SWITCH_INT BIT(7)
0025 #define MBHC_MIC_ELECTRICAL_INS_REM_DET BIT(6)
0026 #define MBHC_BUTTON_PRESS_DET BIT(5)
0027 #define MBHC_BUTTON_RELEASE_DET BIT(4)
0028 #define CDC_D_CDC_RST_CTL (0xf046)
0029 #define RST_CTL_DIG_SW_RST_N_MASK BIT(7)
0030 #define RST_CTL_DIG_SW_RST_N_RESET 0
0031 #define RST_CTL_DIG_SW_RST_N_REMOVE_RESET BIT(7)
0032
0033 #define CDC_D_CDC_TOP_CLK_CTL (0xf048)
0034 #define TOP_CLK_CTL_A_MCLK_MCLK2_EN_MASK (BIT(2) | BIT(3))
0035 #define TOP_CLK_CTL_A_MCLK_EN_ENABLE BIT(2)
0036 #define TOP_CLK_CTL_A_MCLK2_EN_ENABLE BIT(3)
0037
0038 #define CDC_D_CDC_ANA_CLK_CTL (0xf049)
0039 #define ANA_CLK_CTL_EAR_HPHR_CLK_EN_MASK BIT(0)
0040 #define ANA_CLK_CTL_EAR_HPHR_CLK_EN BIT(0)
0041 #define ANA_CLK_CTL_EAR_HPHL_CLK_EN BIT(1)
0042 #define ANA_CLK_CTL_SPKR_CLK_EN_MASK BIT(4)
0043 #define ANA_CLK_CTL_SPKR_CLK_EN BIT(4)
0044 #define ANA_CLK_CTL_TXA_CLK25_EN BIT(5)
0045
0046 #define CDC_D_CDC_DIG_CLK_CTL (0xf04A)
0047 #define DIG_CLK_CTL_RXD1_CLK_EN BIT(0)
0048 #define DIG_CLK_CTL_RXD2_CLK_EN BIT(1)
0049 #define DIG_CLK_CTL_RXD3_CLK_EN BIT(2)
0050 #define DIG_CLK_CTL_D_MBHC_CLK_EN_MASK BIT(3)
0051 #define DIG_CLK_CTL_D_MBHC_CLK_EN BIT(3)
0052 #define DIG_CLK_CTL_TXD_CLK_EN BIT(4)
0053 #define DIG_CLK_CTL_NCP_CLK_EN_MASK BIT(6)
0054 #define DIG_CLK_CTL_NCP_CLK_EN BIT(6)
0055 #define DIG_CLK_CTL_RXD_PDM_CLK_EN_MASK BIT(7)
0056 #define DIG_CLK_CTL_RXD_PDM_CLK_EN BIT(7)
0057
0058 #define CDC_D_CDC_CONN_TX1_CTL (0xf050)
0059 #define CONN_TX1_SERIAL_TX1_MUX GENMASK(1, 0)
0060 #define CONN_TX1_SERIAL_TX1_ADC_1 0x0
0061 #define CONN_TX1_SERIAL_TX1_RX_PDM_LB 0x1
0062 #define CONN_TX1_SERIAL_TX1_ZERO 0x2
0063
0064 #define CDC_D_CDC_CONN_TX2_CTL (0xf051)
0065 #define CONN_TX2_SERIAL_TX2_MUX GENMASK(1, 0)
0066 #define CONN_TX2_SERIAL_TX2_ADC_2 0x0
0067 #define CONN_TX2_SERIAL_TX2_RX_PDM_LB 0x1
0068 #define CONN_TX2_SERIAL_TX2_ZERO 0x2
0069 #define CDC_D_CDC_CONN_HPHR_DAC_CTL (0xf052)
0070 #define CDC_D_CDC_CONN_RX1_CTL (0xf053)
0071 #define CDC_D_CDC_CONN_RX2_CTL (0xf054)
0072 #define CDC_D_CDC_CONN_RX3_CTL (0xf055)
0073 #define CDC_D_CDC_CONN_RX_LB_CTL (0xf056)
0074 #define CDC_D_SEC_ACCESS (0xf0D0)
0075 #define CDC_D_PERPH_RESET_CTL3 (0xf0DA)
0076 #define CDC_D_PERPH_RESET_CTL4 (0xf0DB)
0077 #define CDC_A_REVISION1 (0xf100)
0078 #define CDC_A_REVISION2 (0xf101)
0079 #define CDC_A_REVISION3 (0xf102)
0080 #define CDC_A_REVISION4 (0xf103)
0081 #define CDC_A_PERPH_TYPE (0xf104)
0082 #define CDC_A_PERPH_SUBTYPE (0xf105)
0083 #define CDC_A_INT_RT_STS (0xf110)
0084 #define CDC_A_INT_SET_TYPE (0xf111)
0085 #define CDC_A_INT_POLARITY_HIGH (0xf112)
0086 #define CDC_A_INT_POLARITY_LOW (0xf113)
0087 #define CDC_A_INT_LATCHED_CLR (0xf114)
0088 #define CDC_A_INT_EN_SET (0xf115)
0089 #define CDC_A_INT_EN_CLR (0xf116)
0090 #define CDC_A_INT_LATCHED_STS (0xf118)
0091 #define CDC_A_INT_PENDING_STS (0xf119)
0092 #define CDC_A_INT_MID_SEL (0xf11A)
0093 #define CDC_A_INT_PRIORITY (0xf11B)
0094 #define CDC_A_MICB_1_EN (0xf140)
0095 #define MICB_1_EN_MICB_ENABLE BIT(7)
0096 #define MICB_1_EN_BYP_CAP_MASK BIT(6)
0097 #define MICB_1_EN_NO_EXT_BYP_CAP BIT(6)
0098 #define MICB_1_EN_EXT_BYP_CAP 0
0099 #define MICB_1_EN_PULL_DOWN_EN_MASK BIT(5)
0100 #define MICB_1_EN_PULL_DOWN_EN_ENABLE BIT(5)
0101 #define MICB_1_EN_OPA_STG2_TAIL_CURR_MASK GENMASK(3, 1)
0102 #define MICB_1_EN_OPA_STG2_TAIL_CURR_1_60UA (0x4)
0103 #define MICB_1_EN_PULL_UP_EN_MASK BIT(4)
0104 #define MICB_1_EN_TX3_GND_SEL_MASK BIT(0)
0105 #define MICB_1_EN_TX3_GND_SEL_TX_GND 0
0106
0107 #define CDC_A_MICB_1_VAL (0xf141)
0108 #define MICB_MIN_VAL 1600
0109 #define MICB_STEP_SIZE 50
0110 #define MICB_VOLTAGE_REGVAL(v) (((v - MICB_MIN_VAL)/MICB_STEP_SIZE) << 3)
0111 #define MICB_1_VAL_MICB_OUT_VAL_MASK GENMASK(7, 3)
0112 #define MICB_1_VAL_MICB_OUT_VAL_V2P70V ((0x16) << 3)
0113 #define MICB_1_VAL_MICB_OUT_VAL_V1P80V ((0x4) << 3)
0114 #define CDC_A_MICB_1_CTL (0xf142)
0115
0116 #define MICB_1_CTL_CFILT_REF_SEL_MASK BIT(1)
0117 #define MICB_1_CTL_CFILT_REF_SEL_HPF_REF BIT(1)
0118 #define MICB_1_CTL_EXT_PRECHARG_EN_MASK BIT(5)
0119 #define MICB_1_CTL_EXT_PRECHARG_EN_ENABLE BIT(5)
0120 #define MICB_1_CTL_INT_PRECHARG_BYP_MASK BIT(6)
0121 #define MICB_1_CTL_INT_PRECHARG_BYP_EXT_PRECHRG_SEL BIT(6)
0122
0123 #define CDC_A_MICB_1_INT_RBIAS (0xf143)
0124 #define MICB_1_INT_TX1_INT_RBIAS_EN_MASK BIT(7)
0125 #define MICB_1_INT_TX1_INT_RBIAS_EN_ENABLE BIT(7)
0126 #define MICB_1_INT_TX1_INT_RBIAS_EN_DISABLE 0
0127
0128 #define MICB_1_INT_TX1_INT_PULLUP_EN_MASK BIT(6)
0129 #define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(6)
0130 #define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_GND 0
0131
0132 #define MICB_1_INT_TX2_INT_RBIAS_EN_MASK BIT(4)
0133 #define MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE BIT(4)
0134 #define MICB_1_INT_TX2_INT_RBIAS_EN_DISABLE 0
0135 #define MICB_1_INT_TX2_INT_PULLUP_EN_MASK BIT(3)
0136 #define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(3)
0137 #define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_GND 0
0138
0139 #define MICB_1_INT_TX3_INT_RBIAS_EN_MASK BIT(1)
0140 #define MICB_1_INT_TX3_INT_RBIAS_EN_ENABLE BIT(1)
0141 #define MICB_1_INT_TX3_INT_RBIAS_EN_DISABLE 0
0142 #define MICB_1_INT_TX3_INT_PULLUP_EN_MASK BIT(0)
0143 #define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(0)
0144 #define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_GND 0
0145
0146 #define CDC_A_MICB_2_EN (0xf144)
0147 #define CDC_A_MICB_2_EN_ENABLE BIT(7)
0148 #define CDC_A_MICB_2_PULL_DOWN_EN_MASK BIT(5)
0149 #define CDC_A_MICB_2_PULL_DOWN_EN BIT(5)
0150 #define CDC_A_TX_1_2_ATEST_CTL_2 (0xf145)
0151 #define CDC_A_MASTER_BIAS_CTL (0xf146)
0152 #define CDC_A_MBHC_DET_CTL_1 (0xf147)
0153 #define CDC_A_MBHC_DET_CTL_L_DET_EN BIT(7)
0154 #define CDC_A_MBHC_DET_CTL_GND_DET_EN BIT(6)
0155 #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_INSERTION BIT(5)
0156 #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_REMOVAL (0)
0157 #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK BIT(5)
0158 #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_SHIFT (5)
0159 #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_AUTO BIT(4)
0160 #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_MANUAL BIT(3)
0161 #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_MASK GENMASK(4, 3)
0162 #define CDC_A_MBHC_DET_CTL_MBHC_BIAS_EN BIT(2)
0163 #define CDC_A_MBHC_DET_CTL_2 (0xf150)
0164 #define CDC_A_MBHC_DET_CTL_HS_L_DET_PULL_UP_CTRL_I_3P0 (BIT(7) | BIT(6))
0165 #define CDC_A_MBHC_DET_CTL_HS_L_DET_COMPA_CTRL_V0P9_VDD BIT(5)
0166 #define CDC_A_PLUG_TYPE_MASK GENMASK(4, 3)
0167 #define CDC_A_HPHL_PLUG_TYPE_NO BIT(4)
0168 #define CDC_A_GND_PLUG_TYPE_NO BIT(3)
0169 #define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN_MASK BIT(0)
0170 #define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN BIT(0)
0171 #define CDC_A_MBHC_FSM_CTL (0xf151)
0172 #define CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN BIT(7)
0173 #define CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN_MASK BIT(7)
0174 #define CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_I_100UA (0x3 << 4)
0175 #define CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_MASK GENMASK(6, 4)
0176 #define CDC_A_MBHC_DBNC_TIMER (0xf152)
0177 #define CDC_A_MBHC_DBNC_TIMER_BTN_DBNC_T_16MS BIT(3)
0178 #define CDC_A_MBHC_DBNC_TIMER_INSREM_DBNC_T_256_MS (0x9 << 4)
0179 #define CDC_A_MBHC_BTN0_ZDET_CTL_0 (0xf153)
0180 #define CDC_A_MBHC_BTN1_ZDET_CTL_1 (0xf154)
0181 #define CDC_A_MBHC_BTN2_ZDET_CTL_2 (0xf155)
0182 #define CDC_A_MBHC_BTN3_CTL (0xf156)
0183 #define CDC_A_MBHC_BTN4_CTL (0xf157)
0184 #define CDC_A_MBHC_BTN_VREF_FINE_SHIFT (2)
0185 #define CDC_A_MBHC_BTN_VREF_FINE_MASK GENMASK(4, 2)
0186 #define CDC_A_MBHC_BTN_VREF_COARSE_MASK GENMASK(7, 5)
0187 #define CDC_A_MBHC_BTN_VREF_COARSE_SHIFT (5)
0188 #define CDC_A_MBHC_BTN_VREF_MASK (CDC_A_MBHC_BTN_VREF_COARSE_MASK | \
0189 CDC_A_MBHC_BTN_VREF_FINE_MASK)
0190 #define CDC_A_MBHC_RESULT_1 (0xf158)
0191 #define CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK GENMASK(4, 0)
0192 #define CDC_A_TX_1_EN (0xf160)
0193 #define CDC_A_TX_2_EN (0xf161)
0194 #define CDC_A_TX_1_2_TEST_CTL_1 (0xf162)
0195 #define CDC_A_TX_1_2_TEST_CTL_2 (0xf163)
0196 #define CDC_A_TX_1_2_ATEST_CTL (0xf164)
0197 #define CDC_A_TX_1_2_OPAMP_BIAS (0xf165)
0198 #define CDC_A_TX_3_EN (0xf167)
0199 #define CDC_A_NCP_EN (0xf180)
0200 #define CDC_A_NCP_CLK (0xf181)
0201 #define CDC_A_NCP_FBCTRL (0xf183)
0202 #define CDC_A_NCP_FBCTRL_FB_CLK_INV_MASK BIT(5)
0203 #define CDC_A_NCP_FBCTRL_FB_CLK_INV BIT(5)
0204 #define CDC_A_NCP_BIAS (0xf184)
0205 #define CDC_A_NCP_VCTRL (0xf185)
0206 #define CDC_A_NCP_TEST (0xf186)
0207 #define CDC_A_NCP_CLIM_ADDR (0xf187)
0208 #define CDC_A_RX_CLOCK_DIVIDER (0xf190)
0209 #define CDC_A_RX_COM_OCP_CTL (0xf191)
0210 #define CDC_A_RX_COM_OCP_COUNT (0xf192)
0211 #define CDC_A_RX_COM_BIAS_DAC (0xf193)
0212 #define RX_COM_BIAS_DAC_RX_BIAS_EN_MASK BIT(7)
0213 #define RX_COM_BIAS_DAC_RX_BIAS_EN_ENABLE BIT(7)
0214 #define RX_COM_BIAS_DAC_DAC_REF_EN_MASK BIT(0)
0215 #define RX_COM_BIAS_DAC_DAC_REF_EN_ENABLE BIT(0)
0216
0217 #define CDC_A_RX_HPH_BIAS_PA (0xf194)
0218 #define CDC_A_RX_HPH_BIAS_LDO_OCP (0xf195)
0219 #define CDC_A_RX_HPH_BIAS_CNP (0xf196)
0220 #define CDC_A_RX_HPH_CNP_EN (0xf197)
0221 #define CDC_A_RX_HPH_L_PA_DAC_CTL (0xf19B)
0222 #define RX_HPA_L_PA_DAC_CTL_DATA_RESET_MASK BIT(1)
0223 #define RX_HPA_L_PA_DAC_CTL_DATA_RESET_RESET BIT(1)
0224 #define CDC_A_RX_HPH_R_PA_DAC_CTL (0xf19D)
0225 #define RX_HPH_R_PA_DAC_CTL_DATA_RESET BIT(1)
0226 #define RX_HPH_R_PA_DAC_CTL_DATA_RESET_MASK BIT(1)
0227
0228 #define CDC_A_RX_EAR_CTL (0xf19E)
0229 #define RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK BIT(0)
0230 #define RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE BIT(0)
0231 #define RX_EAR_CTL_PA_EAR_PA_EN_MASK BIT(6)
0232 #define RX_EAR_CTL_PA_EAR_PA_EN_ENABLE BIT(6)
0233 #define RX_EAR_CTL_PA_SEL_MASK BIT(7)
0234 #define RX_EAR_CTL_PA_SEL BIT(7)
0235
0236 #define CDC_A_SPKR_DAC_CTL (0xf1B0)
0237 #define SPKR_DAC_CTL_DAC_RESET_MASK BIT(4)
0238 #define SPKR_DAC_CTL_DAC_RESET_NORMAL 0
0239
0240 #define CDC_A_SPKR_DRV_CTL (0xf1B2)
0241 #define SPKR_DRV_CTL_DEF_MASK 0xEF
0242 #define SPKR_DRV_CLASSD_PA_EN_MASK BIT(7)
0243 #define SPKR_DRV_CLASSD_PA_EN_ENABLE BIT(7)
0244 #define SPKR_DRV_CAL_EN BIT(6)
0245 #define SPKR_DRV_SETTLE_EN BIT(5)
0246 #define SPKR_DRV_FW_EN BIT(3)
0247 #define SPKR_DRV_BOOST_SET BIT(2)
0248 #define SPKR_DRV_CMFB_SET BIT(1)
0249 #define SPKR_DRV_GAIN_SET BIT(0)
0250 #define SPKR_DRV_CTL_DEF_VAL (SPKR_DRV_CLASSD_PA_EN_ENABLE | \
0251 SPKR_DRV_CAL_EN | SPKR_DRV_SETTLE_EN | \
0252 SPKR_DRV_FW_EN | SPKR_DRV_BOOST_SET | \
0253 SPKR_DRV_CMFB_SET | SPKR_DRV_GAIN_SET)
0254 #define CDC_A_SPKR_OCP_CTL (0xf1B4)
0255 #define CDC_A_SPKR_PWRSTG_CTL (0xf1B5)
0256 #define SPKR_PWRSTG_CTL_DAC_EN_MASK BIT(0)
0257 #define SPKR_PWRSTG_CTL_DAC_EN BIT(0)
0258 #define SPKR_PWRSTG_CTL_MASK 0xE0
0259 #define SPKR_PWRSTG_CTL_BBM_MASK BIT(7)
0260 #define SPKR_PWRSTG_CTL_BBM_EN BIT(7)
0261 #define SPKR_PWRSTG_CTL_HBRDGE_EN_MASK BIT(6)
0262 #define SPKR_PWRSTG_CTL_HBRDGE_EN BIT(6)
0263 #define SPKR_PWRSTG_CTL_CLAMP_EN_MASK BIT(5)
0264 #define SPKR_PWRSTG_CTL_CLAMP_EN BIT(5)
0265
0266 #define CDC_A_SPKR_DRV_DBG (0xf1B7)
0267 #define CDC_A_CURRENT_LIMIT (0xf1C0)
0268 #define CDC_A_BOOST_EN_CTL (0xf1C3)
0269 #define CDC_A_SLOPE_COMP_IP_ZERO (0xf1C4)
0270 #define CDC_A_SEC_ACCESS (0xf1D0)
0271 #define CDC_A_PERPH_RESET_CTL3 (0xf1DA)
0272 #define CDC_A_PERPH_RESET_CTL4 (0xf1DB)
0273
0274 #define MSM8916_WCD_ANALOG_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
0275 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000)
0276 #define MSM8916_WCD_ANALOG_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
0277 SNDRV_PCM_FMTBIT_S32_LE)
0278
0279 static int btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
0280 SND_JACK_BTN_2 | SND_JACK_BTN_3 | SND_JACK_BTN_4;
0281 static int hs_jack_mask = SND_JACK_HEADPHONE | SND_JACK_HEADSET;
0282
0283 static const char * const supply_names[] = {
0284 "vdd-cdc-io",
0285 "vdd-cdc-tx-rx-cx",
0286 };
0287
0288 #define MBHC_MAX_BUTTONS (5)
0289
0290 struct pm8916_wcd_analog_priv {
0291 u16 pmic_rev;
0292 u16 codec_version;
0293 bool mbhc_btn_enabled;
0294
0295 int mbhc_btn0_released;
0296 bool detect_accessory_type;
0297 struct clk *mclk;
0298 struct snd_soc_component *component;
0299 struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
0300 struct snd_soc_jack *jack;
0301 bool hphl_jack_type_normally_open;
0302 bool gnd_jack_type_normally_open;
0303
0304 u32 vref_btn_cs[MBHC_MAX_BUTTONS];
0305
0306 u32 vref_btn_micb[MBHC_MAX_BUTTONS];
0307 unsigned int micbias1_cap_mode;
0308 unsigned int micbias2_cap_mode;
0309 unsigned int micbias_mv;
0310 };
0311
0312 static const char *const adc2_mux_text[] = { "ZERO", "INP2", "INP3" };
0313 static const char *const rdac2_mux_text[] = { "RX1", "RX2" };
0314 static const char *const hph_text[] = { "ZERO", "Switch", };
0315
0316 static const struct soc_enum hph_enum = SOC_ENUM_SINGLE_VIRT(
0317 ARRAY_SIZE(hph_text), hph_text);
0318
0319 static const struct snd_kcontrol_new ear_mux = SOC_DAPM_ENUM("EAR_S", hph_enum);
0320 static const struct snd_kcontrol_new hphl_mux = SOC_DAPM_ENUM("HPHL", hph_enum);
0321 static const struct snd_kcontrol_new hphr_mux = SOC_DAPM_ENUM("HPHR", hph_enum);
0322
0323
0324 static const struct soc_enum adc2_enum = SOC_ENUM_SINGLE_VIRT(
0325 ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
0326
0327
0328 static const struct soc_enum rdac2_mux_enum = SOC_ENUM_SINGLE(
0329 CDC_D_CDC_CONN_HPHR_DAC_CTL, 0, 2, rdac2_mux_text);
0330
0331 static const struct snd_kcontrol_new spkr_switch[] = {
0332 SOC_DAPM_SINGLE("Switch", CDC_A_SPKR_DAC_CTL, 7, 1, 0)
0333 };
0334
0335 static const struct snd_kcontrol_new rdac2_mux = SOC_DAPM_ENUM(
0336 "RDAC2 MUX Mux", rdac2_mux_enum);
0337 static const struct snd_kcontrol_new tx_adc2_mux = SOC_DAPM_ENUM(
0338 "ADC2 MUX Mux", adc2_enum);
0339
0340
0341 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 600, 0);
0342
0343 static const struct snd_kcontrol_new pm8916_wcd_analog_snd_controls[] = {
0344 SOC_SINGLE_TLV("ADC1 Volume", CDC_A_TX_1_EN, 3, 8, 0, analog_gain),
0345 SOC_SINGLE_TLV("ADC2 Volume", CDC_A_TX_2_EN, 3, 8, 0, analog_gain),
0346 SOC_SINGLE_TLV("ADC3 Volume", CDC_A_TX_3_EN, 3, 8, 0, analog_gain),
0347 };
0348
0349 static void pm8916_wcd_analog_micbias_enable(struct snd_soc_component *component)
0350 {
0351 struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
0352
0353 snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL,
0354 MICB_1_CTL_EXT_PRECHARG_EN_MASK |
0355 MICB_1_CTL_INT_PRECHARG_BYP_MASK,
0356 MICB_1_CTL_INT_PRECHARG_BYP_EXT_PRECHRG_SEL
0357 | MICB_1_CTL_EXT_PRECHARG_EN_ENABLE);
0358
0359 if (wcd->micbias_mv) {
0360 snd_soc_component_update_bits(component, CDC_A_MICB_1_VAL,
0361 MICB_1_VAL_MICB_OUT_VAL_MASK,
0362 MICB_VOLTAGE_REGVAL(wcd->micbias_mv));
0363
0364
0365
0366
0367 if (wcd->micbias_mv >= 2700)
0368 msleep(50);
0369 }
0370
0371 snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL,
0372 MICB_1_CTL_EXT_PRECHARG_EN_MASK |
0373 MICB_1_CTL_INT_PRECHARG_BYP_MASK, 0);
0374
0375 }
0376
0377 static int pm8916_wcd_analog_enable_micbias(struct snd_soc_component *component,
0378 int event, unsigned int cap_mode)
0379 {
0380 switch (event) {
0381 case SND_SOC_DAPM_POST_PMU:
0382 pm8916_wcd_analog_micbias_enable(component);
0383 snd_soc_component_update_bits(component, CDC_A_MICB_1_EN,
0384 MICB_1_EN_BYP_CAP_MASK, cap_mode);
0385 break;
0386 }
0387
0388 return 0;
0389 }
0390
0391 static int pm8916_wcd_analog_enable_micbias_int(struct snd_soc_dapm_widget *w,
0392 struct snd_kcontrol *kcontrol,
0393 int event)
0394 {
0395 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0396
0397 switch (event) {
0398 case SND_SOC_DAPM_PRE_PMU:
0399 snd_soc_component_update_bits(component, CDC_A_MICB_1_EN,
0400 MICB_1_EN_OPA_STG2_TAIL_CURR_MASK,
0401 MICB_1_EN_OPA_STG2_TAIL_CURR_1_60UA);
0402 break;
0403 }
0404
0405 return 0;
0406 }
0407
0408 static int pm8916_wcd_analog_enable_micbias1(struct snd_soc_dapm_widget *w,
0409 struct snd_kcontrol *kcontrol,
0410 int event)
0411 {
0412 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0413 struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
0414
0415 return pm8916_wcd_analog_enable_micbias(component, event,
0416 wcd->micbias1_cap_mode);
0417 }
0418
0419 static int pm8916_wcd_analog_enable_micbias2(struct snd_soc_dapm_widget *w,
0420 struct snd_kcontrol *kcontrol,
0421 int event)
0422 {
0423 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0424 struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
0425
0426 return pm8916_wcd_analog_enable_micbias(component, event,
0427 wcd->micbias2_cap_mode);
0428
0429 }
0430
0431 static int pm8916_mbhc_configure_bias(struct pm8916_wcd_analog_priv *priv,
0432 bool micbias2_enabled)
0433 {
0434 struct snd_soc_component *component = priv->component;
0435 u32 coarse, fine, reg_val, reg_addr;
0436 int *vrefs, i;
0437
0438 if (!micbias2_enabled) {
0439
0440 snd_soc_component_update_bits(component, CDC_A_MICB_1_INT_RBIAS,
0441 MICB_1_INT_TX2_INT_RBIAS_EN_MASK,
0442 MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE);
0443
0444 snd_soc_component_update_bits(component, CDC_A_MICB_2_EN,
0445 CDC_A_MICB_2_PULL_DOWN_EN_MASK,
0446 0);
0447
0448 snd_soc_component_update_bits(component, CDC_A_MBHC_FSM_CTL,
0449 CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_MASK,
0450 CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_I_100UA);
0451 }
0452 snd_soc_component_update_bits(component, CDC_A_MBHC_FSM_CTL,
0453 CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN_MASK,
0454 CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN);
0455
0456 if (micbias2_enabled)
0457 vrefs = &priv->vref_btn_micb[0];
0458 else
0459 vrefs = &priv->vref_btn_cs[0];
0460
0461
0462 reg_addr = CDC_A_MBHC_BTN0_ZDET_CTL_0;
0463 for (i = 0; i < MBHC_MAX_BUTTONS; i++) {
0464
0465 coarse = (vrefs[i] / 100);
0466 fine = ((vrefs[i] % 100) / 12);
0467 reg_val = (coarse << CDC_A_MBHC_BTN_VREF_COARSE_SHIFT) |
0468 (fine << CDC_A_MBHC_BTN_VREF_FINE_SHIFT);
0469 snd_soc_component_update_bits(component, reg_addr,
0470 CDC_A_MBHC_BTN_VREF_MASK,
0471 reg_val);
0472 reg_addr++;
0473 }
0474
0475 return 0;
0476 }
0477
0478 static void pm8916_wcd_setup_mbhc(struct pm8916_wcd_analog_priv *wcd)
0479 {
0480 struct snd_soc_component *component = wcd->component;
0481 bool micbias_enabled = false;
0482 u32 plug_type = 0;
0483 u32 int_en_mask;
0484
0485 snd_soc_component_write(component, CDC_A_MBHC_DET_CTL_1,
0486 CDC_A_MBHC_DET_CTL_L_DET_EN |
0487 CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_INSERTION |
0488 CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_AUTO |
0489 CDC_A_MBHC_DET_CTL_MBHC_BIAS_EN);
0490
0491 if (wcd->hphl_jack_type_normally_open)
0492 plug_type |= CDC_A_HPHL_PLUG_TYPE_NO;
0493
0494 if (wcd->gnd_jack_type_normally_open)
0495 plug_type |= CDC_A_GND_PLUG_TYPE_NO;
0496
0497 snd_soc_component_write(component, CDC_A_MBHC_DET_CTL_2,
0498 CDC_A_MBHC_DET_CTL_HS_L_DET_PULL_UP_CTRL_I_3P0 |
0499 CDC_A_MBHC_DET_CTL_HS_L_DET_COMPA_CTRL_V0P9_VDD |
0500 plug_type |
0501 CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN);
0502
0503
0504 snd_soc_component_write(component, CDC_A_MBHC_DBNC_TIMER,
0505 CDC_A_MBHC_DBNC_TIMER_INSREM_DBNC_T_256_MS |
0506 CDC_A_MBHC_DBNC_TIMER_BTN_DBNC_T_16MS);
0507
0508
0509 snd_soc_component_update_bits(component, CDC_D_CDC_DIG_CLK_CTL,
0510 DIG_CLK_CTL_D_MBHC_CLK_EN_MASK,
0511 DIG_CLK_CTL_D_MBHC_CLK_EN);
0512
0513 if (snd_soc_component_read(component, CDC_A_MICB_2_EN) & CDC_A_MICB_2_EN_ENABLE)
0514 micbias_enabled = true;
0515
0516 pm8916_mbhc_configure_bias(wcd, micbias_enabled);
0517
0518 int_en_mask = MBHC_SWITCH_INT;
0519 if (wcd->mbhc_btn_enabled)
0520 int_en_mask |= MBHC_BUTTON_PRESS_DET | MBHC_BUTTON_RELEASE_DET;
0521
0522 snd_soc_component_update_bits(component, CDC_D_INT_EN_CLR, int_en_mask, 0);
0523 snd_soc_component_update_bits(component, CDC_D_INT_EN_SET, int_en_mask, int_en_mask);
0524 wcd->mbhc_btn0_released = false;
0525 wcd->detect_accessory_type = true;
0526 }
0527
0528 static int pm8916_wcd_analog_enable_micbias_int2(struct
0529 snd_soc_dapm_widget
0530 *w, struct snd_kcontrol
0531 *kcontrol, int event)
0532 {
0533 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0534 struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
0535
0536 switch (event) {
0537 case SND_SOC_DAPM_PRE_PMU:
0538 snd_soc_component_update_bits(component, CDC_A_MICB_2_EN,
0539 CDC_A_MICB_2_PULL_DOWN_EN_MASK, 0);
0540 break;
0541 case SND_SOC_DAPM_POST_PMU:
0542 pm8916_mbhc_configure_bias(wcd, true);
0543 break;
0544 case SND_SOC_DAPM_POST_PMD:
0545 pm8916_mbhc_configure_bias(wcd, false);
0546 break;
0547 }
0548
0549 return pm8916_wcd_analog_enable_micbias_int(w, kcontrol, event);
0550 }
0551
0552 static int pm8916_wcd_analog_enable_adc(struct snd_soc_dapm_widget *w,
0553 struct snd_kcontrol *kcontrol,
0554 int event)
0555 {
0556 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0557 u16 adc_reg = CDC_A_TX_1_2_TEST_CTL_2;
0558 u8 init_bit_shift;
0559
0560 if (w->reg == CDC_A_TX_1_EN)
0561 init_bit_shift = 5;
0562 else
0563 init_bit_shift = 4;
0564
0565 switch (event) {
0566 case SND_SOC_DAPM_PRE_PMU:
0567 if (w->reg == CDC_A_TX_2_EN)
0568 snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL,
0569 MICB_1_CTL_CFILT_REF_SEL_MASK,
0570 MICB_1_CTL_CFILT_REF_SEL_HPF_REF);
0571
0572
0573
0574
0575
0576 usleep_range(10000, 10010);
0577 snd_soc_component_update_bits(component, adc_reg, 1 << init_bit_shift,
0578 1 << init_bit_shift);
0579 switch (w->reg) {
0580 case CDC_A_TX_1_EN:
0581 snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX1_CTL,
0582 CONN_TX1_SERIAL_TX1_MUX,
0583 CONN_TX1_SERIAL_TX1_ADC_1);
0584 break;
0585 case CDC_A_TX_2_EN:
0586 case CDC_A_TX_3_EN:
0587 snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX2_CTL,
0588 CONN_TX2_SERIAL_TX2_MUX,
0589 CONN_TX2_SERIAL_TX2_ADC_2);
0590 break;
0591 }
0592 break;
0593 case SND_SOC_DAPM_POST_PMU:
0594
0595
0596
0597
0598 usleep_range(12000, 12010);
0599 snd_soc_component_update_bits(component, adc_reg, 1 << init_bit_shift, 0x00);
0600 break;
0601 case SND_SOC_DAPM_POST_PMD:
0602 switch (w->reg) {
0603 case CDC_A_TX_1_EN:
0604 snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX1_CTL,
0605 CONN_TX1_SERIAL_TX1_MUX,
0606 CONN_TX1_SERIAL_TX1_ZERO);
0607 break;
0608 case CDC_A_TX_2_EN:
0609 snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL,
0610 MICB_1_CTL_CFILT_REF_SEL_MASK, 0);
0611 fallthrough;
0612 case CDC_A_TX_3_EN:
0613 snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX2_CTL,
0614 CONN_TX2_SERIAL_TX2_MUX,
0615 CONN_TX2_SERIAL_TX2_ZERO);
0616 break;
0617 }
0618
0619
0620 break;
0621 }
0622 return 0;
0623 }
0624
0625 static int pm8916_wcd_analog_enable_spk_pa(struct snd_soc_dapm_widget *w,
0626 struct snd_kcontrol *kcontrol,
0627 int event)
0628 {
0629 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0630
0631 switch (event) {
0632 case SND_SOC_DAPM_PRE_PMU:
0633 snd_soc_component_update_bits(component, CDC_A_SPKR_PWRSTG_CTL,
0634 SPKR_PWRSTG_CTL_DAC_EN_MASK |
0635 SPKR_PWRSTG_CTL_BBM_MASK |
0636 SPKR_PWRSTG_CTL_HBRDGE_EN_MASK |
0637 SPKR_PWRSTG_CTL_CLAMP_EN_MASK,
0638 SPKR_PWRSTG_CTL_DAC_EN|
0639 SPKR_PWRSTG_CTL_BBM_EN |
0640 SPKR_PWRSTG_CTL_HBRDGE_EN |
0641 SPKR_PWRSTG_CTL_CLAMP_EN);
0642
0643 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL,
0644 RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK,
0645 RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE);
0646 break;
0647 case SND_SOC_DAPM_POST_PMU:
0648 snd_soc_component_update_bits(component, CDC_A_SPKR_DRV_CTL,
0649 SPKR_DRV_CTL_DEF_MASK,
0650 SPKR_DRV_CTL_DEF_VAL);
0651 snd_soc_component_update_bits(component, w->reg,
0652 SPKR_DRV_CLASSD_PA_EN_MASK,
0653 SPKR_DRV_CLASSD_PA_EN_ENABLE);
0654 break;
0655 case SND_SOC_DAPM_POST_PMD:
0656 snd_soc_component_update_bits(component, CDC_A_SPKR_PWRSTG_CTL,
0657 SPKR_PWRSTG_CTL_DAC_EN_MASK|
0658 SPKR_PWRSTG_CTL_BBM_MASK |
0659 SPKR_PWRSTG_CTL_HBRDGE_EN_MASK |
0660 SPKR_PWRSTG_CTL_CLAMP_EN_MASK, 0);
0661
0662 snd_soc_component_update_bits(component, CDC_A_SPKR_DAC_CTL,
0663 SPKR_DAC_CTL_DAC_RESET_MASK,
0664 SPKR_DAC_CTL_DAC_RESET_NORMAL);
0665 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL,
0666 RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK, 0);
0667 break;
0668 }
0669 return 0;
0670 }
0671
0672 static int pm8916_wcd_analog_enable_ear_pa(struct snd_soc_dapm_widget *w,
0673 struct snd_kcontrol *kcontrol,
0674 int event)
0675 {
0676 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0677
0678 switch (event) {
0679 case SND_SOC_DAPM_PRE_PMU:
0680 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL,
0681 RX_EAR_CTL_PA_SEL_MASK, RX_EAR_CTL_PA_SEL);
0682 break;
0683 case SND_SOC_DAPM_POST_PMU:
0684 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL,
0685 RX_EAR_CTL_PA_EAR_PA_EN_MASK,
0686 RX_EAR_CTL_PA_EAR_PA_EN_ENABLE);
0687 break;
0688 case SND_SOC_DAPM_POST_PMD:
0689 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL,
0690 RX_EAR_CTL_PA_EAR_PA_EN_MASK, 0);
0691
0692 usleep_range(7000, 7100);
0693 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL,
0694 RX_EAR_CTL_PA_SEL_MASK, 0);
0695 break;
0696 }
0697 return 0;
0698 }
0699
0700 static const struct reg_default wcd_reg_defaults_2_0[] = {
0701 {CDC_A_RX_COM_OCP_CTL, 0xD1},
0702 {CDC_A_RX_COM_OCP_COUNT, 0xFF},
0703 {CDC_D_SEC_ACCESS, 0xA5},
0704 {CDC_D_PERPH_RESET_CTL3, 0x0F},
0705 {CDC_A_TX_1_2_OPAMP_BIAS, 0x4F},
0706 {CDC_A_NCP_FBCTRL, 0x28},
0707 {CDC_A_SPKR_DRV_CTL, 0x69},
0708 {CDC_A_SPKR_DRV_DBG, 0x01},
0709 {CDC_A_BOOST_EN_CTL, 0x5F},
0710 {CDC_A_SLOPE_COMP_IP_ZERO, 0x88},
0711 {CDC_A_SEC_ACCESS, 0xA5},
0712 {CDC_A_PERPH_RESET_CTL3, 0x0F},
0713 {CDC_A_CURRENT_LIMIT, 0x82},
0714 {CDC_A_SPKR_DAC_CTL, 0x03},
0715 {CDC_A_SPKR_OCP_CTL, 0xE1},
0716 {CDC_A_MASTER_BIAS_CTL, 0x30},
0717 };
0718
0719 static int pm8916_wcd_analog_probe(struct snd_soc_component *component)
0720 {
0721 struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(component->dev);
0722 int err, reg;
0723
0724 err = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
0725 if (err != 0) {
0726 dev_err(component->dev, "failed to enable regulators (%d)\n", err);
0727 return err;
0728 }
0729
0730 snd_soc_component_init_regmap(component,
0731 dev_get_regmap(component->dev->parent, NULL));
0732 snd_soc_component_set_drvdata(component, priv);
0733 priv->pmic_rev = snd_soc_component_read(component, CDC_D_REVISION1);
0734 priv->codec_version = snd_soc_component_read(component, CDC_D_PERPH_SUBTYPE);
0735
0736 dev_info(component->dev, "PMIC REV: %d\t CODEC Version: %d\n",
0737 priv->pmic_rev, priv->codec_version);
0738
0739 snd_soc_component_write(component, CDC_D_PERPH_RESET_CTL4, 0x01);
0740 snd_soc_component_write(component, CDC_A_PERPH_RESET_CTL4, 0x01);
0741
0742 for (reg = 0; reg < ARRAY_SIZE(wcd_reg_defaults_2_0); reg++)
0743 snd_soc_component_write(component, wcd_reg_defaults_2_0[reg].reg,
0744 wcd_reg_defaults_2_0[reg].def);
0745
0746 priv->component = component;
0747
0748 snd_soc_component_update_bits(component, CDC_D_CDC_RST_CTL,
0749 RST_CTL_DIG_SW_RST_N_MASK,
0750 RST_CTL_DIG_SW_RST_N_REMOVE_RESET);
0751
0752 pm8916_wcd_setup_mbhc(priv);
0753
0754 return 0;
0755 }
0756
0757 static void pm8916_wcd_analog_remove(struct snd_soc_component *component)
0758 {
0759 struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(component->dev);
0760
0761 snd_soc_component_update_bits(component, CDC_D_CDC_RST_CTL,
0762 RST_CTL_DIG_SW_RST_N_MASK, 0);
0763
0764 regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
0765 priv->supplies);
0766 }
0767
0768 static const struct snd_soc_dapm_route pm8916_wcd_analog_audio_map[] = {
0769
0770 {"PDM_RX1", NULL, "PDM Playback"},
0771 {"PDM_RX2", NULL, "PDM Playback"},
0772 {"PDM_RX3", NULL, "PDM Playback"},
0773 {"PDM Capture", NULL, "PDM_TX"},
0774
0775
0776 {"PDM_TX", NULL, "ADC2"},
0777 {"PDM_TX", NULL, "ADC3"},
0778 {"ADC2", NULL, "ADC2 MUX"},
0779 {"ADC3", NULL, "ADC2 MUX"},
0780 {"ADC2 MUX", "INP2", "ADC2_INP2"},
0781 {"ADC2 MUX", "INP3", "ADC2_INP3"},
0782
0783 {"PDM_TX", NULL, "ADC1"},
0784 {"ADC1", NULL, "AMIC1"},
0785 {"ADC2_INP2", NULL, "AMIC2"},
0786 {"ADC2_INP3", NULL, "AMIC3"},
0787
0788
0789 {"HPHR DAC", NULL, "RDAC2 MUX"},
0790 {"RDAC2 MUX", "RX1", "PDM_RX1"},
0791 {"RDAC2 MUX", "RX2", "PDM_RX2"},
0792 {"HPHL DAC", NULL, "PDM_RX1"},
0793 {"PDM_RX1", NULL, "RXD1_CLK"},
0794 {"PDM_RX2", NULL, "RXD2_CLK"},
0795 {"PDM_RX3", NULL, "RXD3_CLK"},
0796
0797 {"PDM_RX1", NULL, "RXD_PDM_CLK"},
0798 {"PDM_RX2", NULL, "RXD_PDM_CLK"},
0799 {"PDM_RX3", NULL, "RXD_PDM_CLK"},
0800
0801 {"ADC1", NULL, "TXD_CLK"},
0802 {"ADC2", NULL, "TXD_CLK"},
0803 {"ADC3", NULL, "TXD_CLK"},
0804
0805 {"ADC1", NULL, "TXA_CLK25"},
0806 {"ADC2", NULL, "TXA_CLK25"},
0807 {"ADC3", NULL, "TXA_CLK25"},
0808
0809 {"PDM_RX1", NULL, "A_MCLK2"},
0810 {"PDM_RX2", NULL, "A_MCLK2"},
0811 {"PDM_RX3", NULL, "A_MCLK2"},
0812
0813 {"PDM_TX", NULL, "A_MCLK2"},
0814 {"A_MCLK2", NULL, "A_MCLK"},
0815
0816
0817 {"EAR", NULL, "EAR_S"},
0818 {"EAR_S", "Switch", "EAR PA"},
0819 {"EAR PA", NULL, "RX_BIAS"},
0820 {"EAR PA", NULL, "HPHL DAC"},
0821 {"EAR PA", NULL, "HPHR DAC"},
0822 {"EAR PA", NULL, "EAR CP"},
0823
0824
0825 {"HPH_L", NULL, "HPHL PA"},
0826 {"HPH_R", NULL, "HPHR PA"},
0827
0828 {"HPHL DAC", NULL, "EAR_HPHL_CLK"},
0829 {"HPHR DAC", NULL, "EAR_HPHR_CLK"},
0830
0831 {"CP", NULL, "NCP_CLK"},
0832
0833 {"HPHL PA", NULL, "HPHL"},
0834 {"HPHR PA", NULL, "HPHR"},
0835 {"HPHL PA", NULL, "CP"},
0836 {"HPHL PA", NULL, "RX_BIAS"},
0837 {"HPHR PA", NULL, "CP"},
0838 {"HPHR PA", NULL, "RX_BIAS"},
0839 {"HPHL", "Switch", "HPHL DAC"},
0840 {"HPHR", "Switch", "HPHR DAC"},
0841
0842 {"RX_BIAS", NULL, "DAC_REF"},
0843
0844 {"SPK_OUT", NULL, "SPK PA"},
0845 {"SPK PA", NULL, "RX_BIAS"},
0846 {"SPK PA", NULL, "SPKR_CLK"},
0847 {"SPK PA", NULL, "SPK DAC"},
0848 {"SPK DAC", "Switch", "PDM_RX3"},
0849
0850 {"MIC_BIAS1", NULL, "INT_LDO_H"},
0851 {"MIC_BIAS2", NULL, "INT_LDO_H"},
0852 {"MIC_BIAS1", NULL, "vdd-micbias"},
0853 {"MIC_BIAS2", NULL, "vdd-micbias"},
0854
0855 {"MIC BIAS External1", NULL, "MIC_BIAS1"},
0856 {"MIC BIAS Internal1", NULL, "MIC_BIAS1"},
0857 {"MIC BIAS External2", NULL, "MIC_BIAS2"},
0858 {"MIC BIAS Internal2", NULL, "MIC_BIAS2"},
0859 {"MIC BIAS Internal3", NULL, "MIC_BIAS1"},
0860 };
0861
0862 static const struct snd_soc_dapm_widget pm8916_wcd_analog_dapm_widgets[] = {
0863
0864 SND_SOC_DAPM_AIF_IN("PDM_RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
0865 SND_SOC_DAPM_AIF_IN("PDM_RX2", NULL, 0, SND_SOC_NOPM, 0, 0),
0866 SND_SOC_DAPM_AIF_IN("PDM_RX3", NULL, 0, SND_SOC_NOPM, 0, 0),
0867 SND_SOC_DAPM_AIF_OUT("PDM_TX", NULL, 0, SND_SOC_NOPM, 0, 0),
0868
0869 SND_SOC_DAPM_INPUT("AMIC1"),
0870 SND_SOC_DAPM_INPUT("AMIC3"),
0871 SND_SOC_DAPM_INPUT("AMIC2"),
0872 SND_SOC_DAPM_OUTPUT("EAR"),
0873 SND_SOC_DAPM_OUTPUT("HPH_L"),
0874 SND_SOC_DAPM_OUTPUT("HPH_R"),
0875
0876
0877 SND_SOC_DAPM_SUPPLY("INT_LDO_H", SND_SOC_NOPM, 1, 0, NULL, 0),
0878
0879 SND_SOC_DAPM_PGA_E("EAR PA", SND_SOC_NOPM,
0880 0, 0, NULL, 0,
0881 pm8916_wcd_analog_enable_ear_pa,
0882 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
0883 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
0884 SND_SOC_DAPM_MUX("EAR_S", SND_SOC_NOPM, 0, 0, &ear_mux),
0885 SND_SOC_DAPM_SUPPLY("EAR CP", CDC_A_NCP_EN, 4, 0, NULL, 0),
0886
0887 SND_SOC_DAPM_PGA("HPHL PA", CDC_A_RX_HPH_CNP_EN, 5, 0, NULL, 0),
0888 SND_SOC_DAPM_MUX("HPHL", SND_SOC_NOPM, 0, 0, &hphl_mux),
0889 SND_SOC_DAPM_MIXER("HPHL DAC", CDC_A_RX_HPH_L_PA_DAC_CTL, 3, 0, NULL,
0890 0),
0891 SND_SOC_DAPM_PGA("HPHR PA", CDC_A_RX_HPH_CNP_EN, 4, 0, NULL, 0),
0892 SND_SOC_DAPM_MUX("HPHR", SND_SOC_NOPM, 0, 0, &hphr_mux),
0893 SND_SOC_DAPM_MIXER("HPHR DAC", CDC_A_RX_HPH_R_PA_DAC_CTL, 3, 0, NULL,
0894 0),
0895 SND_SOC_DAPM_MIXER("SPK DAC", SND_SOC_NOPM, 0, 0,
0896 spkr_switch, ARRAY_SIZE(spkr_switch)),
0897
0898
0899 SND_SOC_DAPM_OUTPUT("SPK_OUT"),
0900 SND_SOC_DAPM_PGA_E("SPK PA", CDC_A_SPKR_DRV_CTL,
0901 6, 0, NULL, 0,
0902 pm8916_wcd_analog_enable_spk_pa,
0903 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
0904 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
0905 SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-micbias", 0, 0),
0906 SND_SOC_DAPM_SUPPLY("CP", CDC_A_NCP_EN, 0, 0, NULL, 0),
0907
0908 SND_SOC_DAPM_SUPPLY("DAC_REF", CDC_A_RX_COM_BIAS_DAC, 0, 0, NULL, 0),
0909 SND_SOC_DAPM_SUPPLY("RX_BIAS", CDC_A_RX_COM_BIAS_DAC, 7, 0, NULL, 0),
0910
0911
0912 SND_SOC_DAPM_SUPPLY("MIC_BIAS1", CDC_A_MICB_1_EN, 7, 0,
0913 pm8916_wcd_analog_enable_micbias1,
0914 SND_SOC_DAPM_POST_PMU),
0915 SND_SOC_DAPM_SUPPLY("MIC_BIAS2", CDC_A_MICB_2_EN, 7, 0,
0916 pm8916_wcd_analog_enable_micbias2,
0917 SND_SOC_DAPM_POST_PMU),
0918
0919 SND_SOC_DAPM_SUPPLY("MIC BIAS External1", SND_SOC_NOPM, 0, 0, NULL, 0),
0920 SND_SOC_DAPM_SUPPLY("MIC BIAS External2", SND_SOC_NOPM, 0, 0, NULL, 0),
0921
0922 SND_SOC_DAPM_SUPPLY("MIC BIAS Internal1", CDC_A_MICB_1_INT_RBIAS, 7, 0,
0923 pm8916_wcd_analog_enable_micbias_int,
0924 SND_SOC_DAPM_PRE_PMU),
0925 SND_SOC_DAPM_SUPPLY("MIC BIAS Internal2", CDC_A_MICB_1_INT_RBIAS, 4, 0,
0926 pm8916_wcd_analog_enable_micbias_int2,
0927 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
0928 SND_SOC_DAPM_POST_PMD),
0929 SND_SOC_DAPM_SUPPLY("MIC BIAS Internal3", CDC_A_MICB_1_INT_RBIAS, 1, 0,
0930 pm8916_wcd_analog_enable_micbias_int,
0931 SND_SOC_DAPM_PRE_PMU),
0932
0933 SND_SOC_DAPM_ADC_E("ADC1", NULL, CDC_A_TX_1_EN, 7, 0,
0934 pm8916_wcd_analog_enable_adc,
0935 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
0936 SND_SOC_DAPM_POST_PMD),
0937 SND_SOC_DAPM_ADC_E("ADC2_INP2", NULL, CDC_A_TX_2_EN, 7, 0,
0938 pm8916_wcd_analog_enable_adc,
0939 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
0940 SND_SOC_DAPM_POST_PMD),
0941 SND_SOC_DAPM_ADC_E("ADC2_INP3", NULL, CDC_A_TX_3_EN, 7, 0,
0942 pm8916_wcd_analog_enable_adc,
0943 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
0944 SND_SOC_DAPM_POST_PMD),
0945
0946 SND_SOC_DAPM_MIXER("ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
0947 SND_SOC_DAPM_MIXER("ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
0948
0949 SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux),
0950 SND_SOC_DAPM_MUX("RDAC2 MUX", SND_SOC_NOPM, 0, 0, &rdac2_mux),
0951
0952
0953 SND_SOC_DAPM_SUPPLY("EAR_HPHR_CLK", CDC_D_CDC_ANA_CLK_CTL, 0, 0, NULL,
0954 0),
0955 SND_SOC_DAPM_SUPPLY("EAR_HPHL_CLK", CDC_D_CDC_ANA_CLK_CTL, 1, 0, NULL,
0956 0),
0957 SND_SOC_DAPM_SUPPLY("SPKR_CLK", CDC_D_CDC_ANA_CLK_CTL, 4, 0, NULL, 0),
0958 SND_SOC_DAPM_SUPPLY("TXA_CLK25", CDC_D_CDC_ANA_CLK_CTL, 5, 0, NULL, 0),
0959
0960
0961
0962 SND_SOC_DAPM_SUPPLY("RXD1_CLK", CDC_D_CDC_DIG_CLK_CTL, 0, 0, NULL, 0),
0963 SND_SOC_DAPM_SUPPLY("RXD2_CLK", CDC_D_CDC_DIG_CLK_CTL, 1, 0, NULL, 0),
0964 SND_SOC_DAPM_SUPPLY("RXD3_CLK", CDC_D_CDC_DIG_CLK_CTL, 2, 0, NULL, 0),
0965
0966 SND_SOC_DAPM_SUPPLY("TXD_CLK", CDC_D_CDC_DIG_CLK_CTL, 4, 0, NULL, 0),
0967 SND_SOC_DAPM_SUPPLY("NCP_CLK", CDC_D_CDC_DIG_CLK_CTL, 6, 0, NULL, 0),
0968 SND_SOC_DAPM_SUPPLY("RXD_PDM_CLK", CDC_D_CDC_DIG_CLK_CTL, 7, 0, NULL,
0969 0),
0970
0971
0972 SND_SOC_DAPM_SUPPLY("A_MCLK", CDC_D_CDC_TOP_CLK_CTL, 2, 0, NULL, 0),
0973
0974 SND_SOC_DAPM_SUPPLY("A_MCLK2", CDC_D_CDC_TOP_CLK_CTL, 3, 0, NULL, 0),
0975 };
0976
0977 static int pm8916_wcd_analog_set_jack(struct snd_soc_component *component,
0978 struct snd_soc_jack *jack,
0979 void *data)
0980 {
0981 struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
0982
0983 wcd->jack = jack;
0984
0985 return 0;
0986 }
0987
0988 static irqreturn_t mbhc_btn_release_irq_handler(int irq, void *arg)
0989 {
0990 struct pm8916_wcd_analog_priv *priv = arg;
0991
0992 if (priv->detect_accessory_type) {
0993 struct snd_soc_component *component = priv->component;
0994 u32 val = snd_soc_component_read(component, CDC_A_MBHC_RESULT_1);
0995
0996
0997 if ((val != -1) && !(val & CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK))
0998 priv->mbhc_btn0_released = true;
0999
1000 } else {
1001 snd_soc_jack_report(priv->jack, 0, btn_mask);
1002 }
1003
1004 return IRQ_HANDLED;
1005 }
1006
1007 static irqreturn_t mbhc_btn_press_irq_handler(int irq, void *arg)
1008 {
1009 struct pm8916_wcd_analog_priv *priv = arg;
1010 struct snd_soc_component *component = priv->component;
1011 u32 btn_result;
1012
1013 btn_result = snd_soc_component_read(component, CDC_A_MBHC_RESULT_1) &
1014 CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK;
1015
1016 switch (btn_result) {
1017 case 0xf:
1018 snd_soc_jack_report(priv->jack, SND_JACK_BTN_4, btn_mask);
1019 break;
1020 case 0x7:
1021 snd_soc_jack_report(priv->jack, SND_JACK_BTN_3, btn_mask);
1022 break;
1023 case 0x3:
1024 snd_soc_jack_report(priv->jack, SND_JACK_BTN_2, btn_mask);
1025 break;
1026 case 0x1:
1027 snd_soc_jack_report(priv->jack, SND_JACK_BTN_1, btn_mask);
1028 break;
1029 case 0x0:
1030
1031 if (!priv->detect_accessory_type)
1032 snd_soc_jack_report(priv->jack,
1033 SND_JACK_BTN_0, btn_mask);
1034 break;
1035 default:
1036 dev_err(component->dev,
1037 "Unexpected button press result (%x)", btn_result);
1038 break;
1039 }
1040
1041 return IRQ_HANDLED;
1042 }
1043
1044 static irqreturn_t pm8916_mbhc_switch_irq_handler(int irq, void *arg)
1045 {
1046 struct pm8916_wcd_analog_priv *priv = arg;
1047 struct snd_soc_component *component = priv->component;
1048 bool ins = false;
1049
1050 if (snd_soc_component_read(component, CDC_A_MBHC_DET_CTL_1) &
1051 CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK)
1052 ins = true;
1053
1054
1055 snd_soc_component_update_bits(component, CDC_A_MBHC_DET_CTL_1,
1056 CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK,
1057 (!ins << CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_SHIFT));
1058
1059
1060 if (ins) {
1061 bool micbias_enabled = false;
1062
1063 if (snd_soc_component_read(component, CDC_A_MICB_2_EN) &
1064 CDC_A_MICB_2_EN_ENABLE)
1065 micbias_enabled = true;
1066
1067 pm8916_mbhc_configure_bias(priv, micbias_enabled);
1068
1069
1070
1071
1072
1073
1074
1075 if (priv->mbhc_btn0_released)
1076 snd_soc_jack_report(priv->jack,
1077 SND_JACK_HEADSET, hs_jack_mask);
1078 else
1079 snd_soc_jack_report(priv->jack,
1080 SND_JACK_HEADPHONE, hs_jack_mask);
1081
1082 priv->detect_accessory_type = false;
1083
1084 } else {
1085 snd_soc_jack_report(priv->jack, 0, hs_jack_mask);
1086 priv->detect_accessory_type = true;
1087 priv->mbhc_btn0_released = false;
1088 }
1089
1090 return IRQ_HANDLED;
1091 }
1092
1093 static struct snd_soc_dai_driver pm8916_wcd_analog_dai[] = {
1094 [0] = {
1095 .name = "pm8916_wcd_analog_pdm_rx",
1096 .id = 0,
1097 .playback = {
1098 .stream_name = "PDM Playback",
1099 .rates = MSM8916_WCD_ANALOG_RATES,
1100 .formats = MSM8916_WCD_ANALOG_FORMATS,
1101 .channels_min = 1,
1102 .channels_max = 3,
1103 },
1104 },
1105 [1] = {
1106 .name = "pm8916_wcd_analog_pdm_tx",
1107 .id = 1,
1108 .capture = {
1109 .stream_name = "PDM Capture",
1110 .rates = MSM8916_WCD_ANALOG_RATES,
1111 .formats = MSM8916_WCD_ANALOG_FORMATS,
1112 .channels_min = 1,
1113 .channels_max = 4,
1114 },
1115 },
1116 };
1117
1118 static const struct snd_soc_component_driver pm8916_wcd_analog = {
1119 .probe = pm8916_wcd_analog_probe,
1120 .remove = pm8916_wcd_analog_remove,
1121 .set_jack = pm8916_wcd_analog_set_jack,
1122 .controls = pm8916_wcd_analog_snd_controls,
1123 .num_controls = ARRAY_SIZE(pm8916_wcd_analog_snd_controls),
1124 .dapm_widgets = pm8916_wcd_analog_dapm_widgets,
1125 .num_dapm_widgets = ARRAY_SIZE(pm8916_wcd_analog_dapm_widgets),
1126 .dapm_routes = pm8916_wcd_analog_audio_map,
1127 .num_dapm_routes = ARRAY_SIZE(pm8916_wcd_analog_audio_map),
1128 .idle_bias_on = 1,
1129 .use_pmdown_time = 1,
1130 .endianness = 1,
1131 };
1132
1133 static int pm8916_wcd_analog_parse_dt(struct device *dev,
1134 struct pm8916_wcd_analog_priv *priv)
1135 {
1136 int rval;
1137
1138 if (of_property_read_bool(dev->of_node, "qcom,micbias1-ext-cap"))
1139 priv->micbias1_cap_mode = MICB_1_EN_EXT_BYP_CAP;
1140 else
1141 priv->micbias1_cap_mode = MICB_1_EN_NO_EXT_BYP_CAP;
1142
1143 if (of_property_read_bool(dev->of_node, "qcom,micbias2-ext-cap"))
1144 priv->micbias2_cap_mode = MICB_1_EN_EXT_BYP_CAP;
1145 else
1146 priv->micbias2_cap_mode = MICB_1_EN_NO_EXT_BYP_CAP;
1147
1148 of_property_read_u32(dev->of_node, "qcom,micbias-lvl",
1149 &priv->micbias_mv);
1150
1151 if (of_property_read_bool(dev->of_node,
1152 "qcom,hphl-jack-type-normally-open"))
1153 priv->hphl_jack_type_normally_open = true;
1154 else
1155 priv->hphl_jack_type_normally_open = false;
1156
1157 if (of_property_read_bool(dev->of_node,
1158 "qcom,gnd-jack-type-normally-open"))
1159 priv->gnd_jack_type_normally_open = true;
1160 else
1161 priv->gnd_jack_type_normally_open = false;
1162
1163 priv->mbhc_btn_enabled = true;
1164 rval = of_property_read_u32_array(dev->of_node,
1165 "qcom,mbhc-vthreshold-low",
1166 &priv->vref_btn_cs[0],
1167 MBHC_MAX_BUTTONS);
1168 if (rval < 0) {
1169 priv->mbhc_btn_enabled = false;
1170 } else {
1171 rval = of_property_read_u32_array(dev->of_node,
1172 "qcom,mbhc-vthreshold-high",
1173 &priv->vref_btn_micb[0],
1174 MBHC_MAX_BUTTONS);
1175 if (rval < 0)
1176 priv->mbhc_btn_enabled = false;
1177 }
1178
1179 if (!priv->mbhc_btn_enabled)
1180 dev_err(dev,
1181 "DT property missing, MBHC btn detection disabled\n");
1182
1183
1184 return 0;
1185 }
1186
1187 static int pm8916_wcd_analog_spmi_probe(struct platform_device *pdev)
1188 {
1189 struct pm8916_wcd_analog_priv *priv;
1190 struct device *dev = &pdev->dev;
1191 int ret, i, irq;
1192
1193 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1194 if (!priv)
1195 return -ENOMEM;
1196
1197 ret = pm8916_wcd_analog_parse_dt(dev, priv);
1198 if (ret < 0)
1199 return ret;
1200
1201 priv->mclk = devm_clk_get(dev, "mclk");
1202 if (IS_ERR(priv->mclk)) {
1203 dev_err(dev, "failed to get mclk\n");
1204 return PTR_ERR(priv->mclk);
1205 }
1206
1207 for (i = 0; i < ARRAY_SIZE(supply_names); i++)
1208 priv->supplies[i].supply = supply_names[i];
1209
1210 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(priv->supplies),
1211 priv->supplies);
1212 if (ret) {
1213 dev_err(dev, "Failed to get regulator supplies %d\n", ret);
1214 return ret;
1215 }
1216
1217 ret = clk_prepare_enable(priv->mclk);
1218 if (ret < 0) {
1219 dev_err(dev, "failed to enable mclk %d\n", ret);
1220 return ret;
1221 }
1222
1223 irq = platform_get_irq_byname(pdev, "mbhc_switch_int");
1224 if (irq < 0) {
1225 ret = irq;
1226 goto err_disable_clk;
1227 }
1228
1229 ret = devm_request_threaded_irq(dev, irq, NULL,
1230 pm8916_mbhc_switch_irq_handler,
1231 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
1232 IRQF_ONESHOT,
1233 "mbhc switch irq", priv);
1234 if (ret)
1235 dev_err(dev, "cannot request mbhc switch irq\n");
1236
1237 if (priv->mbhc_btn_enabled) {
1238 irq = platform_get_irq_byname(pdev, "mbhc_but_press_det");
1239 if (irq < 0) {
1240 ret = irq;
1241 goto err_disable_clk;
1242 }
1243
1244 ret = devm_request_threaded_irq(dev, irq, NULL,
1245 mbhc_btn_press_irq_handler,
1246 IRQF_TRIGGER_RISING |
1247 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1248 "mbhc btn press irq", priv);
1249 if (ret)
1250 dev_err(dev, "cannot request mbhc button press irq\n");
1251
1252 irq = platform_get_irq_byname(pdev, "mbhc_but_rel_det");
1253 if (irq < 0) {
1254 ret = irq;
1255 goto err_disable_clk;
1256 }
1257
1258 ret = devm_request_threaded_irq(dev, irq, NULL,
1259 mbhc_btn_release_irq_handler,
1260 IRQF_TRIGGER_RISING |
1261 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1262 "mbhc btn release irq", priv);
1263 if (ret)
1264 dev_err(dev, "cannot request mbhc button release irq\n");
1265
1266 }
1267
1268 dev_set_drvdata(dev, priv);
1269
1270 return devm_snd_soc_register_component(dev, &pm8916_wcd_analog,
1271 pm8916_wcd_analog_dai,
1272 ARRAY_SIZE(pm8916_wcd_analog_dai));
1273
1274 err_disable_clk:
1275 clk_disable_unprepare(priv->mclk);
1276 return ret;
1277 }
1278
1279 static int pm8916_wcd_analog_spmi_remove(struct platform_device *pdev)
1280 {
1281 struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(&pdev->dev);
1282
1283 clk_disable_unprepare(priv->mclk);
1284
1285 return 0;
1286 }
1287
1288 static const struct of_device_id pm8916_wcd_analog_spmi_match_table[] = {
1289 { .compatible = "qcom,pm8916-wcd-analog-codec", },
1290 { }
1291 };
1292
1293 MODULE_DEVICE_TABLE(of, pm8916_wcd_analog_spmi_match_table);
1294
1295 static struct platform_driver pm8916_wcd_analog_spmi_driver = {
1296 .driver = {
1297 .name = "qcom,pm8916-wcd-spmi-codec",
1298 .of_match_table = pm8916_wcd_analog_spmi_match_table,
1299 },
1300 .probe = pm8916_wcd_analog_spmi_probe,
1301 .remove = pm8916_wcd_analog_spmi_remove,
1302 };
1303
1304 module_platform_driver(pm8916_wcd_analog_spmi_driver);
1305
1306 MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>");
1307 MODULE_DESCRIPTION("PMIC PM8916 WCD Analog Codec driver");
1308 MODULE_LICENSE("GPL v2");
